Storage and calculation integrated compatible in-situ encryption method

Abstract

The invention discloses a storage and calculation integrated compatible in-situ encryption method, and belongs to the technical field of novel storage calculation. On the basis of a 1T1R RRAM array, bit-by-bit XOR encryption operation is synchronously completed in the in-situ execution process of matrix vector multiplication. According to the invention, the weight data is efficiently protected on the chip, and the weight does not need to be moved to the outside of the array for processing, so that the high-security on-chip bit-by-bit encryption is realized on the array level. Compared with a traditional scheme, the method has the advantages that the system complexity and the energy consumption overhead are remarkably reduced, universal, extensible and efficient security encryption basic configuration is provided for various in-memory computing systems needing to protect weight parameters or model privacy, and the method is a heterogeneous storage and computing integrated scheme with high efficiency and high security.

Description

TECHNICAL FIELD

[0001] The application belongs to the field of novel in-memory computing technology, and particularly relates to an in-situ encryption method compatible with memory-computing integration based on 1T1R RRAM in-memory computing. BACKGROUND

[0002] With the rapid development of artificial intelligence, Internet of Things and big data analysis, the energy consumption bottleneck and data transmission delay caused by the separation of "storage-computing" in the traditional von Neumann computing architecture have become increasingly prominent. To overcome the above limitations, in-memory computing technology has gradually become a research hotspot. This technology embeds computing functions directly into storage units to realize parallel processing of data within the storage array, thereby significantly reducing data transfer overhead and improving computing efficiency. Among them, in-memory computing based on resistive random access memory (RRAM) is widely used to implement on-chip computing tasks such as large-scale multiplication and logical inference, due to its high write speed, low power consumption, strong scalability and compatibility with CMOS process. Through the cross-bar array structure of 1T1R, in-memory computing based on resistive random access memory can efficiently and parallelly accelerate the matrix-vector multiplication operation in the artificial neural network inference process, laying a foundation for the development of on-chip intelligent accelerators.

[0003] However, when RRAM in-memory computing is applied to neural network inference or security-related computing, the security problem of on-chip weights or critical parameters becomes increasingly prominent. Due to the non-volatility of RRAM, its storage state is physically readable and measurable, and its on-resistance can be analyzed under side-channel attacks (such as current analysis, microscopic probe detection, etc.), thereby causing the weight distribution or sensitive data within the array to be illegally inferred. In addition, in some memory-computing integration architectures, weights are saved in the form of analog conductance values in the storage array for a long time, and once captured, they may not only leak the model structure and parameters, but also cause the inference results to be reverse analyzed or maliciously tampered with. Therefore, how to protect the security of on-chip weights during memory-computing integration computing has become a key technical problem that needs to be solved in this field.

[0004] Among many lightweight security schemes, bitwise XOR encryption is widely used in data obfuscation and fast encryption scenarios due to its simple logical structure, low hardware cost and natural reversibility. Existing research proposes to add XOR / AND / OR operation units on the external logic or use independent encryption modules outside the in-memory computing array. However, these schemes generally have the following problems: (1) Introducing additional logic gates or security circuits: Traditional schemes rely on independent logic gate arrays to implement encryption operations, resulting in an increase in the size of the peripheral hardware and making it difficult to integrate on-chip at low cost.

[0005] (2) Unable to be performed simultaneously with in-memory computing: existing encryption mechanisms are usually performed outside the memory-computing array, and need to be independently processed before or after computing, which cannot be synchronized with the internal computing (such as matrix-vector multiplication) of the RRAM in-memory computing array, increasing the complexity of data flow.

[0006] (3) Additional processing hardware and processing period are needed: since the encryption logic is independent of the in-memory computing module, the operation path and data moving path are lengthened, resulting in additional time delay and energy consumption, reducing the overall system performance.

[0007] (4) Not conducive to on-chip real-time protection: the external encryption process needs to take the weights or part of the data out of the array, forming a new potential leakage point, which does not meet the real-time protection requirements in security-sensitive scenarios.

[0008] In summary, the existing technology still lacks an on-chip encryption mechanism that can be directly implemented inside the 1T1R RRAM array, without additional logic gates, and in parallel with the memory-computing operation, to simultaneously meet the security and computing efficiency requirements. Therefore, it is of great significance to develop an on-chip weight encryption scheme compatible with in-memory computing to simultaneously ensure the efficiency of computing and the security of on-chip data. SUMMARY

[0009] The present application provides an in-situ encryption method compatible with memory-computing integration, which can realize XOR encryption protection of on-chip weights without affecting the calculation of RRAM in-memory computing array, significantly improving processing speed, energy efficiency, and data security, providing a secure hardware acceleration foundation configuration for RRAM-based in-memory computing applications.

[0010] To achieve the above-mentioned purpose, the technical scheme provided by the present application is as follows: An in-situ encryption method compatible with memory-computing integration, comprising the following steps: 1) The memory-computing integrated computing structure adopts a 1T1R RRAM array, each 1T1R cell in the array is composed of a transistor and a resistive memory device in series, the word line WL of the 1T1R RRAM array is perpendicular to the source line SL, the bit line BL is parallel to the word line WL, and they share the same source line SL, wherein, adjacent two 1T1R cells in each column are an XOR encryption unit; 2) Perform a bitwise XOR operation on the binary number W using the key string Key to obtain the encrypted string X, that is , wherein represents a bitwise XOR operation, the binary number W is the weight to be protected, the string X is mapped to the on-chip conductance of the XOR encryption unit, and the 1T1R RRAM array is encrypted; 3) in the in-memory calculation, the BL and WL voltage of each XOR encryption unit is normalized 0 / 1 input, and the multiplication operation of the weight W and the input Input is performed through different WL and BL control, when the BL input of the XOR encryption unit is 0, the SL output is 0, and when the BL input of the XOR encryption unit is 1, the output of the XOR encryption unit is: ， wherein n represents the nth XOR encryption unit; 4) the output of the XOR encryption unit is quantified through the ADC of the peripheral circuit to realize the vector-vector multiplication calculation with the weight XOR encryption protection.

[0011] Further, the low resistance state of the resistive memory in the XOR encryption unit in step 2) represents logical 1, and the high resistance state of the resistive memory represents logical 0.

[0012] Further, the input voltage of the BL of the XOR encryption unit in step 3) adopts an analog voltage corresponding to the bit weight to realize the multiply-accumulate calculation containing the weight bit information, that is: wherein represents the nth XOR encryption unit, is the input voltage size of the mth row, represents the reference inference voltage.

[0013] Further, in step 3), 1 bit is input in each calculation period, and the input is performed bit by bit, and the SL outputs the multiply-accumulate analog current value of the weight W and the input Input in each calculation period, and the output results of multiple periods are added by bit shifting, so that the unsigned multiplication result of any input Input and any weight W can be obtained.

[0014] Further, the resistive memory device is a metal-resistive material-metal structure; the resistive material adopts single-layer or multi-layer metal oxide material, such as hafnium oxide, tantalum oxide, titanium oxide and the like, and the thickness is between 1 nm and 10 nm.

[0015] Compared with the prior art, the present application has the following advantages: The present application constructs an encryption-computation compatible in-situ encryption method based on a 1T1R RRAM array, and the bit-by-bit XOR encryption operation is completed synchronously in the in-situ execution process of the matrix-vector multiplication. By mapping the XOR logic in the XOR encryption unit, the present application realizes the efficient protection of the weight data on the chip, and does not need to move the weight to the outside of the array for processing, so that the high-security bit-by-bit encryption on the chip is realized at the array level.

[0016] ​​The bit-by-bit XOR operation of the key bits of the application can be parallel with the matrix-vector multiplication process, which ensures the high energy efficiency of the RRAM in-memory calculation without introducing additional calculation cycles and read-write instructions, and without the need for additional peripheral logic gates or security modules to complete the encryption.

[0017] Compared with the traditional scheme, the application significantly reduces the system complexity and energy consumption overhead, provides a general, scalable and efficient secure encryption foundation configuration for various in-memory computing systems that need to protect weight parameters or model privacy, and is a heterogeneous in-memory computing scheme with high efficiency and high security. BRIEF DESCRIPTION OF DRAWINGS

[0018] Figure 1 is the in-memory computing structure of the embodiment of the application.

[0019] Figure 2 is the XOR encryption unit and parameter mapping diagram of the embodiment of the application.

[0020] Figure 3 is the calculation truth table of the XOR encryption unit of the embodiment of the application.

[0021] Figure 4 is the single-column bit-by-bit XOR encryption method diagram of the embodiment of the application. DETAILED DESCRIPTION

[0022] The application will be further described below by examples in conjunction with the drawings, but the scope of the application is not limited in any way.

[0023] Figure 1 is the encryption-computing compatible in-memory computing structure of the embodiment of the application.

[0024] The in-memory computing structure of the application adopts a 1T1R RRAM array, each 1T1R unit in the array is composed of a transistor and a resistive memory device in series, and all the 1T1R units are arranged in an array, wherein the word line WL of the 1T1R unit is perpendicular to the source line SL, the bit line BL is parallel to the word line WL, and the same SL is shared, wherein the two adjacent 1T1R units in each column are an XOR encryption unit, the low resistance state of the resistive memory in each XOR encryption unit represents logical 1, and the high resistance state of the resistive memory represents logical 0, the BL and WL voltages are normalized 0 / 1 inputs, and the bit-by-bit XOR encryption operation is completed through binary mapping.

[0025] As shown in Figure 2 , the encryption principle of the XOR encryption unit of the application is as follows: When encrypting any two binary numbers A, B, one of the numbers (take A as an example) can be mapped to the resistance value of the first device RRAM, and the low resistance state represents logic 1, and the high resistance state represents logic 0; and the resistance value of the second device RRAM is mapped to the non-value of A. And the other number (B) is input through the WL of the second device, and the high voltage represents logic 1, and the low voltage represents logic 0. At this time, input high voltage on BL for reasoning calculation, the XOR operation result of A and B will be input on SL, that is: wherein represents the current output on SL, and a large current represents logic 1, and a small current represents logic 0, is an XOR operation symbol.

[0026] Figure 3 is the calculation truth table of the XOR encryption unit of the specific embodiment of the present application. When the BL input standard high voltage 1, by Ohm's law and Kirchhoff's law: Take case 1 as an example: input A is logic 0, then map the first RRAM to 0 (high resistance state), then map the second RRAM to 1 (low resistance state) accordingly; At the same time, input B is logic 0, then WL1 input is 0 (low voltage), the second 1T1R RRAM device calculates the output logic 0; Correspondingly, the WL0 input is 1 (high voltage), but at this time the first RRAM is in a high resistance state, and the first 1T1R RRAM device calculates the output logic 0 (small current), at this time the output current on SL is the sum of the currents of the two devices, and the final output is logic 0.

[0027] Figure 4 is a schematic diagram of the single-column in-situ encryption method compatible with the storage and calculation of the specific embodiment of the present application.

[0028] 1) Two 1T1R units in each column of the 1T1R RRAM array form a group to constitute an XOR encryption unit, representing 1bit binary weight, and 8 rows of devices in the figure form 4 XOR encryption units, which can represent an unsigned 4-bit binary number W, from high to low as (W0, W1, W2, W3).

[0029] 2) In order to prevent on-chip weight leakage, the same length of key string Key (Key0, Key1, Key2, Key3) is used to perform bit-by-bit XOR operation on the binary number, and the encrypted string X (X0, X1, X2, X3) is obtained, that is: wherein This represents a bitwise XOR operation, where the binary number W represents the weights to be protected. The lengths of Key and X can be arbitrarily extended (corresponding to the quantization precision of the neural network), matching the number of bits to be encrypted using XOR. Further based on... Figure 1 The parameter mapping scheme maps the string X to the on-chip conductance of the XOR encryption unit and performs encryption operation on the 1T1R RRAM array. For any matrix consisting of n vectors (each vector is composed of m bits of binary string), a 2m row and n column 1T1R RRAM array is used for mapping.

[0030] 3) During in-memory computation, the BL and WL voltages of the XOR encryption unit are both normalized 0 / 1 inputs. A multiplication operation is performed between the weight W and the input. When the BL input is 0, the SL output is 0; when the BL input is 1, the output of each XOR encryption unit (composed of two adjacent 1T1R units) is as follows: Where n represents the nth XOR encryption unit. Furthermore, to implement multiplication and accumulation calculations containing weight bit information, the input voltage of BL is modified to an analog voltage corresponding to the bit weights, i.e.: in Indicates the first Each XOR encryption unit It is the first The magnitude of the input voltage of the line, Representing the reference inference voltage, we have: In a specific example, n is 4. For any input string Input(In0, In1, In2, In3), the length of the string can be arbitrarily extended. One bit is input in each calculation cycle, and the input is performed bit by bit. In each calculation cycle, SL will multiply the output weight W with a certain bit of the input and accumulate the analog current value. The output results of multiple cycles are added according to the input shift, so as to obtain the unsigned multiplication result of any input and any weight W.

[0031] 4) The output digital quantization result of the XOR encryption unit in the 1T1R RRAM array column is quantized by the ADC of the peripheral circuit; thus realizing vector-vector multiplication calculation with weighted XOR encryption protection.

[0032] The above embodiments are only some preferred embodiments of the present invention and are not intended to limit the scope of protection of the present invention. Any changes made based on the design principles of the present invention, and any non-creative changes made on this basis, should fall within the scope of protection of the present invention.

Claims

1. An in-situ encryption method compatible with storage and computing, comprising the following steps: 1) The in-memory computing structure adopts a 1T1R RRAM array. Each 1T1R cell in the array consists of a transistor and a resistive random access memory device connected in series. The word line WL of the 1T1R RRAM array is perpendicular to the source line SL, and the bit line BL is parallel to the word line WL and shares the same source line SL. In each column, two adjacent 1T1R cells form an XOR encryption unit. 2) Perform a bitwise XOR operation on the binary number W using the key string Key to obtain the encrypted string X, i.e. ,in This represents a bitwise XOR operation, where the binary number W is the weight to be protected. The string X is mapped to the on-chip conductance of the XOR encryption unit, and the 1T1R RRAM array is encrypted. 3) During in-memory computation, the BL and WL voltages of each XOR encryption unit are normalized 0 / 1 inputs. Through different WL and BL controls, a multiplication operation is performed between the weight W and the input. When the BL input of the XOR encryption unit is 0, the SL output is 0; when the BL input of the XOR encryption unit is 1, the output of the XOR encryption unit is: ， Where n represents the nth XOR encryption unit; 4) Vector-vector multiplication calculation with weighted XOR encryption protection is achieved by quantizing the output of the XOR encryption unit of the peripheral circuit's ADC.

2. The in-situ encryption method that integrates storage and computation as described in claim 1, characterized in that, In step 2), the low-resistance state of the resistive variable memory in the XOR encryption unit represents logic 1, and the high-resistance state of the resistive variable memory represents logic 0.

3. The in-situ encryption method that integrates storage and computation as described in claim 1, characterized in that, In step 3), the input voltage of the XOR encryption unit BL is replaced with an analog voltage corresponding to the bit weight, so as to realize the multiplication and accumulation calculation containing the weight bit information, that is: ,in Indicates the first Each XOR encryption unit It is the first The magnitude of the input voltage of the line, This represents the reference inference voltage.

4. The in-situ encryption method that integrates storage and computation as described in claim 1, characterized in that, In step 3), one bit is input for each calculation cycle, and the input is performed bit by bit. In each calculation cycle, SL multiplies the output weight W with a certain bit of the input and accumulates the analog current value. The output results of multiple cycles are added according to the input shift, and the unsigned multiplication result of any input and any weight W is obtained.

5. The in-situ encryption method that integrates storage and computation as described in claim 1, characterized in that, The resistive switching memory device is a metal-resistive switching material-metal structure.

6. The in-situ encryption method that integrates storage and computation as described in claim 5, characterized in that, The resistive switching material is a single-layer or multi-layer hafnium oxide, tantalum oxide, or titanium oxide metal oxide.

7. The in-situ encryption method that integrates storage and computation as described in claim 5, characterized in that, The thickness of the resistive switching material is between 1 nm and 10 nm.

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