Signal flow information searching method and electronic equipment

Abstract

The invention discloses a signal flow information searching method and electronic equipment, and relates to the technical field of computers, and the method comprises the following steps: obtaining netlist information of each board card in a server; determining a terminal insertion relation between the board cards and a pin corresponding relation between insertion terminals based on the netlist information of the board cards; establishing a signal flow node model corresponding to each board card based on the netlist information of each board card; constructing a complete signal flow channel topology in the server according to the terminal plug-in relation between the board cards, the pin corresponding relation between plug-in terminals and the signal flow node model corresponding to each board card; electrical parameter information in the signal flowing process is collected and summarized along the signal flowing channel topology, and the design scheme of the server is checked based on the electrical parameter information and the architecture design rule of the server. According to the method, the signal flow information is automatically, accurately and efficiently searched and checked, and the verification efficiency and reliability of the design scheme are improved.

Description

Technical Field

[0001] This application relates to the field of computer technology, and more specifically, to a method and electronic device for finding signal flow information. Background Technology

[0002] In related technologies, the verification of the electrical design specifications of storage servers is primarily done manually. After completing the electrical schematics and wiring diagrams, design engineers must manually compile information such as connection relationships and component parameters scattered across multiple drawings, and then compare and verify them item by item with the original architecture document. This process is not only time-consuming and labor-intensive, but also highly susceptible to human error when dealing with large-scale, multi-board, high-density complex circuit systems, leading to omissions of signal connections or misjudgments of electrical parameters, which can seriously affect the electrical performance and reliability of server products.

[0003] Therefore, how to automate, accurately, and efficiently locate and inspect signal flow information, and improve the efficiency and reliability of design verification, is a technical problem that needs to be solved by those skilled in the art. Summary of the Invention

[0004] The purpose of this application is to provide a method and electronic device for finding signal flow information, which realizes automated, accurate and efficient finding and checking of signal flow information, and improves the efficiency and reliability of design verification.

[0005] To achieve the above objectives, this application provides a method for finding signal flow information, comprising:

[0006] Obtain the netlist information of each board in the server; wherein, the netlist information of the board includes the devices contained in the board and the pin connection relationships of the devices;

[0007] The terminal mating relationships between each board and the pin correspondence between the mating terminals are determined based on the netlist information of each board.

[0008] Based on the netlist information of each board, the signal flow path inside each board is modeled to identify the devices through which the signal flows and to establish a signal flow node model corresponding to each board.

[0009] Based on the terminal interlocking relationship between each board, the pin correspondence between the interlocking terminals, and the signal flow node model corresponding to each board, a complete signal flow channel topology inside the server is constructed.

[0010] Electrical parameter information during the signal flow process is collected and summarized along the signal flow channel topology, and the server design scheme is checked based on the electrical parameter information and the server architecture design rules.

[0011] To achieve the above objectives, this application provides a signal flow information retrieval device, comprising:

[0012] The acquisition module is used to acquire the netlist information of each board in the server; wherein, the netlist information of the board includes the devices contained in the board and the pin connection relationship of the devices;

[0013] The determination module is used to determine the terminal mating relationship between each board and the pin correspondence between the mating terminals based on the netlist information of each board.

[0014] The modeling module is used to model the signal flow path inside each board based on the netlist information of each board, so as to identify the devices through which the signal flows and establish the signal flow node model corresponding to each board.

[0015] The construction module is used to construct the complete signal flow channel topology inside the server based on the terminal interlocking relationship between each board, the pin correspondence between the interlocking terminals, and the signal flow node model corresponding to each board.

[0016] The inspection module is used to collect and summarize electrical parameter information along the signal flow channel topology, and to inspect the server design scheme based on the electrical parameter information and the server architecture design rules.

[0017] To achieve the above objectives, this application provides an electronic device, comprising:

[0018] Memory, used to store computer programs;

[0019] A processor is used to implement the steps of the signal flow information lookup method described above when executing a computer program.

[0020] To achieve the above objectives, this application provides a computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps of the signal flow information retrieval method described above.

[0021] To achieve the above objectives, this application provides a computer program product, including a computer program that, when executed by a processor, implements the steps of the signal flow information search method described above.

[0022] The signal flow information retrieval method provided in this application automatically determines the terminal plug-in relationships and pin correspondences between boards by acquiring the netlist information of each board in the server, thereby realizing the automated identification and modeling of cross-board signal channels within the system. Based on this, it further models the signal flow path within the board based on the netlist information of each board, establishing a signal flow node model, thus constructing a complete signal flow channel topology within the server. This signal flow channel topology comprehensively covers the entire link path of the signal from initiation, transmission to reception, making the signal flow process visible and structured. Based on the signal flow channel topology, electrical parameter information can be automatically collected and summarized along the signal path, and the design scheme can be automatically checked according to preset architecture design rules. Since the entire process is executed automatically by the system, the execution efficiency of signal retrieval and checking is significantly improved, the design verification cycle is shortened, and the accuracy and reliability of the server electrical design are enhanced. This application also discloses a signal flow information retrieval device, an electronic device, a computer-readable storage medium, and a computer program product, which can achieve the same technical effects.

[0023] It should be understood that the above general description and the following detailed description are merely exemplary and do not limit this application. Attached Figure Description

[0024] To more clearly illustrate the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0025] Figure 1 This is a flowchart illustrating a signal flow information retrieval method according to an exemplary embodiment;

[0026] Figure 2 This is a detailed flowchart illustrating step S13 according to an exemplary embodiment;

[0027] Figure 3 A flowchart of an application embodiment provided in this application;

[0028] Figure 4 This is a structural diagram illustrating a signal flow information retrieval device according to an exemplary embodiment;

[0029] Figure 5 This is a structural diagram of an electronic device according to an exemplary embodiment. Detailed Implementation

[0030] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of this application.

[0031] It should be noted that, in the description of this application, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. The terms "first," "second," etc., in this application are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0032] To enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0033] The embodiments of this application provide a method for finding signal flow information. The method is described in detail below in conjunction with the execution flow of the method for finding signal flow information.

[0034] See Figure 1 A flowchart illustrating a signal flow information lookup method according to an exemplary embodiment is shown below. Figure 1 As shown, it includes:

[0035] S11: Obtain the netlist information of each board in the server; wherein, the netlist information of the board includes the devices contained in the board and the pin connection relationships of the devices;

[0036] In this context, a circuit board refers to an independent hardware circuit unit that constitutes a storage service server, such as a motherboard, hard drive backplane, or expansion card. Each circuit board contains integrated circuits, connectors (terminals), resistors, capacitors, and other electronic components. A netlist is a structured data file describing circuit connections; its full name is a netlist, and it can be generated by Electronic Design Automation (EDA) software during the design phase. The netlist details the identifiers, types, and electrical connections between the pins of all components on the circuit board.

[0037] In this step, information is obtained by reading the standard netlist format files corresponding to each board in the design project. For example, in a storage server project, the netlist files of all boards, such as the motherboard, hard drive backplane, and RAID (Redundant Array of Independent Disks) controller card, are read. These files contain the connection definitions of all components, including resistors, capacitors, integrated circuits, and connectors.

[0038] As can be seen, this step can obtain the underlying connection data of the entire server electrical design, establishing an accurate and complete information foundation for subsequent automated analysis and avoiding errors and omissions that may occur when manually extracting information from drawings.

[0039] S12: Determine the terminal mating relationship between each board and the pin correspondence between the mating terminals based on the netlist information of each board;

[0040] In this context, a terminal is a connector on a circuit board used for electrical interconnection between boards. A mating relationship refers to the physical connection and electrical link between two terminals on different boards. A pin correspondence precisely describes the connection matching relationship between the pins of the two mating terminals.

[0041] In this step, the connection relationships between boards are automatically identified and established by analyzing the terminal connection information recorded in the netlists of each board. This includes analyzing which terminals are paired due to design interconnection intentions, and how to determine the one-to-one mapping rules for the pins of these paired terminals based on design information. For example, by processing the connection data in the netlist, the system can identify that a certain high-speed connector on the motherboard and the corresponding connector on the backplane are paired, and further clarify the specific mating method of hundreds of pins on the connector based on the design logic, such as pin A1 corresponding to pin B1 on the other end.

[0042] As can be seen, this step automates the identification of all physical interconnections within the server, transforming the design intent implied in network names into explicit topology knowledge. This replaces the manual process of consulting connector manuals and drawings for comparison, greatly improving the efficiency and accuracy of building a system-level connection model.

[0043] As a feasible implementation method, the terminal interlocking relationship between each board is determined based on the netlist information of each board, including: extracting the set of network names connected to each terminal from the netlist information of each board; if there is a preset number or more of the same network names between the first terminal and the second terminal, then the first terminal and the second terminal are determined to be interlocking.

[0044] In this context, the network name is a unique identifier assigned to each electrical connection network in the netlist file, and all pins within the same network are electrically connected. The preset quantity is a pre-defined threshold used as a criterion for judgment; its specific value can be determined empirically or experimentally based on system complexity and typical connection patterns, for example, it can be set to 5.

[0045] In practice, the process begins by extracting all network names connected to each terminal from the netlist information of all boards, forming a set of network names for each terminal. This set represents all signals that the terminal interacts with externally. Then, all terminals are compared pairwise to calculate the intersection of their network name sets. If any two terminals share a preset number of identical network names, they are considered to have a matching relationship.

[0046] For example, suppose the network set connected to connector CONN_A on the motherboard includes NET1, NET2, NET3, NET4, NET5, and NET6, while the network set connected to connector CONN_B on the backplane includes NET1, NET2, NET3, NET4, NET5, and NET7. Both connectors share five identical networks. If the default number is set to 5, the system determines that CONN_A and CONN_B have a mating relationship.

[0047] As can be seen, this implementation method utilizes the implicit connection intentions in the design data to automatically identify physical interconnection relationships through simple set comparison, replacing the tedious process of manually reviewing drawings and connector specifications. The preset quantity threshold acts as a filter, effectively avoiding misjudgments caused by a small number of coincidentally identical network names, ensuring the accuracy and reliability of relationship identification.

[0048] As a feasible implementation method, the pin correspondence between the plug-in terminals is determined based on the netlist information of each board, including: if the letter part or the number part of the name of the first pin and the second pin is the same, then the first pin and the second pin are determined to be in a one-to-one correspondence; if the letter part of the name of the third pin and the fourth pin conforms to a preset interchange relationship, then the third pin and the fourth pin are determined to be in a cross-symmetrical correspondence; if the sum of the number part of the name of the fifth pin and the sixth pin is equal to a preset constant value, then the fifth pin and the sixth pin are determined to be in a mirror correspondence.

[0049] The pin mapping precisely describes the one-to-one electrical connection mapping between the pins of a pair of mating terminals. Pin names are typically composed of letter identifiers representing rows or columns and numerical numbers representing sequence numbers, such as A1 and B12. Identical letter parts mean the pin identifiers are completely identical. Identical numerical parts mean the pin numbers are completely identical. Preset interchangeability refers to a pair of letter combinations with a specific functional correspondence, such as A and B, P and N, TX and RX; this relationship is usually predefined in connector standards or designs. Preset constant values ​​are fixed sums, often used to describe the mirror mapping relationship of pins in symmetrical connectors; their value is typically one more than the total number of pins in the mating terminal pair.

[0050] In practice, for two terminals with a known mating relationship, the composition of each pin's name is further analyzed, and a series of preset rules are applied to establish a pin mapping. If the letter parts or numeric parts of two pin names are exactly the same, they are directly determined to be in a one-to-one correspondence. If the letter parts of two pin names are different but conform to a predefined interchangeability relationship, they are determined to be in a cross-symmetrical correspondence. If the numeric parts of two pin names are different, but their sum equals a preset constant value, they are determined to be in a mirror correspondence. It should be noted that these rules can be applied sequentially or in parallel until a correspondence is established for all critical pins.

[0051] For example, assuming pin A10 of terminal A and pin A10 of terminal B have the exact same name, a one-to-one correspondence is established. If pin A7 of terminal A corresponds to pin B7 of terminal B, and A and B are interchangeable by a preset condition, a cross-symmetrical correspondence is established. If pin 2 of terminal A corresponds to pin 40 of terminal B, and the total number of pins in the connector is 40, with a preset constant of 42, then 2 + 40 = 42, satisfying the condition, and a mirror correspondence is established.

[0052] As can be seen, this implementation method automates the reasoning of pin correspondences by parsing the structured information in the pin names, without relying on external connector pairing tables. The combined application of multiple rules can cover different types of connector design habits, enhancing the method's versatility and adaptability, thereby accurately constructing the specific physical channels for inter-board signal connections.

[0053] S13: Model the signal flow path inside each board based on the netlist information of each board, so as to identify the devices through which the signal flows and establish the signal flow node model corresponding to each board.

[0054] Signal flow path modeling refers to transforming the static connection relationships described in the netlist into a structured model that reflects the dynamic flow direction of the signal and its passage through key nodes. The signal flow node model abstracts and defines devices (nodes) with specific functions in the signal path to represent how the signal passes through the device.

[0055] In this step, the board's netlist information is processed. By analyzing the connection relationships between signal networks and devices, the signal flow path within the board is constructed. This process reorganizes the network-centric, tiled connection list in the netlist into a hierarchical model containing functional nodes, guided by signal flow. For example, for a power enable signal, the system identifies, based on the netlist, the complete path the signal passes through, including the source chip pin, possible pull-up resistors, series resistors, and isolation MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors), ultimately reaching the load chip pin. Node models reflecting the electrical characteristics of key devices along the path, such as resistors and MOSFETs, are then established.

[0056] As can be seen, this step transforms the flat connection list in the netlist into a hierarchical model that reflects the signal flow and topology, providing a structured representation for understanding the actual behavior of signals within the board (such as pull-up, voltage division, and isolation).

[0057] S14: Construct the complete signal flow channel topology inside the server based on the terminal interlocking relationship between each board, the pin correspondence between the interlocking terminals, and the signal flow node model corresponding to each board;

[0058] Among them, the signal flow channel topology is a global structural model that describes the complete flow path of a signal from its source to its destination throughout the entire server system. It integrates the flow path within the board and the connection relationship between boards.

[0059] In this step, the inter-board terminal interconnection relationships (including interlocking relationships and pin correspondences) established in step S12 are integrated and spliced ​​with the internal signal flow node models constructed for each board in step S13. By associating the endpoints of the intra-board node models with the corresponding pins of the inter-board interconnection relationships, the signal paths that were originally limited to the inside of a single board can be extended and connected to other interconnected boards, thereby forming a continuous signal channel spanning multiple hardware components.

[0060] S15: Collect and summarize electrical parameter information during the signal flow process along the signal flow channel topology, and check the server design scheme based on the electrical parameter information and the server architecture design rules.

[0061] Among them, electrical parameter information refers to various electrical characteristic data on the signal path, and architecture design rules are predefined electrical and logic design specifications.

[0062] In this step, the pre-constructed complete signal flow channel topology is traversed, and various electrical information involved in the signal flow throughout the entire path is automatically extracted or derived. Simultaneously, a pre-built architecture design rule base is accessed, and the acquired electrical parameters are automatically compared and analyzed with relevant rules, achieving a systematic and automated check on the implementation of the design scheme.

[0063] As a feasible implementation method, collecting and summarizing electrical parameter information during the signal flow process along the signal flow channel topology includes: collecting device configuration parameters along the signal flow path along the signal flow channel topology; wherein the device configuration parameters include any one or a combination of pull-up resistor parameters, pull-down resistor parameters, series resistor parameters, capacitor parameters, and ferrite bead parameters; and / or, identifying and recording the location and isolation method of isolation devices along the signal flow path along the signal flow channel topology; and / or, extracting signal branch structure information along the signal flow channel topology; wherein the signal branch structure information includes any one or a combination of branch level, branch node position, and number of branch paths; and / or, summarizing and calculating electrical characteristic parameters along the signal flow path; wherein the electrical characteristic parameters include any one or a combination of signal internal resistance, effective operating voltage, and signal integrity related parameters.

[0064] Among these, device configuration parameters refer to the key attribute values ​​of passive or active devices that affect the electrical characteristics of the signal. Isolation device location and isolation method refer to the specific location and operating mode of the devices used to disconnect or control the signal path within the topology. Signal branch structure information describes the topological complexity of the signal path; the branch level refers to the maximum nesting depth of branches from the signal source to the current point; the branch node location is the specific device or network node at the fork of the signal path; and the number of branch paths refers to the total number of independent paths branching off from a single branch node. Electrical characteristic parameters are the macroscopic characteristics of the signal obtained through calculation or derivation; the signal internal resistance is the equivalent DC resistance of the signal path to ground; the effective operating voltage is the high or low level voltage value of the signal in steady state; and signal integrity-related parameters may include dynamic characteristics such as rise time, fall time, and overshoot.

[0065] In practical implementation, traversal and analysis are performed on the established complete signal flow channel topology. Depending on different inspection requirements, it can perform one or more of the following information collection and summarization tasks: collect the specific configuration parameters of various devices along the signal path; identify devices used for isolation purposes in the path and record their type and location; analyze the topology of the path and extract detailed information about branches; or calculate the overall electrical characteristics of the signal based on the device parameters and connection relationships on the path.

[0066] As can be seen, this implementation method, through multi-dimensional and selectable information collection, can meet the design inspection needs of different granularities and focuses. By associating and summarizing parameters scattered across multiple devices and boards according to signal paths, it provides an accurate and complete data foundation for subsequent electrical rule checks based on a system-level perspective.

[0067] As a feasible implementation method, the design scheme of the server is checked based on the electrical parameter information and the server's architecture design rules, including: generating a signal topology diagram based on the signal flow channel topology and the electrical parameter information; comparing the signal topology diagram with the server's architecture design rules to verify whether the settings of signal paths, branch structures, and isolation points meet the design requirements.

[0068] Among them, the signal topology diagram is a visual or structured design expression generated by fusing the topology of signal flow channels with key electrical parameter information.

[0069] In practice, the signal flow path topology and various electrical parameter information collected along this path are first used to generate a signal topology diagram containing rich electrical context. This diagram not only shows the signal connection paths but also labels the parameters of key components, branch information, and isolation point locations. Subsequently, the signal topology diagram is automatically compared and analyzed against a pre-built server architecture design rule base. The core of this comparison is to verify whether the design implementation reflected in the diagram—that is, the specific signal paths, the structural forms of any branches, and the setting methods of isolation points—conforms to the design requirements specified in the architecture rules.

[0070] As a feasible implementation method, special rule checks can also be performed for specific signal types, including: checking whether I2C (Inter-Integrated Circuit) signals have duplicate pull-up configurations in different boards of the system, and checking whether JTAG (Joint Test Action Group) signals have anti-static protection devices set at the terminal positions.

[0071] In practice, specific design rules for checking bus or interface signals were further introduced. For I2C signals, the entire server topology was checked to ensure that pull-up resistors were connected to the same voltage source at multiple locations (e.g., on the motherboard and expansion cards) throughout the server. If such duplicate pull-ups were found, they were identified as potential design issues and reported. For JTAG debug interface signals, dedicated electrostatic discharge (ESD) protection devices were checked for installation along the topology path, near the external connectors (terminals), in accordance with design specifications.

[0072] As can be seen, this implementation method can automatically perform global consistency verification and reliability design compliance verification across boards by pre-defining key design rules for typical signal types, thereby enhancing the targeted nature of design verification.

[0073] The signal flow information lookup method provided in this application automatically determines the terminal plug-in relationships and pin correspondences between boards by acquiring the netlist information of each board in the server, thereby achieving automated identification and modeling of cross-board signal channels within the system. Based on this, it further models the signal flow path within the board based on the netlist information of each board, establishing a signal flow node model, thus constructing a complete signal flow channel topology within the server. This signal flow channel topology comprehensively covers the entire link path of the signal from initiation, transmission to reception, making the signal flow process visible and structured. Based on the signal flow channel topology, electrical parameter information can be automatically collected and summarized along the signal path, and the design scheme can be automatically checked according to preset architecture design rules. Since the entire process is executed automatically by the system, the efficiency of signal lookup and checking is significantly improved, the design verification cycle is shortened, and the accuracy and reliability of the server electrical design are enhanced.

[0074] The following is a detailed scheme for step S13 above:

[0075] See Figure 2 A detailed flowchart of step S13 is shown according to an exemplary embodiment, as follows: Figure 2 As shown, it includes:

[0076] S131: Treat each board as a target board and search for the target device connected to the target signal in the netlist information of the target board.

[0077] The target board is a hardware circuit board in the server that needs to be analyzed. The target signal is a specific electrical network specified by the user or selected by the system for flow path analysis. The target devices are all electronic components that have a direct electrical connection with the target signal network.

[0078] In this step, a full data search is performed in the netlist information corresponding to the target board, based on the network name of the target signal. The netlist information records the pin-to-network relationships of all devices in a structured format. By matching network names, the system can identify all devices whose pins are connected to the target signal network and list these devices as target devices connected to that signal.

[0079] S132: Classify the target devices according to their device types to determine channel-type target devices, isolation-type target devices, and endpoint-type target devices;

[0080] The device classification is based on the functional role of the target device in the signal path. Channel devices allow signals to pass through with almost no obstruction or perform only passive processing, typically without changing the signal's on / off state. Isolation devices can switch on / off or isolate signal paths based on control signals, serving a switching or protective function. Terminal devices are the final source or load of the signal, where the signal path either ends or begins.

[0081] As a feasible implementation method, the target device is classified according to its device type to determine channel-type target devices, isolation-type target devices, and endpoint-type target devices. This includes: if the device type of the target device is a resistor, capacitor, ferrite bead, or a predefined isolation chip, then the target device is determined to be a channel-type target device; if the device type of the target device is a MOS transistor, then the target device is determined to be an isolation-type target device; if the target device is a signal endpoint and a flow channel cannot be established, then the target device is determined to be an endpoint-type target device.

[0082] In practice, a pre-defined classification rule is applied based on the type attributes of the target device as marked in the netlist. Specifically, if the device type is a resistor, capacitor, or ferrite bead, these passive components are mainly used for current limiting, filtering, or impedance matching, and signals can essentially flow through them; therefore, they are classified as channel devices. Some predefined dedicated isolation chips (such as digital isolators or analog switches) function to provide electrical isolation or signal routing, but are modeled as controllable channels internally, and are also classified in this category. If the device type is a MOSFET, its function is to control the conduction between the source and drain through the gate voltage to achieve switching control of the signal path; therefore, it is classified as an isolation device. If a device is the final termination of a signal, such as a processor input pin or clock generator output pin that is only connected to a signal line, and it does not have the attribute of establishing a signal flow through another pin, it is determined to be an endpoint device.

[0083] S133: Establish signal flow node models for channel-type and isolation-type target devices;

[0084] As a feasible implementation method, a signal flow node model is established for channel-type target devices and isolation-type target devices, including: if the device type of the target device is a resistor, capacitor, or ferrite bead, then the two pins of the target device are defined as two nodes for signal flow; if the device type of the target device is a MOSFET, then the corresponding pins are defined as signal flow nodes according to the grounding identifier contained in the pin names of the target device; if the device type of the target device is a predefined isolation chip, then multiple sets of signal channel nodes are defined according to the pin names of the target device that have the same prefix.

[0085] In practical implementation, different modeling strategies are adopted for different types of devices. For two-terminal channel devices such as resistors, capacitors, and ferrite beads, the model is very simple: the two physical pins of the device are abstracted as two nodes in the signal flow model, with the signal flowing in from one node and out from the other. For three-terminal (or more) isolated devices such as MOSFETs, modeling requires determining which two pins constitute the controlled main signal channel. The system achieves this by parsing the names of the MOSFET pins: if the pin name contains a network identifier indicating ground (GND), for example, the source pin named S is connected to the GND network, then the other two pins not directly grounded (such as the gate G and drain D) are defined as controlled nodes for signal flow. If the pin name does not contain a GND identifier, the signal flow nodes are defined according to typical naming conventions (e.g., source S and drain D). For predefined isolation chips (such as eight-channel analog switches), the modeling is more structured: multiple independent signal channel nodes are defined by identifying pin pairs with the same functional prefix in their pin names (e.g., IN1 and OUT1, IN2 and OUT2), each pair constituting a controllable signal channel.

[0086] S134: Starting from the signal origin, identify the signal path, branch nodes, and isolation points step by step;

[0087] In this context, the signal start point is typically a pin in an endpoint device that serves as the signal source (such as a clock output pin). Hierarchical identification refers to processing each device node along the path sequentially according to the possible directions of signal flow. A branch node is a location where the signal network connects more than two device pins, causing the signal flow to potentially propagate in multiple directions. An isolation point is a location on the signal path where the signal is controlled by an isolation device.

[0088] In this step, based on the signal flow node model, starting from the determined signal origin (a pin of a destination device), the network connected to the current node is analyzed. Other device nodes connected to this network are located, and the next-hop node is selected, such as a channel or isolation node in a non-return direction. A depth-first or breadth-first traversal is performed along this direction. During the traversal, if a network is encountered that connects three or more device nodes, this location is marked as a branch node, and the branch information is recorded. If an isolation device node is encountered, this location is marked as an isolation point, and the corresponding control logic is associated with it. This process continues until all reachable destination devices (signal endpoints) on the path have been visited.

[0089] As can be seen, this step has enabled the exploration and structured description of the specific flow path of the signal inside the board, clarifying the signal's direction, bifurcation, and control points.

[0090] S135: Calculates electrical parameters at each stage in real time during signal flow.

[0091] As a feasible implementation method, electrical parameters at each stage are calculated in real time during signal flow, including: identifying the status of power network, ground network and high-impedance network based on the device type and connection network through which the signal currently flows; calculating the signal internal resistance and operating voltage step by step along the signal flow direction; and calculating the electrical parameters of each branch path when there are branch nodes in the signal path, and summarizing the calculation results to the branch nodes.

[0092] In practical implementation, electrical calculations are performed synchronously while traversing the signal path. The calculations begin at the signal origin, which typically has an initial state, such as the high-level voltage VCC of a push-pull output. When the signal flows through a channel-type device, the cumulative internal resistance of the path is updated based on the device's parameters. The system also determines whether a new power or ground connection has been introduced based on the network connected to the device, thus updating the signal's voltage to ground or open-circuit state at that point. For example, if the signal is connected to a 3.3V power network via a pull-up resistor, the high-level voltage to ground after the resistor can be calculated or inferred to be close to 3.3V, and the equivalent resistance to ground from that point includes the pull-up resistor value. When encountering an isolation device, its control state determines whether the signal path is interrupted at that location. When encountering a branch node, the calculation process pauses, and the system independently performs the above recursive calculations along each branch path to obtain the electrical parameters at the end of each branch. Then, based on circuit principles, the parameters at these branch endpoints are equivalently backcalculated to the branch node to obtain unified equivalent parameters at the branch node, which can then be used to continue backcalculating to the previous level or as the comprehensive characteristics of that node.

[0093] As can be seen, this embodiment clarifies the specific roles of different devices in the signal flow by classifying the functions of connected devices and modeling nodes. Based on this, it achieves dynamic path-by-path calculation and branch aggregation of key parameters such as signal internal resistance and operating voltage. This allows design checks to go beyond mere connectivity checks, enabling a deeper evaluation of the signal's driving capability, level quality, and the impact of branch loads on the actual physical path, thereby improving the comprehensiveness of the design check.

[0094] The following describes an application embodiment provided by this application, such as... Figure 3 As shown, it includes the following steps:

[0095] Step 1: Automatic identification of inter-board connection relationships.

[0096] First, the netlist information for each board in the system is collected, which includes files containing device and pin connection information. For each terminal, a name-matching process is performed. If five or more identical networks exist between two terminals, they are considered interleaved. The relationships between the pins corresponding to all matching networks on both terminals are then checked. Terminal pins consist of both alphanumeric parts. First, a check for identical parts is performed. If the alphanumeric parts are the same, there is a one-to-one correspondence in one direction; otherwise, the terminals are symmetrical in one direction, and the alphanumeric parts are interchangeable. If the numeric parts are the same, there is a one-to-one correspondence; if they are different, the numeric parts of both pins are added together, and the sum is recorded. If they match, the sum is used as the basis for the numeric part correspondence. Based on the collected correspondences, a terminal pin correspondence table is established, applicable to all identical and different named networks between two terminals. This process is repeated to obtain the interleaving relationships of all terminals and internal pin interleaving relationships within the system, thereby establishing the channel information for cross-board signals within the system.

[0097] Step 2: Collect signal flow information within the board.

[0098] The signal flow information within each board includes pull-up resistors, pull-down resistors, series resistors, isolation methods, signal branch information, and a summary of electrical information about the signals based on the branch structure.

[0099] The netlist provided by the system only contains devices and the network information corresponding to their pins. First, a search is performed based on the required signal name to obtain the information of the connected devices. If there are more than one other device besides the device itself, branch information is marked, and the branch level based on the starting point is recorded. If the device is a resistor, capacitor, or ferrite bead, it is defined as a channel device. If the device type is MOSFET, it is marked as an isolation device. If it is a chip, it is defined in two categories: one is a predefined chip specifically for isolation, marked as a channel device; the other is a signal endpoint chip, marked as an endpoint. To collect signal flow information, signal flow node information is defined for channel devices and isolation devices respectively. Resistors, capacitors, and ferrite beads are 2-pin devices, with only two pins representing flow channels or nodes. For MOSFET devices, the definition is based on the device's pin name. If the device network name contains GND, the two pins labeled G and D are defined as channel flow nodes; if the device network does not contain GND, the two pins named S and D are defined as channel flow nodes. For channel-type chips, pin names containing two or more identical prefixes are defined as channel-type pins. If one channel pin name A is included in other channel names, it is a common channel. The channels of this chip are defined as multiple groups of channels formed by combining A with other channel-type chips. If there are no common channel pin names, and the number of pins containing the same prefix is ​​two, then these paired pins are defined as channel flow nodes of the chip. A chip may have one or more pairs, forming multiple groups of signal channels. If channels cannot be established for any type of device, it is identified as an endpoint device.

[0100] By defining the above-mentioned device-level signal flow nodes, a channel for signal flow within the board is established. During the flow, signals may branch, meaning a network may connect to two or more devices. Signal isolation interruption scenarios also exist. These nodes are identified and their data processed. Starting from the signal's origin, each device is identified by its level and branch number. The current power network is changed to GND, and unconnected networks are defined as high impedance. The signal's internal resistance is calculated, and the voltage value corresponding to the power network is marked as the signal voltage. This process is repeated for each additional level. If a branch is encountered, the branch node is marked, and the calculation is paused. Each branch starts from the branch point and continues until the endpoint device is reached. Then, the branch parameters are summarized back to the parameters before the branch, and so on, until finally summarized to the required signal.

[0101] Step 3: Collection and summarization of signal flow information within the system.

[0102] Through steps 1 and 2, channels for signal flow between boards and within boards are established, and by summarizing these channels, information on signal flow throughout the entire system is obtained.

[0103] As can be seen, this embodiment achieves automatic acquisition and processing of signal flow information applied to storage server systems. Through intelligent technical means, it automatically identifies the complex signal flow and interaction relationships between internal server boards and between various components within a single board, covering the entire information acquisition chain from signal initiation, transmission to reception. Compared with the traditional method of relying on manual point-by-point sorting, recording, and archiving, this solution can automatically collect all information on the signal flow process in the system, form a summary of topology-related information, and based on this, summarize electrical characteristics and perform electrical design rule checks, greatly improving the efficiency of checking the implementation status of the solution.

[0104] The following describes a signal flow information retrieval device provided in an embodiment of this application. The signal flow information retrieval device described below and the signal flow information retrieval method described above can be referred to each other.

[0105] See Figure 4 A structural diagram of a signal flow information retrieval device according to an exemplary embodiment is shown, such as... Figure 4 As shown, it includes:

[0106] The acquisition module 100 is used to acquire the netlist information of each board in the server; wherein, the netlist information of the board includes the devices contained in the board and the pin connection relationship of the devices;

[0107] The determination module 200 is used to determine the terminal mating relationship between each board and the pin correspondence between the mating terminals based on the netlist information of each board.

[0108] Modeling module 300 is used to model the signal flow path inside each board based on the netlist information of each board, so as to identify the devices through which the signal flows and establish the signal flow node model corresponding to each board.

[0109] The construction module 400 is used to construct the complete signal flow channel topology inside the server based on the terminal interlocking relationship between each board, the pin correspondence between the interlocking terminals, and the signal flow node model corresponding to each board.

[0110] The inspection module 500 is used to collect and summarize electrical parameter information during the signal flow process along the topology of the signal flow channel, and to inspect the design scheme of the server based on the electrical parameter information and the architecture design rules of the server.

[0111] The signal flow information lookup device provided in this application automatically determines the terminal plug-in relationships and pin correspondences between boards by acquiring the netlist information of each board in the server, thereby realizing the automated identification and modeling of cross-board signal channels within the system. Based on this, it further models the signal flow path within the board based on the netlist information of each board, establishing a signal flow node model, thus constructing a complete signal flow channel topology within the server. This signal flow channel topology comprehensively covers the entire link path of the signal from initiation, transmission to reception, making the signal flow process visible and structured. Based on the signal flow channel topology, electrical parameter information can be automatically collected and summarized along the signal path, and the design scheme can be automatically checked according to preset architecture design rules. Since the entire process is executed automatically by the system, the execution efficiency of signal lookup and checking is significantly improved, the design verification cycle is shortened, and the accuracy and reliability of the server electrical design are enhanced.

[0112] Based on the above embodiments, as a preferred implementation, the determining module 200 is specifically used to: extract the set of network names connected to each terminal from the netlist information of each board; if there is a preset number or more of the same network names between the first terminal and the second terminal, then determine that the first terminal and the second terminal are interlocked.

[0113] Based on the above embodiments, as a preferred implementation, the determining module 200 is specifically used to: if the letter part or the number part of the name of the first pin and the second pin is the same, then determine that the first pin and the second pin are in a one-to-one correspondence; if the letter part of the name of the third pin and the fourth pin conforms to a preset interchange relationship, then determine that the third pin and the fourth pin are in a cross-symmetrical correspondence; if the sum of the number part of the name of the fifth pin and the sixth pin is equal to a preset constant value, then determine that the fifth pin and the sixth pin are in a mirror correspondence.

[0114] Based on the above embodiments, as a preferred implementation, the modeling module 300 includes:

[0115] The retrieval unit is used to retrieve the target device connected to the target signal from the netlist information of the target board;

[0116] A classification unit is used to classify the target device according to its device type to determine target devices of the channel type, isolation type, and endpoint type.

[0117] A modeling unit is used to create signal flow node models for channel-type and isolation-type target devices.

[0118] The identification unit is used to identify the signal path, branch nodes, and isolation points step by step, starting from the signal origin.

[0119] The computing unit is used to calculate the electrical parameters at each stage in real time during signal flow.

[0120] Based on the above embodiments, as a preferred implementation, the classification unit is specifically used for: if the device type of the target device is a resistor, capacitor, ferrite bead, or a predefined isolation chip, then the target device is determined to be a channel-type target device; if the device type of the target device is a MOS transistor, then the target device is determined to be an isolation-type target device; if the target device is a signal endpoint and a flow channel cannot be established, then the target device is determined to be an endpoint-type target device.

[0121] Based on the above embodiments, as a preferred implementation, the establishment unit is specifically used for: if the target device is a resistor, capacitor, or ferrite bead, then defining the two pins of the target device as two nodes for signal flow; if the target device is a MOSFET, then defining the corresponding pin as a signal flow node according to the grounding identifier contained in the pin name of the target device; if the target device is a predefined isolation chip, then defining multiple sets of signal channel nodes according to the pin names of the target device that have the same prefix.

[0122] Based on the above embodiments, as a preferred implementation, the computing unit is specifically used to: identify the status of the power network, ground network, and high-impedance network based on the device type and connection network through which the signal currently flows; calculate the signal internal resistance and operating voltage step by step along the signal flow direction; when there are branch nodes in the signal path, calculate the electrical parameters of each branch path respectively, and summarize the calculation results to the branch node.

[0123] Based on the above embodiments, as a preferred implementation, the inspection module 500 is specifically used for: collecting device configuration parameters along the signal flow path topology; wherein the device configuration parameters include any one or a combination of pull-up resistor parameters, pull-down resistor parameters, series resistor parameters, capacitor parameters, and ferrite bead parameters; and / or, identifying and recording the location and isolation method of isolation devices along the signal flow path topology; and / or, extracting signal branch structure information along the signal flow path topology; wherein the signal branch structure information includes any one or a combination of branch level, branch node position, and number of branch paths; and / or, summarizing and calculating electrical characteristic parameters along the signal flow path; wherein the electrical characteristic parameters include any one or a combination of signal internal resistance, effective operating voltage, and signal integrity related parameters.

[0124] Based on the above embodiments, as a preferred implementation, the inspection module 500 is specifically used to: generate a signal topology diagram based on the signal flow channel topology and the electrical parameter information; and compare the signal topology diagram with the architecture design rules of the server to verify whether the settings of the signal path, branch structure and isolation point meet the design requirements.

[0125] Regarding the apparatus in the above embodiments, the specific manner in which each module performs its operation has been described in detail in the embodiments related to the method, and will not be elaborated upon here.

[0126] Embodiments of this application also provide an electronic device. Figure 5 This is a structural diagram of an electronic device according to an exemplary embodiment, such as... Figure 5 As shown, the electronic device includes:

[0127] Communication interface 1 enables information exchange with other devices, such as network devices;

[0128] Processor 2 is connected to communication interface 1 to enable information exchange with other devices. When running a computer program, it executes the signal flow information retrieval method provided by one or more of the above-mentioned technical solutions. The computer program is stored in memory 3.

[0129] Of course, in practical applications, the various components in an electronic device are coupled together through bus system 4. It can be understood that bus system 4 is used to achieve communication and connection between these components. In addition to the data bus, bus system 4 also includes a power bus, a control bus, and a status signal bus. However, for clarity, in... Figure 5 The general will label all buses as Bus System 4.

[0130] The memory 3 in this embodiment is used to store various types of data to support the operation of the electronic device. Examples of such data include any computer program used to operate on the electronic device.

[0131] It is understood that memory 3 can be volatile memory or non-volatile memory, or both. Non-volatile memory can be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), ferromagnetic random access memory (FRAM), flash memory, magnetic surface memory, optical disc, or compact disc read-only memory (CD-ROM); magnetic surface memory can be disk storage or magnetic tape storage. Volatile memory can be random access memory (RAM), which is used as an external cache. By way of example, but not limitation, many forms of RAM are available, such as Static Random Access Memory (SRAM), Synchronous Static Random Access Memory (SSRAM), Dynamic Random Access Memory (DRAM), Synchronous Dynamic Random Access Memory (SDRAM), Double Data Rate Synchronous Dynamic Random Access Memory (DDRSDRAM), Enhanced Synchronous Dynamic Random Access Memory (ESDRAM), SyncLink Dynamic Random Access Memory (SLDRAM), and Direct Rambus Random Access Memory (DRRAM).The memory 3 described in the embodiments of this application is intended to include, but is not limited to, these and any other suitable types of memory.

[0132] The methods disclosed in the embodiments of this application can be applied to processor 2, or implemented by processor 2. Processor 2 may be an integrated circuit chip with signal processing capabilities. In the implementation process, each step of the above method can be completed by the integrated logic circuit of the hardware in processor 2 or by instructions in the form of software. The processor 2 may be a general-purpose processor, DSP, or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. Processor 2 can implement or execute the methods, steps and logic block diagrams disclosed in the embodiments of this application. The general-purpose processor may be a microprocessor or any conventional processor, etc. The steps of the methods disclosed in the embodiments of this application can be directly manifested as being executed by a hardware decoding processor, or being executed by a combination of hardware and software modules in the decoding processor. The software modules may be located in a storage medium, which is located in memory 3. Processor 2 reads the program in memory 3 and completes the steps of the aforementioned method in combination with its hardware.

[0133] When processor 2 executes the program, it implements the corresponding processes in the various methods of the embodiments of this application. For the sake of brevity, these will not be described in detail here.

[0134] Embodiments of this application also provide a computer-readable storage medium storing a computer program, wherein the computer program is configured to execute the steps in any of the above-described signal flow information lookup method embodiments when it is run.

[0135] In one exemplary embodiment, the aforementioned computer-readable storage medium may include, but is not limited to, various media capable of storing computer programs, such as a USB flash drive, read-only memory (ROM), random access memory (RAM), portable hard disk, magnetic disk, or optical disk.

[0136] The embodiments of this application also provide a computer program product, which includes a computer program that, when executed by the processor 2, implements the steps in any of the above-described signal flow information search method embodiments.

[0137] Embodiments of this application also provide another computer program product, including a non-volatile computer-readable storage medium storing a computer program, which, when executed by processor 2, implements the steps in any of the above-described signal flow information retrieval method embodiments.

[0138] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0139] The foregoing has provided a detailed description of a signal flow information retrieval system, method, apparatus, device, medium, and product provided in this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are merely for the purpose of helping to understand the method and core ideas of this application. It should be noted that those skilled in the art can make various improvements and modifications to this application without departing from its principles, and these improvements and modifications also fall within the protection scope of this application.

Claims

1. A method for finding signal flow information, characterized in that, include: Obtain the netlist information of each board in the server; wherein, the netlist information of the board includes the devices contained in the board and the pin connection relationships of the devices; The terminal mating relationships between each board and the pin correspondence between the mating terminals are determined based on the netlist information of each board. Based on the netlist information of each board, the signal flow path inside each board is modeled to identify the devices through which the signal flows and to establish a signal flow node model corresponding to each board. Based on the terminal interlocking relationship between each board, the pin correspondence between the interlocking terminals, and the signal flow node model corresponding to each board, a complete signal flow channel topology inside the server is constructed. Electrical parameter information during the signal flow process is collected and summarized along the signal flow channel topology, and the server design scheme is checked based on the electrical parameter information and the server architecture design rules.

2. The signal flow information retrieval method according to claim 1, characterized in that, The terminal mating relationships between each board are determined based on the netlist information of each board, including: Extract the set of network names connected to each terminal from the netlist information of each board; If there is a preset number or more identical network names between the first terminal and the second terminal, then the first terminal and the second terminal are determined to be in a plug-in relationship.

3. The signal flow information retrieval method according to claim 1, characterized in that, The pin correspondence between the mating terminals is determined based on the netlist information of each board, including: If the letter part or the number part of the name of the first pin and the second pin are the same, then it is determined that the first pin and the second pin have a one-to-one correspondence. If the letter parts of the names of the third and fourth pins conform to a preset interchange relationship, then the third and fourth pins are determined to have a cross-symmetrical correspondence. If the sum of the numerical parts in the names of the fifth and sixth pins is equal to a preset constant value, then the fifth and sixth pins are determined to be mirror images of each other.

4. The signal flow information retrieval method according to claim 1, characterized in that, Based on the netlist information of each board, the signal flow path within each board is modeled to identify the devices through which the signal flows and to establish a signal flow node model corresponding to each board, including: Each board is designated as a target board, and the target device connected to the target signal is retrieved from the netlist information of the target board. The target devices are classified according to their device type to determine channel-type target devices, isolation-type target devices, and endpoint-type target devices. Establish signal flow node models for channel-type and isolation-type target devices; Starting from the signal origin, the signal path, branch nodes, and isolation points are identified level by level; The electrical parameters at each stage are calculated in real time during the signal flow process.

5. The signal flow information retrieval method according to claim 4, characterized in that, The target devices are classified according to their device type to determine channel-type target devices, isolation-type target devices, and endpoint-type target devices, including: If the target device is a resistor, capacitor, ferrite bead, or a predefined isolation chip, then the target device is determined to be a channel-type target device. If the target device is a MOS transistor, then the target device is determined to be an isolated target device; If the target device is a signal endpoint and a flow channel cannot be established, then the target device is determined to be an endpoint-type target device.

6. The signal flow information retrieval method according to claim 5, characterized in that, Establish signal flow node models for channel-type and isolation-type target devices, including: If the target device is a resistor, capacitor, or ferrite bead, then the two pins of the target device are defined as two nodes for signal flow. If the target device is a MOSFET, then the corresponding pin is defined as a signal flow node based on the grounding identifier contained in the pin name of the target device. If the target device is a predefined isolation chip, then multiple sets of signal channel nodes are defined based on the pin names with the same prefix contained in the target device.

7. The signal flow information retrieval method according to claim 4, characterized in that, The electrical parameters at each stage are calculated in real time during signal flow, including: Based on the device type and connection network through which the signal is currently flowing, identify the status of the power network, ground network, and high-impedance network; Calculate the signal internal resistance and operating voltage step by step along the signal flow direction; When there are branch nodes in the signal path, the electrical parameters of each branch path are calculated separately, and the calculation results are summarized to the branch node.

8. The signal flow information retrieval method according to claim 1, characterized in that, Electrical parameter information during signal flow is collected and summarized along the signal flow channel topology, including: The device configuration parameters along the signal flow path are collected; wherein, the device configuration parameters include any one or a combination of pull-up resistor parameters, pull-down resistor parameters, series resistor parameters, capacitor parameters, and ferrite bead parameters. And / or, identify and record the location and isolation method of the isolation device in the signal flow path along the topology of the signal flow channel; And / or, extract signal branch structure information along the topology of the signal flow channel; wherein, the signal branch structure information includes any one or a combination of any of the following: branch level, branch node position, and number of branch paths; And / or, summarize and calculate the electrical characteristic parameters of the signal flow path; wherein, the electrical characteristic parameters include any one or a combination of any of the following: signal internal resistance, effective operating voltage, and signal integrity related parameters.

9. The signal flow information retrieval method according to claim 1, characterized in that, The server design scheme is checked based on the electrical parameter information and the server architecture design rules, including: A signal topology diagram is generated based on the signal flow channel topology and the electrical parameter information; The signal topology diagram is compared with the server's architecture design rules to verify whether the signal path, branch structure, and isolation point settings meet the design requirements.

10. An electronic device, characterized in that, include: Memory, used to store computer programs; A processor for executing the computer program to implement the steps of the signal flow information lookup method as described in any one of claims 1 to 9.

Images