Verification device for chip composition module without register

Abstract

The invention relates to the technical field of chip verification, in particular to a verification device for a chip composition module without a register, and the verification device comprises a sequence configuration module which is used for generating a configuration sequence based on a read-write operation interface of a register model and a configuration demand of a to-be-tested chip composition module; the register model is used for initiating a register access request to the adapter based on the configuration sequence; the adapter is used for converting the register access request into a signal control sequence container control request and sending the signal control sequence container control request to the signal control sequence container; the signal control sequence container is used for converting a control sequence container control request into an excitation sequence and sending the excitation sequence to the corresponding signal control verification assembly; and the signal control verification assembly is used for converting the received excitation sequence into a driving signal and sending the driving signal to the to-be-tested chip composition module through a corresponding control signal line. According to the invention, the chip verification efficiency and accuracy are improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the chip verification technical field, and particularly relates to a verification device of a chip component module without a register. BACKGROUND

[0002] In chip verification, especially in chip subsystem level verification, it is usually necessary to further subdivide the subsystem into multiple chip component modules for verification according to the functions and complexity of the chip component modules. Some chip component modules do not have a register chip component module reserved therein due to the function architecture, but directly use the register control signals provided by other chip component modules for control. The chip component module does not have an interface for accessing the register, but only has various control signals, so the register model cannot be directly used, and the chip component module level configuration and verification are performed by directly forcing the control signals in the environment. However, this method cannot be reused as a configuration sequence by the upper chip component module, so it is necessary to write a subsystem level register configuration sequence according to the programming guide or the force control on the chip component module verification environment in the subsystem verification process. Therefore, the existing verification method for the chip component module without a register cannot be vertically reused, resulting in low chip verification efficiency. In addition, the existing technology is prone to errors and omissions in the verification implementation process of the chip component module without a register, resulting in poor chip verification accuracy. SUMMARY

[0003] The present application aims to provide a verification device of a chip component module without a register, which improves the chip verification efficiency and accuracy.

[0004] The present application provides a verification device of a chip component module without a register, comprising a sequence configuration module, a register model, an adapter, a signal control sequence container, M signal control verification components, and a chip component module to be tested, wherein M is greater than or equal to 1, and wherein The sequence configuration module is configured to generate a configuration sequence based on the read-write operation interface of the register model and the configuration requirements of the chip component module to be tested, and send the configuration sequence to the register model. The chip component module to be tested is a chip component module without a register in a chip design to be tested, and the register model is generated based on a register description file corresponding to the chip design to be tested; The register model is configured to initiate a register access request to the adapter based on the configuration sequence; The adapter is configured to convert the register access request into a signal control sequence container control request and send the signal control sequence container control request to the signal control sequence container; The signal control sequence container is used for converting the control sequence container control request into an excitation sequence and sending the excitation sequence to the corresponding signal control verification component. The signal control verification component is used for converting the received excitation sequence into a driving signal and sending the driving signal to the to-be-tested chip component module through a corresponding control signal line.

[0005] Compared with the prior art, the application has obvious advantages and beneficial effects. The verification device for the chip component module without a register provided by the application can achieve considerable technical progress and practicability, and has wide industrial utilization value, and at least has the following beneficial effects: The verification device for the chip component module without a register provided by the application can achieve considerable technical progress and practicability, and has wide industrial utilization value, and at least has the following beneficial effects: BRIEF DESCRIPTION OF DRAWINGS

[0006] In order to more clearly illustrate the technical solutions in the embodiments of the application, the following will briefly introduce the drawings needed to be used in the embodiment description. Obviously, the drawings in the following description are only some embodiments of the application, and other drawings can be obtained by those skilled in the art without creative effort on the basis of these drawings.

[0007] Figure 1 The verification device for the chip component module without a register provided by the application is shown in the schematic diagram. Figure 2 The to-be-tested chip design architecture provided by the embodiment of the application is shown in the schematic diagram. DETAILED DESCRIPTION

[0008] The technical solutions in the embodiments of the application will be described clearly and completely with reference to the drawings of the embodiments of the application. Obviously, the described embodiments are only some of the embodiments of the application, not all the embodiments. Based on the embodiments of the application, all other embodiments obtained by those skilled in the art without creative effort fall within the protection scope of the application.

[0009] The verification device for the chip component module without a register provided by the embodiment of the application is shown in the schematic diagram. Figure 1As shown, it comprises: a sequence configuration module, a register model, an adapter, a signal control sequence container, M signal control verification components (UVC), a to-be-tested chip component module, M≥1, and it should be noted that, Figure 1 In the example shown, M is 2, and in actual applications, the value of M can be adjusted according to specific application requirements.

[0010] The sequence configuration module is configured to generate a configuration sequence based on the read-write operation interface of the register model and the configuration requirements of the to-be-tested chip component module, and send it to the register model. The to-be-tested chip component module is a chip component module that is not provided with a register in the to-be-tested chip design. It should be understood that the to-be-tested chip design also includes a chip component module provided with a register, and the to-be-tested chip design can be a chip subsystem, for example. Figure 2 In the example shown, the to-be-tested chip design (shown as the system top layer in the figure) includes three chip component modules, including a chip component module not provided with a register and a chip component module provided with a register. The chip component modules are module 1, module 2, and module 3, wherein module 1 and module 2 are not provided with a register control bus interface, and the related control signals of module 1 and module 2 are derived from module 3, and module 3 contains a register control bus interface. Module 3 includes four registers, namely register 1, register 2, register 3, and register 4. Register 1 and register 2 are used to control module 1, and the related control signals will be derived from module 3 and connected to module 1. Register 3 is used to control module 2, and the related control signals will be derived from module 3 and connected to module 2. Module 3 also has register 4 for internal use, which does not have control signals that need to be connected to the outside of module 3.

[0011] It should be noted that the chip component module provided with a register can continue to be implemented based on the register model for verification. The chip component module not provided with a register, i.e., the to-be-tested chip component module described in the embodiment of the application, can be verified based on the verification device of the chip component module not provided with a register in the embodiment of the application, and can also be verified based on the register model, without the need to set a forced driving control signal for the to-be-tested chip component module in the verification environment one by one to implement verification. For a higher level to-be-tested chip design, all component modules of the to-be-tested chip design can be verified based on the register model, and therefore, the verification information of all component modules of the to-be-tested chip design can be directly reused in the to-be-tested chip design verification process.

[0012] The register model is generated based on a register description file corresponding to the chip design under test. The register description file corresponding to the chip design under test can specifically include a mapping relationship between a register identifier and a register address, register attribute information, a register domain contained in each register, and attribute information of each register domain, and the like. It should be noted that the existing register model generation method based on the register description file falls within the protection scope of the present application, and will not be described here again. The configuration sequence is not sensitive to the composition of the underlying verification platform, and the operation interface called by the configuration sequence conforms to the definition of the general verification methodology, so the configuration sequence can be reused between different verification platforms.

[0013] The register model is used to initiate a register access request to the adapter based on the configuration sequence, and is also used to provide general operations such as read-write operation interfaces. The register model is implemented as a general processing method defined by the verification methodology, and is applicable to reuse between different verification platforms. The adapter is used to convert the register access request into a signal control sequence container control request and send it to the signal control sequence container. The signal control sequence container is used to convert the control sequence container control request into an excitation sequence and send it to the corresponding signal control verification component. The signal control sequence container can replace the direct control of the control signal driving in the prior art, realize the interaction interface between the signal control sequence and the register model, and enable users to operate the signal control verification component by operating the register model. The signal control verification component is used to convert the received excitation sequence into a driving signal and send it to the chip component module through a corresponding control signal line.

[0014] As an embodiment, the signal control sequence container includes an adapter interaction interface, an address signal mapping table, a container component, and M excitation sequence generation units. Each excitation sequence generation unit corresponds to a signal control verification component. Each signal control verification component is connected to the chip component module through a corresponding control signal line.

[0015] The adapter interaction interface is used to obtain the control sequence container control request from the adapter and send it to the container component. The control sequence container control request includes a register address and a corresponding target value. The register address can be specifically an address corresponding to a register, or an address corresponding to a register domain in a register, which is set according to specific application requirements.

[0016] The address signal mapping table is generated based on a register description file corresponding to the chip design under test. The address signal mapping table stores a mapping relationship between a control signal line identifier and a register address.

[0017] The container component is used to find the address signal mapping table based on the register address in the control sequence container control request, obtain the corresponding target control signal line identifier, determine the target excitation sequence generation unit and the target signal control verification component based on the target control signal line identifier, and send the target value to the target excitation sequence generation unit.

[0018] The excitation sequence generation unit is used to generate an excitation sequence based on the received target value.

[0019] It should be noted that, in general, the register identifier corresponding to the control signal line is corresponding to the identifier of the control signal line, which can specifically include the same field, and therefore, the address signal mapping table can be directly established based on the corresponding register description file of the chip under test design. However, in some application scenarios, the content of the corresponding field in the register description file may be changed, resulting in inconsistency between the control signal line identifier in the register description file and the actual control signal line identifier. At this time, the mapping relationship needs to be changed during the generation of the address signal mapping table to ensure the establishment of the correct mapping relationship. As an embodiment, if the control signal line identifier in the register description file corresponding to the chip under test design is inconsistent with the actual control signal line identifier during the generation of the address signal mapping table based on the register description file corresponding to the chip under test design, the mapping relationship between the control signal line identifier and the register address is established using the actual control signal line identifier during the generation of the address signal mapping table.

[0020] As an embodiment, the adapter interaction interface is used to indirectly call the reg2bus and bus2reg protocol conversion functions in the register model during the read and write operations through the register model, and provides a transaction level modeling (TLM) interface for the adapter to call, to obtain a control sequence container control request converted based on the register access request. The control sequence container control request can be a standard data structure uvm_reg_bus_op encapsulating register bus operation information.

[0021] As an embodiment, the excitation sequence generated by the excitation sequence generation unit is set to a passive sequence, and the excitation sequence generation unit is further used to determine whether there is a call from the register model according to each clock cycle of the clock domain to which the control signal of the corresponding control signal line belongs, and if so, drive the signal control to output or obtain the corresponding drive value. It can be understood that if the control sequence container control request is a write request, the drive signal controls the corresponding signal control verification component to output the corresponding drive value, and if the control sequence container control request is a read request, the drive signal controls the corresponding signal control verification component to obtain the corresponding drive value.

[0022] As one embodiment, the configuration sequence includes a configuration sequence generated based on the verification of any chip component module in the chip under test (DUT) design and the verification of the DUT itself. The configuration sequence is arranged in chronological order of configuration information. Each configuration information includes the configuration information of all registers in the DUT design, and each DUT component module corresponds to at least one register. It should be noted that the configuration sequence can correspond to any component module in the DUT design and the DUT design itself; that is, it can be reused by any component module in the DUT design and the DUT design itself. During the verification of a DUT component module, only the configuration information of the registers corresponding to the DUT component module itself in the configuration sequence can be obtained; the configuration information of other chip component modules is not visible. During the verification of the DUT itself, all configuration information in the configuration sequence is visible. Figure 2 Taking the chip under test (DUT) design structure shown as an example, each configuration information includes configuration information corresponding to register 1, register 2, register 3, and register 4. However, during the verification of module 1, only the configuration information corresponding to register 1 and register 2 in the configuration sequence is effective for verifying module 1; the configuration information corresponding to register 3 and register 4 is not visible to module 1. During the verification of the DUT design, all configuration information in the configuration sequence is visible to the DUT design.

[0023] As one embodiment, the sequence configuration module is specifically used to set execution statements for the register model based on the read / write operation interface of the register model and the configuration requirements of the chip components, and to generate a configuration sequence. The specific implementation can be achieved using the following code statements: class init_sequence ral_model.reg_1.write(status, data); ral_model.reg_2.write(status, data); endclass The above configuration method can be easily reused in higher-level verification environments, and the specific control of the signal lines is completed by the signal control sequence container. Other operations, such as clock (clk) adjustment, reset and other special scenario operation control, can be implemented through the functions of the signal control verification component itself.

[0024] Still with Figure 2 For example, when a separate verification environment needs to be set up for module 1, it is necessary to... Figure 1The system architecture shown is modeled as an example: First, the register description file of the chip under test (DUT) design is obtained. This file includes all characteristic information reflecting all registers in the system (i.e., register 1, register 2, register 3, and register 4). A relevant script or program reads the register description file of the DUT design and generates matching functional components based on user input. These functional components include, but are not limited to, control signal connection binding files, signal control verification components, register models (RAL), signal control sequence containers, and adapters. When the DUT is module 1, it will generate corresponding binding files for control signal 1 (register 1) and control signal 2 (register 2), signal control verification component 1 (register 1), signal control verification component 2 (register 2), a signal control sequence container, a register model, and an adapter for connecting the signal control sequence container. In contrast, when the chip under test (DUT) is module 2, it generates a bind file for the control signal 3 corresponding to register 3, a signal control verification component 3, a signal control sequence container, a register model, and an adapter for connecting the signal control sequence container. As another embodiment, when the DUT is module 3, since register 4 exists internally, it generates a bind file for register 4 access, a register interface control verification component, a register model, and an adapter for connecting the register interface. The register models generated for all modules in the DUT design are identical, thus the relevant configurations can be easily integrated into the DUT design environment.

[0025] After acquiring the corresponding components, they are integrated into the verification system of the relevant modules. The control signal connection includes the hierarchical information and name of the signal to be controlled, indicating which signal the relevant signal control verification component needs to connect to. The connection method may be one of various methods provided by SystemVerilog, such as bind, assign, force, etc. The signal control verification component will be adjusted according to the description file of the corresponding register. For example, if the relevant control signal is controlled by 2 bits of a register, the interface width of the corresponding signal control verification component will also be adjusted to 2 bits. The signal control sequence container will generate different control sequences depending on the component module of the chip under test. For example, when the component module of the chip under test is module 1, since only control signal 1 exists, the control sequence generated in the signal control sequence container will only contain the control sequence corresponding to signal control verification component 1. The address signal mapping table within the signal control sequence container will also be adjusted according to the component module of the chip under test. For example, when module 1 is selected, the mapping table will only generate a mapping between registers and control signal 1.

[0026] After all environment components are integrated, the components of the chip under test (DUT) can be configured using a register model. Since the configuration sequences are unaware of the underlying implementation details and the DUT design uses a completely unified register model, the configuration sequence for the entire DUT design can be managed in a unified manner and used by the verification environments of each component module. The configuration of each component module in the DUT design is updated to a unified subsystem configuration sequence, which generates configuration sequences for each component module and also generates the configuration sequence for the entire DUT design. Compared to traditional verification methods, which may require at least two updates to the configuration sequences of the component modules and the DUT design, and where the number of component modules increases, leading to increased maintenance costs, the unified register model in this embodiment only requires updating and maintaining a single configuration sequence. Furthermore, regardless of whether a component module itself has registers, the register model can be used for configuration.

[0027] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the present invention. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of the present invention without departing from the scope of the present invention shall still fall within the scope of the present invention.

Claims

1. A verification device for a chip component module without registers. Its features are, It includes: a sequence configuration module, a register model, an adapter, a signal control sequence container, M signal control verification components, and a chip under test module, where M ≥ 1. The sequence configuration module is used to generate a configuration sequence based on the read and write operation interface of the register model and the configuration requirements of the chip under test (TB) component modules, and send it to the register model. The TB component modules are chip component modules that do not have registers set in the TB chip design. The register model is generated based on the register description file corresponding to the TB chip design. The register model is used to initiate a register access request to the adapter based on the configuration sequence; The adapter is used to convert the register access request into a signal control sequence container control request and send it to the signal control sequence container; The signal control sequence container is used to convert the control sequence container control request into an excitation sequence and send it to the corresponding signal control verification component; The signal control verification component is used to convert the received excitation sequence into a driving signal and send it to the chip under test module through the corresponding control signal line.

2. The apparatus according to claim 1, characterized in that, The signal control sequence container includes an adapter interaction interface, an address signal mapping table, a container component, and M excitation sequence generation units. Each excitation sequence generation unit corresponds to a signal control verification component, and each signal control verification component is connected to the chip under test module via a corresponding control signal line. The adapter interaction interface is used to obtain a control sequence container control request from the adapter and send it to the container component. The control sequence container control request includes a register address and a corresponding target value. The address signal mapping table is generated based on the register description file corresponding to the chip under test design, and the address signal mapping table stores the mapping relationship between control signal line identifiers and register addresses; The container component is used to look up the address signal mapping table based on the register address in the control sequence container control request, obtain the corresponding target control signal line identifier, determine the target excitation sequence generation unit and the target signal control verification component based on the target control signal line identifier, and send the target value to the target excitation sequence generation unit; The excitation sequence generation unit is used to generate an excitation sequence based on the received target value.

3. The apparatus according to claim 2, characterized in that, During the process of generating the address signal mapping table based on the register description file corresponding to the chip under test design, if the control signal line identifier in the register description file corresponding to the chip under test design is inconsistent with the actual control signal line identifier, then during the generation of the address signal mapping table, the actual control signal line identifier is used to establish the mapping relationship between the control signal line identifier and the register address.

4. The apparatus according to claim 2, characterized in that, The adapter interaction interface is used to indirectly call the reg2bus and bus2reg protocol conversion functions in the register model during read and write operations through the register model, and provides a transaction-level modeling interface for the adapter to call to obtain the control sequence container control request generated based on the register access request conversion.

5. The apparatus according to claim 2, characterized in that, The excitation sequence generated by the excitation sequence generation unit is set as a passive sequence. The excitation sequence generation unit is also used to determine whether there is a call from the register model according to each clock cycle of the clock domain to which the control signal of the corresponding control signal line belongs. If there is, the drive signal controls the corresponding signal control verification component to output or obtain the corresponding drive value.

6. The apparatus according to claim 1, characterized in that, The configuration sequence includes a configuration sequence generated based on the verification of any chip component module in the chip under test design and the verification of the chip under test. The chip component module includes a chip component module without registers and a chip component module with registers. The configuration sequence is arranged in the order of configuration information. Each configuration information includes the configuration information of all registers in the chip under test design. Each chip component module corresponds to at least one register. During the verification process of the chip under test components, only the configuration information of the registers corresponding to the chip under test components in the configuration sequence can be obtained, and the configuration information of other chip components is not visible; During the verification process of the chip under test, all configuration information in the configuration sequence is visible.

7. The apparatus according to claim 1, characterized in that, The sequence configuration module is specifically used to set the execution statements for the register model based on the read and write operation interface of the register model and the configuration requirements of the chip components, and to generate the configuration sequence.

8. The apparatus according to claim 1, characterized in that, The register description file corresponding to the chip under test design includes the mapping relationship between register identifiers and register addresses, register attribute information, register fields contained in each register, and attribute information of each register field.

9. The apparatus according to claim 1, characterized in that, The chip under test is designed as a chip subsystem.

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