Method for estimating dispatching time of semiconductor machine

Abstract

The invention provides a method for estimating dispatching time of a semiconductor machine, which is characterized by comprising the following steps of: firstly, providing a semiconductor machine which comprises a plurality of cavities, then providing a plurality of batches of (Lot) wafer groups, each batch of wafer groups comprising a plurality of wafers, and then sending the plurality of batches of wafer groups to the semiconductor machine for a plurality of manufacture procedures, and according to the process conditions of the plurality of batches of wafer groups in the semiconductor machine, a simulation process flow chart is formulated by a system, and a dispatch time is calculated according to the simulation process flow chart, and the simulation process flow chart formulated by the system is obtained based on a constraint programming (CP) algorithm.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing processes, and more particularly to a method for estimating the dispatch time of semiconductor equipment, which can improve the utilization efficiency of equipment and reduce the total process time. Background Technology

[0002] The manufacturing process of semiconductor wafers is quite complex, involving multiple precision steps. Each wafer undergoes multiple processes, each performed on a different specialized machine. Each process corresponds to a different machine, some even having multiple cavities. Only after one batch of wafers has completed its processing on the semiconductor machine can the next batch be sent to the same machine for further processing. This process of sending a batch of wafers to the semiconductor machine is called the dispatching step, and the earliest point in time when a batch of semiconductor wafers is allowed to be sent to the machine is called the dispatching time. Therefore, accurately predicting the dispatching time of the next batch of wafers helps reduce the gap between processes and improves process efficiency.

[0003] However, there are many uncertainties in the semiconductor manufacturing process, the most common of which is process error. These errors can stem from various reasons such as machine malfunctions, material defects, and environmental changes, causing delays in the process of certain machines. Once a delay occurs, the originally calculated dispatch time for the next batch of wafers will be disrupted, affecting the operational efficiency of the entire production line. At this time, the manufacturer must react quickly, recalculate the dispatch time for the next batch of wafers, and restore the production line to normal operation as soon as possible.

[0004] However, recalculating the dispatch time for the next batch of wafers is no easy task. The complexity of this task stems from the fact that it involves multiple interrelated factors, including machine process time, which machine is delayed, the number of wafers, and wafer process requirements. These factors interact with each other, making the recalculation of the dispatch time for the next batch of wafers an extremely challenging task. Summary of the Invention

[0005] To address the above problems, this invention provides a method for estimating the dispatch time of a semiconductor equipment, characterized by comprising providing a semiconductor equipment including multiple cavities, providing multiple batches of wafers, each batch of wafers including multiple wafers, sending the multiple batches of wafers to the semiconductor equipment for multiple processes, and, based on the process status of the multiple batches of wafers in the semiconductor equipment, having a system formulate a simulated process flow chart, and calculating a dispatch time based on the simulated process flow chart, wherein the simulated process flow chart formulated by the system is obtained based on a constraint programming (CP) algorithm.

[0006] This invention provides a more accurate and automated wafer dispatching planning method. In known procedures, wafer dispatching time (i.e., the earliest time when the next batch of wafers can be dispatched to the machine) is typically calculated based on data stored in a past process database. However, calculating dispatching time using past data is not accurate enough and cannot reflect the process status in a timely manner for adjustments. The feature of this invention is that when each batch of wafers enters the preparation area of ​​the semiconductor machine, various constraints are input into the system, such as the number of wafers, the processes required for each wafer, and the time spent on processing in each cavity. These constraints are input into the system, and an optimal solution is obtained through a constraint programming (CP) algorithm and a solver. The optimal solution is output, along with the production time sequence of each wafer and a graphical simulation of the process flow, to accurately calculate the process completion time of all wafers in this batch at the semiconductor machine, facilitating the dispatching of the next batch of wafers to the semiconductor machine. This invention can further refine the process time calculation from the original batch of wafers to the individual wafers within each batch. Simultaneously, this invention replaces manual calculation with system-based calculation to handle large amounts of complex data, which is more conducive to automated production. Furthermore, when certain machines experience delays for various reasons, the system can react in real time and quickly re-establish a new production time sequence and graphical simulation of the process flow, effectively improving production efficiency. Attached Figure Description

[0007] To facilitate understanding, reference should be made to the accompanying drawings and detailed descriptions while reading this invention. Specific embodiments of the invention are explained in detail through reference to the corresponding drawings, which illustrate the working principles of these embodiments. Furthermore, for clarity, features in the drawings may not be drawn to scale, and the dimensions of some features in certain drawings may be intentionally enlarged or reduced.

[0008] Figure 1 A schematic diagram of a semiconductor machine with multiple cavities is shown.

[0009] Figure 2 A flowchart illustrating the semiconductor steps in one embodiment is shown.

[0010] Figure 3 A flowchart illustrating the wafer dispatching sequence according to another embodiment of the present invention is shown.

[0011] Figure 4 Example of drawing two constraint tables.

[0012] Figure 5An example of a simulated manufacturing process flow diagram is shown.

[0013] Figure 6 A schematic diagram illustrating a simulated process flow chart applicable to continuous processes on multiple semiconductor equipment is shown.

[0014] [Explanation of Key Component Symbols]

[0015] 1: Semiconductor equipment

[0016] 2A: Cavity

[0017] 2B: Cavity

[0018] 2C: Cavity

[0019] 2D: Cavity

[0020] 3: Preparation Area

[0021] L1: Wafer Group

[0022] L2: Wafer Group

[0023] L3: Wafer Group

[0024] L4: Wafer Group

[0025] L5: Wafer Group

[0026] L6: Wafer Group

[0027] QT: Buffer Time

[0028] S1: Steps

[0029] S2: Steps

[0030] S3: Steps

[0031] S3-1: Steps

[0032] S4: Steps

[0033] S5: Steps

[0034] W: Wafer

[0035] W1, W2, W3, W4, W5, W6, W7, W8, W9: Wafers Detailed Implementation

[0036] To enable those skilled in the art to further understand the present invention, preferred embodiments of the present invention are described below, and the composition and desired effects of the present invention are explained in detail with reference to the accompanying drawings.

[0037] For ease of explanation, the accompanying drawings are merely illustrative to facilitate understanding of the invention, and their detailed proportions can be adjusted according to design requirements. The vertical relationships of relative elements in the drawings described herein should be understood by those skilled in the art to refer to the relative positions of objects; therefore, all can be flipped to present the same components, and this should all fall within the scope of this specification, as stated herein.

[0038] Although the present invention uses terms such as first, second, third, etc., to describe elements, components, regions, layers, and / or sections, it should be understood that these elements, components, regions, layers, and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, and / or section from another, and do not in themselves imply or represent any prior ordinal number of the element, nor do they represent the arrangement order of one element with another, or the order of manufacturing processes. Therefore, without departing from the scope of the specific embodiments of the present invention, the first element, component, region, layer, or section discussed below may also be referred to as a second element, component, region, layer, or section.

[0039] The terms "about" or "substantially" as used in this invention generally mean within 20% of a given value or range, for example, within 10%, or within 5%, or within 3%, or within 2%, or within 1%, or within 0.5%. It should be noted that the quantities provided in the specification are approximate quantities; that is, the meaning of "about" or "substantially" may be implied even without specific mention of it.

[0040] The terms "coupled," "coupled," and "electrically connected" as used in this invention include any direct or indirect means of electrical connection. For example, if the text describes a first component coupled to a second component, it means that the first component can be directly electrically connected to the second component, or indirectly electrically connected to the second component through other means or connections.

[0041] Although the invention is described below with reference to specific embodiments, the inventive principles of the invention can also be applied to other embodiments. Furthermore, to avoid obscuring the spirit of the invention, certain details have been omitted; these omitted details are within the scope of knowledge of those skilled in the art.

[0042] Please note that in this invention specification, "dispatch" refers to the process or time point at which a batch of semiconductor chips can be allocated to a semiconductor machine, that is, the process of wafer movement outside the semiconductor machine. "Production" and "process," on the other hand, refer to the process of wafer movement within the preparation area and cavity of the semiconductor machine, or a general term for various manufacturing steps, that is, the process of wafer movement inside the semiconductor machine. For ease of understanding, the difference between the two will be explained here first.

[0043] Please refer to Figure 1 , Figure 1 A schematic diagram of a semiconductor machine with multiple cavities is shown. Figure 1 As shown, a semiconductor equipment 1 includes a preparatory area 3 connected to multiple cavities, which are defined herein as cavities 2A, 2B, 2C, and 2D. When a wafer W is delivered to the preparatory area 3, it can be delivered to different cavities according to the process sequence. The same or different processes can be performed in each cavity 2A, 2B, 2C, and 2D; for example, sputtering, deposition, and etching steps are all possible, and the invention is not limited thereto. Furthermore, depending on the semiconductor equipment, the semiconductor equipment 1 may contain more or fewer cavities. However, preferably, the present invention relates to a method for dispatch planning applicable to semiconductor equipment containing multiple cavities. In the following paragraphs, ... Figure 1 The semiconductor machine 1 with four cavities shown is illustrated as an example.

[0044] Figure 2 A flowchart illustrating the semiconductor steps in one embodiment is shown. Figure 2 As shown, in one embodiment, step 1 illustrates that a batch (lot) of wafers L1 is being processed on a first semiconductor machine, where L1 represents a batch of wafers. Wafer group L1 contains multiple wafers processed on the first semiconductor machine. After step 1 is completed, wafer group L1 is sent to another semiconductor machine (i.e., a second semiconductor machine) for the next process; that is, all the wafers in this batch of wafer group L1 are sent together to the second semiconductor machine. It is worth noting that, as... Figure 2 As shown in step 2 in the middle, during the process of step 1, another batch of wafers L2 is also being processed on the second semiconductor machine. The user needs to estimate the time for wafers L2 to complete the process in the second semiconductor machine and set a buffer time QT. After the wafers L2 in the second semiconductor machine are completed, the process of wafers L1 will begin after the buffer time QT.

[0045] However, as Figure 2As shown in step 2 below, various errors or unforeseen circumstances can occur during semiconductor manufacturing, potentially causing equipment delays. For example, if a problem arises with the second semiconductor equipment, extending the process time of wafer group L2, it will also affect the start time of the process for wafer group L1 on the second semiconductor equipment. This can further impact the timing of subsequent processes, leading to a decrease in overall process efficiency.

[0046] In current technology, manufacturers calculate the approximate time it takes for a batch of wafers to complete the process in a semiconductor machine and plan the timing for the next batch of wafers to be dispatched to the semiconductor machine. This process is called dispatching. More specifically, manufacturers typically estimate the approximate time required for each process based on past process parameters, and then determine an appropriate buffer time (QT). This allows them to deliver the next batch of wafers to the semiconductor machine at the pre-planned time (i.e., dispatching time). Calculating dispatching time requires considering several factors, such as the number of cavities in the semiconductor machine, the number of wafers in each batch, and the specific processes required for each wafer. All of these factors affect the wafer dispatching time. The process becomes even more complex when there are many semiconductor process steps or when a multi-cavity semiconductor machine is used during the process.

[0047] However, as shown above, when unexpected situations occur in the semiconductor manufacturing process and cause delays in certain semiconductor equipment, the estimated process completion time of the semiconductor equipment is affected by multiple factors. Therefore, when such unexpected situations occur, it is difficult for manufacturers to manually recalculate new dispatch times in a short period of time. Usually, all dispatch times can only be postponed after the fault is resolved, but this is not conducive to process efficiency.

[0048] In view of this, the present invention proposes another method for more accurately calculating the estimated dispatch time. The main concept of this invention is to simulate the process sequence within a semiconductor equipment and, based on the simulation results, accurately calculate the completion time of a batch of wafers within the equipment, thus facilitating the scheduling of the next batch of wafers. The system of this invention can display a graphical simulation process flow chart. Furthermore, this invention uses a constraint programming (CP) algorithm and solver to calculate an optimal solution after inputting various constraints, and then converts this optimal solution into a graphical simulation process flow chart, thereby calculating the dispatch time. This invention can calculate the estimated process completion time for multiple wafers in each batch separately, without needing to calculate the estimated process time for the entire batch, thus enabling a more accurate prediction of the process sequence within the semiconductor equipment. In addition, it can monitor the process status in real time and update the simulation process flow chart continuously. More detailed descriptions will follow in the following paragraphs.

[0049] like Figure 3 As shown, Figure 3 A flowchart illustrating the wafer dispatch sequence according to another embodiment of the present invention is shown. First, as shown in step S1, a batch of wafers is sent to the preparation area of ​​a semiconductor machine. The wafers referred to here are, for example, the wafer group L1 containing a plurality of wafers W described above, and the semiconductor machine is, for example, a... Figure 1 The semiconductor equipment 1 shown has multiple cavities 2A to 2D. Wafer set L1 is fed to the preparation area 3 of the semiconductor equipment 1 (reference). Figure 1 After that, subsequent semiconductor equipment will sequentially send each wafer into the cavity for processing.

[0050] Next, as in step S2, constraints (such as process time, the cavities to be processed, etc.) are input into the system. More specifically, when wafer group L1 enters the preparation area 3 of semiconductor equipment 1, the manufacturer knows in advance the number of wafers W contained in wafer group L1, the type of process to be manufactured, which wafers need to be processed, and the time required for each process. All these variables can be input by the manufacturer into the system (e.g., a computer) and converted into various constraints. These constraints can be, for example, various conditional expressions, such as a wafer only being allowed to enter cavities 2A and 2B but not cavities 2C and 2D, or the processing time for a wafer within a cavity being 30 minutes, etc. See also... Figure 4 , Figure 4 Example of two constraint tables, where... Figure 4 The table on the left shows the cavity numbers that the multiple wafers W1, W2, W3, W4, W5, W6, W7, W8, and W9 contained in wafer group L1 need to enter. "1" indicates that the wafer will enter that cavity, and "0" indicates that the wafer will not enter that cavity. For example, wafer W1 can enter cavities 2A and 2B, but not cavities 2C and 2D. For wafer W5, W5 can enter cavities 2A, 2B, 2C, and 2D. It is worth noting that the number of wafers in wafer group L1 or the constraints on wafer entry into cavities described here are only one example of the present invention, and other different constraints may be shown depending on the manufacturing process. Figure 4 The table on the left may contain more or fewer wafers, and the number of each wafer entering the cavity may also change. Even for the same wafer, it may need to sequentially enter different cavities for multiple processes, or it may only need to be processed in one cavity. All of these variations are within the scope of this invention.

[0051] As for Figure 4The table on the right shows the estimated processing time for each wafer in different cavities. For example, wafer W1 is estimated to require 20 minutes of processing time in cavity 2A or cavity 2B. For wafer W5, the estimated processing time in cavities 2A-2D is 30 minutes. Input the constraints listed in the table into the system. However, it is understandable that... Figure 4 The table shown is merely one example of the present invention, and the invention is not limited thereto.

[0052] Please continue to refer to this. Figure 3 Next, as in step S3, the production time sequence of each wafer in each batch of wafers is calculated using constraint programming and a solver. More specifically, after inputting the constraints into the system, the constraint programming (CP) algorithm and solver calculate an optimal solution under multiple constraints and convert the optimal solution into the production time sequence of each wafer. The constraint programming algorithm described here is an algorithm suitable for handling problems involving a large number of variables and complex constraints. The core idea of ​​the constraint programming algorithm is to transform the problem into a set of variables and the constraints between them, and then use a specialized algorithm to find one or more feasible solutions while satisfying all constraints. In other words, given that the system already stores multiple constraints, the system's solver will try multiple sets of possible variables (e.g., enumeration, but not limited to this), eliminate variables that do not meet the conditions, and seek an optimal solution from the remaining combinations of variables. Other detailed knowledge about constraint programming algorithms is known in the art and will not be elaborated here. The constraint programming system used in this invention is IBM ILOG CPLEX Optimizers, and the solver is CP Optimizer (Constraint program solvers). However, the present invention is not limited thereto, and constraint programming systems and solvers from different manufacturers can be used according to different needs.

[0053] The production time sequence described above is, for example, information containing data such as wafer number, predetermined process start time, predetermined process end time, and predetermined cavity number for the process. It displays when each wafer will enter which cavity and when it will leave the cavity. In other words, after the system calculates the process end time of each chip in each batch of wafers in the cavity, a buffer time (e.g., the time required for a wafer to enter and exit the cavity) is added to determine the time when the next wafer can enter the cavity. Listing this data constitutes the production time sequence. Next, as in step S4, the production time sequence is graphically displayed on the screen to establish a simulated process flow chart. This can be referenced together. Figure 5 , Figure 5 An example of a simulated manufacturing process flow diagram is shown below. Figure 5The intermediate cavities 2A to 2D are displayed on the screen. Then, the wafers of each batch of wafers are numbered and arranged next to the corresponding cavity number according to the process sequence to indicate the order in which the wafers enter the cavity. For example, Figure 5 In the wafer numbering, the string of letters and numbers at the beginning represents the wafer group number, while the numbers following it represent the wafer number within that wafer group. For example, wafer number L1.01 represents the first wafer in wafer group L1, number L2.06 represents the sixth wafer in wafer group L2, and number L3.01 represents the first wafer in wafer group L3, and so on. Further details are omitted here.

[0054] like Figure 3 As shown, the system converts the production time sequence into a graphical simulation process flow chart and displays it on the screen. Next, in step S5, based on the simulation process flow chart, the dispatch time for the next batch of wafers to enter the semiconductor equipment is calculated. In other words, the manufacturer can use the simulation process flow chart to present and simulate the process status of each wafer in this batch of wafers in the semiconductor equipment, then calculate the process completion time of all wafers in this batch, and schedule the earliest time when the next batch of wafers can be assigned to the semiconductor equipment (i.e., the dispatch time). In this way, the estimated time result is more accurate than the past method of using empirical data for dispatch time, and it also improves process efficiency.

[0055] In addition, the estimated process completion time calculated by the system, plus the preset buffer time QT, gives the dispatch time for the next batch of wafers, which can be displayed on the screen. For example... Figure 5 The time at which the next batch of wafers can be allocated is shown as X hours and Y minutes. Here, X and Y can be any suitable values.

[0056] Additionally, please continue to refer to Figure 3 Between steps S3 and S4, some wafers undergo processing within the cavity of the semiconductor equipment. At this time, the system calculates the optimal production time sequence based on the current conditions and converts it into a simulated process flow chart displayed on the screen. However, during the process, various unforeseen circumstances may cause changes to the process conditions (i.e., constraints). Therefore, in... Figure 3The process also includes step S3-1, which involves correcting and updating the production time sequence of each wafer based on the actual process conditions. For example, the system can be set to recalculate the production time sequence according to existing constraints after a fixed time interval (e.g., 5 minutes, but not limited to this). Alternatively, the system can recalculate the production time sequence for each wafer when it detects that a specific event has been met, such as when the system detects an error message in the cavity. The new production time sequence calculated above will replace the old production time sequence, and the system will convert it into a graphical simulation process flow chart based on the latest production time sequence for each wafer. In this way, the system can simultaneously detect and identify unexpected situations in the process and quickly correct the simulated process flow chart according to the existing process conditions.

[0057] Apart from Figure 4 In addition to the constraints shown, different manufacturing processes may include other constraints, or these constraints may change as the process progresses. For example, when a cavity in the semiconductor equipment malfunctions or experiences a delay, the constraints are input into the system. For instance, when cavity 2C malfunctions, the system detects the event, treats it as a new constraint, recalculates it, and updates the simulated process flow chart and the earliest possible arrival time (dispatch time) for the next batch of wafers in the semiconductor equipment. More specifically, the updated simulated process flow chart shows that the wafers are no longer processed in cavity 2C, but instead continue processing in cavities 2A, 2B, and 2D. Simultaneously, the system also recalculates the arrival time for the next batch of wafers in the semiconductor equipment.

[0058] This invention is also applicable to methods for scheduling continuous processes using multiple semiconductor equipment. For example... Figure 6 As shown, it illustrates a schematic diagram of a simulated process flow chart applicable to continuous processes using multiple semiconductor equipment. Figure 6 As shown, the vertical axis of the simulated process flow diagram includes a first semiconductor machine, a second semiconductor machine, a third semiconductor machine, and a fourth semiconductor machine. Each semiconductor machine contains multiple cavities, such as cavity 1, cavity 2, cavity 3, and cavity 4. The horizontal axis of the simulated process flow diagram represents time, and the diagram contains blocks representing wafers from different wafer groups, such as wafer group L1, wafer group L2, wafer group L3, wafer group L4, wafer group L5, and wafer group L6. Each wafer in a batch of wafer group is represented by... Figure 6 A single square in the diagram represents the wafers; due to the large number of wafers, this is omitted for brevity. Figure 6 While the numbering of each wafer is not shown on the diagram, it is understood that each square represents a numbered wafer. It is worth noting... Figure 6 The arrangement of the blocks shown is merely one example of the invention, and the invention is not limited thereto. Furthermore...Figure 6 The dispatch time for each semiconductor machine can also be displayed on the screen, but it is not shown on the diagram for the sake of simplicity.

[0059] like Figure 6 As shown, the simulated process flow chart developed in this invention is also applicable to continuous processes involving multiple semiconductor equipment. In continuous processes involving multiple semiconductor equipment, the process is more complex, making it more difficult to accurately calculate the dispatch time for each semiconductor equipment. The method provided by this invention replaces manual labor with a system, allowing for more accurate calculation of the dispatch time for each semiconductor equipment and improving process efficiency.

[0060] Please refer to the above instructions and accompanying drawings. Figures 1 to 6 The present invention discloses a method for estimating the dispatch time of a semiconductor equipment, characterized by comprising providing a semiconductor equipment 1, the semiconductor equipment 1 including multiple cavities 2A to 2D, providing multiple batches of wafer sets, each batch of wafer sets (e.g., wafer sets L1 to L6) containing multiple wafers, sending the multiple batches of wafer sets to the semiconductor equipment 1 for multiple processes, and, based on the process status of the multiple batches of wafer sets in the semiconductor equipment 1, generating a simulated process flow chart by a system. Figure 5 And based on the simulated process flow chart, calculate an estimated process completion time (dispatch time) ( Figure 3 Step S5), wherein the simulated process flow chart formulated by the system is obtained based on a constraint programming (CP) algorithm.

[0061] In some embodiments of the present invention, each batch of wafers includes multiple wafers, each of which has a wafer number (for example, wafer group L1 includes wafers W1 to W9, but is not limited thereto).

[0062] In some embodiments of the present invention, among the multiple wafers included in one of a batch of wafer sets, a portion of the wafers are restricted to being processed only in one of a subset of cavities in a semiconductor equipment, while another portion of the wafers are allowed to be processed in all cavities of the semiconductor equipment (e.g., ...). Figure 4 As shown, wafer W1 can only be processed in cavity 2A or cavity 2B, while wafer W5 can be processed in cavities 2A, 2B, 2C, and 2D.

[0063] In some embodiments of the present invention, among the multiple wafers included in one batch of a multi-batch wafer group, the time spent by a portion of the wafers in the cavity of the semiconductor equipment during processing is defined as a first time, and the time spent by another portion of the wafers in the cavity of the semiconductor equipment during processing is defined as a second time, wherein the first time and the second time are different (e.g.,Figure 4 As shown, the processing time for wafer W1 is 20 minutes, while the processing time for wafer W5 is 30 minutes.

[0064] In some embodiments of the present invention, where the system is based on a constraint programming algorithm, the steps of the simulated process flow chart further include inputting multiple limiting conditions into the system (such as...). Figure 3 Step S2).

[0065] In some embodiments of the present invention, the limiting conditions include: the number of each cavity of the semiconductor machine corresponding to each wafer, the process time of each wafer in each cavity, and the order in which each batch of wafers is sent to a preparatory area of ​​the semiconductor machine.

[0066] In some embodiments of the invention, the system includes a solver that, based on multiple constraints input into the system, derives an optimal solution (such as...). Figure 3 Step S3).

[0067] In some embodiments of the present invention, the process further includes converting the optimal solution obtained by the solver into a simulated process flow chart and outputting it to a system (e.g., Figure 3 Step S4).

[0068] In some embodiments of the invention, the solver includes IBM ILOG CPLEX Optimizers' CP Optimizer (Constraint program solvers).

[0069] In some embodiments of the present invention, the system begins calculations and plans a production time sequence before multiple batches of wafers are sent to a preparatory area 3 of the semiconductor equipment. That is, before the process begins, the system has already planned the start and end times of the process for each wafer in advance based on known conditions, such as the end time of the previous batch of wafers, the number of wafers, and the types of processes that the wafers need to undergo.

[0070] In some embodiments of the present invention, during the process of wafers being fed into the cavities of a semiconductor machine and undergoing manufacturing, the system recalculates and updates the production time sequence of each wafer multiple times based on the process status (e.g., ...). Figure 3 Step S3-1).

[0071] In some embodiments of the present invention, the system extracts multiple parameters from the process at fixed intervals and recalculates the production time sequence of each wafer, with the newly calculated production time sequence replacing the original one. For example, the production time sequence of each wafer can be recalculated every 5 minutes to confirm whether the current production time sequence conforms to the collected parameters.

[0072] In some embodiments of the present invention, after each pre-defined event is met in the manufacturing process, the system extracts multiple parameters from the process and recalculates the production time sequence of each wafer. The newly calculated production time sequence of each wafer replaces the original production time sequence. For example, the production time sequence of each wafer can be recalculated upon receiving an error message.

[0073] In some embodiments of the present invention, the production time sequence of each wafer is converted into a graphical simulation process flow chart (e.g., Figure 5 Or Figure 6 (as shown), and presented on a display screen.

[0074] In some embodiments of the present invention, after the system generates a simulated process flow chart, the dispatch time is calculated based on the simulated process flow chart and displayed on a display screen (e.g., Figure 5 The available time for dispatching the next batch of wafers is shown as X hours and Y minutes.

[0075] This invention provides a more accurate and automated wafer dispatching planning method. In known procedures, wafer dispatching time (i.e., the time it takes to dispatch the next batch of wafers to the machine) is typically calculated based on data stored in a past process database. However, calculating process end times using past data is not accurate enough and cannot reflect process status in a timely manner for adjustments. The feature of this invention is that when each batch of wafers enters the preparation area of ​​the semiconductor machine, various constraints are input into the system, such as the number of wafers, the processes required for each wafer, and the time spent on each process in each cavity. These constraints are input into the system, and an optimal solution is obtained through a constraint programming (CP) algorithm and a solver. The optimal solution is output, along with the production time sequence of each wafer and a graphical simulation of the process flow, to accurately calculate the process end time of this batch of wafers at the semiconductor machine, facilitating the dispatching of the next batch of wafers to the semiconductor machine. This invention can further refine the process time calculation from the original batch of wafers to the individual wafers within each batch. Simultaneously, this invention replaces manual calculation with system-based calculation to handle large amounts of complex data, which is more conducive to automated production. Furthermore, when certain machines experience delays for various reasons, the system can react in real time and quickly re-establish a new production time sequence and graphical simulation of the process flow, effectively improving production efficiency.

[0076] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention shall be within the scope of the present invention.

Claims

1. A method for estimating the dispatch time of a semiconductor machine, characterized in that, Include: A semiconductor equipment is provided, which includes multiple cavities; It provides multiple wafer sets, each containing multiple wafers; The multiple batches of wafers were sent to the semiconductor equipment for various processes. as well as Based on the process conditions of the multiple batches of wafers in the semiconductor equipment, the system formulates a simulated process flow chart and calculates the dispatch time based on the simulated process flow chart. The simulated process flow chart formulated by the system is obtained based on the constraint programming (CP) algorithm.

2. The method for estimating the dispatch time of semiconductor equipment according to claim 1, wherein each batch of the wafer group includes a wafer number for each of the plurality of wafers.

3. The method for estimating the dispatch time of a semiconductor equipment according to claim 1, wherein, among the plurality of wafers included in one of the plurality of wafer batches, a portion of the wafers are restricted to being processed only in one of the cavities of the semiconductor equipment, while another portion of the wafers are allowed to be processed in all the cavities of the semiconductor equipment.

4. The method for estimating the dispatch time of a semiconductor machine according to claim 1, wherein the time spent by a portion of the wafers in one of the multiple wafer batches during the process in the cavity of the semiconductor machine is defined as a first time, and the time spent by another portion of the wafers during the process in the cavity of the semiconductor machine is defined as a second time, wherein the first time is different from the second time.

5. The method for estimating the dispatch time of semiconductor equipment according to claim 1, wherein the system, based on the constraint programming algorithm, further comprises the step of formulating the simulated process flow chart by: Enter multiple limiting conditions into the system.

6. The method for estimating the dispatch time of a semiconductor machine according to claim 5, wherein the limiting conditions include: the number of each cavity of the semiconductor machine corresponding to each wafer, the process time of each wafer in each cavity, and the order in which each batch of wafers is sent to the preparation area of ​​the semiconductor machine.

7. The method for estimating the dispatch time of a semiconductor machine according to claim 6, wherein the system includes a solver and derives an optimal solution based on the plurality of constraints input into the system.

8. The method for estimating the dispatch time of a semiconductor machine according to claim 7, further comprising converting the optimal solution obtained by the solver into the simulated process flow chart and outputting it to the system.

9. The method for estimating the dispatch time of a semiconductor machine according to claim 7, wherein the solver obtains the optimal solution by, under the plurality of constraints, trying multiple sets of possible variables by enumeration and excluding variables that do not meet the conditions, and then seeking the optimal solution in the remaining combinations of variables.

10. The method for estimating the dispatch time of a semiconductor machine according to claim 1, wherein the system begins to calculate and plan the production time sequence of each wafer before the multiple batches of wafers are sent to the preparation area of ​​the semiconductor machine.

11. The method for estimating the dispatch time of a semiconductor machine according to claim 10, wherein during the process of the wafer being delivered to each cavity of the semiconductor machine and the process being performed, the system recalculates and updates the production time sequence of each wafer multiple times based on the process status.

12. The method for estimating the dispatch time of a semiconductor machine according to claim 11, wherein at fixed intervals, the system extracts multiple parameters from the process and recalculates the production time sequence of each wafer, and the newly calculated production time sequence replaces the original production time sequence.

13. The method for estimating the dispatch time of a semiconductor machine according to claim 11, wherein the system pre-sets multiple events, and when the process meets the conditions of an event, the system extracts multiple parameters in the process and recalculates the production time sequence of each wafer, and the newly calculated production time sequence replaces the original production time sequence.

14. The method for estimating the dispatch time of a semiconductor machine according to claim 10, wherein the production time sequence of each wafer is presented on the display screen of the system via a graphical interface, and the production time sequence displayed on the display screen is defined as the simulated process flow chart.

15. The method for estimating the dispatch time of a semiconductor machine according to claim 1, wherein after the system generates the simulated process flow chart, the dispatch time is calculated based on the simulated process flow chart and displayed on a display screen.

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