Display panel and display device

Abstract

The invention discloses a display panel and a display device. The display panel comprises a substrate; the multiple first signal lines are arranged on one side of the substrate, the first signal lines are arranged in the display area, the first signal lines are arranged at intervals in the first direction and extend in the second direction, and the first direction intersects with the second direction; at least part of the connecting line is located in the display area, the first end of the connecting line is electrically connected with the first signal line, the connecting line comprises at least two first sub-parts and at least two second sub-parts, the first sub-parts extend in the first direction, the second sub-parts extend in the second direction, the first sub-parts and the second sub-parts are sequentially and alternately connected, and each first sub-part comprises a first end. By adopting the mode that the first sub-parts and the second sub-parts are sequentially and alternately connected, the situation that coupling capacitance is generated between the single first sub-part and other signal lines, electrodes or via holes arranged on the same layer due to the fact that the extension length of the single first sub-part is too long is avoided, the display effect of the display panel is guaranteed, the visual effect problem is avoided, and the use performance of the display panel is improved.

Description

Technical Field

[0001] This invention belongs to the field of electronic product technology, and particularly relates to a display panel and display device. Background Technology

[0002] With the advancement of technology, digital display panels such as those used in smartphones and tablets are widely used, and the display screen is an indispensable human-computer interaction interface in these panels. OLED (Organic Light Emitting Diode) display panels, for example, have advantages such as self-illumination, energy saving, flexibility, and good adaptability. Furthermore, these display panels do not require a backlight and feature fast response times and excellent display effects, attracting user attention and being widely used in smartphones, tablets, and other terminal products.

[0003] However, due to the structural limitations of existing display panels, their performance cannot meet the requirements.

[0004] Therefore, there is an urgent need for a new display panel and display device. Summary of the Invention

[0005] This invention provides a display panel and a display device. The connecting line includes at least two first sub-parts and at least two second sub-parts. The first sub-parts and second sub-parts extend in different directions, that is, the connecting line can be in the form of a zigzag line with multiple bends. By adopting the form of sequentially alternating connection of the first sub-parts and the second sub-parts, coupling capacitance between the first sub-parts and other signal lines, electrodes or vias arranged in the same layer is avoided due to the excessive extension length of a single first sub-part. This ensures the display effect of the display panel, avoids visual problems, and improves the performance of the display panel.

[0006] In a first aspect, embodiments of the present invention provide a display panel, including a display area and at least a non-display area surrounding the display area; the display panel includes a substrate; a plurality of first signal lines disposed on one side of the substrate, the first signal lines being disposed in the display area, the first signal lines being spaced apart along a first direction and extending along a second direction, the first direction and the second direction intersecting; a connecting line, at least a portion of the connecting line being located in the display area, a first end of the connecting line being electrically connected to the first signal lines, the connecting line including at least two first sub-parts and at least two second sub-parts, the first sub-parts extending along the first direction, the second sub-parts extending along the second direction, the first sub-parts and the second sub-parts being sequentially and alternately connected, the first sub-parts including a first end.

[0007] Secondly, embodiments of the present invention provide a display device, including the display panel in any of the above embodiments.

[0008] Compared with related technologies, the display panel provided in this embodiment of the invention includes a substrate, a first signal line, and a connecting line for electrical connection with the first signal line. The connecting line includes at least two first sub-parts and at least two second sub-parts. The first sub-parts and the second sub-parts extend in different directions, that is, the connecting line can be in the form of a zigzag line with multiple bends. By adopting the form of sequentially and alternately connecting the first sub-parts and the second sub-parts with different extension directions, coupling capacitance between the first sub-part and other signal lines, electrodes or vias in the same layer is avoided due to the excessive extension length of a single first sub-part. This ensures the display effect of the display panel, avoids visual problems, and improves the performance of the display panel. Attached Figure Description

[0009] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the embodiments of the present invention will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0010] Figure 1 This is a schematic diagram of the structure of a display panel according to an embodiment of the present invention; Figure 2 This is provided by one embodiment of the present invention. Figure 1 A partial schematic diagram at point B in the middle; Figure 3 This is provided by one embodiment of the present invention. Figure 1 A partial schematic diagram at point C in the middle; Figure 4 This is provided by another embodiment of the present invention. Figure 1 A partial schematic diagram at point B in the middle; Figure 5 This is a schematic diagram of the film layer structure of a display panel according to an embodiment of the present invention; Figure 6 This is provided by yet another embodiment of the present invention. Figure 1 A partial schematic diagram at point B in the middle; Figure 7 This is provided by yet another embodiment of the present invention. Figure 1 A partial schematic diagram at point B in the middle; Figure 8 This is provided by another embodiment of the present invention. Figure 1 A partial schematic diagram at point C in the middle; Figure 9 This is a schematic diagram showing the relative positions of the connecting line and the auxiliary signal line according to an embodiment of the present invention; Figure 10 This is a schematic diagram of the film layer structure of a display panel according to another embodiment of the present invention; Figure 11 This is a schematic diagram of the film layer structure of a display panel according to another embodiment of the present invention.

[0011] Explanation of reference numerals in the attached figures: 100. Substrate; 200, First signal line; 300, Connecting line; 310, First sub-section; 320, Second sub-section; D1, First terminal; X, First direction; Y, Second direction; AA, Display area; AA1, First display area; AA2, Second display area; NA, Non-display area; 400, Auxiliary signal line; 500, Second signal line; 600, Third signal line; 700, Pixel Definition Layer; P, Pixel unit; T, Pixel circuit; F, Light-emitting unit; F1, First electrode layer; F2, Light-emitting layer; F3, Second electrode layer; M1, First conductive layer; M2, Second conductive layer; M3, Third conductive layer; M4, Fourth conductive layer; M5, Fifth conductive layer; K1, First via; K2, Second via; K3, Third via; J, Insulating layer; G, Gate; S, Source; N, Semiconductor layer; D, Drain; L, Connector; Q, Isolation; H, First pixel row; C, Storage capacitor; C1, First electrode plate; C2, Second electrode plate. Detailed Implementation

[0012] The features and exemplary embodiments of various aspects of the present invention will now be described in detail. In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the invention. However, it will be apparent to those skilled in the art that the invention may be practiced without requiring some of these specific details. The following description of embodiments is merely intended to provide a better understanding of the invention by illustrating examples of the invention.

[0013] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes the element.

[0014] In existing technologies, display panels may employ a FIAA (Fan-out in the active area) scheme to achieve narrow bezels. FIAA refers to the connection lines 300 used to connect data lines or other signal lines to the driver chip located in the display area AA. However, conductive portions corresponding to pixel units P may also exist on the same layer as the connection lines 300, such as anode vias connecting the anode of the light-emitting unit F to the pixel circuit T. These conductive portions generate coupling capacitance with the connection lines 300. The more pixel units P the connection lines 300 pass through in a certain direction, the more anode vias they pass through, resulting in a larger total coupling capacitance. This coupling voltage, when written to the pixels, easily forms mura (moiré patterns), affecting the display effect and performance of the display panel.

[0015] To solve the above problems, the display panel provided in this embodiment of the invention adopts a form in which a first sub-part 310 and a second sub-part 320 with different extension directions are connected alternately in sequence. This avoids the generation of coupling capacitance between the extension length of a single first sub-part 310 and other signal lines, electrodes or vias arranged in the same layer due to excessive extension length. This ensures the display effect of the display panel, avoids visual problems, and improves the performance of the display panel.

[0016] To better understand this invention, the following is combined with... Figures 1 to 11 The display panel and display device according to embodiments of the present invention will be described in detail.

[0017] Please see Figures 1 to 3 , Figure 1 This is a schematic diagram of the structure of a display panel according to an embodiment of the present invention; Figure 2 This is provided by one embodiment of the present invention. Figure 1 A partial schematic diagram at point B in the middle. Figure 3 This is provided by one embodiment of the present invention. Figure 1 A partial schematic diagram at point C.

[0018] This invention provides a display panel, including a display area AA and a non-display area NA surrounding at least part of the display area AA; the display panel includes a substrate 100; a plurality of first signal lines 200 disposed on one side of the substrate 100, the first signal lines 200 being disposed in the display area AA, the first signal lines 200 being spaced apart along a first direction X and extending along a second direction Y, the first direction X and the second direction Y intersecting; a connecting line 300, at least part of the connecting line 300 being located in the display area AA, the first end D1 of the connecting line 300 being electrically connected to the first signal lines 200, the connecting line 300 including at least two first sub-parts 310 and at least two second sub-parts 320, the first sub-parts 310 extending along the first direction X, the second sub-parts 320 extending along the second direction Y, the first sub-parts 310 and the second sub-parts 320 being sequentially and alternately connected, the first sub-part 310 including a first end D1.

[0019] The display panel provided in this embodiment of the invention includes a substrate 100, a first signal line 200, and a connecting line 300 for electrically connecting to the first signal line 200. The connecting line 300 includes at least two first sub-parts 310 and at least two second sub-parts 320. The first sub-parts 310 and the second sub-parts 320 extend in different directions, that is, the connecting line 300 can be in the form of a zigzag line with multiple bends. By adopting the form of sequentially and alternately connecting the first sub-parts 310 and the second sub-parts 320 with different extension directions, coupling capacitance between the first sub-part 310 and other signal lines, electrodes or vias in the same layer is avoided due to the excessive extension length of a single first sub-part 310. This ensures the display effect of the display panel, avoids visual problems, and improves the performance of the display panel.

[0020] Meanwhile, by sequentially and alternately connecting the first sub-part 310 and the second sub-part 320 with different extension directions, the distance between the first sub-part 310 and the electrodes or vias disposed in the same layer can be increased, thereby reducing the coupling capacitance.

[0021] It should be noted that, in this embodiment, a driver chip can be disposed corresponding to the non-display area NA, and the connecting line 300 can extend to the non-display area NA to connect with the driver chip signal. The signal of the driver chip is transmitted to the first signal line 200 using the connecting line 300. The second sub-part 320 needs to extend in the direction of the driver chip, that is, each first sub-part 310 is gradually placed closer to the driver chip along the switching line of the second sub-part 320.

[0022] Optionally, the first signal line 200 may include a data signal line.

[0023] In this embodiment, the first sub-part 310 and the second sub-part 320 are connected alternately in sequence. For example, when the connecting line 300 includes two first sub-parts 310 and two second sub-parts 320, they can be connected end-to-end in the order of first sub-part 310, second sub-part 320, first sub-part 310, second sub-part 320. More first sub-parts 310 and second sub-parts 320 can be provided as needed.

[0024] Optionally, the connecting line 300 may also include three first sub-sections 310 and three second sub-sections 320.

[0025] The first sub-part 310 includes a first terminal D1. The first sub-part 310 can be electrically connected to the first signal line 200 via the first terminal D1 of the first sub-part 310 located near the corresponding first signal line 200. Only one first terminal D1 of the first sub-part 310 needs to be electrically connected to the first signal line 200 in a single connection line 300.

[0026] Optionally, both the first direction X and the second direction Y can be parallel to the direction of the plane where the substrate 100 is located.

[0027] Please see Figures 1 to 2 In some optional embodiments, the extension direction of the first sub-part 310 is perpendicular to the extension direction of the second sub-part 320, in order to facilitate fabrication and to facilitate connection between the connecting line 300 and the driver chip.

[0028] Please see Figures 1 to 2 In some alternative embodiments, the extension length of the second sub-part 320 along the second direction Y is less than the extension length of the first sub-part 310 along the first direction X.

[0029] It should be noted that, considering that the second sub-section 320 is only used for connecting adjacent first sub-sections 310 to realize the switching of the first sub-section 310, and the first sub-section 310 usually needs to extend towards the center of the display panel to electrically connect with the driver chip located in the center of the corresponding display panel, the extension length of the first sub-section 310 along the first direction X can be greater than the extension length of the second sub-section 320 along the second direction Y to facilitate the connection with the driver chip. The connecting line 300 may also include a third sub-section extending to the non-display area NA and connecting with the driver chip. The third sub-section may also extend along the second direction Y or in other directions, such as a direction inclined relative to the second direction Y, as long as it can connect with the driver chip, there is no special limitation.

[0030] Please see Figures 1 to 3 In some optional embodiments, the number of first sub-parts 310 within the connecting line 300 is greater than or equal to the number of second sub-parts 320, in order to reduce the difficulty of manufacturing.

[0031] For example, the connecting line 300 may include three first sub-sections 310 and two second sub-sections 320, which are connected sequentially in the order of first sub-section 310, second sub-section 320, first sub-section 310, second sub-section 320, and first sub-section 310. The first first sub-section 310 may be electrically connected to the first signal line 200, while the last first sub-section 310 may be connected to the driver chip through the third sub-section.

[0032] Alternatively, the connecting line 300 may include two first sub-sections 310 and two second sub-sections 320, connected sequentially in the order of first sub-section 310, second sub-section 320, first sub-section 310, and second sub-section 320. The first first sub-section 310 may be electrically connected to the first signal line 200, while the last second sub-section 320 may be directly connected to the driver chip.

[0033] Please see Figure 4 , Figure 4 This is provided by another embodiment of the present invention. Figure 1 A partial schematic diagram at point B; in some optional embodiments, the display panel further includes a plurality of pixel units P, which are spaced apart along a first direction X and a second direction Y; along the first direction X, a second sub-part 320 overlaps with at least two adjacent pixel units P along the second direction Y.

[0034] It is understood that in this embodiment, the second sub-part 320 can span at least two pixel units P along the second direction Y to increase the distance between adjacent first sub-parts 310 along the second direction Y within the same connecting line 300, which facilitates wiring and allows each connecting line 300 to be connected to different first signal lines 200 respectively, thus avoiding mutual interference.

[0035] In this embodiment, along the first direction X, a second sub-part 320 overlaps with at least two adjacent pixel units P along the second direction Y. Correspondingly, along the first direction X, the length of a second sub-part 320 must be at least greater than the length of a pixel unit P along the first direction X in order for the second sub-part 320 to overlap with at least two adjacent pixel units P.

[0036] Optionally, considering that there is usually a certain interval between adjacent pixel units P, along the first direction X, the length of a second sub-part 320 can be greater than the sum of the lengths of the two pixel units P.

[0037] Please see Figure 5 , Figure 5This is a schematic diagram of the film layer structure of a display panel according to an embodiment of the present invention; in some optional embodiments, the pixel unit P includes a light-emitting unit F and a pixel circuit T electrically connected to the light-emitting unit F. The pixel circuit T includes a semiconductor layer N. Along the direction away from the substrate 100, the light-emitting unit F includes a first electrode layer F1, a light-emitting layer F2 and a second electrode layer F3 stacked together. The first electrode layer F1 includes a plurality of first electrode blocks spaced apart. The display panel also includes at least one insulating layer J disposed between the semiconductor layer N and the first electrode blocks and a third via K3 penetrating at least part of the insulating layer J to connect the first electrode blocks and the semiconductor layer N. The third via K3 is provided with a connecting portion L, and part of the connecting portion L and the first sub-part 310 are disposed on the same layer.

[0038] It should be noted that in this embodiment, since part of the connecting part L and the first sub-part 310 are arranged in the same layer, a coupling capacitance may be generated between the connecting part L and the first sub-part 310, which will affect the light emission effect of the light-emitting layer F2.

[0039] Each light-emitting unit F needs to be connected to the corresponding semiconductor layer N through a third via K3. Therefore, the longer the first sub-part 310 is, the more light-emitting units F and third via K3 it passes through, and the larger the total coupling capacitance between the first sub-part 310 and the connecting part L in the same layer.

[0040] Therefore, by providing a second sub-part 320, this embodiment of the invention avoids reducing the total coupling capacitance between the first sub-part 310 and the connecting part L disposed on the same layer due to the excessive extension length of a single first sub-part 310, thus ensuring the display effect of the display panel, avoiding visual problems, and improving the performance of the display panel.

[0041] It should be noted that in this embodiment, the light-emitting unit F can be an OLED light-emitting unit F. For example, along the direction away from the substrate 100, the light-emitting unit F may include a first electrode layer F1, a light-emitting functional layer and a second electrode layer F3 stacked sequentially.

[0042] Optionally, the light-emitting functional layer includes one or more of the following: an electron injection layer, an electron transport layer, a light-emitting material layer, a hole blocking layer, an electron blocking layer, a hole transport layer, and a hole injection layer. The specific selection depends on the type of the light-emitting layer F2 and is not particularly limited. The electron injection layer, electron transport layer, and hole blocking layer can be disposed between the second electrode layer F3 and the light-emitting material layer. The electron blocking layer, hole transport layer, and hole injection layer can be disposed between the first electrode layer F1 and the light-emitting material layer.

[0043] The material of the first electrode layer F1 is generally a material with a high work function to improve hole injection efficiency. It can be gold (Au), platinum (Pt), titanium (Ti), silver (Ag), indium tin oxide (ITO), zinc tin oxide (IZO), or a transparent conductive polymer (such as polyaniline). For example, the first electrode layer F1 can be made of ITO-Ag-ITO composite material, without any special limitations.

[0044] The material of the second electrode layer F3 can be one of the following metals: silver (Ag), aluminum (Al), lithium (Li), magnesium (Mg), ytterbium (Yb), calcium (Ca), or indium (In). It can also be an alloy of the aforementioned metals, such as magnesium-silver alloy (Mg / Ag) or lithium-aluminum alloy (Li / Al). This embodiment does not impose any restrictions on this.

[0045] Optionally, the pixel circuit T is disposed on the array layer, which includes multiple conductive layers and an insulating layer J located between adjacent conductive layers. The pixel circuit T includes a transistor and a storage capacitor C. The transistor includes a semiconductor layer N, a gate G, a source S, and a drain D. The materials of the source S and the gate G may include one or more combinations of molybdenum, titanium, aluminum, copper, etc. The gate G of the transistor is typically used to receive a control signal, causing the transistor to turn on or off under the control of the control signal. One of the source S and drain D of the thin-film transistor is connected to the light-emitting unit F to control the normal light emission of the light-emitting unit F.

[0046] Since the first electrode block is usually electrically connected to the semiconductor layer N through the source S or the drain D, the connection part L may include the source S or the drain D. At the same time, the connection part L may also include the part where the source S is connected to the first electrode block, or the part where the drain D is connected to the first electrode block. That is, the third via K3 may include multiple sub-vias, which are used to set the connection parts L located in different film layers.

[0047] Optionally, the display panel also includes a planarization layer and a pixel definition layer 700 disposed sequentially on the side of the pixel circuit T away from the substrate 100 along a direction away from the substrate 100. The pixel definition layer 700 includes a pixel opening, and the light-emitting unit F is at least partially located in the pixel opening. The third via K3 can penetrate the planarization layer and the insulating layer J in the array layer.

[0048] The material of some connecting parts L can be the same as that of the first electrode block, while other conductive materials can be used for some connecting parts L used as the source electrode S or the drain electrode D, without any special restrictions.

[0049] Please see Figure 5In some optional embodiments, along the direction away from the plane where the substrate 100 is located, the display panel includes a first conductive layer M1, a first insulating layer J and a second conductive layer M2 sequentially stacked on one side of the substrate 100; the first signal line 200 and the second sub-part 320 are both disposed on the same layer as the second conductive layer M2, the first sub-part 310 and the first conductive layer M1 are disposed on the same layer, and the first sub-part 310 and the second sub-part 320 are connected through a first via K1 disposed on the first insulating layer J.

[0050] It should be noted that the array layer may include driving circuitry. For example, the array layer may include a third conductive layer M3, a fourth conductive layer M4, a first conductive layer M1, and a second conductive layer M2, which are disposed on one side of the substrate 100 and stacked together. The storage capacitor C includes a first electrode C1 and a second electrode C2. As an example, the gate G and the first electrode C1 may be located on the third conductive layer M3, the second electrode C2 may be located on the fourth conductive layer M4, and the source S and drain D may be located on the first conductive layer M1.

[0051] Depending on the specific needs, the array layer can also include more conductive layers. For example, such as Figure 11 As shown, Figure 11 This is a schematic diagram of the film layer structure of a display panel according to another embodiment of the present invention. The array layer may further include a fifth conductive layer M5 disposed on the side of the second conductive layer M2 away from the substrate 100.

[0052] It is understood that in this embodiment, the first sub-part 310 and the second sub-part 320 can be disposed on different conductive layers and connected through the first via K1 to achieve wire switching and avoid the first sub-part 310 from being too long. Since the first sub-part 310 and the second sub-part 320 are located on different conductive layers, the wiring space is larger, reducing the wiring difficulty.

[0053] Optionally, the first insulating layer J can be prepared using at least one of silicon nitride, silicon oxide, and silicon oxynitride. In addition to the first insulating layer J, insulating layers J are also disposed between other adjacent conductive layers. For example, an insulating layer J is also disposed between the third conductive layer M3 and the fourth conductive layer M4.

[0054] Please see Figure 6 , Figure 6 This is provided by yet another embodiment of the present invention. Figure 1 A partial schematic diagram at point B; in some optional embodiments, the extension length of each first sub-part 310 is equal along the first direction X, avoiding the occurrence of excessively long first sub-parts 310, effectively reducing the total coupling capacitance between the connecting line 300 and the connecting part L in the third via K3, and ensuring the display effect.

[0055] For example, in this embodiment, when the length of the connecting line 300 is 1 and includes two first sub-parts 310, the lengths of the two first sub-parts 310 are 0.5 respectively. This is only an example and does not represent the actual length.

[0056] Optionally, along the second direction Y, the extension lengths of each second sub-part 320 are equal to improve the regularity of the arrangement of the connecting lines 300, facilitate the fabrication, and improve the uniformity of the setting of the connecting lines 300.

[0057] It is understood that, in one embodiment, the extension lengths of each first sub-part 310 along the first direction X and the extension lengths of each second sub-part 320 along the second direction Y can be simultaneously limited to improve the regularity of the overall arrangement of the connecting lines 300 and reduce the difficulty of wiring. Of course, depending on actual needs, only the extension length of either the first sub-part 310 or the second sub-part 320 can be limited, without any special limitation.

[0058] Please see Figure 7 , Figure 7 This is provided by yet another embodiment of the present invention. Figure 1 A partial schematic diagram at point B; the number of first sub-parts 310 and second sub-parts 320 within the same connecting line 300 can be greater than two, such as... Figure 7 As shown, three first sub-sections 310 and three second sub-sections 320 can be provided within the same connecting line 300. Of course, more first sub-sections 310 and second sub-sections 320 can be provided according to actual needs, and are not limited to the above example.

[0059] Please see Figures 8 to 10 , Figure 8 This is provided by another embodiment of the present invention. Figure 1 A partial schematic diagram at point C in the middle; Figure 9 This is a schematic diagram showing the relative positions of the connecting line 300 and the auxiliary signal line 400 provided in one embodiment of the present invention; Figure 10 This is a schematic diagram of the film layer structure of a display panel according to another embodiment of the present invention.

[0060] In some optional embodiments, the display panel further includes an auxiliary signal line 400 disposed on the first conductive layer M1 and a second signal line 500 disposed on the second conductive layer M2; the auxiliary signal line 400 extends along a first direction X and is located between adjacent first sub-parts 310, the second signal line 500 extends along a second direction Y, and the second signal line 500 includes a partition portion Q that is separated by the first sub-parts 310, and at least two partition portions Q are electrically connected to the same auxiliary signal line 400 through a second via K2 disposed on the first insulating layer J.

[0061] It should be noted that since both the second signal line 500 and the second sub-part 320 are located on the second conductive layer M2, the added second sub-part 320 may occupy the original wiring position of the second signal line 500, causing the original second signal line 500 to be interrupted by the second sub-part 320, forming the aforementioned interrupted part Q. This results in the interrupted part Q being unable to receive signals, i.e., floating. In this embodiment, at least two interrupted parts Q are electrically connected by an auxiliary signal line 400, and signals are transmitted to the interrupted parts Q using the auxiliary signal line 400, ensuring normal signal transmission of the second signal line 500.

[0062] In this embodiment, since each connecting line 300 is provided with at least two second sub-parts 320, the space on both the upper and lower sides of a certain segment of the second signal line 500 along the second direction Y is occupied by the second sub-parts 320, thus forming a partitioned part Q. An auxiliary signal line 400 located in the first conductive layer M1 is required to connect the partitioned part Q and run the line from other film layers to provide a signal for the partitioned part Q.

[0063] Please see Figure 8 In some optional embodiments, a second signal line 500 is provided in the first conductive layer M1. The second signal line 500 located in the first conductive layer M1 extends along the first direction X and is spaced and insulated from the first sub-part 310 and the auxiliary signal line 400.

[0064] It is understood that in this embodiment, second signal lines 500 can be provided in the first conductive layer M1 and the second conductive layer M2 respectively. The second signal lines 500 in the first conductive layer M1 extend along the first direction X, and the second signal lines 500 in the second conductive layer M2 extend along the second direction Y. The two can be arranged in a crisscross pattern to ensure the signal transmission effect for the light-emitting units F at different positions.

[0065] The second signal line 500 in the first conductive layer M1 needs to avoid the first sub-part 310 and the auxiliary signal line 400 to avoid affecting the arrangement of the first sub-part 310 and the auxiliary signal line 400.

[0066] Please see Figure 8 In some optional embodiments, the display panel further includes a third signal line 600, which is disposed in the non-display area NA on the side of the display area AA along the first direction X. The auxiliary signal line 400 and the second signal line 500 located in the first conductive layer M1 are both electrically connected to the third signal line 600.

[0067] It should be noted that the auxiliary signal line 400 and the second signal line 500 located in the first conductive layer M1 both need to receive the same voltage signal.

[0068] Therefore, in order to facilitate the unified transmission of signals, a third signal line 600 for uniformly transmitting the power supply voltage signal can be set in the non-display area NA on one side of the display area AA along the first direction X, specifically in the non-display areas NA on the left and right sides of the display area AA, so as to reduce the number of required traces.

[0069] Optionally, the second signal line 500 includes at least one of a low-level power supply voltage signal line and a high-level power supply voltage signal line. That is, the second signal line 500 can be used to transmit either a low-level power supply voltage signal or a high-level power supply voltage signal. For example, the second signal line 500 can be a PVEE (low-level power supply voltage signal) signal line.

[0070] Please see Figure 9 In some optional embodiments, the pixel unit P includes a first pixel unit row H, which includes a plurality of pixel units P spaced apart along a first direction X; at least one first pixel unit row H is orthographically projected onto the substrate 100 between the orthographically projected onto the substrate 100 of two adjacent first sub-parts 310 in a connecting line 300.

[0071] It is understood that in this embodiment, since two adjacent first sub-parts 310 are connected by a second sub-part 320, correspondingly, a second sub-part 320 needs to span at least one first pixel unit row H, so that the orthographic projection of at least one first pixel unit row H on the substrate 100 is located between the orthographic projections of two adjacent first sub-parts 310 on the substrate 100 in a connecting line 300. This is to adjust and ensure that the distance between adjacent first sub-parts 310 is large enough, avoiding the situation where the distance between adjacent first sub-parts 310 and the connecting part L disposed in the same layer is too close, and reducing the total coupling capacitance generated between the first sub-part 310 and the connecting part L disposed in the same layer.

[0072] In this embodiment, a first pixel unit row H may include all pixel units P arranged along the first direction X and located in the same row.

[0073] By alternating between the first sub-part 310 and the second sub-part 320, the number of pixel units P that the first sub-part 310 passes through in the same row is reduced, thereby reducing the trace capacitance and achieving the purpose of improving visual effect.

[0074] Please see Figure 9 In some alternative embodiments, the orthographic projection of a first pixel unit row H on the substrate 100 is located between the orthographic projections of two adjacent first sub-parts 310 on the substrate 100 in a connecting line 300; the orthographic projection of the auxiliary signal line 400 on the substrate 100 and the orthographic projection of the first pixel unit row H on the substrate 100 at least partially overlap.

[0075] In this embodiment, multiple signal lines extending along the first direction X can be reserved in the first conductive layer M1 as auxiliary signal lines 400. Since the orthographic projection of a first pixel unit row H on the substrate 100 is located between the orthographic projections of two adjacent first sub-parts 310 on the substrate 100 in a connecting line 300, the first sub-parts 310 can be omitted on the first conductive layer M1 corresponding to the first pixel unit row H. The reserved space is used to set the auxiliary signal lines 400 to avoid mutual interference between the auxiliary signal lines 400 and the first sub-parts 310.

[0076] Of course, depending on actual needs, two, three or more first pixel unit rows H can be set between two adjacent first sub-parts 310 in a connecting line 300 to leave more space for the auxiliary signal line 400.

[0077] The auxiliary signal line 400 corresponding to the first pixel unit row H can be connected to the partition part Q through the second via K2, thereby reducing the trace length of the first sub-part 310 extending along the first direction X by a larger proportion.

[0078] Optionally, while the connecting line is changed more than 300 times, it is easy to make the connection between adjacent first vias K1 of adjacent connecting lines 300 straight. That is, the straight line formed by the connection is inclined relative to the first sub-part 310, and the two form a "V" shape, which preserves the integrity and regularity of the V-shape formed between the first via K1 and the first sub-part 310.

[0079] Please see Figure 1 In some optional embodiments, along the first direction X, the display area AA includes an adjacent first display area AA1 and a second display area AA2, and the first display area AA1 and the second display area AA2 are symmetrically arranged about the center line of the display area AA extending along the second direction Y; the first display area AA1 and the second display area AA2 are respectively provided with connecting lines 300, and the connecting lines 300 in the first display area AA1 and the second display area AA2 are symmetrically arranged about the center line of the display area AA extending along the second direction Y.

[0080] Understandably, since the driver chip is typically positioned along the centerline of the display area AA extending along the second direction Y, and the connecting line 300 needs to be electrically connected to the driver chip, in order to reduce the trace length of the connecting line 300 and lower the impedance, in this embodiment, the connecting lines 300 located in the first display area AA1 and the second display area AA2 can be symmetrically arranged about the centerline of the display area AA extending along the second direction Y. That is, connecting lines 300 are respectively provided in the first display area AA1 and the second display area AA2 to connect to the driver chip.

[0081] It should be noted that in this embodiment, the only difference between the first display area AA1 and the second display area AA2 is their setting position; the display effect is the same.

[0082] Please see Figures 1 to 4 In some optional embodiments, along the second direction Y, the center line of the orthographic projection of the first via K1 corresponding to each connecting line 300 on the substrate 100 is a straight line.

[0083] It is understandable that the position corresponding to the first via K1, that is, the position where the first sub-part 310 and the second sub-part 320 are connected by the first sub-part 310 to the second sub-part 320 through the first via K1, is restricted to be a straight line along the second direction Y, so as to improve the regularity of the position of the first sub-part 310 and the second sub-part 320, reduce the manufacturing difficulty, and facilitate alignment.

[0084] This invention also provides a display device, including the display panel in any of the above embodiments.

[0085] The display device provided in this embodiment of the invention has the technical effects of the display panel in any of the above embodiments. The explanations of the same or corresponding structures and terms in the above embodiments will not be repeated here.

[0086] The display panel provided in the embodiments of the present invention can be an organic light-emitting diode (OLED) display panel, a quantum dot light-emitting diode (QLED) display panel, or a micro flat panel display panel (Micro-OLED or Micro-LED), etc.

[0087] The display device provided in this embodiment of the invention can be applied to mobile phones or any electronic product with display function, including but not limited to the following categories: televisions, laptops, desktop monitors, tablets, digital cameras, smart bracelets, smart glasses, in-vehicle displays, medical devices, industrial control equipment, touch interactive terminals, etc. This embodiment of the invention does not impose any special limitations on these.

[0088] The above are merely specific embodiments of the present invention. Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, modules, and units described above can be referred to the processes in the foregoing method embodiments, and will not be repeated here. It should be understood that the protection scope of the present invention is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in the present invention, and these modifications or substitutions should all be covered within the protection scope of the present invention.

[0089] It should also be noted that the exemplary embodiments mentioned in this invention describe methods or systems based on a series of steps or apparatus. However, this invention is not limited to the order of the steps described above; that is, the steps can be performed in the order mentioned in the embodiments, or in a different order, or several steps can be performed simultaneously.

Claims

1. A display panel, characterized in that, The display panel includes a display area and a non-display area at least partially surrounding the display area; substrate; Multiple first signal lines are disposed on one side of the substrate. The first signal lines are disposed in the display area. The first signal lines are spaced apart along a first direction and extend along a second direction. The first direction and the second direction intersect. A connecting line, at least a portion of which is located in the display area, wherein a first end of the connecting line is electrically connected to the first signal line, the connecting line includes at least two first sub-sections and at least two second sub-sections, wherein the first sub-sections extend along a first direction and the second sub-sections extend along a second direction, the first sub-sections and the second sub-sections are sequentially and alternately connected, and the first sub-section includes the first end.

2. The display panel according to claim 1, characterized in that, It also includes multiple pixel units, which are respectively arranged at intervals along the first direction and the second direction; Along the first direction, a second sub-part and at least two adjacent pixel units along the second direction overlap.

3. The display panel according to claim 2, characterized in that, The pixel unit includes a light-emitting unit and a pixel circuit electrically connected to the light-emitting unit. The pixel circuit includes a semiconductor layer along a direction away from the substrate. The light-emitting unit includes a first electrode layer, a light-emitting layer and a second electrode layer stacked together. The first electrode layer includes a plurality of spaced first electrode blocks. The display panel further includes at least one insulating layer disposed between the semiconductor layer and the first electrode block, and a third via penetrating at least a portion of the insulating layer to connect the first electrode block and the semiconductor layer. The third via is provided with a connecting portion, and a portion of the connecting portion and the first sub-part are disposed on the same layer.

4. The display panel according to claim 1, characterized in that, Along the second direction, the extension lengths of each of the second sub-parts are equal.

5. The display panel according to claim 1, characterized in that, The number of the first sub-parts within the connecting line is greater than or equal to the number of the second sub-parts.

6. The display panel according to claim 1, characterized in that, Along the first direction, the extension lengths of each of the first sub-parts within the same connecting line are equal.

7. The display panel according to claim 1, characterized in that, The extension length of the second sub-part along the second direction is less than the extension length of the first sub-part along the first direction.

8. The display panel according to claim 2, characterized in that, Along a direction away from the plane where the substrate is located, the display panel includes a first conductive layer, a first insulating layer and a second conductive layer sequentially stacked on one side of the substrate; The first signal line and the second sub-part are both disposed on the same layer as the second conductive layer, the first sub-part is disposed on the same layer as the first conductive layer, and the first sub-part and the second sub-part are connected through a first via disposed on the first insulating layer.

9. The display panel according to claim 8, characterized in that, The display panel also includes an auxiliary signal line disposed on the first conductive layer and a second signal line located on the second conductive layer; The auxiliary signal line extends along the first direction and is located between adjacent first sub-parts. The second signal line extends along the second direction and includes a partition portion separated by the first sub-parts. At least two of the partition portions are electrically connected to the same auxiliary signal line through a second via provided in the first insulating layer.

10. The display panel according to claim 9, characterized in that, The first conductive layer has a second signal line, which extends along the first direction and is insulated from the first sub-part and the auxiliary signal line.

11. The display panel according to claim 9, characterized in that, It also includes a third signal line, which is located in the non-display area on one side of the display area along the first direction. The auxiliary signal line and the second signal line located in the first conductive layer are both electrically connected to the third signal line.

12. The display panel according to claim 1, characterized in that, The first signal line includes a data signal line.

13. The display panel according to claim 9, characterized in that, The second signal line includes at least one of a low-level power supply voltage signal line and a high-level power supply voltage signal line.

14. The display panel according to claim 9, characterized in that, The pixel unit includes a first pixel unit row, and the first pixel unit row includes a plurality of pixel units spaced apart along the first direction; At least one of the first pixel unit rows has its orthographic projection on the substrate located between the orthographic projections of two adjacent first sub-parts on the substrate in a connecting line.

15. The display panel according to claim 14, characterized in that, The orthographic projection of a first pixel unit row on the substrate is located between the orthographic projections of two adjacent first sub-parts on the substrate in a connecting line; The orthographic projection of the auxiliary signal line on the substrate and the orthographic projection of the first pixel unit row on the substrate at least partially overlap.

16. The display panel according to claim 1, characterized in that, Along the first direction, the display area includes an adjacent first display area and a second display area, and the first display area and the second display area are symmetrically arranged about the center line extending from the display area along the second direction; The connecting lines are respectively provided in the first display area and the second display area, and the connecting lines in the first display area and the second display area are symmetrically arranged about the center line of the display area extending along the second direction.

17. The display panel according to claim 1, characterized in that, It also includes a driver chip, which is located in the non-display area, and the connecting line is electrically connected to the driver chip.

18. The display panel according to claim 8, characterized in that, Along the second direction, the center line connecting the orthographic projections of the first vias corresponding to each of the connecting lines on the substrate is a straight line.

19. The display panel according to claim 1, characterized in that, The extension direction of the first sub-part is perpendicular to the extension direction of the second sub-part.

20. A display device, characterized in that, Includes the display panel as described in any one of claims 1 to 19.

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