Display driver and display device

Abstract

The present invention provides a display driver and a display device, the display driver including: a driver circuit that outputs a driving signal; an output terminal that outputs a drive signal to a display electrode EL of the electro-optical panel; an input terminal to which a monitoring signal is input from the display electrode EL; and an inspection circuit. The inspection circuit includes: a comparison circuit that compares a voltage of the monitor signal with a reference voltage; a determination circuit that determines an abnormality on the basis of a desired value corresponding to the voltage level of the drive signal and the comparison result of the comparison circuit; and a potential setting circuit that pulls down or pulls up the signal line of the monitor signal in accordance with the voltage level of the drive signal.

Description

TECHNICAL FIELD

[0001] The present application relates to a display driver and a display device, and the like. BACKGROUND

[0002] A liquid crystal driver having a first segment terminal that outputs a drive signal to a segment electrode and a second segment terminal that inputs a monitoring signal from the segment electrode is disclosed in Patent Literature 1. In Patent Literature 1, a detection circuit detects a drive abnormality of the segment electrode based on the monitoring signal, thereby detecting an abnormality in a signal line of a liquid crystal panel.

[0003] Patent Literature 1: Japanese Patent Application Publication No. 2020-106633

[0004] However, for example, if a signal line that connects the detection circuit and the display electrode is disconnected, the potential of the monitoring signal becomes unstable, and the possibility that an abnormality cannot be accurately detected increases. SUMMARY

[0005] One embodiment of the present disclosure relates to a display driver including a driver circuit that outputs a drive signal, an output terminal that outputs the drive signal to a display electrode of an electro-optical panel, an input terminal that inputs a monitoring signal from the display electrode, and a check circuit including a comparison circuit that compares a voltage of the monitoring signal with a reference voltage, a determination circuit that makes a determination of an abnormality based on an expected value corresponding to a voltage level of the drive signal and a comparison result of the comparison circuit, and a potential setting circuit that performs pull-down or pull-up of a signal line of the monitoring signal in accordance with the voltage level of the drive signal.

[0006] Another embodiment of the present disclosure relates to a display device including the above-described display driver and the electro-optical panel. BRIEF DESCRIPTION OF DRAWINGS

[0007] Figure 1 is a configuration example of the display device of the present embodiment.

[0008] Figure 2 is a detailed configuration example of the display device.

[0009] Figure 3 is an example of the configuration of the segment electrode and the wiring of the segment signal line.

[0010] Figure 4 is an example of the configuration of the common electrode and the wiring of the common signal line.

[0011] Figure 5 is a detailed configuration example of the check circuit and the driver circuit.

[0012] Figure 6is a detailed configuration example of the inspection circuit, the driver circuit.

[0013] Figure 7 is an explanatory diagram of the configuration and operation of the potential setting circuit.

[0014] Figure 8 is an explanatory diagram of the configuration and operation of the potential setting circuit.

[0015] Figure 9 is an explanatory diagram of the configuration and operation of the potential setting circuit.

[0016] Figure 10 is another configuration example of the potential setting circuit.

[0017] Figure 11 is a signal waveform diagram that explains the operation of the display device of the present embodiment.

[0018] Explanation of Reference Numerals

[0019] 10: display device; 20: display driver; 30: driver circuit; 31: segment driver circuit; 32: common driver circuit; 33: pre-buffer circuit; 34: output driver; 36: level shifter; 40: inspection circuit; 41: segment inspection circuit; 42: common inspection circuit; 50: comparison circuit; 52: comparator; 54: level shifter; 56: determination circuit; 58: reference voltage generation circuit; 60: potential setting circuit; 70: row latch; 72: latch; 74: polarity inverting circuit; 80: data storage circuit; 100: control circuit; 110: interface circuit; 120: oscillation circuit; 200: electro-optical panel; 300: processing device; EL: display electrode; EV: expected value; L1, L2: signal line; LT: latched signal; RA, RA2, RD, RU: resistor; SD: drive signal; SM: monitor signal; SW, SWD, SWU: switch; TI: input terminal; TQ: output terminal; TRD, TRU: transistor; VR, VRH, VRL: reference voltage. DETAILED DESCRIPTION

[0020] Hereinafter, the present embodiment will be described. Furthermore, the present embodiment described below does not limit the recitations of the claims. In addition, the structures described in the present embodiment are not necessarily all the essential components.

[0021] 1. Figure 1A configuration example of the display device 10 of the present embodiment is shown. The display device 10 includes a display driver 20 and an electro-optical panel 200. The display driver 20 includes a driver circuit 30, an inspection circuit 40, an output terminal TQ, and an input terminal TI. A plurality of display electrodes EL are provided in the electro-optical panel 200. In addition, the display driver 20, the display device 10 are not limited to the configuration Figure 1 of the present embodiment, and various modifications such as omitting a part of the configuration elements, adding other configuration elements, replacing a part of the configuration elements with other configuration elements, and the like can be implemented.

[0022] The display driver 20 is a circuit that performs driving for displaying an image on the electro-optical panel 200, and is realized by, for example, a circuit device called an IC (Integrated Circuit). The circuit device is a semiconductor chip manufactured by a semiconductor process and formed with circuit elements on a semiconductor substrate. The display driver 20 is mounted, for example, to a glass substrate of the electro-optical panel 200. For example, the display driver 20 is mounted to a glass substrate provided with the display electrodes EL. Alternatively, the display driver 20 can be mounted to a circuit substrate connected to the electro-optical panel 200 through a flexible substrate.

[0023] The electro-optical panel 200 is, for example, a display panel such as a liquid crystal panel. The electro-optical panel 200 has a plurality of display electrodes EL and a plurality of electro-optical elements. The electro-optical element is, for example, a liquid crystal element. Each pixel of the electro-optical panel 200 is constituted by the display electrode EL and the electro-optical element, and an image is displayed on the electro-optical panel 200.

[0024] The display device 10 is, for example, a device that performs display of an image based on image data. The display device 10 is also called a display module or an electro-optical device. The display device 10 is, for example, a cluster display that is a display of an instrument panel, a central information display, a head-up display that displays a virtual image in a user's visual field, or an electronic mirror, or the like, a vehicle-mounted display device. The vehicle-mounted display device is a display device mounted on a car such as a four-wheeled car or a two-wheeled car. Alternatively, the display device 10 can be a display device mounted on a moving body other than a vehicle such as a ship, a head-mounted display device called an HMD, a display of a television device or an information processing device, or the like.

[0025] The display driver 20 includes the driver circuit 30, the output terminal TQ, the input terminal TI, and the inspection circuit 40.

[0026] The driver circuit 30 outputs a drive signal SD for driving the electro-optical panel 200. In a case where the electro-optical panel 200 is a segmented liquid crystal panel, the driver circuit 30 outputs a segmented drive signal for driving a segmented electrode, or a common drive signal for driving a common electrode, as the drive signal SD.

[0027] The output terminal TQ is a terminal that outputs a drive signal SD to the display electrode EL of the electro-optical panel 200. The input terminal TI is a terminal that inputs a monitor signal SM from the display electrode EL. The input terminal TI can also be referred to as a monitor terminal. These output terminal TQ and input terminal TI are, for example, pads of the display driver 20 as a circuit device. For example, in a pad region, a metal layer is exposed from a passivation film as an insulating layer, and the exposed metal layer constitutes a pad as a terminal of the display driver 20. The terminal can also be an external connection terminal of a package that houses the display driver 20.

[0028] The inspection circuit 40 is a circuit for inspecting an abnormal state such as disconnection or short circuit of a signal line or the like of the electro-optical panel 200, and includes a comparison circuit 50, a determination circuit 56, and a potential setting circuit 60.

[0029] The comparison circuit 50 compares the voltage of the monitor signal SM with a reference voltage VR. That is, the signal lines L1, L2 to which one end of the display electrode EL is connected are wired in the electro-optical panel 200. Moreover, the drive signal SD from the driver circuit 30 is output to the display electrode EL via the signal line L1, and the monitor signal SM from the display electrode EL is input to the inspection circuit 40 via the signal line L2. The inspection circuit 40 inspects whether an abnormality of the signal line is detected based on the monitor signal SM fed back from the display electrode EL driven by the drive signal SD. Specifically, the comparison circuit 50 of the inspection circuit 40 compares the voltage of the input monitor signal SM with the reference voltage VR, outputs a signal CQ indicating the comparison result, and the determination circuit 56 detects an abnormality based on the comparison result. The reference voltage VR is a threshold voltage for determination, and can be, for example, a voltage that is approximately halfway between the potentials of the high level and the low level of the monitor signal SM. In this case, the comparison circuit 50 can also compare two or more reference voltages VR with the voltage of the monitor signal SM. For example, the comparison circuit 50 can also perform comparison of the voltage of the monitor signal SM with a reference voltage on the high potential side and comparison of the voltage of the monitor signal SM with a reference voltage on the low potential side, and output the comparison results. Note that the connection in the present embodiment is an electrical connection. The electrical connection is a connection in a manner that enables transmission of an electrical signal, and is a connection that enables transmission of information based on an electrical signal. The electrical connection can also be a connection via a passive element or the like.

[0030] The determination circuit 56 determines abnormality based on the expected value EV corresponding to the voltage level of the drive signal SD and the comparison result of the comparison circuit 50. For example, the determination circuit 56 determines drive abnormality in which the drive of the display electrode EL becomes abnormal. For example, the determination circuit 56 determines abnormality of the signal line. Further, the determination circuit 56 outputs a signal JQ indicating the determination result of abnormality. For example, the determination circuit 56 determines whether or not an abnormal state such as disconnection or short-circuit of the signal line Ll, L2 occurs based on the signal of the expected value EV and the signal CQ from the comparison circuit 50, and outputs the signal JQ indicating that such abnormality occurs. The expected value EV is a value expected as the voltage level of the signal output as the drive signal SD by the driver circuit 30. For example, the expected value EV is a value becoming the first logic level in the case where the driver circuit 30 outputs the drive signal SD of the high level, and becoming the second logic level in the case where the driver circuit 30 outputs the drive signal SD of the low level. Hereinafter, the first logic level is described as the high level, and the second logic level is described as the low level. However, the first logic level can be the low level, and the second logic level can be the high level. Further, the high level of the drive signal SD of the driver circuit 30 corresponds to, for example, the high level of the drive power voltage for driving the electro-optical panel 200, and the high level of the expected value EV corresponds to, for example, the high level of the logic power voltage.

[0031] The potential setting circuit 60 sets the potential of the signal line L2 of the monitoring signal SM in correspondence with the voltage level of the drive signal SD. For example, the potential setting circuit 60 performs pull-down or pull-up of the signal line L2 of the monitoring signal SM in correspondence with the voltage level of the drive signal SD. For example, the potential setting circuit 60 performs pull-down or pull-up of the signal line L2 of the monitoring signal SM depending on whether the drive signal SD is the high level or the low level. The signal line L2 is a signal line of which one end is connected to the display electrode EL to which the drive signal SD is input to the driver circuit 30, and is a signal line in which the monitoring signal SM of which the voltage level corresponding to the drive signal SD is expected to be transmitted. In this case, for example, when disconnection or the like of the signal line LI of the drive signal SD occurs, the monitoring signal SM of which the voltage level corresponding to the drive signal SD is not transmitted to the signal line L2, and the potential of the signal line L2 becomes unstable, and it is likely that a situation in which the determination circuit 56 cannot accurately detect abnormality occurs. In view of this, in the present embodiment, the potential setting circuit 60 sets the potential of the signal line L2 of the monitoring signal SM in correspondence with the voltage level of the drive signal SD, and performs, for example, pull-down or pull-up of the signal line L2. Thereby, it is possible to prevent a situation in which the potential of the signal line L2 becomes unstable and the determination circuit 56 cannot accurately detect abnormality.

[0032] Thus, the display driver 20 of the present embodiment includes the driver circuit 30, an output terminal TQ that outputs the drive signal SD from the driver circuit 30 to the display electrode EL, an input terminal TI that inputs the monitor signal SM from the display electrode EL, and the inspection circuit 40. Further, the comparison circuit 50 of the inspection circuit 40 compares the voltage of the monitor signal SM with the reference voltage VR, and the determination circuit 56 makes a determination of a disconnection or the like based on the expected value EV corresponding to the voltage level of the drive signal SD and the comparison result of the comparison circuit 50. Further, the potential setting circuit 60 performs pull-down or pull-up of the signal line L2 of the monitor signal SM in correspondence with the voltage level of the drive signal SD. Thus, for example, in a case where a disconnection or the like of the signal line LI occurs and the potential of the signal line L2 can become unstable, the potential setting circuit 60 also performs pull-down or pull-up of the signal line L2 of the monitor signal SM in correspondence with the voltage level of the drive signal SD, whereby the potential of the signal line L2 is set to the low level or the high level. Thus, it is possible to prevent a situation where the determination circuit 56 fails to accurately detect an abnormality.

[0033] Specifically, the potential setting circuit 60 performs pull-down of the signal line L2 of the monitor signal SM when the drive signal SD output from the driver circuit 30 is at the high level, and performs pull-up of the signal line L2 of the monitor signal SM when the drive signal SD is at the low level. For example, when a disconnection or the like of the signal line LI of the drive signal SD occurs, the signal line L2 of the monitor signal SM becomes a state where it is not driven by the driver circuit 30, and thus the signal line L2 becomes a high-impedance state and the potential of the monitor signal SM becomes unstable. Thus, depending on the potential of the surrounding wiring, the potential of the monitor signal SM is adversely affected due to coupling of a parasitic inter-wiring capacitance or the like.

[0034] For example, assume that the display electrode ELB in the vicinity of the display electrode EL is driven by the drive signal SDB via the signal line LB. At this time, the signal waveform of the drive signal SDB of the display electrode ELB can be the same signal waveform as the drive signal SD of the display electrode EL. For example, in a case where both the display electrode EL and the display electrode ELB are lit, or in a case where both the display electrode EL and the display electrode ELB are not lit, the drive signal SD and the drive signal SDB become the same signal waveform. Also, the signal line LB of the drive signal SDB is wired in the vicinity of the signal line L2 of the monitoring signal SM of the drive signal SD. Then, the monitoring signal SM whose potential becomes unstable due to a disconnection or the like is affected by the drive signal SDB of the signal line LB in the vicinity, and changes in potential in the same manner as the potential change of the drive signal SDB. For example, due to coupling of a wiring capacitance between the signal line L2 and the signal line LB, when the drive signal SDB becomes a high level, the monitoring signal SM also becomes a high level, and when the drive signal SDB becomes a low level, the monitoring signal SM also becomes a low level. As a result, the following situation occurs: although a disconnection or the like abnormality occurs in the signal line LI of the drive signal SD, the inspection circuit 40 cannot accurately detect the abnormality.

[0035] That is, in a case where the monitoring signal SM becomes a high level when the drive signal SD is a high level, and the monitoring signal SM becomes a low level when the drive signal SD is a low level, without an abnormality such as a disconnection occurring, the inspection circuit 40 determines that the comparison result of the comparison circuit 50 is consistent with the expected value, and determines that no abnormality has occurred. However, the monitoring signal SM whose potential becomes unstable due to a disconnection or the like is affected by the drive signal SDB of the signal line LB in the vicinity of the signal line L2. For example, if the drive signal SDB also becomes a high level when the drive signal SD becomes a high level, due to coupling of a parasitic wiring capacitance between the signal line LB and the signal line L2, the monitoring signal SM in a high impedance state also becomes a high level. Also, if the drive signal SDB also becomes a low level when the drive signal SD becomes a low level, due to coupling of a parasitic wiring capacitance between the signal line LB and the signal line L2, the monitoring signal SM in a high impedance state also becomes a low level. Thus, although an abnormality such as a disconnection occurs, it is determined that the monitoring signal SM changes in the same manner as the expected value, and thus the inspection circuit 40 can fail to accurately detect the abnormality.

[0036] In this regard, in the present embodiment, the potential setting circuit 60 performs pull-down of the signal line L2 of the monitoring signal SM when the drive signal SD is at the high level, and performs pull-up of the signal line L2 of the monitoring signal SM when the drive signal SD is at the low level. Thus, when both the drive signal SD and the nearby drive signal SDB are at the high level, the potential setting circuit 60 performs pull-down of the signal line L2, whereby it is possible to prevent the potential of the monitoring signal SM from being pulled to the high level side due to coupling of the inter-wiring capacitance. Further, when both the drive signal SD and the nearby drive signal SDB are at the low level, the potential setting circuit 60 performs pull-up of the signal line L2, whereby it is possible to prevent the potential of the monitoring signal SM from being pulled to the low level side due to coupling of the inter-wiring capacitance. Thus, it is possible to prevent a situation in which the inspection circuit 40 fails to accurately detect an abnormality such as a disconnection.

[0037] Figure 2 Detailed structure examples of the display driver 20, the display device 10 of the present embodiment are shown. In the present embodiment, the display device 10 includes the display driver 20, the electro-optical panel 200, and the processing device 300. In addition, the display driver 20, the display device 10 are not limited to the structure shown in the present embodiment, and various modifications such as omission of a part of the structure elements, addition of other structure elements, replacement of a part of the structure elements with other structure elements, and the like can be implemented. Figure 2 Figure 2

[0038] The electro-optical panel 200 is, for example, a panel driven in a static drive manner. Specifically, the electro-optical panel 200 includes a first glass substrate, a second glass substrate, and liquid crystal. The liquid crystal as an electro-optical element is enclosed between the first glass substrate and the second glass substrate. A segment electrode is provided on the first glass substrate, and a common electrode is provided on the second glass substrate. The display driver 20 outputs a segment drive signal to the segment electrode. Also, the display driver 20 outputs a common drive signal to the common electrode. Thus, a potential difference between the segment drive signal and the common drive signal, that is, a drive signal is applied to the liquid crystal between the segment electrode and the common electrode. The segment electrode and the common electrode are transparent electrodes, for example, ITO (Indium Tin Oxide). In addition, hereinafter, a case where the electro-optical panel 200 is a segment liquid crystal panel having a segment electrode and a common electrode as display electrodes EL as such is mainly described as an example, but the present embodiment is not limited thereto.

[0039] The processing device 300 is, for example, a host device of the display driver 20, and is realized by, for example, a processor or a display controller, or the like. The processor is a CPU or a microcomputer, or the like. In addition, the processing device 300 can also be a circuit device constituted by a plurality of circuit components. For example, in a vehicle-mounted electronic device, the processing device 300 can be an ECU (Electronic Control Unit).​​

[0040] The display driver 20 includes a segment driver circuit 31, a common driver circuit 32, a segment inspection circuit 41, a common inspection circuit 42, a row latch 70, a data storage circuit 80, a control circuit 100, an interface circuit 110, and an oscillation circuit 120. The segment driver circuit 31 and the common driver circuit 32 correspond to the driver circuit 30 of Figure 1 , respectively. The segment inspection circuit 41 and the common inspection circuit 42 correspond to the inspection circuit 40 of Figure 1 , respectively. That is, in this case, the display driver 20 has a plurality of inspection circuits 40.

[0041] The segment driver circuit 31 outputs a segment drive signal to the segment electrode of the electro-optical panel 200. For example, the segment driver circuit 31 drives the electro-optical panel 200 by a static drive method or a duty drive method, or the like. For example, the display driver 20 has an output terminal that outputs the segment drive signal to the segment electrode of the electro-optical panel 200. In this case, Figure 1 the drive signal SD, the display electrode EL, and the output terminal TQ correspond to the above-described segment drive signal, the segment electrode, and the output terminal of the segment drive signal, respectively.

[0042] The common driver circuit 32 outputs a common drive signal to the common electrode of the electro-optical panel 200. For example, the display driver 20 has an output terminal that outputs the common drive signal to the common electrode of the electro-optical panel 200. In this case, Figure 1 the drive signal SD, the display electrode EL, and the output terminal TQ correspond to the above-described common drive signal, the common electrode, and the output terminal of the common drive signal, respectively. That is, in this case, the display driver 20 has a plurality of output terminals TQ.

[0043] The segment inspection circuit 41 is a circuit that inspects an abnormality of a signal line or the like of the segment electrode. For example, the segment inspection circuit 41 inspects whether or not a wire breakage, a short circuit, or the like has occurred in the signal line or the like of the segment electrode. The common inspection circuit 42 is a circuit that inspects an abnormality of a signal line or the like of the common electrode. For example, the common inspection circuit 42 inspects whether or not a wire breakage, a short circuit, or the like has occurred in the signal line or the like of the common electrode. These segment inspection circuit 41 and common inspection circuit 42 correspond to the inspection circuit 40 of Figure 1 , respectively. That is, in this case, the display driver 20 has a plurality of inspection circuits 40.

[0044] The data storage circuit 80 is a circuit that stores data for display, and can be implemented by a memory such as a RAM, for example. The data storage circuit 80 stores data for display of the electro-optical panel 200. The data for display is, for example, on-off data or gradation data of display of a display object corresponding to the segment electrodes, and the like. The data for display is received from the processing device 300 via the interface circuit 110, for example, and stored in the data storage circuit 80.

[0045] The row latch 70 latches the data for display from the data storage circuit 80. The row latch 70 as a data latch latches the data for display from the data storage circuit 80 based on a latch signal from the control circuit 100, for example. Then, the segment driver circuit 31 generates and outputs a segment drive signal based on the data latched in the row latch 70. The row latch 70 is implemented by a flip-flop circuit or the like.

[0046] The control circuit 100 is a logic circuit that operates based on a clock signal from the oscillation circuit 120, for example. The control circuit 100 can be implemented by a circuit of an ASIC (Application Specific Integrated Circuit) that automatically configures a wiring based on a gate array or the like, or a processor such as a CPU, for example. The control circuit 100 performs control of display timing, setting of operation of the display driver 20, and the like.

[0047] The interface circuit 110 is a circuit that becomes an interface with the processing device 300 outside, and performs communication processing between the processing device 300 and the display driver 20. The interface circuit 110 receives various data such as data of an instruction, display data, and the like from the processing device 300, for example. The interface circuit 110 can be implemented by a serial interface circuit such as an I2C (Inter Integrated Circuit) method, an SPI (Serial Peripheral Interface) method, or the like, for example.

[0048] The oscillation circuit 120 generates an oscillation signal, and outputs a clock signal based on the oscillation signal. The clock signal is used for operation of each circuit of the display driver 20 such as the control circuit 100.

[0049] Figure 3 is an example of a configuration of segment electrodes of the electro-optical panel 200 and a wiring of segment signal lines, Figure 4 is an example of a configuration of a common electrode and a wiring of a common signal line.

[0050] In Figure 3In the electro-optic panel 200, segmented electrodes ES1 to ES7 and segmented signal lines LS1 to LS14 are provided. Furthermore, the segmented terminals TS1 and TS2 of the display driver 20 are connected to the segmented electrode ES1 via the segmented signal lines LS1 and LS2, respectively. Similarly, the segmented terminals TS3 and TS4 of the display driver 20 are connected to the segmented electrode ES2 via the segmented signal lines LS3 and LS4, respectively. The connections between the segmented terminals TS5 to TS14 and the segmented electrodes ES3 to ES7 via the segmented signal lines LS5 to LS14 are also similar. Figure 3 The segmented terminals TS1, TS3, TS5, TS7, TS9, TS11, and TS13 are respectively connected to the output... Figure 1 The output terminal TQ of the drive signal SD corresponds to this. Furthermore, the segment terminals TS2, TS4, TS6, TS8, TS10, TS12, and TS14 correspond to the input terminal TI of the input monitoring signal SM. Additionally, in Figure 3 The example shown is a 7-segment display electrode, but there are various other types of segmented electrodes, such as those with warning lights or other icons.

[0051] exist Figure 4 In this design, common electrodes EC1 to EC7 and common signal lines LC1 and LC2 are provided on the electro-optic panel 200. Furthermore, the common terminals TC1 and TC2 of the display driver 20 are connected to the common electrodes EC1 to EC7 via the common signal lines LC1 and LC2, respectively. Figure 4 Common terminal TC1 and output Figure 1 The output terminal TQ of the drive signal SD corresponds to this. Additionally, the common terminal TC2 corresponds to the input terminal TI of the input monitoring signal SM.

[0052] 2. Inspect the circuit and driver circuit.

[0053] Figure 5 , Figure 6 A detailed structural example of the inspection circuit 40 and the driver circuit 30 is shown. Figure 5 The inspection circuit 40 and the driver circuit 30 are respectively Figure 2 Example of the structure in the case of segmented inspection circuit 41 and segmented driver circuit 31. Figure 6 The inspection circuit 40 and the driver circuit 30 are respectively Figure 2 Example of a structure with common check circuit 42 and common driver circuit 32. Therefore, in Figure 5 In this circuit, the driver circuit 30 outputs a segmentation drive signal SD based on display data from the data storage circuit 80. Conversely, in... Figure 6In the present embodiment, the driver circuit 30 is not inputted with such display data, but outputs a common drive signal SD based on the control of the control circuit 100. Hereinafter, the description will be mainly made with the structure of the driver circuit 30 as an example for the sake of simplification of the description. Figure 5

[0054] The polarity inversion circuit 74 performs polarity inversion processing of the segmented display data read out from the data storage circuit 80 based on a polarity signal inputted from the control circuit 100. For example, the polarity inversion circuit 74 outputs data DI of the same logic level as the display data in a frame of positive polarity, and outputs data DI in which the logic level of the display data is inverted in a frame of negative polarity. The latch 72 latches the data DI from the polarity inversion circuit 74 based on a latch signal LT from the control circuit 100. The latch 72 is a latch constituting the row latch 70, and is realized by, for example, a flip-flop circuit or the like. Figure 2

[0055] The driver circuit 30 includes a level shifter 36 and an output driver 34. The level shifter 36 is inputted with the latched data DQ from the latch 72, and performs level shifting of the signal of the data DQ. For example, the level shifter 36 performs level shifting from a logic power supply voltage level to a drive power supply voltage level of the electro-optical panel 200. Further, the output driver 34 outputs a drive signal SD based on the display signal subjected to level shifting by the level shifter 36.

[0056] The inspection circuit 40 includes a comparison circuit 50, a determination circuit 56, a reference voltage generation circuit 58, a potential setting circuit 60, and a switch SW. The comparison circuit 50 includes a comparator 52 and a level shifter 54.

[0057] The switch SW is on when the determination mode in which the determination of the drive abnormality is performed by the inspection circuit 40. By this, the monitor signal SM from the display electrode EL is inputted to the comparator 52 of the comparison circuit 50 via the on switch SW.

[0058] ​​The reference voltage generation circuit 58 generates reference voltages VRH, VRL based on the power supply voltages of VCC, VSS. VCC is a drive power supply voltage of the high potential side of the electro-optical panel 200, and VSS is a power supply voltage of the low potential side. For example, the reference voltage generation circuit 58 is configured by a ladder resistance circuit having a plurality of resistors connected in series with a node of VCC and a node of VSS, and generates the reference voltages VRH, VRL by dividing the voltage based on the plurality of resistors. The reference voltage VRH is a reference voltage of the VCC side, i.e., the high potential side, and the reference voltage VRL is a reference voltage of the VSS side, i.e., the low potential side. The reference voltage VRH is a voltage of, for example, 60% to 90% or so of VCC, and the reference voltage VRL is a voltage of, for example, 10% to 40% or so of VCC. As an example, the reference voltage VRH is a voltage of, for example, 70% or so of VCC, and the reference voltage VRL is a voltage of, for example, 30% or so of VCC.

[0059] Further, the comparator 52 of the comparison circuit 50 compares the voltage of the monitor signal SM from the display electrode EL with the reference voltages VRH, VRL, and the comparison result is output from the comparison circuit 50 as a signal CQ via the level shifter 54. The level shifter 54 performs level shifting from the drive power supply voltage level of the electro-optical panel 200 to the logic power supply voltage level. For example, in the case where the voltage of the monitor signal SM is higher than the reference voltage VRH of the high potential side, the comparison circuit 50 outputs the signal CQ as a first logic level of the high level. Further, in the case where the voltage of the monitor signal SM is lower than the reference voltage VRL of the low potential side, the comparison circuit 50 outputs the signal CQ as a second logic level of the low level. Further, in the case where the voltage of the monitor signal SM is a voltage between the reference voltage VRH of the high potential side and the reference voltage VRL of the low potential side, the comparison circuit 50 can also output the signal CQ indicating a check error.

[0060] The data DQ from the latch 72 is input to the determination circuit 56 as the expected value EV. For example, in the case where the driver circuit 30 outputs the drive signal SD of the high level, the expected value EV of the high level is input to the determination circuit 56. In addition, in the case where the driver circuit 30 outputs the drive signal SD of the low level, the expected value EV of the low level is input to the determination circuit 56. Then, the determination circuit 56 compares the expected value EV with the signal CQ of the comparison result from the comparison circuit 50, and determines whether or not an abnormality has occurred.

[0061] For example, in the case where the drive signal SD is the high level and the expected value EV is the high level, the voltage of the monitor signal SM is higher than the reference voltage VRH and the signal CQ is the high level, the determination circuit 56 determines that no abnormality has occurred. On the other hand, in the case where the signal CQ is the low level in the signal in which the expected value EV is the high level or the signal indicating a detection error, it is determined that an abnormality has occurred.

[0062] Furthermore, when the drive signal SD is low and the desired value EV is low, and the voltage of the monitoring signal SM is lower than the reference voltage VRL and the signal CQ is low, the determination circuit 56 determines that no abnormality has occurred. On the other hand, when the desired value EV is low and the signal CQ is high, or when it indicates a detection error, an abnormality is determined to have occurred.

[0063] Thus, when the driver circuit 30 outputs a high-level drive signal SD to the display electrode EL and the voltage of the monitoring signal SM from the display electrode EL is the voltage corresponding to the high level, the determination circuit 56 can determine that no abnormality has occurred. Similarly, when the driver circuit 30 outputs a low-level drive signal SD to the display electrode EL and the voltage of the monitoring signal SM from the display electrode EL is the voltage corresponding to the low level, the determination circuit 56 can also determine that no abnormality has occurred.

[0064] 3. Potential setting circuit

[0065] Next, the structure and operation of the potential setting circuit 60 in this embodiment will be described in detail. Figure 7 , Figure 8 , Figure 9 A diagram illustrating the structure and operation of the potential setting circuit 60.

[0066] exist Figure 7 In the circuit, the potential setting circuit 60 includes a pull-up resistor RU and a switch SWU, and a pull-down resistor RD and a switch SWD. The pull-up resistor RU and the switch SWU are connected in series between the node of the power supply voltage VCC on the high potential side and the node N1 of the signal line L2 of the monitoring signal SM. The pull-down resistor RD and the switch SWD are connected in series between the node of the power supply voltage VSS on the low potential side and the node N1 of the signal line L2 of the monitoring signal SM.

[0067] Additionally, the reference voltage generation circuit 58 includes resistors RA1 and RA2 connected in series between the node of the power supply voltage VCC on the high-potential side and the node of the power supply voltage VSS on the low-potential side. Furthermore, a reference voltage VR is generated and output at the connection node N2 of resistors RA1 and RA2. Moreover, as... Figure 5 , Figure 6 As shown, in order to accurately detect anomalies, it is preferable to generate two reference voltages VRH and VRL on the high potential side and the low potential side. However, for the sake of simplicity, the following explanation will mainly focus on the case where there is only one reference voltage VR.

[0068] The driver circuit 30 includes a prebuffer circuit 33 composed of an inverter circuit and an output driver 34 that outputs a drive signal SD input with an output signal of the prebuffer circuit 33.

[0069] For example, in Figure 8 , the driver circuit 30 outputs a high-level drive signal SD, but a wire break occurs in the signal line Ll. Due to this wire break, the signal line L2 of the monitoring signal SM is no longer driven by the driver circuit 30, and thus, if the potential setting circuit 60 is not provided, the potential of the monitoring signal SM becomes unstable.

[0070] In this regard, in the present embodiment, when the drive signal SD output by the driver circuit 30 is high, the switch SWD for pull-down of the potential setting circuit 60 is turned on. By thus turning on the switch SWD, the signal line L2 of the monitoring signal SM is pulled down to low by the resistance RD for pull-down. Also, when the monitoring signal SM pulled down to low is input, since the voltage of the monitoring signal SM is lower than the reference voltage VR, the comparison circuit 50 outputs a signal CQ indicating low as a comparison result. On the other hand, when the drive signal SD is high, the expected value EV indicating high is input to the determination circuit 56. Due to this, the level of the signal CQ of the comparison result does not coincide with the expected value EV, and thus the determination circuit 56 determines that an abnormality has occurred. Thus, the wire break of the signal line Ll can be appropriately determined as an abnormality.

[0071] Also, in Figure 9 , the driver circuit 30 outputs a low-level drive signal SD, but a wire break occurs in the signal line Ll. Due to this wire break, the signal line L2 of the monitoring signal SM is no longer driven by the driver circuit 30, and thus, if the potential setting circuit 60 is not provided, the potential of the monitoring signal SM becomes unstable.

[0072] In this regard, in the present embodiment, when the drive signal SD output by the driver circuit 30 is low, the switch SWU for pull-up of the potential setting circuit 60 is turned on. By thus turning on the switch SWU, the signal line L2 of the monitoring signal SM is pulled up to high by the resistance RU for pull-up. Also, when the monitoring signal SM pulled up to high is input, since the voltage of the monitoring signal SM is higher than the reference voltage VR, the comparison circuit 50 outputs a signal CQ indicating high as a comparison result. On the other hand, when the drive signal SD is low, the expected value EV indicating low is input to the determination circuit 56. Due to this, the level of the signal CQ of the comparison result does not coincide with the expected value EV, and thus the determination circuit 56 determines that an abnormality has occurred. Thus, the wire break of the signal line Ll can be appropriately determined as an abnormality.

[0073] As described above, the potential setting circuit 60 includes: a resistance RU and a switch SWU for pull-up, which are connected in series between a node of the high potential side power supply voltage VCC and a node Nl of the signal line L2 of the monitoring signal SM; and a resistance RD and a switch SWD for pull-down, which are connected in series between a node of the low potential side power supply voltage VSS and the node Nl of the signal line L2 of the monitoring signal SM. Thus, for example, the switch SWD for pull-down is turned on in accordance with the control signal SC2 from the control circuit 100, whereby the signal line L2 of the monitoring signal SM can be pulled down by the resistance RD for pull-down. Further, the switch SWU for pull-up is turned on in accordance with the control signal SCI from the control circuit 100, whereby the signal line L2 of the monitoring signal SM can be pulled up by the resistance RU for pull-up. Therefore, even in a case where the potential of the signal line L2 becomes unstable due to an abnormality such as disconnection of the signal line LI, for example, the signal line L2 of the monitoring signal SM can be pulled down or pulled up by the switch SWD for pull-down or the switch SWU for pull-up being turned on. Thus, it is possible to prevent a situation where an abnormality cannot be accurately detected in the determination circuit 56.

[0074] Further, the switch SWD for pull-down is turned on when the drive signal SD is at the high level, and the switch SWU for pull-up is turned on when the drive signal SD is at the low level.

[0075] Thus, when the drive signal SD of the driver circuit 30 is at the high level, the switch SWD for pull-down is turned on, whereby the signal line L2 of the monitoring signal SM is pulled down and thus set to the low level. Thus, the comparison circuit 50 outputs a comparison result corresponding to the low level. Further, when the drive signal SD is at the high level, the determination circuit 56 is input with the expected value EV corresponding to the high level, and thus an abnormality can be accurately detected. Further, when the drive signal SD of the driver circuit 30 is at the low level, the switch SWU for pull-up is turned on, whereby the signal line L2 of the monitoring signal SM is pulled up and thus set to the high level. Thus, the comparison circuit 50 outputs a comparison result corresponding to the high level. Further, when the drive signal SD is at the low level, the determination circuit 56 is input with the expected value EV corresponding to the low level, and thus an abnormality can be accurately detected.

[0076] Further, the resistance values of the resistance RD for pull-down and the resistance RU for pull-up are higher than the on-resistance values of the drive transistors of the driver circuit 30. For example, the drive transistors are MOS transistors, and the resistance values of the resistance RD for pull-down and the resistance RU for pull-up are higher than the on-resistance values of the MOS transistors. Figures 7-9The output driver 34 of the driver circuit 30 uses a P-type or N-type transistor. For example, in normal operation without any abnormalities, when the drive signal SD is high, if the pull-down switch SWD is turned on, the drive signal SD is pulled down to a low potential side via the pull-down resistor RD. Furthermore, when the drive signal SD is low, if the pull-up switch SWU is turned on, the drive signal SD is pulled up to a high potential side via the pull-up resistor RU. In this case, if the resistance values ​​of the pull-down resistor RD and the pull-up resistor RU are lower than the on-resistance value of the driver transistor in the driver circuit 30, it may adversely affect the driving of the display electrode EL based on the drive signal SD. In this embodiment, the resistance values ​​of the pull-down resistor RD and the pull-up resistor RU are higher than the on-resistance value of the driver transistor in the driver circuit 30, for example, set to a resistance value that is 2 to 10 times higher. As an example, the on-resistance of the driving transistor is approximately 1kΩ to several kΩ, and the resistance values ​​of resistors RD and RU are approximately several tens of kΩ to several hundred kΩ. In this way, even when the driving signal SD is high and pulled down by the pull-down resistor RD, or when the driving signal SD is low and pulled up by the pull-up resistor RU, the adverse effects on the driving of the display electrode EL can be sufficiently reduced.

[0077] Figure 10 Other structural examples of the potential setting circuit 60 are shown. Figure 10 In, replacing Figures 7-9 The voltage setting circuit 60 includes a pull-up resistor RU and a switch SWU, a pull-down resistor RD and a switch SWD, and a pull-up transistor TRU and a pull-down transistor TRD. The on-resistance values ​​of transistor TRU and transistor TRD are higher than those of the driving transistors in the driver circuit 30, just as those of resistors RD and RU. The pull-up transistor TRU is located between the node of the high-potential power supply voltage VCC and the node N1 of the signal line L2 of the monitoring signal SM. For example, in a P-type pull-up transistor TRU, the source is connected to the node of VCC, the drain is connected to node N1, and the gate is input with the control signal SC1. Similarly, the pull-down transistor TRD is located between the node of the low-potential power supply voltage VSS and the node N1 of the signal line L2 of the monitoring signal SM. For example, in an N-type pull-down transistor TRD, the source is connected to the node of VSS, the drain is connected to node N1, and the gate is input with the control signal SC2.

[0078] Furthermore, when the drive signal SD is high, the pull-down transistor TRD is turned on according to the control signal SC2 from the control circuit 100, pulling down the signal line L2 of the monitoring signal SM. As a result, the comparator circuit 50 outputs a signal CQ indicating a low level. Moreover, when the drive signal SD is high, the desired value EV indicating a high level is input to the determination circuit 56. Since this value is inconsistent with the signal CQ indicating a low level, an anomaly is appropriately determined.

[0079] Furthermore, when the drive signal SD is low, the pull-up transistor TRU is turned on according to the control signal SC1 from the control circuit 100, pulling up the signal line L2 of the monitoring signal SM. As a result, the comparator circuit 50 outputs a signal CQ indicating a high level. Moreover, when the drive signal SD is low, the expected value EV indicating a low level is input to the determination circuit 56. Since this value is inconsistent with the signal CQ indicating a high level, an anomaly is appropriately determined.

[0080] Thus, the potential setting circuit 60 includes: a pull-up transistor TRU, which is disposed between the node of the power supply voltage VCC on the high potential side and the node N1 of the signal line L2 of the monitoring signal SM; and a pull-down transistor TRD, which is disposed between the node of the power supply voltage VSS on the low potential side and the node N1 of the signal line L2 of the monitoring signal SM.

[0081] Thus, for example, the pull-down transistor TRD is turned on according to the control signal SC2 from the control circuit 100, thereby pulling down the signal line L2 of the monitoring signal SM. Similarly, the pull-up transistor TRU is turned on according to the control signal SC1 from the control circuit 100, thereby pulling up the signal line L2 of the monitoring signal SM. Therefore, even if an abnormality such as a break in signal line L1 occurs and the potential of signal line L2 becomes unstable, the signal line L2 of the monitoring signal SM can be pulled down or pulled up by turning on the pull-down transistor TRD or the pull-up transistor TRU. This prevents situations where abnormalities cannot be accurately detected in the determination circuit 56.

[0082] Figure 11 This is a signal waveform diagram illustrating the operation of this embodiment. For example... Figure 11 As shown in A1 and A2, the data DI used for display is latched. Figure 5 The data is stored in latch 72 and output as data DQ to driver circuit 30. Thus, as shown in A3 and A4, drive signal SD is output to display electrode EL, and monitoring signal SM corresponding to drive signal SD is input to comparison circuit 50 of check circuit 40.

[0083] That is, as shown in A3, in the case where the drive signal SD is at the low level, the monitor signal SM is also at the low level, and as shown in A4, in the case where the drive signal SD is at the high level, the monitor signal SM is also at the high level. Also, in the case where the drive signal SD is at the low level, the switch SWU of the potential setting circuit 60 is turned on, and the signal line L2 of the monitor signal SM is pulled up, but since the on-resistance value of the N-type drive transistor of the driver circuit 30 is sufficiently lower than the resistance value of the resistor RU, the low level of the monitor signal SM is maintained. Further, in the case where the drive signal SD is at the high level, the switch SWD of the potential setting circuit 60 is turned on, and the signal line L2 of the monitor signal SM is pulled down, but since the on-resistance value of the P-type drive transistor of the driver circuit 30 is sufficiently lower than the resistance value of the resistor RD, the high level of the monitor signal SM is maintained. Figure 7

[0084] Further, in A5, the voltage of the monitor signal SM is lower than the reference voltage VRL (or VR), and thus the signal CQ output from the comparison circuit 50 becomes at the low level. Further, in A6, since the voltage of the monitor signal SM is higher than the reference voltage VRH (or VR), the signal CQ becomes at the high level. Also, in the cases of A5 and A6, the voltage level of the expected value EV corresponding to DQ and the voltage level of the signal CQ coincide with each other, and thus, as shown in A7 and A8, the signal JQ of the determination result of the determination circuit 56 becomes at the voltage level (for example, the low level) indicating that no abnormality has occurred.

[0085] Further, in A9, a disconnection of the signal line Ll and the like has occurred. When such a disconnection occurs, the signal line L2 of the monitor signal SM becomes in a state not driven by the driver circuit 30, and thus, the signal line L2 becomes in a high-impedance state. Also, when the signal line in the vicinity of the signal line L2 is driven by a drive signal identical to the drive signal SD, if the drive signal of the signal line in the vicinity becomes at the high level, the monitor signal SM also becomes at the high level due to the coupling of the inter-wiring capacitance. Further, if the drive signal of the signal line in the vicinity becomes at the low level, the monitor signal SM also becomes at the low level due to the coupling of the inter-wiring capacitance. As a result, the voltage level of the monitor signal SM coincides with the expected value EV, and the determination circuit 56 can determine that no abnormality has occurred. Figure 11

[0086] In this regard, in the present embodiment, as shown in A10, in the case where the drive signal SD is at the high level, the monitor signal SM is also at the high level, and as shown in A11, in the case where the drive signal SD is at the low level, the monitor signal SM is also at the low level. Also, in the case where the drive signal SD is at the low level, the switch SWU of the potential setting circuit 60 is turned on, and the signal line L2 of the monitor signal SM is pulled up, but since the on-resistance value of the N-type drive transistor of the driver circuit 30 is sufficiently lower than the resistance value of the resistor RU, the low level of the monitor signal SM is maintained. Further, in the case where the drive signal SD is at the high level, the switch SWD of the potential setting circuit 60 is turned on, and the signal line L2 of the monitor signal SM is pulled down, but since the on-resistance value of the P-type drive transistor of the driver circuit 30 is sufficiently lower than the resistance value of the resistor RD, the high level of the monitor signal SM is maintained. Figure 7 ​​When switch SWD is turned on, signal line L2, which is in a high-impedance state, is pulled down. As a result, as shown in A11, the voltage of monitoring signal SM becomes low, and as shown in A12, the comparison result signal CQ of comparator circuit 50 also becomes low. Therefore, the high voltage level of the expected value EV of drive signal SD is inconsistent with the low voltage level of signal CQ, and thus, as shown in A13, the determination result signal JQ of determination circuit 56 becomes a voltage level indicating an abnormality (e.g., a high level).

[0087] Similarly, as shown in A14, when the drive signal SD is low, Figure 7 When switch SWU is turned on, signal line L2, which is in a high-impedance state, is pulled up. As a result, as shown in A15, the voltage of monitoring signal SM becomes high, and as shown in A16, signal CQ of comparator circuit 50 also becomes high. Therefore, the low voltage level of the expected value EV of drive signal SD is inconsistent with the high voltage level of signal CQ. Consequently, as shown in A17, signal JQ, representing the determination result of determination circuit 56, becomes a voltage level indicating an abnormality.

[0088] Thus, in this embodiment, when the comparison result of the comparison circuit 50 is not the comparison result corresponding to the expected value EV, the determination circuit 56 determines that a break in the signal line L1 of the drive signal SD has occurred. For example, in Figure 11 In A12 and A13, the voltage level of signal CQ, which is the comparison result of comparator circuit 50, is low, and the voltage level of the expected value EV of drive signal SD is high. Therefore, determination circuit 56 determines that an abnormality such as a broken wire has occurred. Furthermore, in A16 and A17, the voltage level of signal CQ, which is high, of comparator circuit 50 is low, and the voltage level of the expected value EV of drive signal SD is low. Therefore, determination circuit 56 determines that an abnormality such as a broken wire has occurred. Thus, determination circuit 56 can determine whether an abnormality such as a broken wire has occurred in signal line L1 of drive signal SD simply by determining whether the comparison result of comparator circuit 50 is consistent with the expected value EV corresponding to the voltage level of drive signal SD. Moreover, in this embodiment, even if the potential of signal line L2 becomes unstable due to a broken wire in signal line L1, the potential setting circuit 60 will pull down when drive signal SD is high and pull up when drive signal SD is low. Therefore, the determination circuit 56, which determines whether the comparison result of the comparison circuit 50 is consistent with the expected value EV, can prevent the situation where the circuit breakage occurs from being detected accurately, as described above.

[0089] As explained above, the display driver of the present embodiment includes a driver circuit that outputs a drive signal, an output terminal that outputs the drive signal to a display electrode of an electro-optical panel, an input terminal to which a monitor signal is input from the display electrode, and a check circuit. Also, the check circuit includes a comparison circuit that compares a voltage of the monitor signal with a reference voltage, a determination circuit that makes a determination of an abnormality based on an expected value corresponding to a voltage level of the drive signal and a comparison result of the comparison circuit, and a potential setting circuit that performs pull-down or pull-up of a signal line of the monitor signal in correspondence with the voltage level of the drive signal.

[0090] According to the present embodiment, the comparison circuit of the check circuit compares the voltage of the monitor signal with the reference voltage, the determination circuit makes a determination of an abnormality such as disconnection based on the expected value corresponding to the voltage level of the drive signal and the comparison result of the comparison circuit. Also, the potential setting circuit performs pull-down or pull-up of the signal line of the monitor signal in correspondence with the voltage level of the drive signal. Therefore, even in a case where the potential of the signal line of the monitor signal becomes unstable due to an abnormality such as disconnection, for example, pull-down or pull-up of the signal line of the monitor signal by the potential setting circuit makes it possible to prevent a situation where the determination circuit fails to accurately detect an abnormality.

[0091] Further, in the present embodiment, it can be that the potential setting circuit performs pull-down of the signal line of the monitor signal when the drive signal is at a high level, and performs pull-up of the signal line of the monitor signal when the drive signal is at a low level.

[0092] In this way, when the drive signal is at a high level, the potential setting circuit performs pull-down of the signal line of the monitor signal, whereby it is possible to prevent the potential of the monitor signal from being pulled to the high level side due to coupling of inter-wiring capacitance or the like. Further, when the drive signal is at a low level, the potential setting circuit performs pull-up of the signal line of the monitor signal, whereby it is possible to prevent the potential of the monitor signal from being pulled to the low level side due to coupling of inter-wiring capacitance or the like.

[0093] Further, in the present embodiment, it can be that the potential setting circuit includes a pull-up resistor and a pull-up switch that are connected in series between a node of a high potential side power supply voltage and a node of the signal line of the monitor signal, and a pull-down resistor and a pull-down switch that are connected in series between a node of a low potential side power supply voltage and the node of the signal line of the monitor signal.

[0094] In this way, even in a case where the potential of the signal line of the monitor signal becomes unstable due to an abnormality such as disconnection, pull-down or pull-up of the signal line of the monitor signal by the pull-down switch or the pull-up switch being turned on makes it possible to prevent a situation where the determination circuit fails to accurately detect an abnormality.

[0095] In addition, in this embodiment, the pull-down switch can be turned on when the drive signal is at a high level, and the pull-up switch can be turned on when the drive signal is at a low level.

[0096] In this way, when the drive signal is at a high level, the pull-down switch is turned on, and thus the signal line of the monitoring signal is pulled down and set to a low level. In addition, when the drive signal is at a low level, the pull-up switch is turned on, and thus the signal line of the monitoring signal is pulled up and set to a high level.

[0097] In addition, in this embodiment, the resistance values of the pull-down resistor and the pull-up resistor can be higher than the on-resistance value of the drive transistor of the driver circuit.

[0098] In this way, even in the case where the signal line of the monitoring signal is pulled down by the pull-down resistor when the drive signal is at a high level or pulled up by the pull-up resistor when the drive signal is at a low level, the adverse effects on the driving of the display electrode can be reduced.

[0099] In addition, in this embodiment, the potential setting circuit can include a pull-up transistor provided between a node of a high-potential side power supply voltage and a node of the signal line of the monitoring signal, and a pull-down transistor provided between a node of a low-potential side power supply voltage and a node of the signal line of the monitoring signal.

[0100] In this way, even in the case where the potential of the signal line of the monitoring signal becomes unstable due to a disconnection or the like, the signal line of the monitoring signal can be pulled down or up by turning on the pull-down transistor or the pull-up transistor, and it is possible to prevent a situation where the abnormality cannot be accurately detected in the determination circuit.

[0101] In addition, in this embodiment, the determination circuit can determine that a disconnection of the signal line of the drive signal has occurred when the comparison result of the comparison circuit is not a comparison result corresponding to the expected value.

[0102] In this way, the determination circuit can determine the occurrence of a disconnection by determining whether the comparison result of the comparison circuit matches the expected value corresponding to the voltage level of the drive signal.

[0103] In addition, the display device of this embodiment includes the display driver and the electro-optical panel described above.

[0104] Furthermore, although the present embodiment has been described in detail as described above, a person skilled in the art can easily understand that various modifications can be made without departing from the gist of the present disclosure. Therefore, such modified examples are all included in the scope of the present disclosure. For example, in the specification or drawings, a term recited at least once together with a different term of broader meaning or synonymous meaning can be replaced with the different term in any part of the specification or drawings. In addition, all combinations of the present embodiment and the modified examples are also included in the scope of the present disclosure. Furthermore, the structure, operation, and the like of the display driver and the display device and the like are not limited to those described in the present embodiment, and various modifications can be made.

Claims

1. A display driver, characterized in that, The display driver includes: The driver circuit, which outputs a drive signal; The output terminal outputs the drive signal to the display electrodes of the electro-optic panel; An input terminal is used to input a monitoring signal from the display electrode. as well as Check the circuit. The inspection circuit includes: A comparator circuit that compares the voltage of the monitored signal with a reference voltage; The determination circuit determines an anomaly based on the expected value corresponding to the voltage level of the driving signal and the comparison result of the comparison circuit. as well as A potential setting circuit that pulls down or up the signal line of the monitoring signal in accordance with the voltage level of the drive signal.

2. The display driver according to claim 1, characterized in that, When the drive signal is high, the potential setting circuit pulls down the signal line of the monitoring signal. When the drive signal is low, the potential setting circuit pulls up the signal line of the monitoring signal.

3. The display driver according to claim 2, characterized in that, The potential setting circuit includes: A pull-up resistor and a pull-up switch are connected in series between the node of the power supply voltage on the high-potential side and the node of the signal line of the monitoring signal; and A pull-down resistor and a pull-down switch are connected in series between the node of the power supply voltage on the low potential side and the node of the signal line of the monitoring signal.

4. The display driver according to claim 3, characterized in that, When the drive signal is high, the pull-down switch is turned on. When the drive signal is low, the pull-up switch is turned on.

5. The display driver according to claim 3, characterized in that, The resistance values ​​of the pull-down resistor and the pull-up resistor are higher than the on-resistance value of the driving transistor in the driver circuit.

6. The display driver according to claim 2, characterized in that, The potential setting circuit includes: A pull-up transistor is positioned between the node of the power supply voltage on the high-potential side and the node of the signal line of the monitoring signal; and A pull-down transistor is positioned between the node of the power supply voltage on the low-potential side and the node of the signal line of the monitoring signal.

7. The display driver according to claim 1, characterized in that, When the comparison result of the comparison circuit is not the comparison result corresponding to the expected value, the determination circuit determines that a break in the signal line of the drive signal has occurred.

8. A display device, characterized in that, The display device includes: The display driver according to any one of claims 1-7; and The electro-optical panel.

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