Display device

Abstract

The invention provides a display device capable of realizing high-speed driving. The display device includes: a first transistor connected between an image data signal line and a second capacitive element; a second transistor connected between the first capacitor element and the fifth transistor; a third transistor connected between the reset potential line and the second capacitor element; a fifth transistor connected between the light emitting element and the second transistor; a sixth transistor connected between the reference potential line and the second capacitor element; a seventh transistor connected between the reference potential line and the first capacitor element; the eighth transistor is connected between the constant potential line and the fifth transistor; a first capacitor element connected between the second capacitor element and the second transistor; the second capacitor element is electrically connected between the first capacitor element and the second transistor; and a light emitting element connected between the constant potential line and the fifth transistor.

Description

Technical Field

[0001] One embodiment of the present invention relates to a display device. Background Technology

[0002] In recent years, display devices including light-emitting elements have become increasingly common in televisions, smartphones, and other devices. For example, a display device includes multiple pixels and control circuitry for driving these pixels. Each pixel includes multiple transistors, capacitors, and light-emitting elements. Light-emitting elements are self-emissive components, such as light-emitting diodes (LEDs), miniature LEDs, or organic electroluminescent (EL) elements. The control circuitry in the display device supplies a potential to each pixel, causing a current corresponding to the supplied potential to flow in the light-emitting elements within each pixel. Each light-emitting element emits light with a brightness corresponding to the current flowing within it, and the pixel including the light-emitting element can display an image at a grayscale corresponding to that brightness.

[0003] For example, Patent Document 1 discloses a display device including a light-emitting element. The pixel in the display device described in Patent Document 1 includes nine transistors (T1 to T9), two capacitor elements (Chold, Cst) connected in series, and a light-emitting element (LED). Furthermore, the driving method of the display device described in Patent Document 1 includes: during the initialization period and the light-emitting period, electrically connecting the gate electrode of transistor T1 to a node (D-node) on one electrode side of capacitor element Chold via transistor T3.

[0004] Patent Document 1: US Patent No. 11,972,726

[0005] For example, during the light-emitting period, when the gate electrode of transistor T1 and the D-node of one electrode side of capacitor Chold are electrically connected through transistor T3, the charge held by capacitors Chold and Cst is redistributed to the gate electrode of transistor T1, capacitors Chold and Cst. For instance, if this charge is redistributed, the potential difference between the potential applied to the gate electrode of transistor T1 and the potential applied to the source electrode of transistor T1 decreases (i.e., the holding potential decreases or is lost), and there is a possibility that the LED light-emitting element may not emit light at the specified brightness. Furthermore, display devices including light-emitting elements have been required to drive at higher speeds in recent years to handle high resolution, large screens, or high frequencies. Summary of the Invention

[0006] In view of such technical problems, one objective of one embodiment of the present invention is to provide a display device capable of suppressing the loss of holding potential. Another objective of one embodiment of the present invention is to provide a display device capable of achieving high-speed driving.

[0007] An embodiment of the present invention relates to a display device comprising: a plurality of pixels arranged in a matrix in a first direction and a second direction intersecting the first direction; an image data signal line supplied with a data potential; a reset potential line supplied with a reset potential; a reference potential line supplied with a reference potential; a base potential line supplied with a base potential; and a constant potential line supplied with a constant potential. Each of the plurality of pixels includes a first transistor, a second transistor, a third transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a first capacitor element, a second capacitor element, and a light-emitting element. The first transistor is controlled by a first control signal and electrically connected between the image data signal line and the second electrode of the second capacitor element. The second transistor has a gate electrode electrically connected to the second electrode of the second capacitor element and electrically connected between the first electrode of the first capacitor element and the first electrode of the fifth transistor. The third transistor is controlled by a second control signal. The first transistor is electrically connected between the reset potential line and the second electrode of the second capacitor element. The fifth transistor is controlled by a third control signal and electrically connected between the first electrode of the light-emitting element and the second electrode of the second transistor. The sixth transistor is controlled by a fourth control signal and electrically connected between the reference potential line and the first electrode of the second capacitor element. The seventh transistor is controlled by a fifth control signal and electrically connected between the reference potential line and the first electrode of the second transistor. The eighth transistor is controlled by the fourth control signal and electrically connected between the constant potential line and the first electrode of the fifth transistor. The first capacitor element is electrically connected between the first electrode of the second capacitor element and the first electrode of the second transistor. The second capacitor element is electrically connected between the second electrode of the first capacitor element and the gate electrode. The light-emitting element is electrically connected between the constant potential line and the first electrode of the fifth transistor. Attached Figure Description

[0008] Figure 1 This is a schematic diagram illustrating the structure of a display device according to the first embodiment of the present invention.

[0009] Figure 2 This is a schematic diagram showing the input signal of the pixel circuit according to the first embodiment of the present invention.

[0010] Figure 3 This is a circuit diagram illustrating the structure of the pixel circuit according to the first embodiment of the present invention.

[0011] Figure 4 This is a timing diagram of a display device according to the first embodiment of the present invention.

[0012] Figure 5 This is a timing diagram of a display device according to the first embodiment of the present invention.

[0013] Figure 6 This is a timing diagram of a display device according to the first embodiment of the present invention.

[0014] Figure 7 This is a timing diagram of a display device according to the first embodiment of the present invention.

[0015] Figure 8 This is a timing diagram of a display device according to the first embodiment of the present invention.

[0016] Figure 9 This is a layout diagram of pixels according to the first embodiment of the present invention.

[0017] Figure 10 This is a layout diagram of pixels according to the first embodiment of the present invention.

[0018] Figure 11 It shows along Figure 9 End face view of the cut-off end face of A1-A2 in the layout shown.

[0019] Figure 12 It shows along Figure 9 End face view of the cut-off end face of B1-B2 in the layout shown.

[0020] Figure 13 It shows along Figure 9 End face view of the cut end face after C1-C2 in the layout shown.

[0021] Figure 14 This is a timing diagram illustrating a method for manufacturing a display device according to the first embodiment of the present invention.

[0022] Figure 15 This is a timing diagram illustrating a method for manufacturing a display device according to the first embodiment of the present invention.

[0023] Figure 16 This is a layout diagram of pixels according to the first embodiment of the present invention.

[0024] Figure 17 This is a layout diagram of pixels according to the first embodiment of the present invention.

[0025] Figure 18 This is a layout diagram of pixels according to the first embodiment of the present invention.

[0026] Figure 19 This is an end view view showing the end face of the display device according to the first embodiment of the present invention.

[0027] Figure 20This is an end view view showing the end face of the display device according to the first embodiment of the present invention.

[0028] Figure 21 This is an end view view showing the end face of the display device according to the first embodiment of the present invention.

[0029] Figure 22 This is an end view view showing the end face of the display device according to the first embodiment of the present invention.

[0030] Figure 23 This is a schematic diagram illustrating an example of the driving potential line and the reference potential line according to the first embodiment of the present invention.

[0031] Figure 24 This is a schematic diagram illustrating the structure of a display device according to a second embodiment of the present invention.

[0032] Figure 25 This is a schematic diagram showing the input signal of the pixel circuit according to the second embodiment of the present invention.

[0033] Figure 26 This is a circuit diagram illustrating the structure of the pixel circuit according to the second embodiment of the present invention.

[0034] Figure 27 This is a timing diagram of a display device according to the second embodiment of the present invention.

[0035] Figure 28 This is a timing diagram of a display device according to the second embodiment of the present invention.

[0036] Figure 29 This is a timing diagram of the control circuit according to the second embodiment of the present invention.

[0037] Figure 30 This is a timing diagram of the pixel circuit according to the second embodiment of the present invention.

[0038] Explanation of reference numerals in the attached figures

[0039] 10. Display device; 20. Display device; 22. Display area; 24. Peripheral area; 26. Terminal area; 32. First electrode; 34. Second electrode; 42. First electrode; 44. Second electrode; 52. First electrode; 54. Second electrode; 100. Array substrate; 101. Substrate; 101A. First surface; 101B. Second surface; 110. IC chip; 120. Control circuit; 121. Substrate layer; 122. Semiconductor layer; 122A. Semiconductor layer; 122B. Semiconductor layer; 122C. Semiconductor layer; 122D. Semiconductor layer; 122E. Semiconductor layer; 123. Channel region; 124A. Impurity region; 125. Gate insulating layer; 126. Conductive layer; 127. 127A, Gate wiring; 127B, Gate wiring; 127C, Gate wiring; 127D, Gate wiring; 127E, Gate wiring; 127F, Gate wiring; 127G, Gate wiring; 128, Insulating layer; 130, Shift register circuit; 131, Insulating layer; 132, Conductive layer; 132A, First wiring; 132B, First wiring; 132C, First wiring; 132D, First wiring; 132E, First wiring; 132F, First wiring; 132G, First wiring; 132H, First wiring; 132I, First wiring; 132J, First wiring; 132K, First wiring; 132L, First wiring; 132M, First wiring; 135, First... Contact hole opening portion; 135A, first contact hole opening portion; 135B, first contact hole opening portion; 135C, first contact hole opening portion; 135D, first contact hole opening portion; 135E, first contact hole opening portion; 135F, first contact hole opening portion; 135G, first contact hole opening portion; 135H, first contact hole opening portion; 135I, first contact hole opening portion; 135J, first contact hole opening portion; 135K, first contact hole opening portion; 135L, first contact hole opening portion; 135M, first contact hole opening portion; 135N, first contact hole opening portion; 136, insulating layer; 137, organic insulating film opening portion; 137A, organic insulating film opening portion; 137B, organic insulating... 138. Membrane opening; 138A. Second contact hole opening; 138B. Second contact hole opening; 138C. Second contact hole opening; 138D. Second contact hole opening; 138E. Second contact hole opening; 138F. Second contact hole opening; 139. Conductive layer; 140. Second wiring; 140A. Second wiring; 140B. Second wiring; 140C. Second wiring; 140D. Second wiring; 141. Insulating layer; 143. Cathode electrode; 144. First layer; 145. Second layer; 146. Third layer; 147. Contact hole opening; 147A. Contact hole opening; 148. Functional layer; 149. Common electrode; 150. Terminal portion;152. First inorganic insulating layer; 154. Organic insulating layer; 156. Second inorganic insulating layer; 158. Cover film; 160. Scan driving circuit; 165. Sealing film; 170. Array section; 180. Pixel; 180A. Pixel; 181. Pixel circuit; 181A. Pixel circuit; 190. Insulating layer; 191A. Back side opening; 191B. Back side opening; 191C. Back side opening; 191D. Back 192. Via; 192A. Via; 192B. Via; 192C. Via; 192D. Via; 193. Conductive layer; 193A. Backside wiring; 193B. Backside wiring; 193C. Backside wiring; 193D. Backside wiring; 194. Backside organic insulating film opening; 195. Pad; 200. Flexible printed circuit board; 321. Image data signal line; 322. Image data signal line; 323, Image data signal line; 330, Scan signal line; 331, Scan signal line; 332, Scan signal line; 333, Scan signal line; 334, Scan signal line; 335, Scan signal line; 341, Connecting wiring; 342, Connecting wiring; 612, Gate electrode; 614, First electrode; 616, Second electrode; 622, Gate electrode; 624, First electrode; 626, Second electrode; 632, Gate electrode; 634, First electrode; 636, Second electrode; 642, Gate electrode; 644, First electrode; 646, Second electrode; 652, Gate electrode; 654, First electrode; 656, Second electrode; 662, Gate electrode; 664, First electrode; 666, Second electrode; 672, Gate electrode; 674, First electrode; 676, Second electrode; 682, Gate electrode; 684, First electrode; 686, Second electrode. Detailed Implementation

[0040] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. However, the present invention can be implemented in many different aspects and is not limited to the description of the embodiments illustrated below. Furthermore, in order to make the explanation clearer, the drawings sometimes schematically represent the width, thickness, shape, structure, etc., of each part compared to the actual aspects; however, this is only an example and does not limit the interpretation of the present invention. It should be noted that the words "first" and "second" used to label each element are convenient identifiers used to distinguish each element and do not have further meaning unless specifically explained.

[0041] Furthermore, in this specification, unless otherwise expressly stated, expressions such as "α includes A, B, or C," "α includes any one of A, B, and C," and "α includes one selected from the group consisting of A, B, and C" do not exclude the possibility that α includes multiple combinations of A to C. Moreover, these expressions do not exclude the possibility that α includes other elements.

[0042] In one embodiment of the present invention, the first direction D1 intersects with the second direction D2, and the third direction D3 intersects with the first direction D1 and the second direction D2 (D1D2 plane).

[0043] In the description of this application, when expressions such as "identical" and "consistent" are used, "identical" and "consistent" may also include errors within the design range. Additionally, in one embodiment of the invention, when errors within the design range are included, expressions such as "substantially identical" and "substantially consistent" are sometimes used.

[0044] For example, one embodiment of the present invention relates to a display device that uses an EL element as a self-emissive light-emitting element. For example, a display device using an EL element is sometimes referred to as a self-emissive display device, an EL display device, etc.

[0045] [1. First Implementation Method]

[0046] [1-1. Overview of display device 10]

[0047] Reference Figure 1 This section provides an overview of the display device 10 according to the first embodiment. Figure 1 This is a schematic diagram showing the structure of the display device 10. Figure 1 The structure of the display device 10 shown is an example, and the structure of the display device 10 is not limited to... Figure 1 The structure shown.

[0048] The display device 10 includes an array substrate 100, a flexible printed circuit board 200 (FPC 200), and an IC chip 110. In addition, the display device 10 includes a display area 22 disposed on the array substrate 100, a peripheral area 24 surrounding the display area 22, and a terminal area 26.

[0049] In display area 22, a plurality of pixels 180 are arranged in a matrix along a first direction D1 (column direction) and a second direction D2 (row direction) intersecting the first direction D1. Pixel 180 is the smallest unit constituting a part of the image displayed in display area 22. Each of the plurality of pixels 180 may correspond to, for example, sub-pixel R, sub-pixel G, and sub-pixel B. Alternatively, three sub-pixels may form one pixel. The arrangement of the pixels 180 is not limited; for example, the arrangement of the plurality of pixels 180 may be a stripe arrangement. The arrangement in display device 10 may be a Delta arrangement, a PenTile arrangement, etc.

[0050] Subpixels R, G, and B are configured to display images of different colors. For example, subpixels R, G, and B each have a light-emitting element that includes a light-emitting layer emitting red, green, and blue light, respectively. By supplying arbitrary potentials or currents to the three subpixels, the display device 10 can display an image.

[0051] An IC chip 110 and two control circuits 120 are disposed in the peripheral area 24. The two control circuits 120 are located on the left and right sides of the display area 22. The IC chip 110 is connected to the terminal portion 150 via connecting wires 341. The two control circuits 120 are each connected to the IC chip 110 via connecting wires 342. The peripheral area 24 is sometimes referred to as the border area. Connecting wires 341 are sometimes referred to individually as connecting wires 341, and bundles of multiple connecting wires 341 are sometimes referred to as connecting wires 341. Similarly, connecting wires 342 are sometimes referred to individually as connecting wires 342, and bundles of multiple connecting wires 342 are sometimes referred to as connecting wires 342.

[0052] Terminal area 26 is provided with terminal portion 150 and FPC 200 electrically connected to terminal portion 150. Terminal area 26 is the area opposite to the area where display area 22 is provided along the first direction D1 relative to peripheral area 24.

[0053] The FPC 200 is connected to an external device (not shown) on the outside of the display device 10. The display device 10 is connected to the external device via the FPC 200 and the terminal portion 150 connected to the FPC. Control signals and potentials are sent from the external device to the display device 10 via the FPC 200 and the terminal portion 150 connected to the FPC. The display device 10 uses the received control signals and potentials from the external device to drive each pixel 180 set in the display device 10. As a result, the display device 10 is able to display an image in the display area 22.

[0054] IC chip 110 supplies signals, potentials, etc. that drive each pixel 180 to the two control circuits 120 and each pixel 180 (pixel circuit 181) via FPC 200, terminal 150 and connection wiring 341.

[0055] The IC chip 110 and the two control circuits 120 can each be referred to as a control circuit individually, or a circuit group including part or all of the IC chip 110 and the two control circuits 120 can be referred to as a control circuit.

[0056] [1-2. Structure of IC chip 110]

[0057] Reference Figure 1This section describes the overview of IC chip 110. IC chip 110 is located adjacent to display area 22 along the first direction D1. Image data signal lines 321, 322, and 323 extend from IC chip 110 along the first direction D1 and are connected to a plurality of pixels 180 arranged along the first direction D1.

[0058] For example, IC chip 110 includes multiple selection circuits (not shown). Each selection circuit is a switch controlled by an on signal and an off signal supplied to a selection signal. The selection circuit is selected by the on signal supplied to the selection signal, supplying an image data signal SL(m), including a data signal VDATA, to the image data signal line 321 and the pixel 180 electrically connected to the image data signal line 321. The selection signal and the image data signal SL(m) are transmitted from an external device to IC chip 110 via FPC 200 and terminal portion 150 connected to the FPC. For example, the data signal VDATA (image data signal SL(m)) includes a potential VSIGL (see reference). Figure 5 ) and above and potential VSIGH (refer to) Figure 5 The following data potentials. Potential VSIGH is greater than potential VSIGL.

[0059] For example, an on signal is a signal that includes the potential of the selection circuit (switch) being turned on, and an off signal is a signal that includes the potential of the selection circuit (switch) being turned off. In this invention, the on signal can be a high-level potential (High, HI), and the off signal can be a low-level potential (Low, LO). A high-level potential is greater than a low-level potential. It should be noted that, as an example, in a display device according to one embodiment of this specification, the on signal is a high-level potential, and the off signal is a low-level potential.

[0060] [1-3. Structure of Control Circuit 120]

[0061] Reference Figure 1 This section describes the general outline of the control circuit 120. Two control circuits 120 are positioned adjacent to both sides of the display area 22 along the second direction D2. Scan signal lines 330, 331, 332, 333, 334, and 335 extend from the control circuits 120 along the second direction D2 and connect to a plurality of pixels 180 arranged along the second direction D2. As an example, Figure 1The scan signal lines of the display device 10 shown are connected to both of the two control circuits 120. Each scan signal line can also be connected to one of the two control circuits 120. For example, the nth scan signal line can be electrically connected along the second direction D2 to the control circuit 120 on the right side of the display area 22, and the (n+1)th scan signal line can be electrically connected along the second direction D2 to the control circuit 120 on the left side of the display area 22. The value n is a positive integer.

[0062] The control circuit 120 includes a shift register circuit 130 and a scan drive circuit 160. For example, the control circuit 120 is a gate driver, and is input to control signals including clock signals, start pulses, multiple enable signals, etc., and a drive potential VDDEL (see reference). Figure 2 ) and reference potential VSSEL (refer to Figure 2 Equipotential. The control circuit 120 can sequentially select scan lines through the input of control signals and power supply.

[0063] Shift register circuit 130 is electrically connected to scan drive circuit 160. Shift register circuit 130 includes multiple shift registers (not shown). Additionally, the aforementioned multiple control signals are supplied to shift register circuit 130 via multiple connection lines 342, via drive potential line PVDD (see reference). Figure 2 The shift register circuit 130 is supplied with a drive potential VDDEL via the reference potential line PVSS (refer to...). Figure 2 The reference potential VSSEL is supplied to the shift register circuit 130. The shift register circuit 130 has the following function: based on the above-mentioned multiple control signals, it generates multiple output signals (not shown) that shift at different times, and outputs them to the scan drive circuit 160 in sequence.

[0064] The scan drive circuit 160 includes multiple scan drivers. For example, multiple output signals are supplied from the shift register circuit 130 to the multiple scan drivers, and multiple enable signals are supplied from the IC chip 110 to the multiple scan drivers via multiple connection lines 342. A drive potential VDDEL is supplied to the multiple scan drivers via the drive potential line PVDD, and a reference potential VSSEL is supplied to the multiple scan drivers via the reference potential line PVSS. The multiple scan drivers have the following function: based on the multiple output signals and multiple enable signals (not shown), they sequentially supply scan signals at different times (e.g., first scan signal SC1(n), second scan signal SC2(n), third scan signal SC3(n), fourth scan signal SC4(n), fifth scan signal SC5(n), and sixth scan signal SC6(n)) to each scan signal line, and drive the pixels 180 (pixel circuit 181) electrically connected to each scan signal line. For example, the fourth scan signal SC4(n) and the scan signal line 333 to which the fourth scan signal SC4(n) is supplied are called scan signals and scan signal lines.

[0065] [1-4. Pixel 180 structure]

[0066] Reference Figures 1-3 This section provides an overview of pixel 180 and pixel circuit 181. Figure 2 This is a schematic diagram showing the input signal to the pixel circuit 181 included in pixel 180. Figure 3 This is a circuit diagram showing the structure of pixel circuit 181. As an example, Figure 2 as well as Figure 3 It shows Figure 1 The structure of pixel circuit 181 of pixel 180 is shown. The structure of pixel 180 and pixel circuit 181 is not limited to... Figures 1-3 The structure shown. Adjustments can be made as needed. Figure 1 Explanation of the same or similar structure, sometimes omitting the similarity. Figure 1 Descriptions of the same or similar structures.

[0067] Pixel circuit 181 is used to drive pixel 180. The pixel circuits for sub-pixels R, G, and B included in pixel 180 are the same as those for pixel circuit 181, but the light-emitting elements OLED emit different colors. In the following description, as an example, an OLED emitting red light will be described.

[0068] like Figure 2As shown, the pixel circuit 181 is supplied with image data signal SL(m), first scan signal SC1(n), second scan signal SC2(n), third scan signal SC3(n), fourth scan signal SC4(n), fifth scan signal SC5(n), sixth scan signal SC6(n), reset potential VRES, reference potential VREF, and initialization potential VINI. Additionally, as power supplies for driving the pixel 180, the pixel circuit 181 is supplied with driving potential VDDEL and reference potential VSSEL. For example, the reset potential VRES, reference potential VREF, initialization potential VINI, driving potential VDDEL, and reference potential VSSEL can be constant potentials or variable potentials that change according to the timing of each signal.

[0069] The first scan signal SC1(n) is supplied to scan signal line 330, the second scan signal SC2(n) is supplied to scan signal line 331, the third scan signal SC3(n) is supplied to scan signal line 332, the fourth scan signal SC4(n) is supplied to scan signal line 333, the fifth scan signal SC5(n) is supplied to scan signal line 334, and the sixth scan signal SC6(n) is supplied to scan signal line 335. The first scan signal SC1(n) is sometimes referred to as the second control signal, the second scan signal SC2(n) is sometimes referred to as the fifth control signal, the third scan signal SC3(n) is sometimes referred to as the fourth control signal, the fourth scan signal SC4(n) is sometimes referred to as the first control signal, the fifth scan signal SC5(n) is sometimes referred to as the third control signal, and the sixth scan signal SC6(n) is sometimes referred to as the sixth control signal.

[0070] Additionally, the reset potential VRES is supplied to the reset potential line SVRE, the reference potential VREF is supplied to the reference potential line SVR, the initialization potential VINI is supplied to the initialization potential line SVI, the drive potential VDDEL is supplied to the drive potential line PVDD, and the reference potential VSSEL is supplied to the reference potential line PVSS. For example, the reset potential line SVRE, the reference potential line SVR, the initialization potential line SVI, the drive potential line PVDD, and the reference potential line PVSS are each electrically connected to different connection lines 342. Alternatively, for example, the reset potential line SVRE, the reference potential line SVR, the initialization potential line SVI, the drive potential line PVDD, and the reference potential line PVSS can also be different connection lines 342.

[0071] For example, the reset potential VRES, reference potential VREF, initialization potential VINI, drive potential VDDEL, and reference potential VSSEL are supplied from an external device to the IC chip 110 via FPC 200, terminal section 150, and connection wiring 341. Additionally, for example, the reset potential VRES, reference potential VREF, initialization potential VINI, drive potential VDDEL, and reference potential VSSEL are supplied from the IC chip 110 to multiple pixels 180 (pixel circuit 181) via connection wiring 342, reset potential line SVRE, reference potential line SVR, initialization potential line SVI, drive potential line PVDD, and reference potential line PVSS. It should be noted that, although the illustration is omitted, the reset potential VRES, reference potential VREF, initialization potential VINI, drive potential VDDEL, and reference potential VSSEL can be connected from an external device to the reset potential line SVRE, reference potential line SVR, initialization potential line SVI, drive potential line PVDD, and reference potential line PVSS via FPC200, terminal section 150, and connection wiring 341 without via IC chip 110 and connection wiring 342, and can also be supplied to multiple pixels 180 (pixel circuit 181). For example, the reset potential VRES, reference potential VREF, initialization potential VINI, and reference potential VSSEL are less than the drive potential VDDEL.

[0072] like Figure 3 As shown, the device includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a capacitor element CV, a capacitor element CD, and a light-emitting element OLED. Each of these transistors includes a gate electrode and a pair of electrodes (source electrode and drain electrode) composed of a first electrode and a second electrode. Each of the capacitor elements CV, CD, and OLED has a pair of electrodes composed of a first electrode and a second electrode. It should be noted that the capacitor element CV is sometimes referred to as the first capacitor element, and the capacitor element CD is sometimes referred to as the second capacitor element.

[0073] For example, the first transistor T1 is a selection transistor. The first transistor T1 has the function of supplying the image data signal SL(m) to the second node N2.

[0074] For example, the second transistor T2 is a driving transistor. Between the gate electrode 622 and the first electrode (source) 624 of the second transistor T2, a threshold voltage (the potential difference Vgs that becomes the threshold) VTH is acquired based on the reset potential VRES. The acquired threshold voltage VTH is applied to the capacitor element CV, thereby performing the acquisition and holding (storage) of the threshold voltage VTH, as detailed later. Furthermore, the second transistor T2 controls the amount of current flowing into the light-emitting element OLED from the driving potential line PVDD based on the gate potential (potential between the gate electrode 622 and the first electrode 624) after correcting for the deviation of the threshold voltage VTH, and the input image data signal SL(m). That is, the second transistor T2 has the function of causing the light-emitting element OLED to emit light by allowing a current corresponding to the displayed grayscale (brightness) to flow into it according to the driving potential VDDEL.

[0075] For example, the third transistor T3 has the following function: it turns on the second node N2 and the reset potential line SVRE to supply the reset potential VRES to the second node N2, and fixes the potential supplied to the second node N2 to the reset potential VRES. When the potential supplied to the second node N2 is fixed to the reset potential VRES, the current flows through the fifth transistor T5 from the drive potential line PVDD to the fifth node N5, the fourth node N4, and the third node N3. The capacitor element CV (the first electrode 42 of the capacitor element CV) begins to charge. When the potential difference Vgs (the potential difference Vgs between the potential supplied to the gate electrode 622 (the second node N2) and the potential supplied to the first electrode 624 (the third node N3)) reaches the threshold voltage VTH, the charging stops. Details are described later.

[0076] The fourth transistor T4 has the following function: it turns on the third node N3 and the initialization potential line SVI to supply the initialization potential VINI to the third node N3, thereby initializing the third node N3.

[0077] The fifth transistor T5 has the function of turning on the fifth node N5 and the fourth node N4.

[0078] The sixth transistor T6 has the following functions: it turns on the first node N1 and the reference potential line SVR to supply the reference potential line SVR to the first node N1; during the initialization of the first node N1, during the acquisition and holding of the threshold voltage VTH, and during the writing of the image data signal SL(m), it fixes the potential supplied to the first node N1 to the reference potential VREF.

[0079] The seventh transistor T7 has the following function: to turn on the third node N3 and the reference potential line PVSS, thereby supplying the reference potential VSSEL to the third node N3.

[0080] The eighth transistor T8 has the following functions: to turn on the first electrode 32 and the second electrode 34 of the light-emitting element OLED so that the potential difference between the first electrode 32 and the second electrode 34 of the light-emitting element OLED is zero, to suppress the light emission of the light-emitting element OLED during periods other than the light emission period; and to allow current to flow from the driving potential line PVDD to the second electrode 626 and the first electrode 624 (i.e., the fifth node N5 and the third node N3) of the second transistor T2 when the threshold voltage VTH is acquired and maintained, so as to charge the fifth node N5 and the third node N3.

[0081] The capacitor element CV has the function of maintaining (storing) a charge equivalent to the threshold voltage VTH of the second transistor T2. That is, the capacitor element CV has the function of maintaining (storing) the potential difference between the potential supplied to the first node N1 and the potential supplied to the second node N2, which includes information about the threshold voltage VTH of the second transistor T2. The driving method of the display device 10 includes obtaining the threshold voltage VTH from the first electrode 624 (source electrode) side of the second transistor T2.

[0082] The capacitor element CD has the ability to hold (save) the data potential (potential VSIGL (reference) of the image data signal SL(m) supplied to the second node N2. Figure 5 ) and above and potential VSIGH (refer to) Figure 5 The capacitor element CD has the function of maintaining (storing) the potential difference between the potential supplied to the second node N2 and the potential supplied to the first node N1, which includes the data potential information of the image data signal SL(m).

[0083] The OLED (Optical Display Panel) exhibits diode characteristics, emitting light based on the current flowing within it. The current flowing within the OLED is the drain current (Ion) of the second transistor T2.

[0084] The first transistor T1 includes a gate electrode 612, a first electrode 614, and a second electrode 616. The gate electrode 612 is electrically connected to the scan signal line 333. The first electrode 614 is electrically connected to the image data signal line 321. The second electrode 616 is electrically connected to the second node N2, the gate electrode 622 of the second transistor T2, the second electrode 636 of the third transistor T3, and the second electrode 54 of the capacitor element CD. The first transistor T1 is switched on and off using a fourth scan signal SC4(n). In other words, the first transistor T1 is controlled by the fourth scan signal SC4(n) to be in a conducting state (on state) and a non-conducting state (off state). When the signal supplied to the fourth scan signal SC4(n) is LO, the first transistor T1 is in a non-conducting state. When the signal supplied to the fourth scan signal SC4(n) is HI, the first transistor T1 is in a conducting state.

[0085] The second transistor T2 includes a gate electrode 622, a first electrode 624, and a second electrode 626. The first electrode 624 is electrically connected to the third node N3, the first electrode 42 of the capacitor element CV, and the second electrode 676 of the seventh transistor T7. The second electrode 626 is electrically connected to the fifth node N5 and the first electrode 654 of the fifth transistor T5. The threshold voltage of the second transistor T2 is the threshold voltage VTH. The second transistor T2 controls the amount of current flowing in the light-emitting element OLED based on the potential difference Vgs and the potential difference Vds between the potential supplied to the second electrode 626 (fifth node N5) and the potential supplied to the first electrode 624 (third node N3). For example, when the potential difference Vgs is less than the threshold voltage VTH, the second transistor T2 is in a non-conducting state. At this time, no current flows in the light-emitting element OLED, so pixel 180 displays black. For example, when the potential difference Vgs is above the threshold voltage VTH and the potential difference Vds is greater than 0V, the second transistor T2 becomes on. Based on the grayscale value of the potential difference Vgs, the current flowing in the light-emitting element OLED is controlled, and the light-emitting element OLED emits light with a brightness based on the grayscale value of the display.

[0086] The third transistor T3 includes a gate electrode 632, a first electrode 634, and a second electrode 636. The gate electrode 632 is electrically connected to the scan signal line 330. The first electrode 634 is electrically connected to the reset potential line SVRE. The switching of the third transistor T3 is controlled by the first scan signal SC1(n). In other words, the third transistor T3 is controlled by the first scan signal SC1(n) to be in a conducting state (on state) and a non-conducting state (off state). When the signal supplied to the first scan signal SC1(n) is LO, the third transistor T3 is in a non-conducting state; when the signal supplied to the first scan signal SC1(n) is HI, the third transistor T3 is in a conducting state.

[0087] The fourth transistor T4 includes a gate electrode 642, a first electrode 644, and a second electrode 646. The gate electrode 642 is electrically connected to the scan signal line 335. The first electrode 644 is electrically connected to the initialization potential line SVI. The switching of the fourth transistor T4 is controlled by the sixth scan signal SC6(n). In other words, the fourth transistor T4 is controlled by the sixth scan signal SC6(n) to be in a conducting state (on state) and a non-conducting state (off state). When the signal supplied to the sixth scan signal SC6(n) is LO, the fourth transistor T4 is in a non-conducting state; when the signal supplied to the sixth scan signal SC6(n) is HI, the fourth transistor T4 is in a conducting state.

[0088] The fifth transistor T5 includes a gate electrode 652, a first electrode 654, and a second electrode 656. The gate electrode 652 is electrically connected to the scan signal line 331. The second electrode 656 is electrically connected to the fifth node N5, the first electrode 32 of the light-emitting element OLED, and the first electrode 684 of the eighth transistor T8. The switching of the fifth transistor T5 is controlled by the second scan signal SC2(n). In other words, the fifth transistor T5 is controlled by the second scan signal SC2(n) to be in a conducting state (on state) and a non-conducting state (off state). When the signal supplied to the second scan signal SC2(n) is LO, the fifth transistor T5 is in a non-conducting state; when the signal supplied to the second scan signal SC2(n) is HI, the fifth transistor T5 is in a conducting state.

[0089] The sixth transistor T6 includes a gate electrode 662, a first electrode 664, and a second electrode 666. The gate electrode 662 is electrically connected to the scan signal line 332. The first electrode 664 is electrically connected to the reference potential line SVR. The second electrode 666 is electrically connected to the first node N1, the second electrode 44 of the capacitor element CV, and the first electrode 52 of the capacitor element CD. The switching of the sixth transistor T6 is controlled by a third scan signal SC3(n). In other words, the sixth transistor T6 is controlled by the third scan signal SC3(n) to be in a conducting state (on state) and a non-conducting state (off state). When the signal supplied to the third scan signal SC3(n) is LO, the sixth transistor T6 is in a non-conducting state; when the signal supplied to the third scan signal SC3(n) is HI, the sixth transistor T6 is in a conducting state.

[0090] The seventh transistor T7 includes a gate electrode 672, a first electrode 674, and a second electrode 676. The gate electrode 672 is electrically connected to the scan signal line 331. The first electrode 674 is electrically connected to the reference potential line PVSS. The switching of the seventh transistor T7 is controlled by the second scan signal SC2(n). In other words, the seventh transistor T7 is controlled by the second scan signal SC2(n) to be in a conducting state (on state) and a non-conducting state (off state). When the signal supplied to the second scan signal SC2(n) is LO, the seventh transistor T7 is in a non-conducting state; when the signal supplied to the second scan signal SC2(n) is HI, the seventh transistor T7 is in a conducting state.

[0091] The eighth transistor T8 includes a gate electrode 682, a first electrode 684, and a second electrode 686. The gate electrode 682 is electrically connected to the scan signal line 332 and the gate electrode 662 of the sixth transistor T6. The second electrode 686 is electrically connected to the second electrode 34 of the light-emitting element OLED and the driving potential line PVDD. The switching of the eighth transistor T8 is controlled by a third scan signal SC3(n). In other words, the eighth transistor T8 is controlled by the third scan signal SC3(n) to be in a conducting state (on state) and a non-conducting state (off state). When the signal supplied to the third scan signal SC3(n) is LO, the eighth transistor T8 is in a non-conducting state; when the signal supplied to the third scan signal SC3(n) is HI, the eighth transistor T8 is in a conducting state.

[0092] The capacitor element CV includes a first electrode 42 and a second electrode 44.

[0093] The capacitor element CD includes a first electrode 52 and a second electrode 54.

[0094] The first electrode 32 of the OLED light-emitting element is a cathode electrode, and the second electrode 34 of the OLED light-emitting element is an anode electrode.

[0095] For example, the ON state of a transistor in display device 10 refers to the state where the source and drain electrodes of the transistor are connected and the transistor is turned on (ON), and the OFF state of a transistor in display device 10 refers to the state where the source and drain electrodes of the transistor are not connected and the transistor is turned off (OFF). It should be noted that in each transistor, the source and drain electrodes may sometimes be interchanged depending on the potential supplied to each electrode. Furthermore, those skilled in the art will readily understand that even when a transistor is in the OFF state, a slight current will still flow, similar to leakage current.

[0096] Figure 3The transistors shown are n-channel field-effect transistors, with the channel region containing Group 14 elements such as silicon and germanium, or oxides exhibiting semiconductor properties. For example, crystalline silicon can be used as the channel region containing Group 14 elements. The crystalline silicon can be low-temperature polycrystalline silicon (LTPS) or monocrystalline silicon. Furthermore, metal oxides exhibiting semiconductor properties can be used, for example, as oxides exhibiting semiconductor properties. As an example, an oxide semiconductor containing two or more metals, including indium (In), can be used. Besides indium, metal oxides exhibiting semiconductor properties can also include gallium (Ga), zinc (Zn), aluminum (Al), hafnium (Hf), yttrium (Y), zirconium (Zr), and lanthanides. Additionally, the metal oxide exhibiting semiconductor properties can be amorphous, crystalline, or a mixture of amorphous and crystalline phases.

[0097] For example, each transistor in the display device 10 is formed using a thin-film transistor (TFT). The channel region of each transistor can also be formed using single-crystal silicon such as a silicon wafer or an SOI substrate. Furthermore, when the display device 10 includes both transistors with a channel region containing a Group 14 element and transistors with a channel region containing an oxide exhibiting semiconductor properties, the manufacturing method of the display device 10 includes: forming a semiconductor layer containing a Group 14 element; and forming a semiconductor layer containing an oxide exhibiting semiconductor properties (e.g., an oxide semiconductor layer). The display device 10 can be appropriately matched according to its application and specifications, including the transistor structure, the connection of the retaining capacitor, and the power supply potential.

[0098] For example, transistors containing metal oxides with semiconductor properties have extremely low leakage current. Therefore, when using transistors containing metal oxides with semiconductor properties, the charge equivalent to the potential of a written capacitor element is less likely to leak from the capacitor element. As a result, by using transistors containing metal oxides with semiconductor properties, the charge written to the capacitor element can be maintained for a longer period. Furthermore, under the same gate-source potential difference (the potential difference between the gate electrode and the source electrode) and source-drain potential difference, the drain current of transistors containing metal oxides with semiconductor properties is sometimes larger than that of transistors containing crystalline silicon (e.g., low-temperature polycrystalline silicon (LTPS)). As a result, under the same drain current conditions, the gate-source potential difference and source-drain potential difference of transistors containing metal oxides with semiconductor properties can be smaller than those of transistors containing crystalline silicon. Therefore, by using transistors containing metal oxides with semiconductor properties, the power consumption of the display device 10 can be suppressed.

[0099] [1-5. Driving method of display device 10]

[0100] Reference Figures 4-8 This describes the driving method of the display device 10. Figures 4-8 This is a schematic diagram showing the timing of the display device 10. Adjustments can be made as needed. Figures 1-3 Explanation of the same or similar structure, sometimes omitting the similarity. Figures 1-3 Descriptions of the same or similar structures.

[0101] It should be noted that the horizontal axis of the timing diagram in each embodiment is time. Furthermore, in the image data signal SL(m) including the data signal VDATA in each embodiment, as an example, the data signal VDATA supplied to the selected pixel (pixel circuit) is represented by a diagonal line as a data potential above VSIGL and below VSIGH, while the data signal VDATA supplied to pixels (pixel circuits) other than the selected pixel (pixel circuit) is omitted and represented by a solid line. In fact, in the image data signal SL(m) including the data signal VDATA in each embodiment, the potential of the data signal VDATA supplied to pixels (pixel circuits) other than the selected pixel (pixel circuit) is also supplied continuously or intermittently.

[0102] For example, the frequency driving the display device 10 is 60Hz, and one frame (1 FRAME) is driven at 60Hz. For example, in Figure 4 The image shows a portion of the current frame (KthFRAME), the previous frame (K-1stFRAME), and the next frame (K+1stFRAME). Additionally, Figures 5-8 This shows the emission period PEM of the previous frame (K-1stFRAME), the period PIN, period PVH, period PWR, and period PEM of the current frame (KthFRAME), and the period PIN, period PVH, period PWR, and period PEM of the next frame. Additionally, Figures 5-8 A horizontal period (horizontal period HRP) is shown for a pixel 180 (pixel circuit 181).

[0103] First, refer to Figure 4 This provides an overview of the driving method for the display device 10. (For example...) Figure 4As shown, the driving method of the display device 10 includes at least an initialization period PIN (period PIN), a threshold voltage acquisition and holding period PVH (period PVH), and a write period PWR (period PWR) in one frame. In the pixels 180 (pixel circuit 181) included in the display device 10, the period PWR is executed after the period PVH. In addition, after the emission period PEM of the previous frame of the current frame, the period PIN, period PVH, and period PWR of the current frame are executed, and after the emission period PEM of the current frame, the period PIN, period PVH, and period PWR of the next frame of the current frame are executed.

[0104] The PIN period is the period during which the first node N1, the second node N2, and the third node N3 are initialized. The PVH period is the period during which the threshold voltage of the second transistor T2 is acquired by implementing the operation of making the potential difference Vgs of the second transistor T2 the same as the threshold voltage, and the capacitor element CV is maintained with a charge equivalent to the threshold voltage. The PWR period is the period during which the data signal VDATA is written to the pixel 180 (pixel circuit 181). That is, the PWR period is the period during which the data potential is supplied to the second node N2 and the capacitor element CD is maintained with a charge equivalent to the data potential. Furthermore, the PEM period is the period during which the pixel 180 emits light based on the written data potential and the acquired threshold voltage of the second transistor T2 (threshold voltage correction).

[0105] Next, refer to Figures 4-8 This describes the specific driving method of the pixel 180 (pixel circuit 181) of the display device 10.

[0106] Pixel 180 (pixel circuit 181) is input to a first scan signal SC1(n), a second scan signal SC2(n), a third scan signal SC3(n), a fourth scan signal SC4(n), a fifth scan signal SC5(n), a sixth scan signal SC6(n), an image data signal SL(m) including a data signal VDATA, a reset potential VRES, an initialization potential VINI, and a reference potential VREF. For example, pixel 180 (pixel circuit 181) is selected based on the timing of the first scan signal SC1(n), the second scan signal SC2(n), the third scan signal SC3(n), the fourth scan signal SC4(n), the fifth scan signal SC5(n), and the sixth scan signal SC6(n). The image data signal SL(m), the reset potential VRES, the initialization potential VINI, and the reference potential VREF are input to the selected pixel 180 (pixel circuit 181) according to the timing of each signal. The same operation is performed on all pixels 180 (pixel circuit 181), and an image equivalent to the current frame of 1 frame is displayed in the display area 22 of the display device 10 based on the image data signal SL(m) input to all pixels 180 (pixel circuit 181).

[0107] For example, Table 1 shows the direction Figures 4-8 The timing diagram shown includes the signals and potentials supplied by each node in each period of each frame.

[0108]

[0109] For example, as shown in Table 1, when the potential VSIGH is 4V, the pixel 180 supplied with potential VSIGH emits light and displays white. Conversely, when the potential VSIGL is 0V, the pixel 180 supplied with potential VSIGL does not emit light and appears black. For example, the threshold voltage VTH of the second transistor T2 is 1V, the potential VH (HI) is 10V, the potential VL (LO) is -2V, the initialization potential VINI is -1V, the reference potential VREF is 2.2V, the reset potential VRES is 1V, the drive potential VDDEL is 8V, the reference potential VSSEL is 0V, and the potential VM is 5V. That is, the reference potential VREF is different from the reset potential VRES, and both the reference potential VREF and the reset potential VRES are higher than the reference potential VSSEL and lower than the drive potential VDDEL. The initialization potential VINI is lower than the reference potential VSSEL. The potentials shown in Table 1 are examples, and the potentials involved in the display device 10 are not limited to those shown in Table 1. The various potentials involved in the display device 10 can be appropriately selected according to the application and specifications of the display device 10.

[0110] [1-5-1. First Example of a Driving Method for Display Device 10]

[0111] Reference Figure 5 Table 1 illustrates a first example of the driving method for the display device 10. The driving method shown in the first example includes: after pixel 180 (pixel circuit 181) displays a white image based on the potential VSIGH of the data signal VDATA in the previous frame (K-1st FRAME) of the current frame (Kth FRAME), pixel 180 (pixel circuit 181) displays a black image based on the potential VSIGL of the data signal VDATA in Kth FRAME. In other words, the driving method shown in the first example includes displaying images of different colors in consecutive frames.

[0112] Depending on the period, an image data signal SL(m), including the data signal VDATA, is input to each pixel 180 (pixel circuit 181). The data signal VDATA is analog data (analog potential) including potentials above VSIGL and below VSIGH. For example, in period PWR, a selection signal (not shown) is used to select a potential above VSIGL and below VSIGH and supply it to the image data signal SL(m). For example, in periods other than PWR, the data signal VDATA is supplied with potentials other than those supplied to the selected pixel 180 (pixel circuit 181).

[0113] The emission period PEM of K-1stFRAME is the period during which pixel 180 (pixel circuit 181) emits light according to the potential difference Vgs of the second transistor T2. For example, pixel 180 (pixel circuit 181) emits red light, and white light is emitted by using three pixels: pixel 180 that emits red light, pixel 180 that emits blue light, and pixel 180 that emits green light.

[0114] For example, during the PEM of the K-1stFRAME, the image data signal SL(m) (data signal VDATA) is supplied with the potential of the data signal VDATA supplied to the selected pixel 180 (pixel circuit 181). The first scan signal SC1(n), the third scan signal SC3(n), the fourth scan signal SC4(n), and the sixth scan signal SC6(n) are supplied with LO, and the second scan signal SC2(n) and the fifth scan signal SC5(n) are supplied with HI. The first transistor T1, the third transistor T3, the fourth transistor T4, the sixth transistor T6, and the eighth transistor T8 are in the off state, and the fifth transistor T5 and the seventh transistor T7 are in the on state. In addition, for example, at this time, the potential held by the first node N1 is potential Va (reference potential VREF, 2.2V), the potential held by the third node N3 is 0V, the potential held by the second node N2 is potential Vnb (e.g., potential VSIGH, 4V), and the potential difference Vgs is 4V. Therefore, the second transistor T2 is turned on, enabling the current Ion, based on the potential difference Vgs and Vds corresponding to the potential VSIGH input during the K-1stFRAME level, to flow from the driving potential line PVDD to the light-emitting element OLED and the reference potential line PVSS. As a result, the light-emitting element OLED emits light. For example, pixel 180 (pixel circuit 181) emits red light, and white light is emitted by using three pixels: pixel 180 emitting red light, pixel 180 emitting blue light, and pixel 180 emitting green light. It should be noted that the potential held by the first node N1 becomes potential Vna (2.2V) through the capacitive coupling of the capacitor element CV and the capacitor element CD.

[0115] During the period between the light emission period PEM of K-1stFRAME and the period PIN of KthFRAME, following the light emission period PEM of K-1stFRAME, the image data signal SL(m) (data signal VDATA) is supplied with the potential of the data signal VDATA supplied to the selected pixel 180 (pixel circuit 181). First, the fifth scan signal SC5(n) changes from a state supplied with HI to a state supplied with LO. When the fifth scan signal SC5(n) is in a state supplied with LO, the second scan signal SC2(n) changes from a state supplied with HI to a state supplied with LO. When the second scan signal SC2(n) is in a state supplied with LO, the third scan signal SC3(n) changes from a state supplied with LO to a state supplied with HI. The first scan signal SC1(n), the fourth scan signal SC4(n), and the sixth scan signal SC6(n) are in a state supplied with LO.

[0116] Additionally, during the period PIN of KthFRAME, the image data signal SL(m) (data signal VDATA) is supplied with the potential of the data signal VDATA supplied to the selected pixel 180 (pixel circuit 181). When the third scan signal SC3(n) is supplied with HI, the sixth scan signal SC6(n) changes from being supplied with LO to being supplied with HI. After maintaining the state of being supplied with HI, the sixth scan signal SC6(n) changes from being supplied with HI to being supplied with LO. Furthermore, when the sixth scan signal SC6(n) is supplied with LO, the first scan signal SC1(n) changes from being supplied with LO to being supplied with HI. The second scan signal SC2(n), the fourth scan signal SC4(n), and the fifth scan signal SC5(n) maintain the state of being supplied with LO, and the third scan signal SC3(n) maintains the state of being supplied with HI.

[0117] As a result, during the period from the period PEM of K-1stFRAME to the period PIN of KthFRAME, the fifth transistor T5 and the seventh transistor T7 change from the ON state to the OFF state, and the current Ion no longer flows from the drive potential line PVDD to the light-emitting element OLED and the reference potential line PVSS. The sixth transistor T6 and the eighth transistor T8 change from the OFF state to the ON state, the potential difference between the first electrode 32 and the second electrode 34 of the light-emitting element OLED becomes 0V, the light-emitting element OLED stops emitting light, the first node N1 is connected to the reference potential line SVR, and a potential Vna (reference potential VREF, 2.2V) is supplied to the first node N1. Since a potential Vna has been supplied to the first node N1, and the potential supplied to the first node N1 maintains the potential Vna, the potential supplied to the first node N1 continues to maintain the potential Vna. Here, as an example, the potential Vna (2.2V) is the potential supplied to the first node N1 in the PEM during the light emission period of the K-1stFRAME when the threshold voltage VTH of the second transistor T2 is 1V (design value). For example, if the threshold voltage VTH is 1.1V due to manufacturing deviation, the potential Vna in the PEM during the light emission period of the K-1stFRAME becomes 2.3V. By supplying the reference potential VREF (2.2V) to the first node N1, the potential supplied to the first node N1 changes from the potential Vna (2.3V) to the reference potential VREF (2.2V). In addition, since the first transistor T1 and the third transistor T3 remain in the off state, the potential supplied to the second node N2 is maintained at potential Vnb. At this time, the potential difference Vgs is still 4V, and the second transistor T2 is in the on state. When the state of supplying HI to the sixth scan signal SC6(n) is reached, the fourth transistor T4 changes from the off state to the on state, and the third node N3 is connected to the initialization potential line SVI. Furthermore, since the second transistor T2 and the fourth transistor T4 are in the ON state, the current Ion flows from the fifth node N5 and the third node N3 toward the initialization potential line SVI. That is, the potential supplied to the fifth node N5 and the potential supplied to the third node N3 become the initialization potential VINI (potential Vnd, -1V). Then, when the state of supplying HI to the sixth scan signal SC6(n) changes to supplying LO, and then to supplying HI to the first scan signal SC1(n), the third transistor T3 changes from the OFF state to the ON state, the second node N2 is connected to the reset potential line SVRE, and the potential supplied to the second node N2 decreases from potential Vnb toward the reset potential (potential Vnc, 1V) to become potential Vnc.

[0118] As described above, during the period PIN, the first node N1 is initialized by the reference potential VREF, the second node N2 is initialized by the reset potential VRES, and the third node N3 (the fifth node N5) is initialized by the initialization potential VINI.

[0119] During the period PVH following the period PIN, the image data signal SL(m) (data signal VDATA) is supplied with the potential of the data signal VDATA supplied to the selected pixel 180 (pixel circuit 181), changing from the state of supplying LO to the state of supplying HI, and the fifth transistor T5 changes from the off state to the on state. Other scan signals and other transistors are in the same state as the period PIN.

[0120] As a result, during the PVH period, the first node N1 maintains the potential Vna, and the second node N2 maintains the potential Vnc. Furthermore, at the beginning of the PVH period, the potential difference Vgs is 2V, and the second transistor T2 is in the ON state. Since the eighth transistor T8, the fifth transistor T5, and the second transistor T2 are in the ON state, the fourth node N4, the fifth node N5, and the third node N3 are turned on, and the current Ion flows from the drive potential line PVDD to the fourth node N4, the fifth node N5, and the third node N3. Therefore, since the sixth scan signal SC6(n) has been supplied to LO, the fourth transistor is in the OFF state, and the potential supplied to the third node N3 is released, gradually rising from the potential Vnd (the third node N3 is charged). When the potential difference Vgs (the potential difference between the potential supplied to the second node N2 and the potential supplied to the third node N3) reaches the threshold voltage VTH, the second transistor T2 becomes OFF. At this time, the first node N1 maintains the potential Vna (2.2V), and the second node N2 maintains the potential Vnc (1V). Therefore, for example, when the threshold voltage VTH is 1V (design value), the potential supplied to the third node N3 becomes 0V. At this time, with the potential Vnc (reset potential VRST) supplied to the second node N2 as a reference, the potential difference between the potential Vnc supplied to the second node N2 (the second electrode 54 of the capacitor element CD) and the 0V supplied to the third node N3 (the first electrode 42 of the capacitor element CV) becomes the threshold voltage VTH (the potential of the third node N3 = VRES - VTH). In reality, the threshold voltage VTH may deviate during manufacturing; for example, when the threshold voltage VTH is 1.1V, the potential supplied to the third node N3 becomes -0.1V. Since the driving method of the display device 10 includes acquiring the threshold voltage VTH through operation during PVH and performing correction using the acquired threshold voltage VTH, the driving method of the display device 10 can achieve the correction of the threshold voltage VTH through operation during PVH.

[0121] As described above, during the PVH period, the threshold voltage VTH of the second transistor T2 is obtained by changing the potential difference Vgs of the second transistor T2 to the same operation as the threshold voltage VTH, and a charge equivalent to the threshold voltage VTH is maintained in the capacitor element CV.

[0122] During the period between period PVH and period PWR following period PVH, the image data signal SL(m) (data signal VDATA) is supplied with the potential of the data signal VDATA supplied to the selected pixel 180 (pixel circuit 181). First, the fifth scan signal SC5(n) changes from being supplied HI to being supplied LO. When it becomes supplied LO to the fifth scan signal SC5(n), the first scan signal SC1(n) changes from being supplied HI to being supplied LO. The third scan signal SC3(n) is in the supplied HI state, and the second scan signal SC2(n), the fourth scan signal SC4(n), and the sixth scan signal SC6(n) are in the supplied LO state. The fifth transistor T5 and the third transistor T3 change from the on state to the off state. The other transistors are in the same state as during period PVH. The potential supplied to the first node N1 is maintained at potential Vna, the potential supplied to the second node N2 is maintained at potential Vnc (1V), the potential supplied to the third node N3 is maintained at 0V, and the potential difference Vgs is 1V.

[0123] During the period PWR following the period between PVH and PWR, the image data signal SL(m) (data signal VDATA) is supplied with a potential VSIGL (0V). The fourth scan signal SC4(n) changes from being supplied with LO to being supplied with HI, and the first transistor T1 changes from being off to being on. Other control signals and transistors are in the same state as during period PVH. The potential supplied to the first node N1 is maintained at potential Vna, and the potential supplied to the third node N3 is maintained at 0V. By the first transistor T1 changing from being off to being on, the second node N2 is connected to the image data signal line 321, and the potential supplied to the second node N2 gradually decreases from potential Vnc toward 0V (potential VSIGL) to 0V. At this time, the capacitor element CD maintains the potential difference (based on the potential supplied to the first node N1, -2.2V) by maintaining a charge equivalent to the potential difference between Vna supplied to the first node N1 (reference potential VREF, 2.2V) and the potential difference between 0V supplied to the second node N2. Furthermore, capacitor CV maintains the potential difference (based on the potential supplied to the third node N3, 2.2V) by maintaining a charge equivalent to the potential difference between Vna (reference potential VREF, 2.2V) supplied to the first node N1 and 0V supplied to the third node N3. The sum of the potential difference maintained by capacitor CD and the potential difference maintained by capacitor CV (-2.2V + 2.2V) is 0V, that is, the potential difference Vgs is 0V. Therefore, the second transistor T2 is in the off state.

[0124] As described above, during the PWR period, a data signal VDATA is written to pixel 180 (pixel circuit 181). Additionally, the capacitor element CD maintains the data potential of the data signal VDATA.

[0125] During the period following PWR, the fourth scan signal SC4(n) changes from being supplied with HI to being supplied with LO. When it becomes the state of supplying LO to the fourth scan signal SC4(n), the third scan signal SC3(n) changes from being supplied with HI to being supplied with LO. When it becomes the state of supplying LO to the third scan signal SC3(n), the second scan signal SC2(n) changes from being supplied with LO to being supplied with HI. The first transistor T1, the sixth transistor T6, and the eighth transistor T8 change from the ON state to the OFF state, and the seventh transistor T7 changes from the OFF state to the ON state. Other scan signals and other transistors are in the same state as during period PWR. The potential supplied to the first node N1, which is capacitively coupled through capacitor elements CV and CD, is maintained at potential Vna, and the potential supplied to the second node N2 and the third node N3 is maintained at 0V. That is, the potential difference Vgs is maintained at 0V, and the second transistor T2 is in the OFF state.

[0126] During the PWR period of KthFRAME, following the PWR period, the image data signal SL(m) (data signal VDATA) is supplied with the potential of the data signal VDATA supplied to the selected pixel 180 (pixel circuit 181). Additionally, the fifth scan signal SC5(n) changes from being supplied with LO to being supplied with HI. Consequently, the fifth transistor T5 changes from being off to being on. Other scan signals and other transistors remain in the same state as during the period following the PWR period of KthFRAME.

[0127] As a result, the fifth transistor T5 becomes active, and the first electrode 32 of the OLED light-emitting element is connected to the second electrode 626 (fifth node N5) of the second transistor T2. The seventh transistor T7 becomes active, thus electrically connecting the third node N3 to the reference potential line PVSS, supplying the third node N3 with a reference potential VSSEL (0V). Since 0V is supplied to the third node N3, the potential supplied to the third node N3 remains at 0V. Additionally, the potential supplied to the second node N2 is maintained at 0V through the capacitive coupling of capacitors CD and CV. The first node N1 is also maintained at 2.2V through the capacitive coupling of capacitors CD and CV. It should be noted that, for example, if the threshold voltage TVH is 1V (set value) due to manufacturing, the potential supplied to the third node N3 remains unchanged at 0V even if the seventh transistor T7 is turned on. If the threshold voltage TVH is 1.1V due to manufacturing deviation, the potential supplied to the third node N3 becomes -0.1V, and the potential supplied to the third node N3 changes from -0.1V to 0V by turning on the seventh transistor T7. The potential difference Vgs is the sum of the potential difference maintained by capacitor CD and capacitor CV (the potential of data signal VDATA (potential VSIGL, 0V) - reference potential VREF (2.2V) + reference potential VREF (2.2V) - (reset potential VRES (1V) - threshold voltage VTH (1V) = 0V). In pixel 180 (pixel circuit 181) where data signal VDATA includes potential VSIGL, the potential difference Vgs is 0V, the second transistor T2 is off, and therefore no drain current Ion flows. As a result, the light-emitting element OLED does not emit light. Consequently, pixel 180 (pixel circuit 181) emitting red light becomes black. Similarly, as with pixel 180 emitting red light, pixel 180 emitting blue light and pixel 180 emitting green light also do not emit light. Therefore, by using the three pixels emitting red light, blue light, and green light, a black screen is achieved.

[0128] As described above, the display device 10 has the following structure: it does not include a transistor connected between the gate electrode 622 of the second transistor T2 and the second electrode 54 of the capacitor element CD, and the gate electrode 622 of the second transistor T2 is connected to the second electrode 54 of the capacitor element CD. Furthermore, the display device 10 has the following structure: a light-emitting element OLED is disposed between the second electrode 626 of the second transistor T2 and the driving potential line PVDD. Additionally, the display device 10 includes the following structure: a capacitor element CV and a capacitor element CD connected in series, the first electrode 52 of the capacitor element CD and the second electrode 44 of the capacitor element CV are connected to a first node N1, and a reference potential VREF is supplied to the first node N1; a potential difference corresponding to the charge corresponding to the data potential is acquired and maintained in the capacitor element CD based on the reference potential VREF, and a potential difference corresponding to the charge corresponding to the threshold voltage of the second transistor T2 is acquired and maintained in the capacitor element CV based on the reference potential VREF. Furthermore, the display device 10 is capable of independently controlling each node. Additionally, the driving method of the display device 10 includes performing a periodic PWR after the periodic PVH, and includes the step of supplying a driving potential VDDEL (or a potential larger than the driving potential VDDEL) to the fourth node N4 during the periodic PVH.

[0129] For example, in the driving method of the display device 10 including the above structure, during the PVH period, a driving potential VDDEL is supplied to the second electrode 626 of the second transistor T2, thereby increasing the current Ion flowing in the second transistor T2. As a result, the display device 10 can acquire the threshold voltage at high speed.

[0130] Furthermore, for example, the driving method of the display device 10 including the above structure can make the potential supplied to the gate electrode 622 of the second transistor T2 and the potential supplied to the first electrode 624 during the PWR period the same as the potential supplied to the gate electrode 622 of the second transistor T2 and the potential supplied to the first electrode 624 during the PEM period. As a result, the potential loss caused by the reduction of the write potential during light emission can be minimized.

[0131] Furthermore, the display device 10 can apply threshold voltage VTH information (data) to the low potential side of the potential difference Vgs of the second transistor T2 (the first electrode 42, the first electrode 624, and the third node N3 of the capacitor element CV) based on the reference potential VREF, and apply the potential of data signal VDATA to the high potential side of the potential difference Vgs of the second transistor T2 (the second electrode 54, the gate electrode 622, and the second node N2 of the capacitor element CD). During the period PWR to the light-emitting period PEM, the potential variation (potential variation) supplied to the first node N1, the second node N2, and the third node N3 can be minimized. In addition, the display device 10 can make the potential supplied to the gate electrode 622 of the second transistor T2 and the potential supplied to the first electrode 624 during the period PWR the same as the potential supplied to the gate electrode 622 of the second transistor T2 and the potential supplied to the first electrode 624 during the period PEM. Therefore, the display device 10 can suppress power consumption during the period from PWR to PEM, and can suppress charge redistribution caused by the gate capacitance (capacitance between gate electrode 622 and second electrode 626) of the second transistor T2 due to the potential change of the second node N2. As a result, the display device 10 can minimize the potential loss caused by the reduction of the write potential during light emission.

[0132] [1-5-2. A second example of a driving method for the display device 10]

[0133] Reference Figure 6 This section describes a second example of the driving method for pixel circuit 181. The driving method shown in the second example includes: after pixel 180 (pixel circuit 181) displays a white image in the previous frame (K-1st FRAME) based on the potential VSIGH included in the data signal VDATA, pixel 180 (pixel circuit 181) also displays a white image in Kth FRAME based on the potential VSIGH included in the data signal VDATA. In other words, the driving method shown in the second example includes displaying images of the same color (white) in consecutive frames. The method can be adjusted as needed. Figures 1-5 Explain the same or similar structures.

[0134] The potentials of each node during the light emission period PEM of K-1thFRAME to the period PVH of K-1thFRAME, and during the period between the period PVH of K-1thFRAME and the period PWR of K-1thFRAME, are the same as those described in "1-5-1. First Example of Driving Method of Display Device 10". Furthermore, the structure of each scan signal and the operation of each transistor during each period are the same as those described in "1-5-1. First Example of Driving Method of Display Device 10". Therefore, structures identical to those described in "1-5-1. First Example of Driving Method of Display Device 10" will be described as needed, and some omissions will be made. It should be noted that the image data signal SL(m) is supplied with a data signal VDATA including VSIGH (4V) corresponding to white during the period PWR of K-1thFRAME, and is supplied with the same data signal VDATA as described in "1-5-1. First Example of Driving Method of Display Device 10" during periods other than the period PWR of K-1thFRAME.

[0135] During the light emission period PEM of the K-1stFRAME, similar to the structure described in "1-5-1. First Example of Driving Method of Display Device 10", the pixel 180 emits white light by using three pixels: a pixel 180 that emits red light, a pixel 180 that emits blue light, and a pixel 180 that emits green light.

[0136] During the period from the light emission period PEM of K-1stFRAME to the period PIN of KthFRAME, similar to the structure described in "1-5-1. First Example of Driving Method of Display Device 10", the first node N1 is initialized by the reference potential VREF, the second node N2 is initialized by the reset potential VRES, and the third node N3 (fifth node N5) is initialized by the initialization potential VINI.

[0137] In the period PVH following the period PIN, similar to the structure described in "1-5-1. First example of the driving method of display device 10", the threshold voltage VTH of the second transistor T2 is obtained by changing the potential difference Vgs of the second transistor T2 to the same operation as the threshold voltage VTH, and the charge equivalent to the threshold voltage VTH is maintained in the capacitor element CV.

[0138] During the period between the period PVH and the period PWR following the period PVH, similar to the structure described in "1-5-1. First Example of Driving Method of Display Device 10", the potential maintenance potential Vna supplied to the first node N1, the potential maintenance potential Vnc (1V) supplied to the second node N2, the potential maintenance potential 0V supplied to the third node N3, and the potential difference Vgs is 1V.

[0139] During the period PWR following the period PVH, the image data signal SL(m) (data signal VDATA) is supplied with a potential VSIGH (potential Vnb, e.g., 4V). The potential supplied to the first node N1 is maintained at potential Vna, and the potential supplied to the third node N3 is maintained at 0V. The potential supplied to the second node N2 gradually rises from potential Vnc (reset potential VRES, 1V) toward potential Vnb, becoming potential Vnb. At this time, the capacitor element CD maintains this potential difference (based on the potential supplied to the second node N2, 1.8V) by maintaining a charge equivalent to the potential difference (1.8V) between Vna supplied to the first node N1 (reference potential VREF, 2.2V) and the 4V (potential VSIGH) supplied to the second node N2. Furthermore, capacitor CV maintains the potential difference (based on the potential supplied to the third node N3, 2.2V) by maintaining a charge equivalent to the potential difference between Vna (reference potential VREF, 2.2V) supplied to the first node N1 and 0V supplied to the third node N3. The sum of the potential difference maintained by capacitor CD and the potential difference maintained by capacitor CV (1.8V + 2.2V) is 4V, and the potential difference Vgs is 4V. Therefore, the second transistor T2 is in the ON state. For example, if the threshold voltage VTH deviates and the potential supplied to the third node N3 becomes 0.1V (assuming the threshold voltage VTH becomes 0.9V and the potential of the third node N3 is VRES(1V) - VTH(0.9V) = 0.1V), the potential difference Vgs becomes 3.9V (Vgs = (VDATA(Vnb, 4V) - VREF(2.2V)) + (VREF(2.2V) - 0.1V). That is, if the threshold voltage VTH is 0.1V lower than the design value, the write potential difference Vgs becomes 3.9V, which is 0.1V lower than the design value of 4V.

[0140] As described above, during the PWR period, a data signal VDATA is written to pixel 180 (pixel circuit 181). Additionally, the capacitor element CD maintains the data potential of the data signal VDATA.

[0141] During the period following PWR, the potential maintained at Vna is supplied to the first node N1, which is capacitively coupled through capacitor elements CV and CD; the potential maintained at Vnb is supplied to the second node N2; and the potential maintained at 0V is supplied to the third node N3. That is, the potential difference Vgs is maintained at 4V, and the second transistor T2 is in the ON state.

[0142] During the PWR period following the KthFRAME, the potential supplied to the third node N3 is maintained at 0V, and the potential supplied to the second node N2 is maintained at 4V through the capacitive coupling of the capacitor element CD and the capacitor element CV. The potential difference Vgs is the sum of the potential difference held by capacitor CD and capacitor CV (the potential of data signal VDATA (potential VSIGH, 4V) - reference potential VREF (2.2V) + reference potential VREF (2.2V) - (reset potential VRES (1V) - threshold voltage VTH (1V) = 4V). When data signal VDATA includes potential VSIGH, the potential difference Vgs is 4V, the second transistor T2 is turned on, so current Ion flows from the drive potential line PVDD to the light-emitting element OLED and the reference potential line PVSS, and the light-emitting element OLED emits light. For example, pixel 180 emitting red light, pixel 180 emitting blue light, and pixel 180 emitting green light emit light respectively, and white is achieved by using the three pixels emitting red light, blue light, and green light. That is, based on data signal VDATA and the corrected threshold voltage, pixel 180 (pixel circuit 181) can display an image.

[0143] The second example of the driving method for the display device 10 has the same effect as that described in "1-5-1. The first example of the driving method for the display device 10".

[0144] [1-5-3. A third example of a driving method for display device 10]

[0145] Reference Figure 7 This describes a third example of the driving method for the display device 10. The driving method shown in the third example includes: after pixel 180 (pixel circuit 181) displays a black image in the Kth FRAME based on the potential VSIGL included in the data signal VDATA, in the previous frame (K-1st FRAME) of the current frame (Kth FRAME), pixel 180 (pixel circuit 181) also displays a black image in the Kth FRAME based on the potential VSIGL included in the data signal VDATA. In other words, the driving method shown in the third example includes displaying images of the same color (black) in consecutive frames. The method can be adjusted as needed. Figures 1-6Explain the same or similar structures.

[0146] The potentials of each node in the PEM during the KthFRAME's PVH to KthFRAME's light-emitting period are the same as those described in "1-5-1. First Example of a Driving Method for Display Device 10". Furthermore, the structures of each scan signal in each period and the operation of each transistor are the same as those described in "1-5-1. First Example of a Driving Method for Display Device 10". Therefore, the same structures as those described in "1-5-1. First Example of a Driving Method for Display Device 10" will be described as needed.

[0147] During the light emission period of the K-1stFRAME in the PEM, for example, the potential maintained by the first node N1 is Vna (2.2V). Meanwhile, the potential supplied to the second node N2 and the potential maintained by the third node N3 are 0V, and the potential difference Vgs is 0V. Therefore, the second transistor T2 is in the off state, the drain current Ion does not flow, and the OLED does not emit light.

[0148] As a result, the red-emitting pixel 180 (pixel circuit 181), the blue-emitting pixel 180, and the green-emitting pixel 180 do not emit light, and become black by using the three pixels that emit red light, blue light, and green light.

[0149] During the period from the PEM of the K-1stFRAME to the period PIN of the KthFRAME, following the PEM of the K-1stFRAME's light emission, similar to the structure described in "1-5-1. First Example of the Driving Method of Display Device 10", the potential supplied to the first node N1 is maintained at potential Vna (reference potential VREF), the potential supplied to the fifth node N5 and the potential supplied to the third node N3 are initialized at potential VINI (potential Vnd, -1V). During the period when the third transistor T3 remains in the off state, the potential supplied to the second node N2 remains at 0V. When the state of supplying HI to the sixth scan signal SC6(n) changes to the state of supplying LO, and then to the state of supplying HI to the first scan signal SC1(n), the third transistor T3 changes from the off state to the on state, the second node N2 is connected to the reset potential line SVRE, and the potential supplied to the second node N2 gradually rises from 0V toward the reset potential (potential Vnc, 1V) to become potential Vnc. Therefore, the potential difference Vgs is 2V (1V-(-1V)=2V), and the second transistor T2 is in the ON state.

[0150] As described above, similar to the structure explained in "1-5-1. First Example of Driving Method for Display Device 10", in the period PIN, the first node N1 is initialized by the reference potential VREF, the second node N2 is initialized by the reset potential VRES, and the third node N3 (the fifth node N5) is initialized by the initialization potential VINI.

[0151] In the period PVH following the period PIN, similar to the structure described in "1-5-1. First example of the driving method of display device 10", the threshold voltage VTH of the second transistor T2 is obtained by changing the potential difference Vgs of the second transistor T2 to the same operation as the threshold voltage VTH, and the charge equivalent to the threshold voltage VTH is maintained in the capacitor element CV.

[0152] During the period PWR following the period PVH, a data signal VDATA is written to the pixel 180 (pixel circuit 181) in the same manner as described in "1-5-1. First Example of Driving Method for Display Device 10". Additionally, the capacitor element CD maintains the data potential of the data signal VDATA.

[0153] During the light-emitting period PEM of the KthFRAME following the PWR period and the period after the PWR period, the pixel circuit 181 operates in the same manner as the structure described in "1-5-1. First Example of Driving Method of Display Device 10". The potential difference Vgs is 0V, the second transistor T2 is in the off state, so the drain current Ion does not flow, and the light-emitting element OLED does not emit light. As a result, pixel 180 becomes black by using three pixels: pixel 180 emitting red light, pixel 180 emitting blue light, and pixel 180 emitting green light.

[0154] The third example of the driving method of the display device 10 has the same effect as that described in "1-5-1. The first example of the driving method of the display device 10".

[0155] [1-5-4. Fourth example of a driving method for display device 10]

[0156] Reference Figure 8This describes a fourth example of the driving method for the display device 10. The driving method shown in the fourth example includes: after pixel 180 (pixel circuit 181) displays a black image in the previous frame (K-1st FRAME) based on the potential VSIGL of the data signal VDATA, pixel 180 (pixel circuit 181) displays a white image in Kth FRAME based on the potential VSIGH of the data signal VDATA. In other words, the driving method shown in the fourth example includes displaying images of different colors in consecutive frames. The method can be adjusted as needed. Figures 1-7 Explain the same or similar structures.

[0157] The potentials of each node, the structure of each scan signal, and the operation of each transistor in the period from the light-emitting period PEM of K-1stFRAME to the period PVH of KthFRAME are the same as those described in "1-5-3. Third Example of Driving Method for Display Device 10". Furthermore, the potentials of each node, the structure of each scan signal, and the operation of each transistor in the period from the period PVH of KthFRAME to the light-emitting period PEM of KthFRAME are the same as those described in "1-5-2. Second Example of Driving Method for Display Device 10". Therefore, the description is omitted here.

[0158] The fourth example of the driving method for the display device 10 has the same effect as that described in "1-5-1. The first example of the driving method for the display device 10".

[0159] [1-6. End face structure of pixel 180]

[0160] Reference Figures 9-13 This describes the end face structure of pixel 180. Figure 9 This is a layout diagram of the pixels 180 when viewing the display device 10 from the surface (first surface 101A) side. Figure 10 This is a layout diagram of the pixels 180 when viewing the display device 10 from the rear (second side 101B) side. Figure 11 It shows along Figure 9 End face view of the cut-off end face of A1-A2 in the layout shown. Figure 12 It shows along Figure 9 End face view of the cut-off end face of B1-B2 in the layout shown. Figure 13 It shows along Figure 9 End face view of the cut end face after C1-C2 in the layout shown. Figure 9 as well as Figure 10 The layout of the 180 pixels shown and Figures 11-13 The end face of pixel 180 shown is an example; the layout and end face of pixel 180 are not limited to this. Figures 9-13 The example shown. Adjustments can be made as needed. Figures 1-8 Explain the same or similar structures.

[0161] It is important to note that, in Figure 9 In the layout of pixel 180 shown, for ease of observation of the accompanying drawings, portions other than the semiconductor layer 122, gate wiring 127, conductive layer 132, first contact hole opening 135, organic insulating film opening 137, second contact hole opening 138, second wiring 140, and contact hole opening 147 for the cathode electrode are omitted. Additionally, in Figure 10 In the layout of the 180 pixels shown, dashed lines are used to indicate the components for easier observation of the accompanying drawings. Figure 9 The elements of the first wiring 132J, 132L, and 132M, the back-side openings 191A-191D, and the vias 192A-192D are shown. Back-side wiring 193A-193D is shown in solid lines. Other elements and their reference numerals are omitted. Additionally, Figure 12 as well as Figure 13 The end face of the pixel 180 shown omits the structure along the third direction D3 above the insulating layer 141 (the side opposite to the substrate 101).

[0162] Additionally, as an example of the end face with pixel 180, Figure 11 The end face of pixel 180 shown is the end face along the first wiring 132M, functional layer 148, contact hole opening 147A for the cathode electrode, second wiring 140C, second contact hole opening 138E, first wiring 132I, first contact hole opening 135I, semiconductor layer 122D, gate wiring 127E, first wiring 132E, and first contact hole opening 135D. As an example of the end face of pixel 180, Figure 12 The end face of pixel 180 shown is the end face along the second wiring 140D, the organic insulating film opening 137A for capacitor element CS, the first wiring 132G, the first contact hole opening 135H, the semiconductor layer 122A, the second wiring 140A, the organic insulating film opening 137B for capacitor element CS, the first wiring 132D, the gate wiring 127A, the first wiring 132C, the organic insulating film opening 137A for capacitor element CS, and the semiconductor layer 122B. As an example of the end face of pixel 180, Figure 13 The end face of the pixel 180 shown is the end face along the back wiring 193C, semiconductor layer 122A, first wiring 132F, first contact hole opening 135E, gate wiring 127C, back wiring 193A, back side opening 191A and via 192A.

[0163] The substrate 101 includes a first surface 101A and a second surface 101B opposite to the first surface 101A. A semiconductor layer 122 is disposed on the first surface 101A of the substrate 101, separated by a base layer 121. The semiconductor layer 122 includes semiconductor layers 122A, 122B, 122D, and 122C. Semiconductor layer 122B includes a channel region 123 (see reference). Figure 16 ) and impurity region 124A (refer to Figure 16 For example, the impurity region is called the source region or the drain region. Additionally, for example, the second transistor T2 (see...) Figure 16 ) includes semiconductor layer 122B, first electrode 624 (refer to Figure 16 ) and the second electrode 626 (refer to Figure 16 The semiconductor layer 122B includes the impurity region 124A. In other words, the semiconductor layer 122B includes the channel region of the second transistor T2.

[0164] Similar to semiconductor layer 122B, the first transistor T1 (refer to...) Figure 16 ) and the third transistor T3 (refer to Figure 16 This includes semiconductor layer 122A and fourth transistor T4 (see reference). Figure 16 ) and the seventh transistor T7 (refer to Figure 16 This includes semiconductor layer 122C, and the fifth transistor T5 (see reference). Figure 16 ) and the eighth transistor T8 (refer to Figure 16 The transistor includes a semiconductor layer 122D. Additionally, the first electrode and second electrode of each transistor include impurity regions. For example, the first electrode 614 of the first transistor T1 (see reference...) Figure 16 ) and the second electrode 616 (refer to) Figure 16 ), and the first electrode 634 of the third transistor T3 (refer to Figure 16 ) and the second electrode 636 (refer to) Figure 16 The semiconductor layer 122A includes the channel region of the first transistor T1 and the channel region of the third transistor T3, and serves as both the channel region of the first transistor T1 and the channel region of the third transistor T3.

[0165] Above the semiconductor layer 122, a gate insulating layer 125, a conductive layer 126, an insulating layer 128, and a conductive layer 132 are sequentially disposed. The conductive layer 126 includes gate wiring 127E (gate electrode 652), gate wiring 127A (gate electrode 622), and gate wiring 127C (scan signal line 330, gate electrode 632). The conductive layer 132 includes first wiring 132M (drive potential line PVDD), first wiring 132I, first wiring 132E, first wiring 132D (first electrode 42), first wiring 132C (second electrode 54), and first wiring 132F. It should be noted that the area where the conductive layer 126 overlaps with the semiconductor layer 122 is the channel region. In other words, the area where the gate electrode of each transistor overlaps with the semiconductor layer is the channel region.

[0166] Each transistor of pixel 180 is formed using a semiconductor layer 122 (e.g., semiconductor layer 122B, channel region 123, and impurity region 124A), a gate insulating layer 125, and a conductive layer 126 (e.g., gate wiring 127A).

[0167] First contact hole openings 135I, 135D, and 135A, reaching the semiconductor layer 122, penetrate the gate insulating layer 125 and the insulating layer 128 and are disposed thereon. For example, the first contact hole openings 135I and 135D expose the semiconductor layer 122D (e.g., the second electrode 656 and the first electrode 654), and the first wiring 132I is electrically connected to the semiconductor layer 122D through the first contact hole openings 135I and 135D. Additionally, the first contact hole opening 135E exposes the semiconductor layer 122A (e.g., the second electrode 626), and the first wiring 132F is electrically connected to the semiconductor layer 122A through the first contact hole opening 135E. Furthermore, the first wiring 132C (refer to...) Figure 17 ) through the first contact hole opening 135N (refer to Figure 17 The first wiring 132C is electrically connected to the gate wiring 127A and passes through the first contact hole opening 135B (see reference). Figure 17 It is electrically connected to the semiconductor layer 122A. That is, the opening of the first contact hole can penetrate the gate insulating layer 125 and the insulating layer 128 and open to expose the semiconductor layer 122. The opening of the first contact hole can also penetrate the insulating layer 128 and open to expose the conductive layer 126.

[0168] Insulating layer 131 is provided such that it covers conductive layer 132 and the insulating layer 131 not exposed by conductive layer 132. Insulating layer 136 is provided such that it covers insulating layer 131.

[0169] The second contact hole opening is disposed on insulating layer 131 and insulating layer 136. For example, the second contact hole opening includes second contact hole opening 138E. Additionally, organic insulating film openings 137A and 137B for capacitor element CS are disposed on insulating layer 136. Conductive layer 139 is disposed on insulating layer 136, organic insulating film openings 137A and 137B for capacitor element CS, and second contact hole opening 138E. Conductive layer 139 includes second wiring 140C (first electrode 32) and second wiring 140D (first electrode 52 and second electrode 44). Second contact hole opening 138E penetrates insulating layer 136 and exposes first wiring 132I. Second wiring 140C is electrically connected to first wiring 132I via second contact hole opening 138E. Organic insulating film openings 137A and 137B for capacitor element penetrate insulating layer 136 and expose insulating layer 131. For example, capacitor element CV is formed using insulating layer 131 as dielectric and first wiring 132D (first electrode 42) and second wiring 140D (second electrode 44), while capacitor element CD is formed using insulating layer 131 as dielectric and first wiring 132C (second electrode 54) and second wiring 140C (first electrode 52). For example, second wiring 140C also serves as a pixel electrode. Furthermore, although not shown in the figures, for example, the second contact hole opening 138 exposes a portion of the plurality of terminals (not shown) included in terminal portion 150. A portion of the exposed terminals is electrically connected to FPC 200 using a conductive film such as an anisotropic conductive film (not shown). Furthermore, pixel electrodes are provided independently for each pixel.

[0170] An insulating layer 141 is disposed on an insulating layer 136 on which no conductive layer 139 is disposed, and is disposed in such a way as to cover the conductive layer 139.

[0171] For example, the base layer 121, semiconductor layer 122, gate insulating layer 125, conductive layer 126, insulating layer 128, conductive layer 132, insulating layer 131, insulating layer 136, conductive layer 139, and insulating layer 141 are collectively referred to as array section 170.

[0172] Next, the multiple layers stacked on the insulating layer 141 will be described. A contact hole opening 147 for the cathode electrode is provided on the insulating layer 141. The contact hole opening 147 for the cathode electrode includes a contact hole opening 147A for the cathode electrode. The contact hole opening 147A for the cathode electrode penetrates through the insulating layer 141 and is provided on the insulating layer 141, exposing the conductive layer 139 (e.g., the second wiring 140C).

[0173] The cathode electrode 143 is provided to cover the exposed conductive layer 139, the contact hole opening 147A for the cathode electrode, and the insulating layer 141. A functional layer 148 is provided on top of the cathode electrode 143. A common electrode 149 is provided on top of the functional layer 148, covering it. The common electrode 149 is electrically connected to the cathode electrode (the first electrode 32 of the OLED). Here, the OLED is composed of the cathode electrode 143, the functional layer 148, and the common electrode 149 (anode electrode).

[0174] The structure of functional layer 148 can be appropriately selected. For example, functional layer 148 can be constructed by combining carrier injection layer, carrier transport layer, light emission layer, carrier blocking layer, exciton blocking layer, etc. For example, Figure 9 The functional layer 148 shown includes a first layer 144, a second layer 145, and a third layer 146. For example, the first layer 144 is a carrier (electron) injection and transport layer, the second layer 145 is a light-emitting layer, and the third layer 146 is a carrier (hole) injection and transport layer. For example, the functional layer 148 is set independently for each pixel, just like the pixel electrodes.

[0175] A sealing film 165 is disposed on the common electrode 149. For example, the sealing film 165 includes a first inorganic insulating layer 152, an organic insulating layer 154, and a second inorganic insulating layer 156. It should be noted that the first inorganic insulating layer 152 and the second inorganic insulating layer 156 are formed in such a way that they at least cover the display area 22. A cover film 158 is disposed on the second inorganic insulating layer 156.

[0176] For example, the first layer 144, the second layer 145 (light-emitting layer), and the third layer 146, as well as the common electrode 149, included in the functional layer 148 are not disposed on the IC chip 110 and the control circuit 120. A sealing film 165 and a cover film 158 are disposed on the IC chip 110 and the control circuit 120. The sealing film 165 and the cover film 158 prevent impurities (water, oxygen, etc.) from entering the light-emitting element OLED and various transistors from the outside of the display device 10.

[0177] Next, the multiple layers stacked on the back side opening, via 192, and the second surface 101B (back side) will be described. For example, the back side opening includes a back side opening 191A, which penetrates the substrate 101, the base layer 121, the gate insulating layer 125, and the insulating layer 128, and is disposed on the substrate 101, the base layer 121, the gate insulating layer 125, and the insulating layer 128, exposing the conductive layer 132 (first wiring 132F). That is, the multiple back side openings penetrate the substrate 101, the base layer 121, the gate insulating layer 125, and the insulating layer 128, and are disposed on the substrate 101, the base layer 121, the gate insulating layer 125, and the insulating layer 128, respectively, and expose the conductive layer 132 on each of the back side openings.

[0178] For example, via 192 includes via 192A, which is disposed on the substrate 101, base layer 121, gate insulating layer 125, insulating layer 128, and exposed conductive layer 132 (first wiring 132F) through the back side opening portion 191A. That is, a plurality of vias 192 are respectively disposed on their respective back side opening portions and their respective exposed conductive layers 132.

[0179] For example, a conductive layer 193 is disposed on the second surface 101B. For example, the conductive layer 193 includes a back trace 193A (Reset Potential Line SVRE) and a reference potential line 193C. The back trace 193C is electrically connected to a via 192A.

[0180] The insulating layer 190 is provided such that it covers the second surface 101B where the conductive layer 193 is not provided, as well as the conductive layer 193. Additionally, the back side organic insulating film opening 194 (see reference) Figure 22 A pad 195 is disposed on the exposed conductive layer 193 and the insulating layer 190, penetrating the insulating layer 190.

[0181] As substrate 101, a rigid substrate without flexibility, such as a glass substrate, quartz substrate, sapphire substrate, or silicon substrate, can be used. Alternatively, substrate 101 can be flexible; for example, a flexible substrate containing resin, such as a polyimide substrate, acrylic substrate, siloxane board, or fluoropolymer substrate, can be used as substrate 101.

[0182] The conductive layers 126, 132, 139, common electrode 149, via 192, and conductive layer 193 are made of common metallic materials. For example, aluminum (Al), titanium (Ti), chromium (Cr), cobalt (Co), nickel (Ni), molybdenum (Mo), hafnium (Hf), tantalum (Ta), tungsten (W), bismuth (Bi), silver (Ag), copper (Cu), and their alloys or compounds are used as common metallic materials.

[0183] For example, semiconductor layer 122 may contain crystalline silicon or metal oxide.

[0184] The materials used to form the substrate layer 121, gate insulating layer 125, insulating layer 131, first inorganic insulating layer 152, and second inorganic insulating layer 156 can be general insulating materials. For example, silicon oxide (SiO2) can be used as these insulating layers. x ), silicon oxynitride (SiO) x N y Silicon nitride (SiN) x ), silicon oxynitride (SiN) x O y Inorganic insulating layers such as ( ).

[0185] The materials used to form insulating layers 128, 136, 141, 154, and 190 can be, for example, organic compound materials with excellent surface flatness. Insulating layers 128, 136, 141, and 190 are sometimes referred to as organic insulating layers. Additionally, insulating layer 190 is sometimes referred to as a back-side organic insulating layer.

[0186] [1-7. Method for manufacturing display device 10]

[0187] Reference Figure 9 , Figure 10 , Figures 14-22 This describes the manufacturing method of the display device 10 (pixel 180). Figure 14 as well as Figure 15 This is a timing diagram showing the manufacturing method of the display device 10. Figures 16-18 This is a layout diagram of the pixels 180 when viewing the display device 10 from the surface (first surface 101A) side. Figures 19-22 This is an end view view showing the end face of the display device 10 (pixel 180). Adjustments can be made as needed. Figures 1-13 Explanations of similar or identical structures are sometimes omitted. As an example, Figure 13 The manufacturing method shown includes an oxide semiconductor layer formed using an oxide semiconductor.

[0188] When the manufacturing of the display device 10 (pixel 180) begins, the substrate 121 (refer to...) Figures 11-13 , Figures 19-22 ) is formed on substrate 101 (refer to Figures 11-13 , Figures 19-22 ) First face 101A (refer to) Figures 11-13 , Figures 19-22 () Figure 14 Step 10 (S10). For example, substrate 101 is a glass substrate.

[0189] like Figure 9 , Figures 16-18 As shown, semiconductor layer 122 includes semiconductor layers 122A, 122B, 122C, 122D, and 122E. Semiconductor layer 122A serves as the semiconductor layer for both the first transistor T1 and the third transistor T3. Semiconductor layer 122B serves as the semiconductor layer for the second transistor T2. Semiconductor layer 122C serves as the semiconductor layer for both the fourth transistor T4 and the seventh transistor T7. Semiconductor layer 122D serves as the semiconductor layer for both the fifth transistor T5 and the eighth transistor T8. Semiconductor layer 122E serves as the semiconductor layer for the sixth transistor T6. In other words, semiconductor layer 122A includes the channel region of the first transistor T1 and the channel region of the third transistor T3, semiconductor layer 122B includes the channel region of the second transistor T2, semiconductor layer 122C includes the channel region of the fourth transistor T4 and the channel region of the seventh transistor T7, semiconductor layer 122D includes the channel region of the fifth transistor T5 and the channel region of the eighth transistor T8, and semiconductor layer 122E includes the channel region of the sixth transistor T6.

[0190] Gate insulating layer 125 (reference) Figures 11-13 , Figures 19-22 ) is formed on the semiconductor layer 122 and on the substrate layer 121 where the semiconductor layer 122 is not formed. Figure 14 Step 12 (S12)).

[0191] A conductive layer 126 is formed on the gate insulating layer 125 (see reference). Figures 11-13 , Figures 19-22 () Figure 14 Step 13 (S13)). For example... Figure 9 , Figures 16-18As shown, the conductive layer 126 includes gate wiring 127A (gate electrode 622), gate wiring 127B (scan signal line 333), gate wiring 127C (scan signal line 330), gate wiring 127D (scan signal line 335), gate wiring 127E (scan signal line 334), gate wiring 127F (scan signal line 332), and gate wiring 127G (scan signal line 331). Gate wiring 127B includes gate electrode 612, gate wiring 127C includes gate electrode 632, gate wiring 127D includes gate electrode 642, gate wiring 127E includes gate electrode 652, gate wiring 127F includes gate electrodes 662 and 682, and gate wiring 127G includes gate electrode 672.

[0192] The region where the gate electrode 622 of the second transistor T2 overlaps with the semiconductor layer 122B is the channel region 123, which corresponds to the channel length of the second transistor T2. Similarly, the region where the gate electrode 612 of the first transistor T1 overlaps with the semiconductor layer 122A is the channel region of the first transistor T1, and also corresponds to its channel length. For transistors other than the second transistor T2 and the first transistor T1, the region where the gate electrode overlaps with the semiconductor layer is the channel region of the transistor, and also corresponds to its channel length.

[0193] like Figure 16 As shown, in a top-down view, the channel region 123 of the second transistor T2 is larger (longer) than the channel regions of the first transistor T1, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8. That is, the channel length of the second transistor T2 is longer than the channel lengths of the first transistor T1, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8. Since the second transistor T2 operates in the saturation region, it is necessary to suppress the kink effect. Therefore, the second transistor T2 needs to have higher tolerance to hot carriers than the other transistors within pixel 180. To suppress kinking effects and ensure reliability (hot carrier tolerance), the channel length of the second transistor T2 is longer than that of the other transistors within pixel 180.

[0194] Insulation layer 128 (reference) Figures 11-13 , Figures 19-22 ) is formed on the conductive layer 126 and on the gate insulating layer 125 where the conductive layer 126 is not formed. Figure 14 Step 14 (S14)).

[0195] like Figure 9 , Figures 16-18 As shown, the first contact hole opening portion 135A~135M is opened ( Figure 14 Step 15 (S15)). Each opening is formed in the gate insulating layer 125 and the insulating layer 128, exposing the wiring, semiconductor layer, or electrode corresponding to each opening. For example, the first contact hole opening 135A exposes the semiconductor layer 122A, and the first contact hole opening 135N exposes the gate wiring 127A. The other openings also expose their respective wiring, semiconductor layer, or electrode.

[0196] A conductive layer 132 is formed on top of the insulating layer 128 (see reference). Figures 11-13 , Figures 19-22 () Figure 14 Step 16 (S16)). For example... Figure 9 , Figures 16-18 As shown, the conductive layer 132 includes first wiring 132A (image data signal line 321), first wiring 132B, first wiring 132C (second electrode 54), first wiring 132D (first electrode 42), first wiring 132E, first wiring 132F, first wiring 132G (initialization potential line SVI), first wiring 132H, first wiring 132I, first wiring 132J, first wiring 132K, first wiring 132L (reference potential line PVSS), and first wiring 132M (drive potential line PVDD).

[0197] like Figure 17 As shown, in a top view, for example, the first wiring 132B is electrically connected to the first transistor T1 via the first contact hole opening 135A. Additionally, the first wiring 132C is electrically connected to both the first transistor T1 and the third transistor T3 via the first contact hole opening 135B, and is also electrically connected to the gate wiring 127A via the first contact hole opening 135C. Other first wirings are also electrically connected to the gate wiring or transistors (semiconductor layer 122) via their respective corresponding openings.

[0198] In addition, such as Figure 17 As shown, the first wiring 132C (second electrode 54), the gate wiring 127A (gate electrode 622), and the semiconductor layer 122B (channel region 123) overlap. That is, the second transistor T2 (channel region 123 and gate electrode 622) overlaps with the second electrode 54 of the capacitor element CD. In addition, the first wiring 132C (second electrode 54) and the first wiring 132D (first electrode 42) are arranged adjacent to each other along the second direction D2 above the gate electrode 622.

[0199] Insulating layer 131 (reference) Figures 11-13 , Figures 19-22 ) is formed on the conductive layer 132 and on the insulating layer 128 where the conductive layer 132 is not formed. Figure 14 Step 17 (S17)).

[0200] like Figure 9 , Figure 17 or Figure 18 As shown, the second contact hole opening portions 138B~138F are made open ( Figure 14 Step 18 (S18)). Each opening portion is made in the insulating layer 131, so that the wiring corresponding to each opening portion is exposed.

[0201] Insulating layer 136 (organic insulating layer) (refer to) Figures 11-13 , Figures 19-22 ) is formed on the insulating layer 131 ( Figure 14 Step 19 (S19)).

[0202] like Figure 9 , Figure 17 or Figure 18 As shown, insulating layer 136 (organic insulating layer) has openings ( Figure 14 Step 20 (S20)). In the openings of S20, openings 137A and 137B of the organic insulating film for the capacitor element are made. Additionally, in the openings of S20, similar to the openings of S18, second contact hole openings 138B to 138F are made. That is, second contact hole openings 138B to 138F are made twice. Each opening is made in the insulating layer 136, exposing the corresponding insulating layer, wiring, or electrode. For example, in the organic insulating film opening 137A for the capacitor element, only the insulating layer 136 above the first wiring 132C (second electrode 54) is removed, exposing the insulating layer 131. On the other hand, in the organic insulating film opening 137B for the capacitor element, only the insulating layer 136 above the first wiring 132D (first electrode 42) is removed, exposing the insulating layer 131. The other openings also expose their respective corresponding insulating layers, wiring, or electrodes.

[0203] Conductive layer 139 (reference) Figures 11-13 , Figures 19-22 ) is formed on the insulating layer 136, on the insulating layer 131 exposed at the opening 137A of the organic insulating film for the capacitor element, and on the insulating layer 131 exposed at the opening 138B of the organic insulating film for the capacitor element. Figure 14 Step 21 (S21)). For example... Figure 9 or Figure 16As shown, the conductive layer 139 includes a second wiring 140A, a second wiring 140B, a second wiring 140C (first electrode 32), and a second wiring 140D (first electrode 52 and second electrode 44).

[0204] like Figure 18 As shown, when viewed from above, the second wiring 140A is electrically connected to the first wiring 132A (image data signal line 321) via the second contact hole opening 138A, and is electrically connected to the first transistor T1 via the second contact hole opening 138B, the first wiring 132B, and the first contact hole opening 135A. Other second wirings are also electrically connected to the first wiring, the gate wiring, or the transistor (semiconductor layer 122) via their respective corresponding openings.

[0205] In addition, such as Figure 18 As shown, the second wiring 140D (first electrode 52 and second electrode 44), the first wiring 132C (second electrode 54), the gate wiring 127A (gate electrode 622), and the semiconductor layer 122B (channel region 123) overlap. That is, the second transistor T2 overlaps with the capacitor element CD. Furthermore, the second wiring 140D (first electrode 52 and second electrode 44), the first wiring 132D (first electrode 42), and the gate wiring 127A (gate electrode 622) overlap, and the first electrode 42 and the second electrode 54 are arranged adjacent to each other on the gate electrode 622. That is, the capacitor element CV and the capacitor element CD are arranged adjacent to each other along the second direction D2.

[0206] Insulating layer 141 (organic insulating layer) (refer to) Figures 11-13 , Figures 19-22 ) is formed on the conductive layer 139 and on the insulating layer 136 where the conductive layer 139 is not formed. Figure 14 Step 22 (S22)).

[0207] For example, since multiple display devices 10 are formed using a mother glass, the mother glass is broken (the substrate is broken), thus making the multiple display devices 10 monolithic. Figure 14 Step 23 (S23)). It should be noted that, for example, S23 is performed by attaching a protective film to the mother glass.

[0208] After S23, the second surface 101B side of the monolithic display device 10 is ground. Figure 14 Step 24 (S24). At this time, the size of the monolithized substrate is preferably such that it can be chemically mechanically polished (CMP). S24 can be performed using a polishable apparatus. For example, S24 can be performed using CMP. For example, in Figure 19 In the diagram, a dashed line shows the substrate before thinning (thickness T1) to be monolithized, and a solid line shows the substrate after thinning (thickness T2) to be monolithized. Through step S24, the monolithized substrate is thinned from thickness T1 to thickness T2.

[0209] After S24, openings are made in the substrate 101, base layer 121, gate insulating layer 125, and insulating layer 128 of the thinned substrate from the second surface 101B side to form back side openings 191A~191D. Figure 14 Step 25 (S25). For example, as Figure 10 or Figure 20 As shown, a back-side opening 191A is formed on the substrate 101, base layer 121, gate insulating layer 125, and insulating layer 128, exposing the first wiring 132F. For example, the opening is formed on the substrate 101, base layer 121, gate insulating layer 125, and insulating layer 128 by dry etching. Alternatively, for example, if the substrate 101 is flexible, the opening is formed on the substrate 101, base layer 121, gate insulating layer 125, and insulating layer 128 by laser processing. In this case, to suppress the rise in substrate temperature caused by laser processing, it is preferable to perform the opening time in femtoseconds by laser processing.

[0210] After S25, via 192 is formed. Figure 14 Step 26 (S26)). For example, S26 includes forming a metal film on the back side opening 191A and the second surface 101B, and grinding the formed metal film to form vias 192A to 192D (see reference). Figure 10 or Figure 21 For example, similar to S24, CMP is used to perform grinding.

[0211] After S26, conductive layer 193 is formed to create back wiring 193A~193D. Figure 14 Step 27 (S27)). For example, as Figure 21 As shown, back-side routing 193C and back-side routing 193A are formed, with back-side routing 193A (reset potential line SVRE) electrically connected to via 192A. Additionally, as... Figure 10 As shown, back-side routing 193C (reference potential line PVSS) is electrically connected to via 192C, back-side routing 193B (reference potential line SVR) is electrically connected to via 192B, and back-side routing 193D (drive potential line PVDD) is electrically connected to via 192D.

[0212] After S27, the insulating layer 190 is formed such that it covers the second surface 101B on which the conductive layer 193 is not disposed and the conductive layer 193. Figure 14 Step 28 (S28), refer to Figure 22 Additionally, after S28, an opening 194 is formed in the organic insulating film on the back side. Figure 14 Step 29 (S29), refer to Figure 22 An opening 194 in the back-side organic insulating film penetrates the insulating layer 190 and is disposed on the insulating layer 190, exposing the conductive layer 193. Furthermore, after S29, a back-side electrode (pad 195) is formed on the exposed conductive layer 193 and the insulating layer 190. Figure 14 Step 30 (S30), refer to Figure 22 ).

[0213] Furthermore, such as Figure 9 as well as Figure 11 As shown, an opening is made in the insulating layer 141 (organic insulating layer) on the first surface 101A side. Figure 15 Step 31 (S31)). In the opening of S31, a contact hole opening portion 147A for the cathode electrode is made. The insulating layer 141 above the second wiring 140C is removed from the contact hole opening portion 147A for the cathode electrode, exposing the second wiring 140C. The contact hole opening portion 147A for the cathode electrode is sometimes referred to as an organic insulating layer opening portion.

[0214] Cathode electrode 143 (reference) Figure 11 It is disposed on the exposed second wiring 140C, on the contact hole opening 147A for the cathode electrode, and on the insulating layer 141. Figure 15 Step 32 (S32)). Additionally, functional layer 148 (see...) Figure 11 The common electrode 149 is disposed on the cathode electrode 143. Figure 9 as well as Figure 11 ) is set above functional layer 148 ( Figure 15 Step 33 (S33). It should be noted that, for example, the cathode electrode 143 and the functional layer 148 are provided for each pixel, and the common electrode 149 is provided in a manner that overlaps with the display area 22.

[0215] Following S33, a sealing film 165 is disposed on the common electrode 149, and a cover film 158 is disposed on the sealing film 165 (see reference). Figure 11 , Figure 15 Step 34 (S34). That is, the sealing film 165 and the covering film 158 are sequentially disposed on the common electrode 149 (see reference). Figure 11 ).

[0216] After S34, the multiple disconnected display devices 10 are each formed (substrate cutting) ( Figure 15Step 35 (S35). Additionally, after S35, for example, various IC chips, including IC chip 110, are electrically connected to multiple pads 195 or connected via wiring 341, and FPC 200 is connected to terminal section 150 (…). Figure 15 Step 36 (S36). Following S36, for example, a substrate fixing film (not shown) is adhered to the back side (second side 101B side). The substrate fixing film can be adhered to the insulating layer 190, the pads 195, or the IC chip electrically connected to the pads 195. For example, the substrate fixing film can protect the thin-film substrate 101 and improve the strength of the display device 10 including the thin-film substrate 101.

[0217] As described above, the manufacturing of the display device 10 (pixels 180) is complete. For example, steps S27 to S30 are not necessarily processes requiring miniaturization; therefore, steps S27 to S30 may include the use of an exposure machine with low resolution and high productivity. Furthermore, pre-processing or post-processing, such as substrate cleaning, may be performed before or after each step. Additionally, after each step, an inspection process may be performed to check whether each step was performed correctly.

[0218] For example, if the current supply from the drive potential line PVDD to the pixel 180 (pixel circuit 181) is insufficient, the potential supplied to the second electrode 626 of the second transistor T2 may decrease. The second transistor T2 is required to operate in the saturation region, but when the potential supplied to the second electrode 626 decreases, the second transistor T2 may operate in the linear region. As a result, insufficient current Ion corresponding to brightness may not flow through the second transistor T2, and the image displayed by the display device 10 may become darker. Furthermore, if the reset potential VRES and reference potential VREF supplied from the reset potential line SVRE and the reference potential line SVR are unstable, it is difficult to accurately maintain the data potential of the data signal VDATA and the threshold voltage VTH at the capacitor elements CD and CV. As a result, the display quality of the display device 10 may be degraded.

[0219] On the other hand, the second surface 101B of the display device 10 includes an area where wiring can be formed in a region larger than that of the first surface 101A. Therefore, the manufacturing method of the display device 10 includes forming a reference potential line PVSS, a drive potential line PVDD, a reset potential line SVRE, and a reference potential line SVR along the second direction D2 on the second surface 101B, making the line width of each of the reference potential line PVSS, drive potential line PVDD, reset potential line SVRE, and reference potential line SVR formed on the second surface 101B thicker. Furthermore, the first surface 101A of the display device 10 includes the reference potential line PVSS, drive potential line PVDD, reset potential line SVRE, and reference potential line SVR formed along the first direction D1. That is, the display device 10 has a structure in which the reference potential line PVSS, drive potential line PVDD, reset potential line SVRE, and reference potential line SVR are arranged in both the row and column directions by thickening the wiring width of each. Therefore, the display device 10 can reduce the resistance values ​​of the reference potential line PVSS, the drive potential line PVDD, the reset potential line SVRE, and the reference potential line SVR, thus enabling a stable and sufficient current to be supplied to the pixel 180. As a result, the display device 10 has a structure that can suppress the degradation of the display quality of the display device.

[0220] Additionally, for example, a decoupling capacitor is formed by bringing the distance between the reference potential line PVSS and the drive potential line PVDD formed on the second surface 101B side closer together. As a result, the display device 10 is able to suppress power supply noise and supply sufficient current to the pixel 180 more stably.

[0221] Furthermore, for example, in recent years, large display devices have been formed by arranging multiple display devices in a manner where adjacent display devices do not overlap (e.g., called tiling). In this case, the seams between adjacent display devices become a problem. For example, if IC chips are tiled and disposed around the display devices surrounding the display device, gaps caused by the IC chips are created between adjacent display devices, and thus the seams between adjacent display devices are visually visible, causing a problem. On the other hand, the display device 10 has a structure in which IC chips are disposed on the back side (second surface 101B side) and IC chips 110 on the surface side (first surface 101A side) are disposed in the peripheral area 24. Thus, when a large display device is formed using multiple display devices 10, the seams between adjacent display devices 10 can be minimized. As a result, by using multiple display devices 10, gaps caused by IC chips are not generated, and the seams between adjacent display devices 10 can be minimized, forming a large display device that covers multiple display devices 10.

[0222] Additionally, for example, if the substrate 101 is flexible, the display device 10 can be bent. For example, the display device 10 can be bent, and multiple display devices 10 can be connected to form a spherical display device.

[0223] [1-8. Variations]

[0224] Reference Figure 23 This illustrates a modified example of the display device 10. Figure 23 This is a schematic diagram showing an example of the drive potential line PVDD and the reference potential line PVSS of the display device 10.

[0225] like Figure 23 As shown, for example, the display device 10 includes a structure in which pixels 180 emitting red light, pixels 180 emitting blue light, and pixels 180 emitting green light are respectively formed along a first direction D1.

[0226] Pixel 180 emitting red light (R) and pixel 180 emitting green light (G) are electrically connected to the first wiring 132L (reference potential line PVSS) of line width W1 and the first wiring 132M (drive potential line PVDD) of line width W1.

[0227] Pixel 180, which emits blue light (B), is electrically connected to the first wiring 132L (reference potential line PVSS) of line width W2 and the first wiring 132M (drive potential line PVDD) of line width W2.

[0228] The line width W2 is thicker than the line width W1. As a result, the pixel 180 that emits blue light (B) is electrically connected to the reference potential line PVSS and the drive potential line PVDD, which have lower resistance, compared to the pixel 180 that emits red light (R) and the pixel 180 that emits green light (G).

[0229] For example, the luminous efficiency of pixel 180 emitting blue light (B) is lower than that of pixel 180 emitting red light (R) and pixel 180 emitting green light (G). By making the linewidth of the reference potential line PVSS and drive potential line PVDD electrically connected to pixel 180 emitting blue light (B) thicker than that of pixel 180 emitting red light (R) and pixel 180 emitting green light (G), the deviation in luminous efficiency corresponding to the color displayed by pixel 180 can be made more uniform. It should be noted that the pixels for which the linewidth of the reference potential line PVSS and drive potential line PVDD is thickened are not limited to pixel 180 emitting blue light (B). For example, when the luminous efficiency of a pixel 180 emitting red light (R) is lower than that of a pixel 180 emitting blue light (B) and a pixel 180 emitting green light (G), by making the linewidth of the reference potential line PVSS and the drive potential line PVDD electrically connected to the pixel 180 emitting red light (R) thicker than the linewidth of the reference potential line PVSS and the drive potential line PVDD electrically connected to the pixel 180 emitting blue light (B) and the pixel 180 emitting green light (G), the deviation in luminous efficiency corresponding to the color displayed by the pixel 180 can be made more uniform. In other words, the display device 10, which includes multiple pixels 180 displaying different colors, can make the deviation in luminous efficiency corresponding to the color displayed by the pixel 180 more uniform by changing the linewidth of the reference potential line PVSS and the drive potential line PVDD according to the luminous efficiency of the pixel 180.

[0230] [2. Second Implementation]

[0231] Reference Figure 4 , Figures 24-30 The outline of the display device 20 according to the second embodiment is explained. Figure 24 This is a schematic diagram showing the structure of the display device 20. Figure 25 This is a schematic diagram showing the input signal for pixel 180A (pixel circuit 181A) according to the second embodiment. Figure 26 This is a circuit diagram showing the structure of pixel circuit 181A. Figures 27-30 This is a timing diagram of display device 20. Adjustments can be made as needed. Figures 1-23 Explanation of the same or similar structure, sometimes omitting the similarity. Figures 1-23 Descriptions of the same or similar structures.

[0232] The display device 20 includes a pixel 180A and a pixel circuit 181A. The structure of the pixel 180A and the pixel circuit 181A differs from the structure of the pixel 180 and the pixel circuit 181 of the display device 10 according to the first embodiment. Specifically, the display device 20 includes the structures shown in (1) to (5) below. Mainly, the structures shown in (1) to (5) and the structures associated with the structures shown in (1) to (5) differ from the structure of the display device 10 according to the first embodiment.

[0233] (1) The structure and function of the display device 10 according to the first embodiment having a pixel 180 (pixel circuit 181) replaced by a pixel 180A (pixel circuit 181A), and the structure and function associated with the pixel 180A (pixel circuit 181A) are different from the structure and function associated with the pixel 180 (pixel circuit 181).

[0234] (2) The electrical connection between the control circuit 120 and the pixel 180A (pixel circuit 181A) is different from the electrical connection between the control circuit 120 and the pixel 180 (pixel circuit 181).

[0235] (3) The display device 20 does not include the scan signal SC6(n) and the scan signal line 335 to which the scan signal SC6(n) is supplied. The timing of the falling and rising of the second scan signal SC2(n) and the timing of the falling and rising of the third scan signal SC3(n) are different from those in the first embodiment.

[0236] (4) Excluding the fourth transistor T4, the initialization potential VINI, and the initialization potential line SVI supplied with the initialization potential VINI.

[0237] (5) Includes constant potential VSH and constant potential line SVS supplied with constant potential VSH.

[0238] The structures in display device 20 other than those shown in (1) to (5) and the structures in display device 20 other than those associated with the structures shown in (1) to (5) are the same structures as those in display device 10 according to the first embodiment. When describing the structure and function of display device 20, the same structures and functions as those in display device 10 will be described as needed, and sometimes omitted.

[0239] [2-1. Structure of pixel 180A]

[0240] Reference Figures 24-26 This section provides an overview of pixel 180A and pixel circuit 181A.

[0241] As explained in (5) above, the display device 20 includes a constant potential VSH and a constant potential line SVS to which the constant potential VSH is supplied. The pixel circuit 181A is electrically connected to the same scan signal lines 330 to 334, constant potential line SVS, drive potential line PVDD, reference potential line PVSS, reset potential line SVRE, and reference potential line SVR as the pixel circuit 181. On the other hand, as explained in (1) to (5) above, the display device 20 does not include the scan signal SC6(n) and the scan signal line 335 to which the scan signal SC6(n) is supplied, or the initialization potential VINI and the initialization potential line SVI to which the initialization potential VINI is supplied. Similar to the display device 10, the scan signal lines 330 to 334 in the display device 20 extend from the control circuit 120 in the second direction D2 and are connected to a plurality of pixels 180 arranged in the second direction D2.

[0242] For example, the constant potential line SVS is electrically connected to a different connection wiring 342 than the reset potential line SVRE, the reference potential line SVR, the drive potential line PVDD, and the reference potential line PVSS. Alternatively, the constant potential line SVS may also be a different connection wiring 342 than the reset potential line SVRE, the reference potential line SVR, the drive potential line PVDD, and the reference potential line PVSS.

[0243] For example, similar to the reset potential VRES, reference potential VREF, drive potential VDDEL, and reference potential VSSEL, the constant potential VSH is supplied from an external device to the IC chip 110 via FPC 200, terminal portion 150, and connection wiring 341, and is supplied from the IC chip 110 to multiple pixels 180A (pixel circuits 181A) via the constant potential line SVS. It should be noted that, although not illustrated, the constant potential VSH can be supplied to multiple pixels 180A (pixel circuits 181A) from an external device connected to the constant potential line SVS via FPC 200, terminal portion 150, and connection wiring 341 without going through the IC chip 110 and connection wiring 342. For example, the constant potential VSH is the same potential as the drive potential VDDEL.

[0244] The second electrode 686 of the eighth transistor T8 is electrically connected to the constant potential line VSH. The eighth transistor T8 functions to: connect the first electrode 32 (fourth node N4) of the light-emitting element OLED to the second electrode 686, supply a constant potential VSH (8V) to the first electrode 32 of the light-emitting element OLED, make the potential difference between the first electrode 32 and the second electrode 34 of the light-emitting element OLED zero, and suppress the light emission of the light-emitting element OLED during periods other than the light-emitting period. Furthermore, the eighth transistor T8 functions to: when the threshold voltage VTH is acquired and maintained, allow current to flow from the constant potential line VSH to the second electrode 626 and the first electrode 624 (i.e., the fifth node N5 and the third node N3) of the second transistor T2, charging the fifth node N5 and the third node N3. The structure of the eighth transistor T8 in the pixel circuit 181A, except for the structure described above, is the same as the structure of the eighth transistor T8 in the pixel circuit 181.

[0245] The first electrode 42 of the capacitor element CV is electrically connected to the third node N3, the first electrode 624 of the second transistor T2, and the second electrode 676 of the seventh transistor T7.

[0246] The structure and function of pixel circuit 181A, other than those described in “2-1. Structure of pixel 180A”, are the same as those of pixel circuit 181.

[0247] [2-2. Driving method of pixel circuit 181A]

[0248] Reference Figures 27-30 This describes the driving method of the display device 20. As needed, [the method will be adjusted accordingly]. Figures 1-26 Explain the same or similar structures. The horizontal axis of the sequence diagram represents time.

[0249] The driving method of the display device 20 includes and Figure 4 The same period applies to the driving method of the display device 10 according to the first embodiment shown.

[0250] During a horizontal period (horizontal period HRP) in the driving method of the display device 20, pixel 180A (pixel circuit 181A) is input with a first scan signal SC1(n), a second scan signal SC2(n), a third scan signal SC3(n), a fourth scan signal SC4(n), a fifth scan signal SC5(n), an image data signal SL(m) including a data signal VDATA, a constant potential VSH, a reset potential VRES, and a reference potential VREF. For example, pixel 180A (pixel circuit 181A) is selected based on the timing of the first scan signal SC1(n), the second scan signal SC2(n), the third scan signal SC3(n), the fourth scan signal SC4(n), and the fifth scan signal SC5(n). The image data signal SL(m) is input to the selected pixel 180A (pixel circuit 181A) according to the timing of each signal. The same operation is performed on all pixels 180A (pixel circuit 181A), and based on the image data signal SL(m) input to all pixels 180A (pixel circuit 181A), an image equivalent to the current frame of 1 frame is displayed in the display area 22 of the display device 10.

[0251] For example, Table 2 shows the direction Figures 27-30 The timing diagram shows the signals of each frame and the potential supplied by each node.

[0252]

[0253] For example, as shown in Table 2, when the potential VSIGH is 5V, the pixel 180 supplied with potential VSIGH emits light and displays white. Conversely, when the potential VSIGL is 1V, the pixel 180 supplied with potential VSIGL does not emit light and displays black. The reference potential VREF is 3.2V, the potential VH (HI) is 10V, and the potential VL (LO) is -2V. The constant potential VSH is 8V, the same as the driving potential VDDEL. The settings for other potentials are the same as those shown in Table 1 described in "1-5. Driving Method of Display Device 10". It should be noted that, similar to the potentials in display device 10, the potentials in display device 20 shown in Table 2 are examples, and the potentials involved in display device 20 are not limited to those shown in Table 2. The potentials involved in display device 20 can be appropriately selected according to the application and specifications of display device 20.

[0254] [2-2-1. First Example of a Driving Method for Display Device 20]

[0255] Reference Figure 27Table 2 illustrates a first example of the driving method for the display device 20. This first example of the driving method for the display device 20 is the same as the first example of the driving method for the display device 10 according to the first embodiment, including displaying images of different colors in consecutive frames. The method may be adjusted as needed. Figures 1-26 Explain the same or similar structures.

[0256] Similar to the first example of the driving method for the display device 10 according to the first embodiment, an image data signal SL(m), including a data signal VDATA, is input to each pixel 180A (pixel circuit 181A) according to each period. The data signal VDATA is analog data including a potential above VSIGL and a potential below VSIGH. For example, during period PWR, the potential supplied to the selected pixel 180A (pixel circuit 181A) is supplied to the image data signal SL(m). For example, during periods other than period PWR, the data signal VDATA is supplied to potentials other than those supplied to the selected pixel 180A (pixel circuit 181A).

[0257] The emission period PEM of K-1stFRAME is the period during which pixel 180A (pixel circuit 181A) emits light according to the potential difference Vgs of the second transistor T2. For example, pixel 180A emits white light by using three pixels: pixel 180A emitting red light, pixel 180A emitting blue light, and pixel 180A emitting green light.

[0258] For example, during the PEM of the K-1stFRAME, the image data signal SL(m) (data signal VDATA) is supplied with the potential of the data signal VDATA supplied to the selected pixel 180A (pixel circuit 181A). The first scan signal SC1(n), the third scan signal SC3(n), and the fourth scan signal SC4(n) are supplied with LO, and the second scan signal SC2(n) and the fifth scan signal SC5(n) are supplied with HI. The first transistor T1, the third transistor T3, the sixth transistor T6, and the eighth transistor T8 are in the off state, and the fifth transistor T5 and the seventh transistor T7 are in the on state. In addition, for example, at this time, the potential held by the first node N1 is potential Vna (2.2V), the potential held by the third node N3 is 0V, the potential held by the second node N2 is potential Vnb (e.g., 4V), and the potential difference Vgs is 4V. Therefore, the second transistor T2 is turned on, enabling the current Ion, based on the potential difference Vgs and Vds corresponding to the potential VSIGH input in the HRP during the K-1stFRAME horizontal period, to flow from the driving potential line PVDD to the light-emitting element OLED and the reference potential line PVSS. As a result, the light-emitting element OLED emits light. For example, pixel 180A (pixel circuit 181A) emits red light, and white light is emitted by using three pixels: pixel 180A emitting red light, pixel 180A emitting blue light, and pixel 180A emitting green light. It should be noted that the potential held by the first node N1 becomes potential Vna (2.2V) through the capacitive coupling of the capacitor element CV and the capacitor element CD.

[0259] During the period between the light emission period PEM of K-1stFRAME and the period PIN of KthFRAME following the light emission period PEM of K-1stFRAME, the image data signal SL(m) (data signal VDATA) is supplied with the potential of the data signal VDATA supplied to the selected pixel 180A (pixel circuit 181A). First, the fifth scan signal SC5(n) changes from being supplied HI to being supplied LO. When it becomes supplied LO to the fifth scan signal SC5(n), the third scan signal SC3(n) changes from being supplied LO to being supplied HI.

[0260] As a result, during the period between the PEM of K-1stFRAME and the PIN of KthFRAME, the fifth transistor T5 changes from the ON state to the OFF state. After the fifth transistor T5 becomes OFF, the sixth transistor T6 and the eighth transistor T8 change from the OFF state to the ON state. The first transistor T1 and the third transistor remain OFF, while the second transistor T2 and the seventh transistor T7 remain ON. Consequently, the fifth node N5 and the third node N3 are connected, and the third node N3 is connected to the reference potential line PVSS, supplying 0V (reference potential VSSEL) to the third node N3. Since 0V has been supplied to the third node N3, the potential supplied to the third node N3 continues to remain at 0V. Furthermore, the potential difference between the first electrode 32 and the second electrode 34 of the OLED becomes zero, thus the current Ion no longer flows from the driving potential line PVDD into the OLED, thereby stopping the OLED's light emission. Additionally, the first node N1 is connected to the reference potential line SVR, and the potential supplied to the first node N1 rises from potential Vna (2.2V) towards potential Vne (reference potential VREF, 3.2V) to become potential Vne. Since the first transistor T1 and the third transistor remain off, the second node N2 is in a floating state. The potential supplied to the first node N1 rises by 1V from potential Vna to potential Vne. Therefore, through the capacitive coupling between the first node N1 and the second node N2 based on the capacitor element CD, the potential supplied to the second node N2 rises by 1V from potential Vna (4V) to become potential VM (5V).

[0261] As described above, during the period between the light emission period PEM of K-1stFRAME and the period PIN of KthFRAME, the first node N1 is supplied with a potential Vne (reference potential VREF, 3.2V), the second node N2 is supplied with a potential VM (5V), and the potential supplied to the third node N3 is maintained at 0V.

[0262] During the period between the PEM of K-1stFRAME and the period PIN of KthFRAME, the image data signal SL(m) (data signal VDATA) is supplied with the potential of the data signal VDATA supplied to the selected pixel 180A (pixel circuit 181A). The second scan signal SC2(n) changes from being supplied HI to being supplied LO. When it becomes supplied LO to the second scan signal SC2(n), the first scan signal SC1(n) changes from being supplied LO to being supplied HI. The fourth scan signal SC4(n) and the fifth scan signal SC5(n) remain in the state of being supplied LO.

[0263] As a result, since the sixth transistor T6 remains on, the potential supplied to the first node N1 is maintained at potential Vne (reference potential VREF, 3.2V). Additionally, the potential supplied to the third node N3 remains at 0V (reference potential VSSEL). The seventh transistor T7 changes from on to off, and after the seventh transistor T7 becomes off, the third transistor T3 changes from off to on. If the third transistor T3 becomes on, the second node N2 is connected to the reset potential line SVRE, and the potential supplied to the second node N2 gradually decreases from potential VM towards the reset potential (potential Vnf, 2V), becoming potential Vnf. It should be noted that the eighth transistor T8 remains on, and the potential difference between the first electrode 32 and the second electrode 34 of the light-emitting element OLED is zero; therefore, the light-emitting element OLED does not emit light. Furthermore, since the fifth transistor T5 remains off, the current Ion does not flow from the constant potential VSH to the light-emitting element OLED and the reference potential line PVSS.

[0264] As described above, during the period PIN, the first node N1 is initialized by the reference potential VREF, the second node N2 is initialized by the reset potential VRES, and the third node N3 is initialized by the reference potential VSSEL.

[0265] In the period PVH following the period PIN, the image data signal SL(m) (data signal VDATA) is supplied with the potential of the data signal VDATA supplied to the selected pixel 180A (pixel circuit 181A), changing from the state of supplying LO to the fifth scan signal SC5(n) to the state of supplying HI, and the fifth transistor T5 changes from the off state to the on state. Other scan signals and other transistors are in the same state as the period PIN.

[0266] As a result, during the PVH period, the first node N1 maintains a potential Vne, and the second node N2 maintains a potential Vnf. Furthermore, at the beginning of the PVH period, the potential difference Vgs is 2V, and the second transistor T2 is in the ON state. Since the eighth transistor T8, the fifth transistor T5, and the second transistor T2 are in the ON state, the fourth node N4, the fifth node N5, and the third node N3 are turned on, and the current Ion flows from the constant potential line SVS to the fourth node N4, the fifth node N5, and the third node N3. Therefore, since LO has been supplied to the second scan signal SC2(n) and the seventh transistor T7 is in the OFF state, the potential supplied to the third node N3 has been released, gradually increasing from 0V (the third node N3 is charged). When the potential difference Vgs (the potential difference between the potential supplied to the second node N2 and the potential supplied to the third node N3) reaches the threshold voltage VTH, the second transistor T2 becomes OFF. At this time, the first node N1 maintains a potential Vne (3.2V), and the second node N2 maintains a potential Vnf (2V). Therefore, for example, when the threshold voltage VTH is 1V (design value), the potential supplied to the third node N3 becomes 1V. Furthermore, at this time, based on the potential Vnf (reset potential VRST) supplied to the second node N2, the potential difference between Vnf supplied to the second node N2 (the second electrode 54 of the capacitor element CD) and the potential Vnc supplied to the third node N3 (the first electrode 42 of the capacitor element CV) becomes the threshold voltage VTH (the potential of the third node N3 = VRES - VTH). In reality, the threshold voltage VTH may deviate during manufacturing; for example, when the threshold voltage VTH is 1.1V, the potential supplied to the third node N3 becomes 0.9V. Since the driving method of the display device 10 includes acquiring a threshold voltage VTH through operation during the PVH and performing correction using the acquired threshold voltage VTH, the driving method of the display device 10 can achieve correction of the threshold voltage VTH through operation during the PVH. Since the driving method of the display device 10 includes acquiring a threshold voltage VTH through operation during the PVH and performing correction using the acquired threshold voltage VTH, the driving method of the display device 20 can achieve correction of the threshold voltage VTH through operation during the PVH.

[0267] As described above, during the PVH period, the threshold voltage VTH of the second transistor T2 is obtained by changing the potential difference Vgs of the second transistor T2 to the same operation as the threshold voltage VTH, and a charge equivalent to the threshold voltage VTH is maintained in the capacitor element CV.

[0268] During the period between period PVH and period PWR following period PVH, the image data signal SL(m) (data signal VDATA) is supplied with the potential of the data signal VDATA supplied to the selected pixel 180A (pixel circuit 181A). First, the fifth scan signal SC5(n) changes from being supplied HI to being supplied LO. When it becomes supplied LO to the fifth scan signal SC5(n), the first scan signal SC1(n) changes from being supplied HI to being supplied LO. The third scan signal SC3(n) is in the supplied HI state, and the second scan signal SC2(n) and the fourth scan signal SC4(n) are in the supplied LO state. The fifth transistor T5 and the third transistor T3 change from the on state to the off state. The other transistors are in the same state as during period PVH. The potential sustaining potential Vne is supplied to the first node N1, the potential sustaining potential Vnf (2V) is supplied to the second node N2, the potential sustaining potential Vnc (1V) is supplied to the third node N3, and the potential difference Vgs is 1V. It is important to note that with the eighth transistor T8 remaining on, the potential difference between the first electrode 32 and the second electrode 34 of the OLED is zero, therefore the OLED does not emit light. The fifth transistor T5 is off, and the current Ion does not flow from the constant potential VSH to the OLED and the reference potential line PVSS.

[0269] During the period PWR following the period between PVH and PWR, the image data signal SL(m) (data signal VDATA) is supplied with a potential VSIGL (1V). The fourth scan signal SC4(n) changes from being supplied with LO to being supplied with HI, and the first transistor T1 changes from being off to being on. Other control signals and transistors are in the same state as during period PVH. The potential supplied to the first node N1 is maintained at potential Vne, and the potential supplied to the third node N3 is maintained at potential Vnc. By the first transistor T1 changing from being off to being on, the second node N2 is connected to the image data signal line 321, and the potential supplied to the second node N2 gradually decreases from potential Vnf toward potential VSIGL (potential Vnc, 1V) to potential Vnc. At this time, capacitor CD maintains the potential difference (based on the potential supplied to the first node N1, -2.2V) by maintaining a charge equivalent to the potential difference between Vne (reference potential VREF, 3.2V) supplied to the first node N1 and the potential Vnc (1V) supplied to the second node N2. Additionally, capacitor CV maintains the potential difference (based on the potential supplied to the third node N3, 2.2V) by maintaining a charge equivalent to the potential difference between Vne (reference potential VREF, 3.2V) supplied to the first node N1 and the potential Vnc (1V) supplied to the third node N3. The sum of the potential differences maintained by capacitor CD and capacitor CV (-2.2V + 2.2V) is 0V, that is, the potential difference Vgs is 0V. Therefore, the second transistor T2 is in the off state. It should be noted that, similar to the period between PVH and PWR, the OLED light-emitting element does not emit light during the PWR period.

[0270] As described above, during the PWR period, a data signal VDATA is written to pixel 180A (pixel circuit 181A). Additionally, the capacitor element CD maintains the data potential of the data signal VDATA.

[0271] During the period following PWR, the fourth scan signal SC4(n) changes from being supplied with HI to being supplied with LO. When it becomes the state of supplying LO to the fourth scan signal SC4(n), the third scan signal SC3(n) changes from being supplied with HI to being supplied with LO. When it becomes the state of supplying LO to the third scan signal SC3(n), the second scan signal SC2(n) changes from being supplied with LO to being supplied with HI. The first transistor T1, the sixth transistor T6, and the eighth transistor T8 change from the ON state to the OFF state, and the seventh transistor T7 changes from the OFF state to the ON state. Other scan signals and other transistors are in the same state as during period PWR. By turning on the seventh transistor T7, the third node N3 is connected to the reference potential line PVSS (0V), and the potential supplied to the third node N3 gradually decreases from the potential Vnc (VSIGL, 1V) towards 0V to 0V. The sixth transistor T6 is in the OFF state, and the first node N1 and the second node N2 are in the floating state. Therefore, by supplying the potential to the third node N3 from potential Vnc (1V) to 0V, and through the capacitive coupling between the third node N3 and the first node N1, the potential supplied to the first node N1 from potential Vne (3.2V) to potential Vna (2.2V). Additionally, through the capacitive coupling between the first node N1 and the second node N2, the potential supplied to the second node N2 from potential Vnc (1V) to 0V. It should be noted that although the eighth transistor T8 is off, because the fifth transistor T5 is off, the current Ion does not flow from the driving potential line PVDD and the constant potential VSH to the light-emitting element OLED and the reference potential line PVSS, and the light-emitting element OLED does not emit light.

[0272] As a result, during the period following PWR, the potential supplied to the first node N1 via capacitors CV and CD becomes potential Vna (2.2V), while the potentials supplied to the second node N2 and the third node N3 become 0V. At this time, the potential difference Vgs is 0V (-2.2V + 2.2V = 0V), and the second transistor T2 is in the off state.

[0273] During the PWR period of KthFRAME, following the PWR period, the image data signal SL(m) (data signal VDATA) is supplied with the potential of the data signal VDATA supplied to the selected pixel 180A (pixel circuit 181A). Additionally, the fifth scan signal SC5(n) changes from being supplied with LO to being supplied with HI. Consequently, the fifth transistor T5 changes from being off to being on. Other scan signals and other transistors remain in the same state as during the period following the PWR period of KthFRAME.

[0274] As a result, the fifth transistor T5 is turned on, and the first electrode 32 of the light-emitting element OLED is connected to the second electrode 626 (fifth node N5) of the second transistor T2. The seventh transistor T7 is turned on, and the third node N3 is electrically connected to the reference potential line PVSS, so the potential supplied to the third node N3 is maintained at 0V. In addition, the potential supplied to the second node N2 is maintained at 0V through the capacitive coupling of the capacitor element CD and the capacitor element CV. The first node N1 is maintained at 2.2V through the capacitive coupling of the capacitor element CD and the capacitor element CV. The potential difference Vgs is the sum of the potential difference maintained by the capacitor element CD and the potential difference maintained by the capacitor element CV (the potential of the data signal VDATA (potential VSIGL, 1V) - reference potential VREF (3.2V) + reference potential VREF (3.2V) - (reset potential VRES (2V) - threshold voltage VTH (1V) = 0V). The data signal VDATA includes the pixel 180A (pixel circuit 181A) with potential VSIGL. Since the potential difference Vgs is 0V, the second transistor T7 is turned on. 2 is in the off state, therefore no drain current Ion flows. Consequently, the OLED light-emitting element does not emit light. As a result, the red-emitting pixel 180A (pixel circuit 181A), the blue-emitting pixel 180A (pixel circuit 181A), and the green-emitting pixel 180A (pixel circuit 181A) do not emit light, and thus pixel 180A is formed as black by using these three pixels.

[0275] Similar to display device 10, display device 20, which includes the structure described above, can acquire threshold voltage at high speed and can minimize potential loss caused by the reduction of write potential during light emission.

[0276] Furthermore, the display device 20 includes the structures described in (1) to (5) above. During the periodic pin, the fourth transistor T4 is not used to supply the initialization potential VINI to the third node N3, but the seventh transistor T7 is used to supply the reference potential VSSEL to the third node N3, thereby enabling the initialization of the third node N3. As a result, the display device 20 has a structure that eliminates the fourth transistor T4, thus reducing parasitic capacitance caused by the switching of the fourth transistor T4, and can acquire the threshold voltage more quickly. In addition, since the display device 20 does not include the fourth transistor T4, nor the initialization potential VINI, nor the scan signal line 335 used to supply the initialization potential VINI, the number of components, power supplies, and signal lines can be reduced compared to the display device 10.

[0277] [2-2-2. A second example of a driving method for the display device 20]

[0278] Reference Figure 28 This describes a second example of the driving method for the display device 20. The driving method shown in this second example of the display device 20 is the same as the second example of the driving method for the display device 10 according to the first embodiment, including displaying an image of the same color (white) in consecutive frames. The method can be adjusted as needed. Figures 1-27 Explain the same or similar structures.

[0279] The potentials of each node during the light emission period PEM of K-1thFRAME to the period PVH of K-1thFRAME, and the period between the period PVH of K-1thFRAME and the period PER of K-1thFRAME, are the same as those described in "2-2-1. First Example of Driving Method for Display Device 20". Furthermore, the structure of each scan signal in each period and the operation of each transistor are the same as those described in "2-2-1. First Example of Driving Method for Display Device 20". Therefore, the same structure as described in "2-2-1. First Example of Driving Method for Display Device 20" will be described as needed. It should be noted that the image data signal SL(m) is supplied with a data signal VDATA including VSIGL (0V) corresponding to white during the period PWR of K-1thFRAME, and is supplied with the same data signal VDATA as the structure described in "2-2-1. First Example of Driving Method for Display Device 20" during periods other than the period PWR of K-1thFRAME.

[0280] During the light emission period PEM of the K-1stFRAME, similar to the structure described in "2-2-1. First Example of Driving Method of Display Device 20", pixel 180A emits white light by using three pixels: pixel 180A that emits red light, pixel 180A that emits blue light, and pixel 180A that emits green light.

[0281] During the period between the light emission period PEM of K-1stFRAME and the period PIN of KthFRAME, similar to the structure described in "2-2-1. First Example of Driving Method of Display Device 20", the first node N1 is supplied with a potential Vne (reference potential VREF, 3.2V), the second node N2 is supplied with a potential VM (5V), and the potential supplied to the third node N3 is maintained at 0V.

[0282] In the period PIN of KthFRAME, similar to the structure described in "2-2-1. First Example of Driving Method of Display Device 20", the first node N1 is initialized by the reference potential VREF, the second node N2 is initialized by the reset potential VRES, and the third node N3 is initialized by the reference potential VSSEL.

[0283] In the period PVH following the period PIN, similar to the structure described in "2-2-1. First Example of Driving Method of Display Device 20", the threshold voltage VTH of the second transistor T2 is obtained by changing the potential difference Vgs of the second transistor T2 to the same operation as the threshold voltage VTH, and a charge equivalent to the threshold voltage VTH is maintained in the capacitor element CV.

[0284] During the period between the period PVH and the period PWR following the period PVH, similar to the structure described in "2-2-1. First Example of Driving Method of Display Device 20", the potential sustaining potential Vne is supplied to the first node N1, the potential sustaining potential Vnf (2V) is supplied to the second node N2, the potential sustaining potential Vnc (1V) is supplied to the third node N3, and the potential difference Vgs is 1V.

[0285] During the period PWR following the period PVH and the period PWR, the image data signal SL(m) (data signal VDATA) is supplied with a potential VSIGH (potential VM, 5V). The potential supplied to the first node N1 is maintained by potential Vne, and the potential supplied to the third node N3 is maintained by potential Vnc. The potential supplied to the second node N2 gradually rises from potential Vnf (2V) towards potential VM, becoming potential VM (potential VSIGH, 5V). At this time, the capacitor element CD maintains the potential difference (based on the potential supplied to the first node N1, 1.8V) by maintaining a charge equivalent to the potential difference between Vne supplied to the first node N1 (reference potential VREF, 3.2V) and the potential VM (5V) supplied to the second node N2. Furthermore, capacitor CV maintains the potential difference (based on the potential supplied to the third node N3, 2.2V) by maintaining a charge equivalent to the potential difference between Vne (reference potential VREF, 3.2V) supplied to the first node N1 and Vnc (1V) supplied to the third node N3. The sum of the potential difference maintained by capacitor CD and capacitor CV (1.8V + 3.2V) is 4V, and the potential difference Vgs is 4V. Therefore, the second transistor T2 is in the ON state. For example, if the threshold voltage VTH deviates and the potential VM supplied to the third node N3 becomes 0.9V (assuming the threshold voltage VTH becomes 1.1V and the potential of the third node N3 is VRES(2V) - VTH(1.1V) = 0.9V), the potential difference Vgs becomes 4.1V (Vgs = (VDATA(Vnb, 5V) - VREF(3.2V)) + (VREF(3.2V) - 0.9V). That is, if the threshold voltage VTH is 0.1V higher than the design value, the write potential difference Vgs becomes 4.1V, which is 0.1V higher than the design value of 4V.

[0286] As described above, during the PWR period, a data signal VDATA is written to pixel 180A (pixel circuit 181A). Additionally, the capacitor element CD maintains the data potential of the data signal VDATA.

[0287] During the period following PWR, the seventh transistor T7 is turned on, thereby connecting the third node N3 to the reference potential line PVSS (0V). The potential supplied to the third node N3 gradually decreases from potential Vnc (VSIGL, 1V) towards 0V. The sixth transistor T6 is turned off, and the first node N1 and the second node N2 are in a floating state. As a result, the potential supplied to the third node N3 decreases from potential Vnc (1V) to 0V, and through the capacitive coupling of the first node N1 and the third node N3 based on the capacitor element CV, the potential supplied to the first node N1 decreases from potential Vne (3.2V) to potential Vna (2.2V). In addition, through the capacitive coupling of the second node N2 and the first node N1 based on the capacitor element CD, the potential supplied to the second node N2 decreases from potential VM (5V) to potential Vnb (4V).

[0288] During the PWR period following the KthFRAME's emission period, the potential supplied to the third node N3 is maintained at 0V. Additionally, the potential supplied to the second node N2 is maintained at potential Vnb (4V) through the capacitive coupling of capacitor elements CD and CV. The first node N1 is also maintained at potential Vna (2.2V) through the capacitive coupling of capacitor elements CD and CV. The potential difference Vgs is the sum of the potential difference maintained by capacitor CD and capacitor CV (the potential of data signal VDATA (potential VSIGH, 5V) - reference potential VREF (3.2V) + reference potential VREF (3.2V) - (reset potential VRES (2V) - threshold voltage VTH (1V) = 4V). The data signal VDATA includes pixel 180A (pixel circuit 181A) with potential VSIGH. Since the potential difference Vgs is 4V and the second transistor T2 is on, the current Ion flows from the driving potential line PVDD to the light-emitting element OLED and the reference potential line PVSS, and the light-emitting element OLED emits light. For example, pixel 180A that emits red light, pixel 180A that emits blue light, and pixel 180A that emits green light emit light respectively, and white is achieved by using the three pixels that emit red light, blue light, and green light.

[0289] The second example of the driving method for the display device 20 has the same effect as that described in "2-2-1. The first example of the driving method for the display device 20".

[0290] [2-2-3. A third example of a driving method for display device 20]

[0291] Reference Figure 29This describes a third example of the driving method for the display device 20. The driving method shown in this third example of the driving method for the display device 20 is the same as the third example of the driving method for the display device 10 according to the first embodiment, including displaying an image of the same color (black) in consecutive frames. The method can be adjusted as needed. Figures 1-28 Explain the same or similar structures.

[0292] The potentials of each node in the PEM during the KthFRAME's PVH to KthFRAME's light-emitting period are the same as those described in "2-2-1. First Example of the Driving Method for Display Device 20". Furthermore, the structures of each scan signal in each period and the operation of each transistor are the same as those described in "2-2-1. First Example of the Driving Method for Display Device 20". Therefore, the same structures as those described in "2-2-1. First Example of the Driving Method for Display Device 20" will be described as needed.

[0293] During the light emission period of the K-1stFRAME in the PEM, for example, the potential supplied to the first node N1 is potential Vna (2.2V). Meanwhile, the potentials supplied to the second node N2 and the third node N3 are 0V, and the potential difference Vgs is 0V. Therefore, the second transistor T2 is in the off state, the drain current Ion does not flow, and the OLED does not emit light.

[0294] As a result, pixel 180A (pixel circuit 181A) that emits red light, pixel 180A that emits blue light, and pixel 180A that emits green light do not emit light. Therefore, pixel 180A becomes black by using the three pixels that emit red light, blue light, and green light.

[0295] During the period between the light-emitting period PEM of K-1stFRAME and the period PIN of KthFRAME, since 0V has been supplied to the third node N3, the potential supplied to the third node N3 continues to remain at 0V. Furthermore, the current Ion no longer flows from the driving potential line PVDD to the light-emitting element OLED and the reference potential line PVSS, and the light-emitting element OLED stops emitting light. However, the first node N1 and the reference potential line SVR are turned on, and the potential supplied to the first node N1 rises from potential Vna (2.2V) towards potential Vne (reference potential VREF, 3.2V), becoming potential Vne. Since the first transistor T1 and the third transistor remain off, the second node N2 is in a floating state. The potential supplied to the first node N1 rises by 1V from potential Vna to potential Vne. Therefore, through the capacitive coupling of the first node N1 and the second node N2 based on the capacitive element CD, the potential supplied to the second node N2 rises by 1V from 0V, becoming potential Vc (1V).

[0296] As described above, during the period between the light emission period PEM of K-1stFRAME and the period PIN of KthFRAME, the first node N1 is supplied with a potential Vne (reference potential VREF, 3.2V), the second node N2 is supplied with a potential Vc (1V), and the potential supplied to the third node N3 is maintained at 0V.

[0297] During the period PIN of KthFRAME following the period PIN of KthFRAME, the potential supplied to the first node N1 is maintained at potential Vne (reference potential VREF, 3.2V). The potential supplied to the third node N3 is maintained at 0V (reference potential VSSEL). When the third transistor T3 is turned on, the second node N2 is connected to the reset potential line SVRE, and the potential supplied to the second node N2 gradually rises from potential Vnc toward the reset potential (potential Vnf, 2V) to become potential Vnf.

[0298] As described above, during the period PIN, the first node N1 is initialized by the reference potential VREF, the second node N2 is initialized by the reset potential VRES, and the third node N3 is initialized by the reference potential VSSEL.

[0299] In the period PVH following the period PIN, similar to the structure described in "2-2-1. First Example of Driving Method of Display Device 20", the threshold voltage VTH of the second transistor T2 is obtained by changing the potential difference Vgs of the second transistor T2 to the same operation as the threshold voltage VTH, and a charge equivalent to the threshold voltage VTH is maintained in the capacitor element CV.

[0300] During the period between the period PVH and the period PWR following the period PVH, similar to the structure described in "2-2-1. First Example of Driving Method of Display Device 20", the potential sustaining potential Vne is supplied to the first node N1, the potential sustaining potential Vnf (2V) is supplied to the second node N2, the potential sustaining potential Vnc (1V) is supplied to the third node N3, and the potential difference Vgs is 1V.

[0301] During the period PWR following the period PVH and the period PWR, similar to the structure described in "2-2-1. First Example of Driving Method for Display Device 20", a data signal VDATA is written to pixel 180A (pixel circuit 181A) during the period PWR. Additionally, the capacitor element CD maintains the data potential of the data signal VDATA.

[0302] During the period following PWR, similar to the structure described in "2-2-1. First Example of Driving Method for Display Device 20", the potential supplied to the first node N1 via capacitor element CV and capacitor element CD is voltage Vna (2.2V), and the potentials supplied to the second node N2 and the third node N3 are 0V. At this time, the potential difference Vgs is 0V (-2.2V+2.2V=0V), and the second transistor T2 is in the off state.

[0303] During the light-emitting period PEM of the KthFRAME following the period PWR, similar to the structure described in "2-2-1. First Example of Driving Method for Display Device 20", the potential difference Vgs is 0V, the second transistor T2 is in the off state, therefore the drain current Ion does not flow, and the light-emitting element OLED does not emit light. As a result, pixel 180A becomes black by using three pixels: pixel 180A emitting red light, pixel 180A emitting blue light, and pixel 180A emitting green light.

[0304] The third example of the driving method for the display device 20 has the same effect as that described in "2-2-1. The first example of the driving method for the display device 20".

[0305] [2-2-4. Fourth example of a driving method for display device 20]

[0306] Reference Figure 30 This describes a fourth example of the driving method for the display device 20. The driving method shown in this fourth example of the driving method for the display device 20 is the same as the fourth example of the driving method for the display device 10 according to the first embodiment, including displaying images of different colors in consecutive frames. Depending on the needs, [the method can be modified / adjusted / adjusted]. Figures 1-29 Explain the same or similar structures.

[0307] The potentials of each node, the structure of each scan signal, and the operation of each transistor in the period from the light-emitting period PEM of K-1stFRAME to the period PVH of KthFRAME are the same as those described in "2-2-3. Third Example of the Driving Method of Display Device 20". Furthermore, the potentials of each node, the structure of each scan signal, and the operation of each transistor in the period from the period PVH of KthFRAME to the light-emitting period PEM of KthFRAME are the same as those described in "2-2-2. Second Example of the Driving Method of Display Device 20". Therefore, the explanation is omitted here.

[0308] The fourth example of the driving method for the display device 20 has the same effect as that described in "2-2-1. The first example of the driving method for the display device 20".

[0309] The various embodiments or parts thereof described above as embodiments of the present invention can be appropriately combined and implemented as long as they do not contradict each other.

[0310] Even if other effects are different from those brought about by the solutions described above, if they are effects that are clearly defined according to the description in this specification, or effects that can be easily predicted by those skilled in the art, they are of course understood to be effects brought about by the present invention.

Claims

1. A display device comprising: a plurality of pixels arranged in a matrix shape in a first direction and a second direction intersecting the first direction; an image data signal line to which a data potential is supplied; a reset potential line to which a reset potential is supplied; a reference potential line to which a reference potential is supplied; a reference potential line to which a reference potential is supplied; a reference potential line to which a reference potential is supplied; and a constant potential line to which a constant potential is supplied, each of the plurality of pixels includes a first transistor, a second transistor, a third transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a first capacitor element, a second capacitor element, and a light emitting element, the first transistor is controlled by a first control signal and electrically connected between the image data signal line and a second electrode of the second capacitor element, the second transistor has a gate electrode electrically connected to the second electrode of the second capacitor element and is electrically connected between a first electrode of the first capacitor element and a first electrode of the fifth transistor, the third transistor is controlled by a second control signal and electrically connected between the reset potential line and the second electrode of the second capacitor element, the fifth transistor is controlled by a third control signal and electrically connected between a first electrode of the light emitting element and a second electrode of the second transistor, the sixth transistor is controlled by a fourth control signal and electrically connected between the reference potential line and a first electrode of the second capacitor element, the seventh transistor is controlled by a fifth control signal and electrically connected between the reference potential line and a first electrode of the second transistor, the eighth transistor is controlled by the fourth control signal and electrically connected between the constant potential line and the first electrode of the fifth transistor, the first capacitor element is electrically connected between the first electrode of the second capacitor element and the first electrode of the second transistor, the second capacitor element is electrically connected between a second electrode of the first capacitor element and the gate electrode, the light emitting element is electrically connected between the constant potential line and the first electrode of the fifth transistor.

2. The display device according to claim 1, wherein the display device further includes a control circuit that outputs the first control signal to the fifth control signal, the control circuit is configured to be capable of controlling so that, after a potential difference corresponding to a threshold voltage of the second transistor is held in the first capacitor element, a potential difference corresponding to the data potential is held in the second capacitor element.

3. The display device according to claim 2, wherein the control circuit is configured to be capable of controlling: before the potential difference corresponding to the threshold voltage of the second transistor is held in the first capacitor element, the first transistor is made to be in an off state using the first control signal, the third transistor is made to be in an off state using the second control signal, the fifth transistor is made to be in an off state using the third control signal, the sixth transistor and the eighth transistor are made to be in an on state using the fourth control signal, the seventh transistor is made to be in an on state using the fifth control signal, and the reference potential is supplied to the first electrode of the second capacitor element, Before the potential difference corresponding to the threshold voltage of the second transistor is held in the first capacitor element and after the reference potential is supplied to the first electrode of the second capacitor element, the seventh transistor is made off using the fifth control signal, the third transistor is made on using the second control signal, and the reset potential is supplied to the second electrode of the second capacitor element.

4. The display device according to claim 1, wherein Each of the plurality of pixels includes a fourth transistor whose switching is controlled using a sixth control signal, and the fourth transistor is electrically connected between an initialization potential line to which an initialization potential is supplied and the first electrode of the first capacitor element.

5. The display device according to claim 4, wherein The display device further includes a control circuit which outputs the first to sixth control signals, The control circuit is configured to be capable of controlling: the potential difference corresponding to the threshold voltage of the second transistor is held in the first capacitor element and the potential difference corresponding to the data potential is held in the second capacitor element.

6. The display device according to claim 5, wherein The control circuit is configured to be capable of controlling: Before the potential difference corresponding to the threshold voltage of the second transistor is held in the first capacitor element and after the reference potential is supplied to the first electrode of the second capacitor element, the seventh transistor is made off using the fifth control signal, the third transistor is made on using the second control signal, and the reset potential is supplied to the second electrode of the second capacitor element. Before the potential difference corresponding to the threshold voltage of the second transistor is held in the first capacitor element and after the reference potential is supplied to the first electrode of the second capacitor element, the seventh transistor is made off using the fifth control signal, the third transistor is made on using the second control signal, and the reset potential is supplied to the second electrode of the second capacitor element. Before the potential difference corresponding to the threshold voltage of the second transistor is held in the first capacitor element and after the initialization potential is supplied to the first electrode of the first capacitor element, the fourth transistor is made off using the sixth control signal, the third transistor is made on using the second control signal, and the reset potential is supplied to the second electrode of the second capacitor element.

7. The display device according to claim 3 or 6, wherein The control circuit is configured to be capable of controlling: After the reset potential is supplied to the second electrode of the second capacitor element, the fifth transistor is made on using the third control signal, and the potential difference corresponding to the threshold voltage of the second transistor is held in the first capacitor element.

8. The display device according to claim 7, wherein the control circuit is configured to be capable of controlling: after a potential difference which corresponds to a threshold voltage of the second transistor is held in the first capacitor element, the third transistor is made off state using the second control signal, the first transistor is made on state using the first control signal, the data potential is supplied to the second electrode of the second capacitor element, and a potential difference which corresponds to the data potential is held in the second capacitor element.

9. The display device according to claim 4, wherein the first transistor to the eighth transistor are n-channel field effect transistors, a channel region of each of the first transistor to the eighth transistor includes an oxide semiconductor.

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