Implementing sign bits for decision feedback equalizers using reference voltage multiplexers

Abstract

The disclosure relates to implementing sign bits for decision feedback equalizers using reference voltage multiplexers. A selection device outside a feedback loop of the DFE circuit is to selectively output the reference signal based on the sign bits stored in the one or more mode registers. The reference signal includes a reference voltage signal used by an amplifier or equalizer of the DFE circuit to generate a correction signal of a distorted signal. By generating the reference signal using the selection device outside the feedback loop of the DFE circuit, a feedback loop delay time is reduced and a total operating time of the DFE circuit is reduced. Therefore, the efficiency of the DFE circuit is improved.

Description

[0001] Cross Reference to Related Applications

[0002] This application claims priority to U.S. Provisional Application No. 63 / 699,922, filed September 27, 2024, the entirety of which is incorporated herein by reference. TECHNICAL FIELD

[0003] Embodiments of the present disclosure generally relate to the field of semiconductor memory devices. More specifically, embodiments of the present disclosure relate to loop-unrolled decision feedback equalizer (DFE) architecture for semiconductor memory devices. BACKGROUND

[0004] The operating speed of memory devices, including the data rate of memory devices, continues to increase over time. As a side effect of the increasing speed of memory devices, data errors due to distortion can increase. For example, intersymbol interference between transmitted data can occur, where previously received data affects the currently received data (e.g., previously received data affects and interferes with subsequently received data). One way to correct for this interference is by using a decision feedback equalizer (DFE) circuit, which can be programmed to cancel out (i.e., undo, mitigate, or counteract) the effects of the channel on the transmitted data.

[0005] Additionally, correcting for distortion of a transmitted signal remains important. However, conventional distortion correction techniques can not sufficiently correct for distortion of the signal. Errors caused by the slow process of conventional distortion correction techniques result in additional distortion of the final data, thus reducing the reliability of the data transmitted within the memory device. One way to correct for this slow process is by using a loop-unrolled decision feedback equalizer (DFE) circuit, which means that the possible decision of a single previous data bit is processed in parallel with the corresponding latch. However, DFE circuits typically use a sign bit within the feedback loop to determine the appropriate distortion correction, which can result in an increase in the feedback loop delay time. SUMMARY

[0006] In one aspect, the present disclosure provides a device comprising: a selection device configured to select a reference value from a plurality of reference values based on a sign bit; and an input receiver circuit configured to: receive an input signal; receive the reference value from the selection device; and generate an adjusted signal for the input signal based on the reference value.

[0007] In another aspect, the present disclosure provides a method comprising: receiving an input signal; selecting a first reference value from a plurality of reference values based on a sign bit; selecting a second reference value from the plurality of reference values based on an inversion of the sign bit; and generating an adjusted signal for the input signal based on the first reference value and the second reference value.

[0008] On the other hand, this disclosure provides an input receiver circuit comprising: a first component for receiving an input signal and receiving a first reference value selected from a plurality of reference values ​​based on a sign bit; a second component for receiving the input signal and receiving a second reference value selected from the plurality of reference values ​​based on an inversion of the sign bit; and a selection means for selecting an adjustment signal for the signal from a first result generated based on the first reference value and a second result generated based on the second reference value. Attached Figure Description

[0009] A better understanding of the various aspects of this disclosure can be achieved by reading the following detailed description and referring to the figures, in which:

[0010] Figure 1 This is a simplified block diagram illustrating certain features of a memory device according to embodiments of the present disclosure;

[0011] Figure 2 Description of embodiments according to this disclosure Figure 1 A block diagram of a data transceiver for the I / O interface;

[0012] Figure 3 Description of embodiments according to this disclosure Figure 2 A block diagram of an embodiment of a data transceiver;

[0013] Figure 4 Description of embodiments according to this disclosure Figure 2 A block diagram of a second embodiment of a data transceiver;

[0014] Figure 5 A block diagram illustrating a distortion correction circuit according to an embodiment of the present disclosure;

[0015] Figure 6 This describes an embodiment of implementing a distortion correction circuit for the sign bit in a loop-expanded DFE using a reference voltage multiplexer according to an embodiment of the present disclosure;

[0016] Figure 7 This describes another embodiment of the circuitry for implementing sign bit distortion correction in a loop-expanded DFE using a reference voltage multiplexer, according to embodiments of the present disclosure; and

[0017] Figure 8 A flowchart illustrating a method for implementing a sign bit to generate a correction bit according to an embodiment of the present disclosure. Detailed Implementation

[0018] One or more specific embodiments will be described below. To provide a context for these embodiments, Figure 1 is provided. In order to provide a concise description of these embodiments, all features of an actual implementation can not be described in the specification. It should be appreciated that in the development of any such actual implementation, as in any engineering or design project, numerous implementation-specific decisions must be made to achieve the developers' specific goals, such as compliance with system-related and business-related constraints, which can vary from one implementation to another. Moreover, it should be appreciated that such a development effort might be complex and time-consuming, but would nevertheless be a routine undertaking of design, fabrication, and manufacture for those of ordinary skill having the benefit of this disclosure.

[0019] It can be valuable to perform distortion correction techniques using a decision feedback equalizer (DFE) of a memory device, such as to properly compensate for distortion of received data of the memory device. This ensures that accurate values are stored in the memory of the memory device. The DFE can use previous bit data to create a correction value to compensate for distortion caused by the previous bit data. For example, a most recent previous bit can have a greater distortion impact on a current bit than bits transmitted a number of data points before, resulting in a correction value that differs between the two bits. For these levels to be corrected, the DFE can operate to correct the distortion of the transmitted bit.

[0020] In some embodiments, the DFE can utilize a number of bits of previous data to accurately calculate a distortion correction factor. In further embodiments, when receiving and processing a number of bits, the DFE can not receive a correction voltage for a distorted bit from a most recent bit, as there can be an additional time delay in correcting the distorted bit while waiting for a correction signal from the most recent bit. A loop unrolling technique and associated hardware reduces the delay in correcting the distorted bit caused by the delay in receiving the previous bit by applying a correction to the distorted bit from an assumed value of the previous bit, such as an assumed logic high or logic low, and passing this bit to a selection circuit. Once the previous bit is known, the correct distorted bit is selected from the distorted bits based on the assumed correction. The loop unrolling technique and associated hardware can allow for receiving and processing a number of bits at nearly the same time, resulting in a very efficient system that can process the distortion of received bits much faster than can be achieved via a traditional DFE solution. However, DFE circuits typically use a sign bit to determine the appropriate distortion correction, which can result in an increased feedback loop delay time. Accordingly, it is desirable to improve DFE circuits to reduce the feedback loop delay time.

[0021] The present disclosure provides systems and methods of selectively outputting a reference signal based on a sign bit stored in one or more mode registers using a selection device outside of a feedback loop of a DFE circuit. The reference signal includes a reference voltage signal used by an amplifier or equalizer of the DFE circuit to generate a correction signal for a distorted signal. By using a selection device outside of a feedback loop of a DFE circuit to generate the reference signal, the feedback loop delay time is reduced and the overall operation time of the DFE circuit is reduced. Accordingly, the efficiency of the DFE circuit is improved.

[0022] Reference is now made to the drawings, Figure 1 is a simplified block diagram illustrating certain features of memory device 10. Specifically, Figure 1 The block diagram of FIG. 1 is a functional block diagram illustrating certain functionality of memory device 10. According to one embodiment, memory device 10 can be a double data rate type five synchronous dynamic random access memory (DDR5 SDRAM) device. Various features of DDR5 SDRAM allow for reduced power consumption, greater bandwidth, and more storage capacity compared to previous generations of DDR SDRAM.

[0023] Memory device 10 can include a number of memory banks 12. For example, memory banks 12 can be DDR5 SDRAM memory banks. Memory banks 12 can be provided on one or more chips (e.g., SDRAM chips) arranged on a dual in-line memory module (DIMM). It should be appreciated that each DIMM can include a number of SDRAM memory chips (e.g., x8 or x16 memory chips). Each SDRAM memory chip can include one or more memory banks 12. Memory device 10 represents a portion of a single memory chip (e.g., SDRAM chip) having a number of memory banks 12. For DDR5, memory banks 12 can be further arranged to form memory bank groups. For example, for an 8 gigabit (Gb) DDR5 SDRAM, a memory chip can include 16 memory banks 12 arranged into 8 memory bank groups, each memory bank group including 2 memory banks. For example, for a 16 GB DDR5 SDRAM, a memory chip can include 32 memory banks 12 arranged into 8 memory bank groups, each memory bank group including 4 memory banks. Various other configurations, organizations, and sizes of memory banks 12 on memory device 10 can be utilized depending on the application and design of the overall system.

[0024] Memory device 10 can include a command interface 14 and an input / output (I / O) interface 16 configured to exchange (e.g., receive and transmit) signals with an external device. Command interface 14 is configured to provide a number of signals (e.g., signals 15) from an external device (not shown), such as a processor or controller. The processor or controller can provide various signals 15 to memory device 10 to facilitate the transmission and reception of data written to or read from memory device 10.

[0025] It should be appreciated that command interface 14 can include a number of circuits, such as clock input circuit 18 and command address input circuit 20, for example, to ensure proper handling of signals 15. Command interface 14 can receive one or more clock signals from an external device. Generally, double data rate (DDR) memory utilizes a differential pair of system clock signals, referred to herein as true clock signal (Clk_t) and complementary clock signal (Clk_c). The positive clock edge of DDR refers to the point at which the rising true clock signal Clk_t crosses the falling complementary clock signal Clk_c, while the negative clock edge indicates the falling true clock signal Clk_t transition and the rising complementary clock signal Clk_c. Commands (e.g., read commands, write commands, etc.) are generally input on the positive edge of the clock signal and data is transmitted or received on both the positive and negative clock edges.

[0026] Clock input circuit 18 receives true clock signal (Clk_t) and complementary clock signal (Clk_c) and generates an internal clock signal CLK. Internal clock signal CLK is supplied to an internal clock generator 30, such as a delay locked loop (DLL) circuit. Internal clock generator 30 generates a phased internal clock signal LCLK based on the received internal clock signal CLK. Phased internal clock signal LCLK is supplied to, for example, I / O interface 16 and used as a timing signal for determining the output timing of read data.

[0027] Internal clock signal CLK can also be provided to various other components within memory device 10 and can be used to generate various additional internal clock signals. For example, internal clock signal CLK can be provided to a command decoder 32. Command decoder 32 can receive command signals from a command bus 34 and can decode the command signals to provide various internal commands. For example, command decoder 32 can provide command signals to internal clock generator 30 via a bus 36 to coordinate the generation of phased internal clock signal LCLK. Phased internal clock signal LCLK can be used to clock data, for example, through I / O interface 16.

[0028] Further, command decoder 32 can decode commands, such as read commands, write commands, mode register set commands, activate commands, etc., and provide access to a particular bank 12 corresponding to the command via a bus path 40. It should be appreciated that memory device 10 can include various other decoders, such as row decoders and column decoders, to facilitate access to banks 12. In one embodiment, each bank 12 includes a bank control block 22 that provides the necessary decoding (e.g., row decoders and column decoders), as well as other features (e.g., timing control and data control) to facilitate the execution of commands to and from bank 12. Banks 12 and bank control blocks 22 can be collectively referred to as memory array 23.

[0029] Memory device 10 performs operations such as read and write commands based on command / address signals received from an external device, such as a processor. In one embodiment, the command / address bus can be a 14-bit bus that accommodates command / address signals (CA<13:0>). The command / address signals to command interface 14 are clocked using clock signals (Clk_t and Clk_c). The command interface can include command address input circuitry 20 configured to receive and transmit commands to provide access to memory banks 12, such as through command decoder 32. In addition, command interface 14 can receive a chip select signal (CS_n). The CS_n signal enables memory device 10 to process commands on the incoming CA<13:0> bus. Access to a particular memory bank 12 within memory device 10 is encoded with a command on the CA<13:0> bus.

[0030] In addition, command interface 14 can be configured to receive a number of other command signals. For example, a command / address on-die termination (CA_ODT) signal can be provided to facilitate proper impedance matching within memory device 10. A reset command (RESET_n) can be used to reset command interface 14, status registers, state machines, and the like, such as during power-up. Command interface 14 can also receive a command / address inversion (CAI) signal, which can be provided to, for example, invert the state of command / address signals CA<13:0> of the command / address bus, depending on the command / address routing of a particular memory device 10. A mirror (MIR) signal can also be provided to facilitate mirror functionality. The MIR signals can be used to multiplex signals so that they can be swapped based on the configuration of multiple memory devices in a particular application to achieve certain routing of signals to memory device 10. Various signals can also be provided to facilitate testing of memory device 10, such as a test enable (TEN) signal. For example, the TEN signal can be used to place memory device 10 in a test mode for connectivity testing.

[0031] Command interface 14 can also be used to provide an alert signal (ALERT_n) to a system processor or controller for certain errors that can be detected. For example, if a cyclic redundancy check (CRC) error is detected, an alert signal (ALERT_n) can be transmitted from memory device 10. Other alert signals can also be generated. In addition, the bus and pin used to transmit the alert signal (ALERT_n) from memory device 10 can be used as an input pin during certain operations, such as a connectivity test mode performed using the TEN signal, as described above.

[0032] With the transmission and reception of data signals 44 through the I / O interface 16, data can be sent to and from the memory device 10 using the command and timing signals discussed above. More specifically, data can be sent to or retrieved from the memory bank 12 over a data bus 46, which includes a plurality of bidirectional data buses. Data I / O signals, commonly referred to as DQ signals, are typically transmitted and received in one or more bidirectional data buses. For certain memory devices, such as DDR5 SDRAM memory devices, the I / O signals can be divided into high and low bytes. For example, for an x16 memory device, the I / O signals can be divided into high and low I / O signals (e.g., DQ<15:8> and DQ<7:0>) corresponding to high and low bytes of data signals, for example.

[0033] To allow for higher data rates within the memory device 10, certain memory devices, such as DDR memory devices, can utilize a data strobe signal, commonly referred to as a DQS signal. The DQS signal is driven by an external processor or controller sending data (e.g., for a write command) or by the memory device 10 (e.g., for a read command). For read commands, the DQS signal is effectively an additional data output (DQ) signal with a predetermined pattern. For write commands, the DQS signal is used as a clock signal to capture the corresponding input data. Like the clock signals (Clk_t and Clk_c), the data strobe (DQS) signal can be provided as a differential pair of data strobe signals (DQS_t and DQS_c) to provide differential pair signaling during reads and writes. For certain memory devices, such as DDR5 SDRAM memory devices, the differential pair of DQS signals can be divided into high and low data strobe signals (e.g., UDQS_t and UDQS_c, LDQS_t and LDQS_c) corresponding to high and low bytes of data sent to and from the memory device 10, for example.

[0034] Impedance (ZQ) calibration signals can also be provided to the memory device 10 through the I / O interface 16. The ZQ calibration signals can be used to tune the output drivers of external pins (e.g., DQ pads, CA pads) and on-die termination (ODT) values by adjusting the pull-up and pull-down driver cells of the memory device 10 across process, voltage, and temperature (PVT) values. Because PVT characteristics can affect the driver cell values, the resistance of the driver cells can fluctuate from a predefined value (e.g., 240Ω). The driver cells are tunable, and the ZQ calibration signals can be used to calibrate the resistance of the driver cells to the predefined value by using an external resistor with an exact resistance. This process is referred to as ZQ calibration. It should be appreciated that the precision resistor is typically coupled between a ZQ pad on the memory device 10 and a GND / VSS external to the memory device 10. This precision resistor is used as a reference for the ZQ calibration.

[0035] Additionally, a loopback signal (LOOPBACK) can be provided to the memory device 10 through the I / O interface 16. The loopback signal can be used during a testing or debugging phase to set the memory device 10 into a mode in which the memory device 10 loops back the signal through the same pin. For example, the loopback signal can be used to set the memory device 10 to test the data output of the memory device 10. The loopback can include both data and strobe pins or can be only the data pin. This is often desirable for monitoring the data captured at the I / O interface 16 by the memory device 10.

[0036] It should be appreciated that various other components (e.g., power supply circuitry (for receiving external VDD and VSS signals), mode registers (for defining various modes of programmable operation and configuration), read / write amplifiers (for amplifying signals during read / write operations), temperature sensors (for sensing the temperature of the memory device 10), etc.) can also be incorporated into the memory system 10. Thus, it should be understood, Figure 1 The block diagram of FIG. 1 is provided merely to highlight certain functional features of the memory device 10 to aid in the following detailed description.

[0037] In some embodiments, the memory device 10 can be disposed in a host device (physically integrated into the host device or otherwise connected to the host device) or otherwise coupled to a host device. The host device can include any of a desktop computer, a laptop computer, a pager, a cellular telephone, a personal organizer, a portable audio player, a control circuit, a camera, etc. The host device can also be a network node, such as a router, a server, or a client (e.g., one of the aforementioned computer types). The host device can be some other kind of electronic device, such as a copier, a scanner, a printer, a game console, a television, a set-top video distribution or recording system, a cable box, a personal digital media player, a factory automation system, an automotive computer system, or a medical device. (The term "system," as used in describing these various examples, as well as many other terms used herein, can share some referents and thus should not be narrowly construed because of the other items listed.)

[0038] Accordingly, the host device can be a processor-based device that can include a processor such as a microprocessor, which controls the processing of system functions and requests in the host. Moreover, any host processor can comprise multiple processors sharing system control. The host processor can be coupled directly or indirectly to additional system elements of the host, such that the host processor controls operations of the host by executing instructions that can be stored in the host or external to the host.

[0039] As discussed above, data can be written to and read from the memory device 10, e.g., by a host, with the memory device 10 operating as volatile memory, such as double data rate DRAM (e.g., DDR5 SDRAM). In some embodiments, the host can also include separate non-volatile memory, such as read-only memory (ROM), PC-RAM, silicon-oxide-nitride-oxide-silicon (SONOS) memory, metal-oxide-nitride-oxide-silicon (MONOS) memory, poly-silicon floating gate based memory, and / or other types of flash memory of various architectures (e.g., NAND memory, NOR memory, etc.) as well as other types of memory devices (e.g., storage devices), such as solid state drives (SSDs), multimedia cards (MMCs), secure digital (SD) cards, compact flash (CF) cards, or any other suitable device. Further, it should be appreciated that the host can include, for example, one or more external interfaces, such as universal serial bus (USB), peripheral component interconnect (PCI), PCI express (PCI-E), small computer system interface (SCSI), IEEE 1394 (FireWire), or any other suitable interface, as well as one or more input devices, such as buttons, switch elements, keyboards, light pens, stylus pens, mice, and / or voice recognition systems, that allow a user to input data into the host. The host can also optionally include output devices, such as a display coupled to the processor and a network interface device, such as a network interface card (NIC), for interfacing with a network (e.g., the Internet). It should be appreciated that the host can include many other components, depending on the application of the host.

[0040] The host can be operable to transfer data to the memory device 10 for storage and can read data from the memory device 10 to perform various operations at the host. Thus, to facilitate these data transfers, in some embodiments, the I / O interface 16 can include a data transceiver 48 that is operable to receive DQ signals from and transmit DQ signals to the I / O interface 16.

[0041] Figure 2 The I / O interface 16 of the memory device 10, and more specifically, the data transceiver 48, is generally illustrated. As illustrated, the data transceiver 48 of the I / O interface 16 can include a DQ connector 50, a DQ transceiver 52, and a serializer / deserializer 54. It should be noted that in some embodiments, multiple data transceivers 48 can be utilized, such that each individual data transceiver 48 can be utilized in connection with a respective one of each of high and low I / O signals (e.g., DQ<15:8> and DQ<7:0>) corresponding to, for example, high and low bytes of a data signal. Thus, the I / O interface 16 can include multiple data transceivers 48 each corresponding to one or more I / O signals (e.g., including respective DQ connectors 50, DQ transceivers 52, and serializer / deserializers 54).

[0042] The DQ connectors 50 can be, for example, pins, pads, combinations thereof, or another type of interface that operates to receive DQ signals, such as for transferring data to the memory array 23 as part of a data write operation. Additionally, the DQ connectors 50 can operate to transfer DQ signals from the memory device 10, such as transferring data from the memory array 23 as part of a data read operation. To facilitate these data reads / writes, the DQ transceivers 52 are present in the data transceivers 48. In some embodiments, for example, the DQ transceivers 52 can receive a clock signal generated by the internal clock generator 30 as a timing signal for determining output timing of a data read operation from the memory array 23. The clock signal transmitted by the internal clock generator 30 can be based on one or more clock signals received by the memory device 10 at clock connectors 56 (e.g., pins, pads, combinations thereof, etc.) and routed to the internal clock generator 30 via the clock input circuit 18. Thus, the DQ transceivers 52 can receive a clock signal generated by the internal clock generator 30 as a timing signal for determining output timing of a data read operation from the memory array 23.

[0043] For example, Figure 2 The DQ transceivers 52 can also receive one or more DQS signals to operate in a gated data mode as part of a data write operation. The DQS signals can be received at DQS connectors 58 (e.g., pins, pads, combinations thereof, etc.) and routed to the DQ transceivers 52 via DQS transceivers 60 that operate to control the data gating mode by selectively transmitting the DQS signals to the DQ transceivers 52. Thus, the DQ transceivers 52 can receive DQS signals to control a data write operation from the memory array 23.

[0044] As noted above, the data transceivers 48 can operate in modes that facilitate data transfer to / from the memory device 10 (e.g., to / from the memory array 23). For example, to allow for higher data rates within the memory device 10, a data gating mode can occur in which DQS signals are utilized. The DQS signals can be driven by an external processor or controller that sends data (e.g., for a write command) that is received by the DQS connectors 58 (e.g., pins, pads, combinations thereof, etc.). In some embodiments, the DQS signals are used as clock signals to capture corresponding input data.

[0045] Additionally, as Figure 2As explained, the data transceiver 48 also includes a serializer / deserializer 54 that operates to translate serial data bits (e.g., a serial bit stream) to parallel data bits (e.g., a parallel bit stream) for transmission along the data bus 46 during data write operations of the memory device 10. Likewise, the serializer / deserializer 54 operates to translate parallel data bits (e.g., a parallel bit stream) to serial data bits (e.g., a serial bit stream) during read operations of the memory device 10. In this manner, the serializer / deserializer 54 operates to translate data received from, for example, a host device, in a serial format to a parallel format suitable for storage in the memory array 23. Likewise, the serializer / deserializer 54 operates to translate data received from, for example, the memory array 23, in a parallel format to a serial format suitable for transmission to a host device.

[0046] Figure 3 The data transceiver 48 is illustrated as including a DQ connector 50 coupled to the data transfer bus 51, a DQ receiver 62, a DQ transmitter 64 (which, in combination with the DQ receiver 62, forms a DQ transceiver 52), a deserializer 66, and a serializer 68 (which, in combination with the deserializer 66, forms the serializer / deserializer 54). In operation, a host (e.g., the host processor described above or other memory device) can be operable to transmit data to the data transceiver 48 in serial form across the data transfer bus 51 as part of a data write operation to the memory device 10. This data is received at the DQ connector 50 and transmitted to the DQ receiver 62. For example, the DQ receiver 62 can perform one or more operations on the data (e.g., amplify, drive the data signals, etc.) and / or can operate as a latch for the data until a corresponding DQS signal is received, the DQS signal operating to coordinate (e.g., control) the transmission of the data to the deserializer 66. As part of the data write operation, the deserializer 66 can be operable to convert (e.g., translate) the data from a format in which it was transmitted along the data transfer bus 51 (e.g., serial form) to a format for transmission of the data to the memory array 23 for storage therein (e.g., parallel form).

[0047] Similarly, during a read operation (e.g., reading data from the memory array 23 and transmitting the read data to the host via the data transfer bus 51), the serializer 68 can receive the data read from the memory array in a format used by the memory array (e.g., a parallel form) and can convert (e.g., translate) the received data to a second format (e.g., a serial form) so that the data can be compatible with one or more of the data transfer bus 51 and / or the host. The converted data can be transmitted from the serializer 68 to the DQ transmitter 64, where one or more operations can occur on the data (e.g., attenuating, driving the data signal, etc.). Additionally, the DQ transmitter 64 can operate as a latch that receives the data until, for example, a corresponding clock signal is received from the internal clock generator 30, which operates to coordinate (e.g., control) the transmission of the data to the DQ connector 50 for transmission along the data transfer bus 51 to one or more components of the host.

[0048] In some embodiments, the data received at the DQ connector 50 can be distorted. For example, the data received at the DQ connector 50 can be affected by inter-symbol interference (ISI), where previously received data interferes with subsequently received data. For example, as the amount of data transmitted across the data transfer bus 51 to the DQ connector 50 increases, the data received at the DQ connector 50 can be distorted relative to the data transmitted by the host. One technique to mitigate (e.g., counteract or cancel) this distortion and effectively reverse the effects of ISI is to apply an equalization operation to the data. Figure 4 An embodiment of the data transceiver 48 is illustrated that includes an equalizer that can be used for this equalization operation.

[0049] Figure 4 One embodiment of the data transceiver 48 is illustrated that includes an equalizer, specifically a decision feedback equalizer (DFE) 70. As illustrated, the DFE 70 is a multi-tap (e.g., 4-tap) DFE 70. However, fewer or more than 4 taps can be utilized in conjunction with the DFE 70. Similarly, the DFE 70 can be disposed separately from or internal to the deserializer 66 or the DQ receiver 62. In operation, a binary output (e.g., from a latch or decision slicer) is captured in one or more data latches or data registers. In this embodiment, these data latches or data registers can be disposed in the deserializer 66 and the values stored therein can be latched or transmitted along paths 72, 74, 76, and 78.

[0050] When a data bit is received at the DQ receiver 62, it can be identified as being transmitted from the host as bit "n" and can be received as a distorted bit n (e.g., a bit n that has been distorted due to ISI) at time to. The most recent bit received prior to the receipt of the distorted bit n at the DQ receiver 62 (e.g., at time t -1The received bit (n-1) can be identified as being transmitted along path 72 from the data latch or data register. The second most recent bit received before the distorted bit n is received at DQ receiver 62 (e.g., immediately following time t). -1 The previous time t -2 The received data (n-2) can be identified as being transmitted along path 74 from the data latch or data register. The third most recent bit received before the distortion bit n is received at DQ receiver 62 (e.g., immediately following time t). -2 The previous time t -3 The received data (n-3) can be identified as being transmitted along path 76 from the data latch or data register. The fourth most recent bit received before the distortion bit n is received at DQ receiver 62 (e.g., immediately following time t). -2 The previous time t -3 The received data (n-4) can be identified as being transmitted from a data latch or data register along path 78. Bits n-1, n-2, n-3, and n-4 can be considered as a group of bits interfering with the received distorted bit n (e.g., bits n-1, n-2, n-3, and n-4 cause ISI in the host transmitted bit n), and DFE 70 is operable to cancel the distortion caused by the group of bits n-1, n-2, n-3, and n-4 on the host transmitted bit n. Therefore, the values ​​latched or transmitted along paths 72, 74, 76, and 78 can respectively correspond to the most recent previous data values ​​(e.g., previous bits n-1, n-2, n-3, and n-4) stored in memory array 23 transmitted from DQ receiver 62. These previously transmitted bits are fed back to DFE 70 along paths 72, 74, 76, and 78. DFE 70 operates to generate a weighted tap / tap bias (e.g., voltage), which can be added to the received input signal (e.g., data received from DQ connector 50, e.g., distortion bit n) by means of a summer (e.g., a summing amplifier). In other embodiments, the weighted tap (e.g., voltage) can be combined with an initial reference value to produce a cancellation corresponding to or mitigating distortion of the received data (e.g., mitigating distortion of distortion bit n). In some embodiments, the taps are weighted to reflect that the most recently received data (e.g., bit n-1) may have a stronger effect on the distortion of the received data (e.g., distortion bit n) than bits received at earlier times (e.g., bits n-1, n-2, and n-3). DFE 70 is operable to generate a tap bias (e.g., voltage) (including magnitude and polarity) for each previous bit to collectively cancel out the distortion caused by these previously received bits.

[0051] The polarity of the tap offset for a tap is the sign bit for that tap, which can be stored in a mode register. For example, for a +50mV tap offset, the polarity is "+" and the sign bit is high (e.g., "1"); while for a -50mV tap offset, the polarity is "-" and the sign bit is low (e.g., "0"). The sign bit can be used to select (e.g., by a multiplexer) a feedback (e.g., one of a DFE output and an inverted DFE output) or an adjusted reference value (e.g., a reference signal for an amplification device). For example, ISI can have two types of residuals. The first type of residual is greater than 0 and the second type of residual is less than 0. The sign bit option can be used for DFE to handle both cases. For example, if the sign bit is low, it can be considered that the residual is greater than 0 and the corresponding feedback for the first type of ISI can be selected; if the sign bit is high, it can be considered that the residual is less than 0 and the corresponding feedback for the second type of ISI can be selected. For example, for the first type of ISI, the reference value (e.g., a reference voltage for an amplifier) can be increased when the previous data has a logical high (e.g., "1"); and the reference value can be decreased when the previous data has a logical low (e.g., "0"). For example, for the second type of ISI, the reference value (e.g., a reference voltage for an amplifier) can be decreased when the previous data has a logical high (e.g., "1"); and the reference value can be increased when the previous data has a logical low (e.g., "0").

[0052] For example, for the present embodiment, each of the previously received bits n-1, n-2, n-3, and n-4 can have had one of two values (e.g., binary 0 or 1) transmitted to the deserializer 66 for transmission to the memory array 23 and additionally latched or saved in a register for subsequent transmission along the respective paths 72, 74, 76, and 78. In the illustrated embodiment, this results in 16 (e.g., 2 4 The DFE 70 operates to select and / or generate a corresponding tap value for determining which of the above 16 combinations is present (e.g., based on the received values along the paths 72, 74, 76, and 78) for adjusting an input value (e.g., a distorted bit n) received from the DQ connector 50 or modifying a reference value (e.g., a reference signal for an amplification device) subsequently applied to an input value (e.g., a distorted bit n) received from the DQ connector 50 in order to eliminate ISI distortion from the previous bits (e.g., the group of n-1, n-2, n-3, and n-4) in the data stream.

[0053] It can be beneficial to use a distortion correction (e.g., the DFE 70) so that data transmitted from the DQ connector 50 is correctly and undistortedly represented in the memory array 23. Thus, it can be useful to store previous bit data for distortion correction. As Figure 5As illustrated by the block diagram, distortion correction circuit 80 can be included as part of DQ receiver 62, but can not need to be physically located there (e.g., distortion correction circuit 80 can instead be coupled to DQ receiver 62). In some embodiments, distortion correction circuit 80 can be operated to provide previous transmit bit data to correct distorted bits 81 (e.g., bits that have been distorted due to ISI and / or system distortion) transmitted via channel 84 (e.g., connections, transmission lines, and / or conductive material).

[0054] Distorted bits 81 can be transmitted from channel 84 to amplification device 82 (e.g., a variable gain amplifier). Distorted bits 81 can be transmitted from amplification device 82 to DFE 70, which is illustrated as having a single weighted tap 86. Distorted bits 81 can be transmitted to DFE 70 concurrently with DQ reference signal 83. DQ reference signal 83 can represent a threshold (e.g., a voltage level) for determining whether a transmitted bit received by DQ connection 50 is a logical low (e.g., 0) or a logical high (e.g., 1).

[0055] DFE 70 can be operated to correct distortion of distorted bits 81 (e.g., n-bit data) using a weighted tap of previous bit data (e.g., n-1-bit data). The n-1-bit data (e.g., a logical 1 or a logical 0) can be transmitted through path 72. The magnitude and polarity (i.e., sign bit) of single weighted tap 86 can be used via summer circuit 85, which operates as a current summer, to cancel the total distortion caused by n-1-bit to distorted bits 81. For example, if it is determined that the received bit at DQ connection 50 is below DQ reference signal 83, then received bit 81 is transmitted as a logical low to memory array 23. The magnitude and polarity (i.e., sign bit) of weighted tap 86 can be determined to correct distorted bits 81 and DQ reference signal 83. The sign bit of weighted tap 86 can be used to select (e.g., via a multiplexer) feedback or an adjusted reference value based on the type of ISI.

[0056] A modified version of distorted bits 81 and a modified version of DQ reference signal 83 can be transmitted to data latch 94. Corrected bits 88 can be generated via data latch 94 and transmitted from data latch 94 to deserializer 66, which can occur on a rising edge of DQS signal 96. In other embodiments, variations of the timing scheme can be followed to include additional or alternative data transmission methods. For example, when corrected bits 88 are received in deserializer 66, the value of the new n-1-bit can be stored in deserializer 66 for transmission along path 72.

[0057] As Figure 5As explained, the distortion correction circuit 80 can include multiple elements in a feedback loop for correcting distortion of the bit 81, such as an amplification device 82 (e.g., a variable gain amplifier), a summer circuit 85, a data latch 94, etc. Thus, a feedback loop delay time can occur due to processing times of the multiple elements in the feedback loop and times for generating signals used in the feedback loop (e.g., the weighted taps 86). In some embodiments, the tap bias (e.g., voltage) including magnitude and polarity (i.e., sign bit) can be determined during normal operation (e.g., during DQ training) and fixed, and values of the tap bias (e.g., for various tap and / or weight options) can be stored in a mode register setting. Thus, the sign bit can be fixed during normal operation and obtained from the mode register setting. The feedback loop delay time can be reduced by using a selection device (e.g., a multiplexer) outside the feedback loop of the DFE circuit to select a feedback or adjusted reference value for the DFE circuit based on the mode register setting of the sign bit. For example, a multiplexer can be used outside the feedback loop of the DFE 70 to select an adjusted value for the DQ reference signal 83 of the amplification device 82 based on the determined sign bit of the weighted taps 86, which can reduce the total feedback loop delay time. In some embodiments, a loop-unrolled DFE circuit can be used to obtain distortion correction faster by processing possible decisions for a single previous data bit in parallel with the corresponding latches. In some loop-unrolled DFE circuits, the sign bit can be used to select (e.g., via a multiplexer) a feedback or adjusted reference value based on a type of ISI, which can result in a corresponding time delay. The feedback loop delay time can be reduced by using a selection device (e.g., a multiplexer) outside the feedback loop of the unrolled DFE circuit to select a feedback or adjusted reference value, as explained in more detail below. Figure 6 and Figure 7 as explained.

[0058] Figure 6 An embodiment of a distortion correction circuit 150 for a 2-phase input receiver with a loop-unrolled 1-tap DFE is explained that implements a sign bit to select an adjusted value for a reference voltage of an amplifier. The distortion correction circuit 150 can include a first circuit 160 for processing one bit received at CK1 (i.e., at a first phase (e.g., a rising edge of the DQS signal 96)) and a second circuit 200 for processing one bit received at CK2 (i.e., at a second phase (e.g., a falling edge of the DQS signal 96)). For example, a first distortion bit 162 can be received by the first circuit 160 at CK1, a second distortion bit 202 can be received by the second circuit 200 at CK2, and a third distortion bit can be rolled back to be received by the first circuit 160 once a first iteration of distortion correction is complete.

[0059] as Figure 6As explained, the first circuit 160 can include two paths to separately and concurrently process possible decisions (e.g., "1" or "0") of the previous bit T2 determined by the second circuit 200. For example, the first circuit 160 can include a T2 high path 164 corresponding to the previous bit T2 being a logical high (e.g., "1") and a T2 low path 184 corresponding to the previous bit T2 being a logical low (e.g., "0"). As previously mentioned, there can be two types of ISI, where the first type corresponds to the sign bit being a logical low and the second type corresponds to the sign bit being a logical high. For the first type of ISI, when the previous bit has a logical high (e.g., "1"), the reference value (e.g., reference voltage) can increase (e.g., V REF + Δtapl); when the previous bit has a logical low (e.g., "0"), the reference value can decrease (e.g., V REF - Δtapl). For the second type of ISI, when the previous bit has a logical high (e.g., "1"), the reference value can decrease (e.g., V REF - Δtapl); when the previous bit has a logical low (e.g., "0"), the reference value can increase (e.g., V REF + Δtapl). Thus, the sign bit can be used to select a corresponding reference value (e.g., "V REF + Δtapl" or "V REF - Δtapl") for the T2 high path 164 and the T2 low path 184.

[0060] As Figure 6 explained, the T2 high path 164 can include an amplifier 166 to receive the first distorted bit 162. The T2 high path 166 can include a selection device 168 (e.g., multiplexer) to select a reference value 170 (e.g., reference voltage) for the amplifier 166 based on the sign bit 172. For the first type of ISI, when the previous bit T2 has a logical high (e.g., "1"), the reference value 170 can increase (e.g., V REF + Δtapl); while for the second type of ISI, when the previous bit T2 has a logical high (e.g., "1"), the reference value 170 can decrease (e.g., V REF - Δtapl). Thus, the sign bit 172 can be used to select a corresponding value (e.g., "V REF + Δtapl" or "V REF - Δtapl") for the reference value 170. The T2 high path 164 can include a latch 174 and an SR latch 176 to process the distorted bit 162 using the reference value 170, and a result 178 from the SR latch 176 can be sent to a selection device 180 (e.g., a demultiplexer) along with a result obtained from the T2 low path 184.

[0061] As Figure 6As described, the T2 low path 184 may include an amplifier 186 to receive the first distortion bit 162. The T2 low path 184 may include a selection device 188 (e.g., a multiplexer) to select a reference value 190 (e.g., a reference voltage) for the amplifier 186 based on the sign bit 172. For the first type of ISI, the reference value 190 may be reduced (e.g., V) when the previous bit T2 has a logic low (e.g., "0"). REF -Δtap1); while for the second type of ISI, when the previous bit T2 has a logic low (e.g., "0"), the reference value 190 can be increased (e.g., V). REF +Δtap1). Therefore, as Figure 6 As illustrated in the embodiments, sign bit 172 or the inversion of sign bit 172 can be used to select a corresponding value (e.g., "V") for reference value 190. REF -Δtap1" or "V" REF +Δtap1”). The high path 184 of T2 may include latch 192 and SR latch 194 to process the distortion bit 162 using the reference value 190, and the result 196 of SR latch 194 may be sent together with the result 178 obtained from the high path 164 of T2 to the selection device 180 (e.g., an unwinding multiplexer). The selection device 180 may make a final decision on which value (e.g., the value of result 178 or result 196) the correction bit 198 takes based on the value of the previous bit T2 (result 238) generated by the second circuit 200. For example, when the previous bit T2 generated by the second circuit 200 has logic high, the correction bit 198 takes the result 178 generated by the high path 164 of T2; when the previous bit T2 generated by the second circuit 200 has logic low, the correction bit 198 takes the result 196 generated by the low path 184 of T2.

[0062] like Figure 6 As explained, the second circuit 200 may include two paths to process, respectively, the possible decisions (e.g., "1" or "0") of the previous bit T1 determined by the first circuit 160 in parallel. For example, the second circuit 200 may include a T1 high path 204 corresponding to the previous bit T1 being logic high (e.g., "1") and a T1 low path 224 corresponding to the previous bit T1 being logic low (e.g., "0"). As previously mentioned, there may be two types of ISI, where the first type corresponds to the sign bit being logic low and the second type corresponds to the sign bit being logic high. For the first type of ISI, when the previous bit has logic high (e.g., "1"), the reference value (e.g., reference voltage) may be increased (e.g., V). REF +Δtap1); when the previous bit has a logic low (e.g., "0"), the reference value can be reduced (e.g., V). REF -Δtap1). For the second type of ISI, the reference value can be reduced (e.g., V) when the previous bit has a logic high (e.g., "1"). REF-Δtap1); When the previous bit has a logic low (e.g., "0"), the reference value can be increased (e.g., V). REF +Δtap1). Therefore, the sign bit can be used to select the corresponding reference value (e.g., "V") for T1 high path 204 and T1 low path 224. REF +Δtap1” or “V” REF -Δtap1”).

[0063] like Figure 6 As described, the high path 204 of T1 may include an amplifier 206 to receive the first distortion bit 202. The high path 204 of T1 may include a selection device 208 (e.g., a multiplexer) to select a reference value 210 (e.g., a reference voltage) for the amplifier 206 based on the sign bit 172. For the first type of ISI, the reference value 210 may be increased (e.g., V) when the previous bit T1 has a logic high (e.g., "1"). REF +Δtap1); while for the second type of ISI, when the previous bit T1 has a logic high (e.g., "1"), the reference value 210 can be reduced (e.g., V). REF -Δtap1). Therefore, sign bit 172 can be used to select a corresponding value for reference value 210 (e.g., "V"). REF +Δtap1” or “V” REF -Δtap1). The high path 204 of T1 may include latch 214 and SR latch 216 to process the distortion bit 202 using reference value 210, and the result 218 from SR latch 216 may be sent together with the result obtained from the low path 224 of T1 to the selection device 220 (e.g., an unwinding multiplexer).

[0064] like Figure 6 As described, the low path 224 of T1 may include an amplifier 226 to receive the first distortion bit 202. The low path 224 of T1 may include a selection device 228 (e.g., a multiplexer) to select a reference value 230 (e.g., a reference voltage) for the amplifier 226 based on the sign bit 172. For the first type of ISI, when the preceding bit T1 has a logic low (e.g., "0"), the reference value 230 may decrease (e.g., VREF - Δtap1); while for the second type of ISI, when the preceding bit T1 has a logic low (e.g., "0"), the reference value 230 may increase (e.g., VREF + Δtap1). Therefore, as Figure 6As illustrated in the embodiments, sign bit 172 or the inversion of sign bit 172 can be used to select a corresponding value for reference value 230 (e.g., "VREF-Δtap1" or "VREF+Δtap1"). The low path 224 of T1 may include latch 232 and SR latch 234 to process the distortion bit 202 using reference value 230, and the result 236 of SR latch 234 may be sent together with the result 218 obtained from the high path 204 of T1 to selection device 220 (e.g., an unwinding multiplexer). Selection device 220 may make a final decision on which value (e.g., the value of result 218 or result 236) to take for correction bit 238 based on the result 198 of the previous bit T1 generated by the first circuit 160. For example, when the previous bit T1 generated by the first circuit 160 has a logic high, the correction bit 238 takes the result 218 generated by the high path 204 of T1; when the previous bit T1 generated by the first circuit 160 has a logic low, the correction bit 238 takes the result 236 generated by the low path 224 of T1.

[0065] like Figure 7 As illustrated in the embodiments, since the sign bit 172 can be determined and fixed during normal operation (e.g., during DQ training), the selection devices associated with the sign bit 172 (e.g., selection devices 168, 188, 208, 228) can be excluded from the feedback loop of the distortion correction circuit 150, thereby reducing the feedback loop delay time.

[0066] Figure 7 Another embodiment of a distortion correction circuit 364 with a basic 2-phase input receiver having a loop-unwound 1-tap DFE is described, which is capable of processing two data bits, one bit received at DQS0 (i.e., at the rising edge of the first phase, e.g., the DQS signal 96) and the other bit received at DQS180 (i.e., at the falling edge of the second phase, e.g., the DQS signal 96). The distortion correction circuit 364 includes a first circuit 366 and a second circuit 368, which may be distortion correction circuits similar to distortion correction circuits 160 and 200, respectively. For example, distortion bit 81 may be received by the first circuit 366 at DQS0, a second distortion bit 281 may be received by the second circuit 368 at DQS180, and a third distortion bit may be rolled back to be received by the first circuit 366 once the first iteration of distortion correction is completed.

[0067] The first circuit 366 may include two equalizers to process, respectively, the possible decisions (e.g., "1" or "0") of the previous bit determined by the second circuit 368 in parallel. For example, the first circuit 366 may include an equalizer 370 corresponding to a previous bit being logic high (e.g., "1") and an equalizer 372 corresponding to a previous bit being logic low (e.g., "0"). The sign bit 172 can be used to select a corresponding reference value (e.g., "V") for equalizers 370 and 372. REF+Δtap1” or “V” REF -Δtap1”).

[0068] To further illustrate, the first circuit 366 may receive the distortion bit 81 and may begin processing it using the method described by the distortion correction circuit 160, and an enable signal (i.e., EN) may be used to enable or disable the corresponding equalizer (e.g., equalizer 370 or equalizer 372). The first circuit 366 may include a selection device 300 (e.g., a multiplexer) to select a reference value 374 (e.g., a reference voltage) for equalizer 370 based on the sign bit 172. For the first type of ISI, the reference value 374 may be increased (e.g., V) when the previous bit 390 generated by the second circuit 368 has a logic high (e.g., "1"). REF +Δtap1); while for the second type of ISI, when the previous bit 390 has a logic high (e.g., "1"), the reference value 374 can be reduced (e.g., V). REF -Δtap1). Therefore, sign bit 172 can be used to select the corresponding value for reference value 374 (e.g., "V"). REF +Δtap1” or “V” REF -Δtap1”). The first circuit 366 may include a selection device 310 (e.g., a multiplexer) to select a reference value 376 (e.g., a reference voltage) for the equalizer 372 based on the sign bit 172. For the first type of ISI, the reference value 376 may be reduced (e.g., V) when the previous bit 390 has a logic low (e.g., “0”). REF -Δtap1); while for the second type of ISI, when the previous bit 390 has a logic low (e.g., "0"), the reference value 376 can be increased (e.g., V). REF +Δtap1). Therefore, as Figure 7 As illustrated in the embodiments, sign bit 172 or the inversion of sign bit 172 can be used to select a corresponding value (e.g., "V") for reference value 376. REF -Δtap1" or "V" REF +Δtap1”).

[0069] like Figure 7 As explained, the output 378 from equalizer 370 and the output 380 from equalizer 372 can be transmitted to selection device 386 (e.g., multiplexer) at DQS0 (e.g., the rising edge of DQS signal 96). Selection device 386 can make a final decision on which value (e.g., the value of output 378 or output 380) the correction bit 394 should take based on the value of the previous bit 390 generated by the second circuit 368.

[0070] The second circuit 368 may include two equalizers to process, respectively, the possible decisions (e.g., "1" or "0") of the previous bit determined by the first circuit 366 in parallel. For example, the second circuit 368 may include an equalizer 396 corresponding to a logic high (e.g., "1") of the previous bit 394 and an equalizer 398 corresponding to a logic low (e.g., "0") of the previous bit 394. The sign bit 172 can be used to select a corresponding reference value (e.g., "V") for equalizers 396 and 398. REF +Δtap1” or “V” REF -Δtap1”).

[0071] The second circuit 368 can receive the distortion bit 281 and can begin processing it using the method described by the distortion correction circuit 366, and an enable signal (i.e., EN) can be used to enable or disable the corresponding equalizer (e.g., equalizer 396 or equalizer 398). The second circuit 368 may include a selection device 320 (e.g., a multiplexer) to select a reference value 400 (e.g., a reference voltage) for equalizer 396 based on the sign bit 172. For the first type of ISI, the reference value 400 can be increased (e.g., V) when the previous bit 394 has a logic high (e.g., "1"). REF +Δtap1); while for the second type of ISI, when the previous bit 394 has a logic high (e.g., "1"), the reference value 400 can be reduced (e.g., V). REF -Δtap1). Therefore, sign bit 172 can be used to select the corresponding value for reference value 400 (e.g., "V"). REF +Δtap1” or “V” REF -Δtap1”). The second circuit 368 may include a selection device 330 (e.g., a multiplexer) to select a reference value 402 (e.g., a reference voltage) for the equalizer 398 based on the sign bit 172. For the first type of ISI, the reference value 402 may be reduced (e.g., V) when the preceding bit 394 has a logic low (e.g., “0”). REF -Δtap1); while for the second type of ISI, when the previous bit 394 has a logic low (e.g., "0"), the reference value 402 can be increased (e.g., V). REF +Δtap1). Therefore, as Figure 7 As illustrated in the embodiments, sign bit 172 or the inversion of sign bit 172 can be used to select a corresponding value (e.g., "V") for reference value 402. REF -Δtap1" or "V" REF +Δtap1”).

[0072] like Figure 8As explained, output 404 from equalizer 396 and output 406 from equalizer 398 can be transmitted to selection device 412 (e.g., multiplexer) at DQS 180 (e.g., the falling edge of DQS signal 96). Selection device 412 can make a final decision on which value (e.g., the value of output 404 or output 406) the correction bit 390 should take based on the value of the previous bit 394 generated by the first circuit 366.

[0073] ​ This is a flowchart of a method 500 for implementing a sign bit in a distortion correction circuit. At block 502, the distortion correction circuit (e.g., distortion correction circuits 150, 160, 200, 364, 366, or 368) may receive a distortion bit (e.g., distortion bit 162). At block 504, a sign bit (e.g., sign bit 172) may be used to select a first reference value (e.g., reference value 170) corresponding to a previous bit (e.g., T2 bit 238) of the distortion bit as logic high, and a first possible result (e.g., result 178) of the correction bit corresponding to the distortion bit where the previous bit was logic high may be determined. At block 506, a sign bit (e.g., sign bit 172) may be used to select a second reference value (e.g., reference value 190) corresponding to a previous bit (e.g., T2 bit 238) of the distortion bit as logic low, and a second possible result (e.g., result 196) of the correction bit corresponding to the distortion bit where the previous bit was logic low may be determined. At block 508, the distortion correction circuit can select the correction bit (e.g., bit 198) of the distortion bit from the first possible result and the second possible result based on the value of the previous bit (e.g., bit 238 of T2).

[0074] Although method 500 is described above in a specific order, it should be noted that method 500 can be executed in any suitable order and is not limited to the order presented herein. For example, a first possible result and a second possible result can be obtained in parallel.

[0075] Therefore, the technical advantages of this disclosure include a method and system for selectively outputting a reference signal based on sign bits stored in one or more mode registers using a selection device outside the feedback loop of the DFE circuit. The reference signal includes a reference voltage signal, which is used by an amplifier or equalizer of the DFE circuit to generate a correction signal for the distorted signal. By using a selection device outside the feedback loop of the DFE circuit to generate the reference signal, the feedback loop delay time is reduced, and the total operating time of the DFE circuit is reduced. Therefore, the efficiency of the DFE circuit is improved.

[0076] In the embodiments described above, the memory devices and systems are primarily described in the context of devices incorporating DRAM storage media. However, memory devices configured according to other embodiments of the present technology may include other types of memory devices and systems incorporating other types of storage media, including PCM, SRAM, FRAM, RRAM, MRAM, read-only memory (ROM), erasable programmable ROM (EPROM) and electrically erasable programmable ROM (EEPROM), ferroelectric, magnetoresistive and other storage media, including non-volatile, flash (e.g., NAND and / or NOR) storage media. It should also be noted that in the embodiments described above, the DFE circuitry is primarily described in the context of a 1-tap DFE or a loop-unwound 1-tap DFF. However, implementing a sign bit outside the DFE feedback loop can be used for other types of DFE circuitry (e.g., 2-tap, 3-tap, 4-tap, loop-unwound or non-unwound).

[0077] While various modifications and alternatives are permissible with respect to this disclosure, specific embodiments have been shown by way of example in the drawings and described in detail herein. However, it should be understood that this disclosure is not intended to be limited to the specific forms disclosed. Rather, this disclosure is intended to cover all modifications, equivalents, and alternatives falling within the spirit and scope of this disclosure as defined by the appended claims.

[0078] The techniques proposed and claimed herein are referenced and applied to practical objects and specific examples that clearly improve the field of technology and are therefore not abstract, intangible, or purely theoretical. Furthermore, if any claim appended to this specification contains one or more elements designated as “a component for [performing…function]” or “a step for [performing…function]”, then those elements are intended to be interpreted according to 35U.SC112(f). However, for any claim containing elements designated in any other way, such elements are not intended to be interpreted according to 35U.SC112(f).

Claims

1. An apparatus comprising: The selection device is configured to select a reference value from a plurality of reference values ​​based on the sign bit; and The input receiver circuit is configured to: Receive input signals; Receive the reference value from the selection device; and An adjustment signal is generated for the input signal based on the reference value.

2. The apparatus of claim 1, wherein the selection device comprises a multiplexer.

3. The apparatus of claim 1, wherein the value of the sign bit is stored in one or more mode registers.

4. The apparatus of claim 3, wherein the value of the sign bit is fixed.

5. The apparatus of claim 1, wherein the reference value includes a reference voltage value.

6. The apparatus of claim 5, wherein the input receiver circuitry includes an amplifier to receive the reference value.

7. The apparatus of claim 5, wherein the input receiver circuitry includes an equalizer to receive the reference value.

8. The apparatus of claim 1, wherein the apparatus includes another selection means for selecting another reference value from the plurality of reference values ​​based on the inversion of the sign bit.

9. The apparatus of claim 8, wherein the reference value corresponds to a previous signal of the input signal being logic high, and the other reference value corresponds to the previous signal of the input signal being logic low.

10. The apparatus of claim 9, wherein the input receiver circuitry is configured to generate the adjustment signal based on the reference value and the other reference value.

11. A method comprising: Receive input signals; The first reference value is selected from multiple reference values ​​based on the sign bit. The second reference value is selected from the plurality of reference values ​​based on the inversion of the sign bit; and An adjustment signal is generated for the input signal based on the first reference value and the second reference value.

12. The method of claim 11, wherein the value of the sign bit is stored in one or more mode registers.

13. The method of claim 12, wherein the value of the sign bit is fixed.

14. The method of claim 11, wherein the first reference value includes a reference voltage value.

15. An input receiver circuit, comprising: The first component, which is used for: Receive input signals; and Receive a first reference value selected from multiple reference values ​​based on the sign bit; The second component is used for: Receive the input signal; and Receive a second reference value selected from the plurality of reference values ​​based on the inversion of the sign bit; and A selection device is used to select an adjustment signal for the signal from a first result generated based on the first reference value and a second result generated based on the second reference value.

16. The circuit of claim 15, wherein the value of the sign bit is stored in one or more mode registers.

17. The circuit of claim 16, wherein the value of the sign bit is fixed.

18. The circuit of claim 15, wherein the reference value includes a reference voltage value.

19. The circuit of claim 18, wherein the first component includes an amplifier to receive the first reference value.

20. The circuit of claim 18, wherein the first component includes an equalizer to receive the first reference value.

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