Memory device and driving method of sensing device included in memory device

Abstract

The present disclosure provides a memory device including a first memory cell connected to a first bit line, a second memory cell connected to a second bit line, a first transistor connected to the first bit line and configured to transfer a first data signal based on first data stored in the first memory cell to an input node of the bit line sense amplifier, and a second transistor connected to the second bit line and configured to transfer a second data signal based on second data to the input node. The bit line sense amplifier is configured to amplify a selected one of the first data signal or the second data signal to output the first amplified signal to the local sense amplifier through the local transistor.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2024-0131672, filed with the Korean Intellectual Property Office on September 27, 2024, and all benefits derived therefrom, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] This disclosure relates to memory devices, and more particularly, to memory devices including sensing devices and driving methods. Background Technology

[0004] During read or refresh operations in a memory device, a sense amplifier senses the voltage difference between a bit line and its complementary bit line to sense data in the memory cell. Because memory cells are becoming smaller and the load on the bit lines increases due to the high integration of memory devices, maintaining a sufficient margin in the voltage difference can be difficult. If this margin cannot be maintained, data sensing of the memory cell may fail. Summary of the Invention

[0005] Various aspects of this disclosure provide a memory device with improved performance for sensing data stored in memory cells.

[0006] Various aspects of this disclosure also provide a memory device including a sense amplifier circuit that operates at low power.

[0007] The present disclosure also provides a memory device with improved accuracy.

[0008] According to one aspect of this disclosure, a memory device is provided, including a first memory cell connected to a first bit line, a second memory cell connected to a second bit line, a first transistor connected to the first bit line and configured to transmit a first data signal based on first data stored in the first memory cell to an input node of a bit-line sense amplifier, and a second transistor connected to the second bit line and configured to transmit a second data signal based on second data stored in the second memory cell to the input node of the bit-line sense amplifier. The bit-line sense amplifier may be connected to the input node to amplify a selected one of the first data signal or the second data signal provided to the input node to output a first amplified signal. A local transistor may be connected to the output node of the bit-line sense amplifier and may be connected to the input of a local sense amplifier configured to amplify the first amplified signal to output a second amplified signal.

[0009] According to another aspect of this disclosure, a memory device is provided, including a first memory cell connected to a first bit line and configured to store first data; a first transistor having a first terminal connected to the first bit line and configured to transmit a first data signal based on the stored first data to a second terminal; a bit line sense amplifier connected to the first transistor and configured to amplify the first data signal to output a first amplified signal to an output node via a precharge transistor; a local transistor having a first local terminal connected to the output node of the bit line sense amplifier and a second local terminal connected to the local sense amplifier, wherein the local sense amplifier is configured to amplify the first amplified signal to output a second amplified signal; and control logic circuitry configured to control the transmission of the first amplified signal to the local sense amplifier by controlling the local transistor to be in an on state and controlling the precharge transistor to be in an off state.

[0010] According to another aspect of this disclosure, a method for driving a memory device is provided, the memory device including a first memory cell connected to a first bit line and storing data, a first transistor connected to the first bit line, a bit line sense amplifier connected to the first transistor and including a precharge transistor, and a local transistor connected to the bit line sense amplifier and a local sense amplifier, the method including, when the first transistor is turned on, providing a first data signal based on the stored data to the bit line sense amplifier, amplifying the first data signal by the bit line sense amplifier to obtain a first amplified signal, providing the first amplified signal to an output node of the bit line sense amplifier when the precharge transistor is turned on, and providing the output of the bit line sense amplifier to the local sense amplifier when the local transistor has an on state and the precharge transistor has an off state, so as to provide the first amplified signal from the output node of the bit line sense amplifier to the local sense amplifier. Attached Figure Description

[0011] The above and other aspects and features of this disclosure will become more apparent from the detailed description of illustrative embodiments with reference to the accompanying drawings, in which:

[0012] Figure 1 This is a block diagram used to explain a memory device according to some embodiments of the present disclosure.

[0013] Figure 2 This is a diagram used to explain the memory cell array and sense amplifier in a memory device according to some embodiments of the present disclosure.

[0014] Figure 3 This is a diagram used to explain the memory cells and sense amplifier circuitry in a memory device according to some embodiments of the present disclosure.

[0015] Figure 4 This illustrates the implementation according to an embodiment. Figure 1 A perspective view of the memory device.

[0016] Figure 5 This illustrates the implementation according to an embodiment. Figure 1 The circuit diagram of the memory cell array.

[0017] Figure 6 This is an exemplary circuit diagram 600 of a sense amplifier circuit in a memory device according to some embodiments of the present disclosure.

[0018] Figure 7 It is used for explanation Figure 6 An exemplary timing diagram 700 of the first operation of the sensing amplifier circuit is shown.

[0019] Figure 8 This is an exemplary circuit diagram 800 illustrating a sense amplifier circuit in a memory device according to some embodiments.

[0020] Figure 9 It is used for explanation Figure 6 An exemplary timing diagram of the second operation of the sensing amplifier circuit is shown.

[0021] Figures 10 to 13 This is a circuit diagram of the sense amplifier circuit that performs the second operation.

[0022] Figure 14 It is used for explanation Figure 6 An exemplary timing diagram of the third operation of the sensing amplifier circuit is shown in the figure.

[0023] Figure 15 It is used for explanation Figure 6 An exemplary timing diagram of the fourth operation of the sense amplifier circuit is shown in the figure.

[0024] Figure 16 It is used for explanation Figure 6 An exemplary timing diagram of the fifth operation of the sensing amplifier circuit is shown in the figure.

[0025] Figure 17 This is a graph showing the sensing data of the internal power supply of a sensing amplifier circuit in a memory device according to some embodiments.

[0026] Figure 18 This is a graph illustrating sensing data of a sensing amplifier circuit in a memory device according to some embodiments.

[0027] Figure 19 This is a block diagram illustrating a computer device including a memory device according to some embodiments. Detailed Implementation

[0028] The contents of this disclosure will now be described clearly and in detail so that those skilled in the art can readily implement this disclosure using the accompanying drawings.

[0029] Throughout this specification, when a component is described as “comprising” a particular element or group of elements, it should be understood that the component is formed solely by that element or group of elements, or that the element or group of elements may be combined with additional elements to form the component, unless the context otherwise requires. On the other hand, the term “composed of” indicates that the component is formed solely by the listed elements.

[0030] As used herein, components described as "electrically connected" are configured such that electrical signals can be transmitted from one component to another (although the strength of these signals may attenuate as they are transmitted and they can be selectively transmitted). Furthermore, components with "direct electrical connections" form a common electrical node through electrical connections of one or more conductors (such as wires, pads, internal wires, vias, etc.). Therefore, directly electrically connected components do not include components electrically connected via active elements, such as transistors or diodes.

[0031] Ordinal numbers such as "first," "second," and "third" can simply be used as labels to distinguish certain elements, steps, etc., from one another. Terms not described using "first," "second," etc., in the specification may still be referred to as "first" or "second" in the claims. Furthermore, a term referenced with a specific ordinal number (e.g., "first" in a particular claim) may be described elsewhere using a different ordinal number (e.g., "second" in the specification or another claim).

[0032] Figure 1 This is a block diagram used to explain a memory device according to some embodiments of the present disclosure.

[0033] refer to Figure 1 The memory device 100 may include a memory cell array 110, control logic circuitry 120, address buffer 130, sense amplifier 140, row decoder 150, column decoder 160, input / output (I / O) gating circuitry 170, and data I / O buffer 180. In some embodiments, the memory device 100 may be dynamic random-access memory (DRAM).

[0034] The memory cell array 110 may include multiple rows, multiple columns, and multiple memory cells MC arranged at the intersections of the multiple rows and multiple columns. The multiple rows may be defined by multiple word lines WL, and the multiple columns may be defined by multiple bit lines BL.

[0035] Control logic circuitry 120 may be an internal controller of memory device 100 and may control the operation of memory device 100. For example, control logic circuitry 120 may generate control signals that cause memory device 100 to perform read, write, or refresh operations. In some embodiments, control logic circuitry 120 may generate control signals by decoding a command CMD received from the memory controller. In some embodiments, control logic circuitry 120 may transmit control signals to sense amplifier 140, row decoder 150, and column decoder 160. In some examples, control logic circuitry 120 may also be configured to control the timing of control signals provided to sense amplifier 140, row decoder 150, and column decoder 160.

[0036] Address buffer 130 can receive address ADDR provided from the memory controller. Address ADDR may include row address RA indicating a row of memory cell array 110 and column address CA indicating a column. Row address RA may be provided to row decoder 150, and column address CA may be provided to column decoder 160.

[0037] The row decoder 150 can select the row to be activated from among multiple rows of the memory cell array 110 based on the row address RA. To do this, the row decoder 150 can apply a drive voltage to the word line WL corresponding to the row to be activated.

[0038] The column decoder 160 can select the column to be activated from among multiple columns of the memory cell array 110 based on the column address CA. To this end, the column decoder 160 can activate the sense amplifier 140 corresponding to the column address CA via the I / O gating circuit 170. The sense amplifier 140 can be connected to the bit line BL of the memory cell array 110. The sense amplifier 140 can sense the voltage of the bit line BL and output the sensed voltage. In some embodiments, the I / O gating circuit 170 may include a data latch for gating input / output data and storing data read from the memory cell array 110, and a write driver for writing data to the memory cell array 110. The data read from the memory cell array 110 can be sensed by the sense amplifier 140 and stored in the I / O gating circuit 170 (e.g., the data latch).

[0039] In some embodiments, data read from the memory cell array 110 (e.g., data stored in a data latch) can be provided to the memory controller via the data I / O buffer 180. Data to be written to the memory cell array 110 is provided from the memory controller to the data I / O buffer 180, and the data provided to the data I / O buffer can be provided to the I / O gating circuit 170.

[0040] Figure 2 This is a diagram used to explain the memory cell array and sense amplifier in a memory device according to some embodiments of the present disclosure.

[0041] refer to Figure 2 The memory cell array 200 may include multiple memory cell blocks CB 11, CB 12, CB13, ..., CB 1n and multiple sense amplifier blocks SA 10, SA 11, SA 12, ..., SA 1n-1, SA 1n (where n is a positive integer). Each sense amplifier block SA 1i corresponds to two adjacent memory cell blocks CB 1i and CB 1i+1 among the multiple memory cell blocks CB 11 to CB 1n, and can be connected to two adjacent memory cell blocks CB 1i and CB 1i+1 (where i is an integer from 1 to (n-1)).

[0042] Each memory cell block CB 1i may include multiple bit lines BL extending in a predetermined direction (e.g., column direction). Multiple memory cells may be connected to each bit line BL. The memory cell block CB 1i may also include multiple word lines extending in different directions (e.g., row direction). Each of the multiple memory cells connected to each bit line BL may be connected to one of the multiple word lines WL.

[0043] In some embodiments, such as Figure 2 As shown, some of the multiple memory cell blocks CB 11 to CB 1n may include complementary bit lines BLB as bit lines. For example, complementary bit lines BLB may be functionally equivalent to bit lines BL, but may be distinguished based on their location and / or connection to the corresponding sense amplifier blocks, as described herein. In this case, memory cell blocks in which bit lines BL are formed are alternately arranged with memory cell blocks in which complementary bit lines BLB are formed, and bit lines BL and complementary bit lines BLB may form complementary bit line pairs. Each sense amplifier block SA 1i may be connected to bit lines BL and complementary bit lines BLB. For example, each sense amplifier block SA 1i may be configured to sense data from bit lines BL and / or complementary bit lines BLB connected to sense amplifier block SA 1i, as described herein.

[0044] Sensing amplifier block SA 1i can be connected to some bit lines BL of a memory cell block CB 1i and some complementary bit lines BLB of an adjacent memory cell block CB 1i+1. In some embodiments, sensing amplifier block SA 1i can be connected to the odd-numbered bit lines BL of the memory cell block CB 1i (e.g., bit lines BL are numbered in a consistent manner, such as from...). Figure 2In the example, the top of memory cell block CB 1i) and the odd-numbered complementary bit lines BLB of memory cell block CB 1i+1 (e.g., the complementary bit lines BLB are numbered in a consistent manner, such as from the top of memory cell block CB 1i+1). In this case, the even-numbered bit lines BL of memory cell block CB 1i can be connected to the adjacent sense amplifier block SA 1i-1, and the even-numbered complementary bit lines BLB of memory cell block CB 1i+1 can be connected to another adjacent sense amplifier block SA 1i+1. Alternatively, in another embodiment, sense amplifier block SA 1i can be connected to the even-numbered bit lines BL of memory cell block CB 1i and the even-numbered complementary bit lines BLB of memory cell block CB 1i+1.

[0045] In some embodiments, the sensing amplifier block SA 10 at the first end can be connected to the bit line BL of a memory cell block CB 11, and the sensing amplifier block SA 1n at the other end can be connected to the complementary bit line BLB of a memory cell block CB1n.

[0046] The sense amplifier block SA 1i may include a plurality of sense amplifiers S / A. Each of the plurality of sense amplifiers S / A may correspond to some bit lines BL of memory cell block CB 1i and may correspond to some complementary bit lines BLB of adjacent memory cell block CB 1i+1. Each sense amplifier S / A may be connected to a corresponding complementary bit line BLB of some complementary bit lines (e.g., odd-numbered complementary bit lines) BLB of memory cell block CB 1i+1 that is different from the corresponding bit line BL in some bit lines (e.g., odd-numbered bit lines) BL of memory cell block CB 1i.

[0047] In some embodiments, a plurality of sense amplifiers S / A may be connected to bit line BL and complementary bit line BLB. The plurality of sense amplifiers S / A included in sense amplifier block SA 1i may be single-ended, for example, each of bit line BL and complementary bit line BLB may be connected to a first node N 1. In some embodiments, the plurality of sense amplifiers S / A located at the end of the memory device may be single-ended. For example, the plurality of sense amplifiers S / A included in the nth sense amplifier block SA 1n may be single-ended, for example, bit line BL or complementary bit line BLB may be connected to the sense amplifier S / A. This disclosure can be a structure applicable to multiple sense amplifiers S / A.

[0048] Figure 3 This is a diagram used to explain the memory cells and sense amplifier circuitry in a memory device according to some embodiments of the present disclosure.

[0049] like Figure 3As shown, each of the bit lines BL0 and BL2 in the cell array block CB1i can be connected to the sense amplifiers S / Ai,0 and S / Ai,1 of the sense amplifier block SA1i, and each of the bit lines BL1 and BL3 can be connected to the sense amplifiers S / Ai-1,0 and S / Ai-1,1 of the sense amplifier block SA1i-1. For ease of illustration, Figure 3 A word line WL and a memory cell MC connected to that word line WL are shown. Although Figure 3 Each memory cell MC is shown to include a transistor and a capacitor, but the structure of the memory cell MC is not limited to this.

[0050] Figure 4 This illustrates the implementation according to an embodiment. Figure 1 A perspective view of the memory device.

[0051] refer to Figures 1 to 3 Memory devices ( Figure 1 The 100 may include a unit chip 410, a peripheral (e.g., peripheral) chip 420, and bonding pads 430 that electrically connect the unit chip 410 and the peripheral chip 420.

[0052] The cell wafer 410 may include multiple memory cell regions 411 to 416. Some of the memory cell regions 411, 413, and 415 may include multiple word lines WL, multiple bit lines BL, and multiple memory cells MC disposed at the intersections of the multiple word lines WL and the multiple bit lines BL. The remaining memory cell regions 412, 414, and 416, other than some of the memory cell regions 411, 413, and 415, may include multiple word lines WL, multiple complementary bit lines BLB, and multiple memory cells MC disposed at the intersections of the multiple word lines WL and the multiple complementary bit lines BLB. The cell wafer 410 and the peripheral wafer 420 may be configured to overlap each other along the third axis D3 and may be coupled to each other.

[0053] The peripheral chip 420 may include a plurality of peripheral (e.g., periphery) regions 431 to 436. Each of the plurality of peripheral regions 431 to 436 may include a sub-word line driver region SWD disposed along a second axis D2, and sense amplifier regions SA1 and SA2 disposed along a first axis D1. The plurality of sub-word line drivers may be disposed in the sub-word line driver region SWD. The plurality of sub-word line drivers may activate a specific word line among a plurality of word lines. The plurality of sense amplifier circuits may be disposed in the sense amplifier regions SA1 and SA2. The plurality of sense amplifier circuits may distinguish the state of memory cells connected to a plurality of bit lines BL or a plurality of complementary bit lines BLB.

[0054] Sensing amplifier regions SA1 and SA2 can be electrically connected to some of the plurality of memory cell regions 411 to 416 via bonding pad 430. In this case, sensing amplifier regions SA1 and SA2 can be connected to bit line BL and complementary bit line BLB included in the plurality of memory cell regions 411 to 416.

[0055] For example, the sense amplifier regions SA1 and SA2 of the first peripheral region 433 can be electrically connected to the bit line BL of the third memory cell region 413 and the complementary bit line BLB of the fourth memory cell region 414, which are adjacent to each other in the second axial direction D2. In some examples, each pair of bit lines BL and complementary bit lines BLB connected to the same sense amplifier can be aligned with each other in the second axial direction D2.

[0056] Figure 5 This illustrates a three-dimensional implementation according to an embodiment. Figure 1 The circuit diagram of the memory cell array.

[0057] refer to Figure 5 The memory cell array 500 may include multiple memory cells MC1 to MC16 stacked along the third axis D3. The multiple memory cells MC1 to MC16 may be connected to multiple bit segments BL11, BL12, BL21, and BL22 arranged along the third axis D3. For example, the first memory cells MC1 to the fourth memory cell MC4 may be connected to the first bit segment BL11, and the fifth memory cells MC5 to the eighth memory cells MC8 may be connected to the second bit segment BL21. Furthermore, the ninth memory cells MC9 to the twelfth memory cells MC12 may be connected to the third bit segment BL12, and the thirteenth memory cells MC13 to the sixteenth memory cells MC16 may be connected to the fourth bit segment BL22.

[0058] The first bit segment BL 11 and the third bit segment BL 12 can be connected to the first strap STRAP1, which is arranged along the first axis D 1. Furthermore, the second bit segment BL 21 and the fourth bit segment BL 22 can be connected to the second strap STRAP2, which is also arranged along the first axis D 1. The number of bit lines connected to the first strap STRAP1 and the second strap STRAP2, and the number of memory cells connected to the bit lines, are merely examples.

[0059] Multiple word lines WL 11, WL 12, WL 13, WL 14, WL 21, WL 22, WL 23 and WL 24 are arranged along the second axis D 2 and can apply voltage to the gates of transistors TR1 to TR16 included in multiple memory cells MC 1 to MC 16.

[0060] Word lines WL 11, WL 12, WL 13, and WL 14 can be connected to transistors TR1 to TR4 connected to the first bit segment BL 11, and transistors TR5 to TR8 connected to the second bit segment BL 21. For example, the first word line WL 11 can be connected to the gate of the first transistor TR1 and the gate of the fifth transistor TR5, and the second word line WL 12 can be connected to the gate of the second transistor TR2 and the gate of the sixth transistor TR6. Furthermore, the third word line WL 13 can be connected to the gate of the third transistor TR3 and the gate of the seventh transistor TR7, and the fourth word line WL 14 can be connected to the gate of the fourth transistor TR4 and the gate of the eighth transistor TR8. Similarly, word lines WL 21, WL 22, WL 23, and WL 24 can be connected to transistors TR9 to TR12 connected to the third bit segment BL 12, and transistors TR13 to TR16 connected to the fourth bit segment BL 22. In some embodiments, in Figure 5 In the examples, the corresponding bit line segment connected to a single corresponding band can correspond to a single bit line BL or a complementary bit line BLB, as elsewhere in this document (e.g. Figure 2 Those described in the text. For example, the first segment BL 11 and the third segment BL 12 connected to the first band STRAP1 can correspond to a single segment (e.g., BL 1) or a complementary segment (e.g., BLB 1). Similarly, the second segment BL 21 and the fourth segment BL 22 connected to the second band STRAP2 can correspond to a single segment (e.g., BL 2) or a complementary segment (e.g., BLB 2).

[0061] The capacitors CS1 to CS16 included in each of the memory cells MC1 to MC16 can be connected to the transistors TR1 to TR16 included in each of the memory cells MC1 to MC16 in a first axis D1 direction, which is a direction perpendicular to the third axis D3 of the stacked plurality of memory cells MC1 to MC16. For example, each of the first capacitors CS1 to the fourth capacitors CS4 can be connected to the first transistors TR1 to the fourth transistors TR4 in the first axis D1 direction, and each of the fifth capacitors CS5 to the eighth capacitors CS8 can be connected to the fifth transistors TR5 to the eighth transistors TR8 in the first axis D1 direction. Furthermore, each of the ninth capacitors CS9 to the twelfth capacitors CS12 can be connected to the ninth transistors TR9 to the twelfth transistors TR12 in the first axis D1 direction, and each of the thirteenth capacitors CS13 to the sixteenth capacitors CS16 can be connected to the thirteenth transistors TR13 to the sixteenth transistors TR16 in the first axis D1 direction.

[0062] When each of the first capacitors CS1 to the sixteenth capacitor CS16 is connected along the first axis D1 to the sixteenth transistor TR16, the chip space efficiency of the memory cell array 500 can be improved. With improved chip space efficiency, the number of memory cells MC1 to MC16 that can be integrated per unit area increases, and therefore the overall memory capacity can be improved.

[0063] Figure 6 This is an exemplary circuit diagram 600 of a sense amplifier circuit in a memory device according to some embodiments of the present disclosure.

[0064] refer to Figure 6 The sense amplifier circuit 610 may include a bit line sense amplifier circuit 620, a local transistor ML1, and a local sense amplifier circuit 630. The sense amplifier circuit 610 may be connected to the control logic circuit 120 to receive control signals, which will be discussed in detail below (it may be directly or indirectly connected, such as through the I / O gate circuit 170 for the control signal CSL).

[0065] One end of the bit line sense amplifier circuit 620 can be connected to a plurality of memory cells MC via bit line BL and complementary bit line BLB. Each of the plurality of memory cells MC may include a transistor TR and a capacitor CS. The other end of the bit line sense amplifier circuit 620 can be electrically connected to a local I / O line LIO. The voltage of the output node OUT of the bit line sense amplifier circuit 620 can be transmitted to the local I / O line LIO via a local transistor ML1. Furthermore, in some embodiments, the bit line sense amplifier circuit 620 may have a single input (single input node) connected to the bit line BL and complementary bit line BLB via bit line transistor MB1 and complementary bit line transistor MB2.

[0066] Bit line transistor MB1 and complementary bit line transistor MB2 can be electrically connected to a first node N1, for example, the input node of the bit line sense amplifier circuit 620. For example, one end of bit line transistor MB1 (e.g., source / drain, also known as S / D) can be connected to the first node N1, and its other end (e.g., S / D) can be connected to bit line BL. One end of complementary bit line transistor MB2 (e.g., S / D) can be connected to the first node N1, and its other end (e.g., S / D) can be connected to complementary bit line BLB. Bit line transistor MB1 can be operated by a first control signal RB (e.g., gated by the first control signal RB). Complementary bit line transistor MB2 can be operated by a second control signal LB (e.g., gated by the second control signal LB).

[0067] For example, the bit line sense amplifier circuit 620 may include a control transistor MB3, a first inverter IN1, a second inverter IN2, a precharge transistor MB4, a first transistor (MD3), and a second transistor (MD4).

[0068] Control transistor MB3 can be connected to bit line BL via bit line transistor MB1. Therefore, bit line BL can be selectively connected to node N2 via control transistor MB3 and bit line transistor MB1. Control transistor MB3 can also be connected to complementary bit line BLB via complementary bit line transistor MB2. Therefore, complementary bit line BLB can be selectively connected to node N2 via control transistor MB3 and complementary bit line transistor MB2.

[0069] The control transistor MB3 can selectively connect the first node N1 to the second node N2 (the control transistor MB3 can be connected between nodes N1 and N2).

[0070] A fifth control signal PTG can be applied to the gate of control transistor MB3. The fifth control signal PTG can be the bias voltage Vb of control transistor MB3 or a supply voltage Va having a higher voltage level than the bias voltage Vb. The bias voltage Vb can be provided by a fourth transistor MD2, which is turned on by a control signal PC based on an active level. The supply voltage Va can be provided by a third transistor MD1, which is turned on by a control signal PR based on an active level. The bias voltage Vb and the supply voltage Va can be generated from separate voltage generators (not shown).

[0071] A first transistor (MD3) may be connected between the second node N2 and ground (e.g., VSS), and a second transistor (MD4) may be connected between the second node N2 and the line supplying the pre-charge voltage Vpc. The first transistor (MD3) may transfer the first voltage VSS to the second node N2 in response to a control signal PE having an active state (e.g., logic high), and the second transistor (MD4) may transfer the pre-charge voltage Vpc to the second node N2 in response to a control signal PI having an active state (e.g., logic high).

[0072] For example, the first transistor (MD3) may be an NMOS transistor and has a drain connected to the second node N2, a source connected to ground (e.g., VSS), and a gate connected to receive the control signal PE. Furthermore, the second transistor (MD4) may be an NMOS transistor and has a drain connected to the line supplying the pre-charge voltage Vpc, a source connected to the second node N2, and a gate connected to receive the control signal PI.

[0073] The first inverter IN1 can be connected to the second node N2. For example, the input of the first inverter IN1 can be connected to the second node N2. In some embodiments, the input of the first inverter IN1 can be connected to the control transistor MB3 and the precharge transistor MB4 through the second node N2. In some embodiments, the first inverter IN1 can be a complementary MOS (CMOS) inverter.

[0074] The second inverter IN2 can be connected to the first inverter IN1 and the output node OUT. For example, the input of the second inverter IN2 can be connected to the output of the first inverter IN1. For example, by inverting the signal twice, it can be logically equivalent to the input of the first inverter IN1 (e.g., unchanged from the input of the first inverter IN1), except that it is amplified. The output of the second inverter IN2 can be connected to the output node OUT of the bit line sense amplifier circuit 620. For example, the outputs of the two inverters IN1 and IN2 in series can be provided as the output of the bit line sense amplifier circuit 620. In some embodiments, the output of the second inverter IN2 can be connected to the precharge transistor MB4. In some embodiments, the second inverter IN2 can also be a complementary MOS (CMOS) inverter. The first inverter IN1 can be connected to the second inverter IN2 to form a data latch that senses and latches the data signal provided by the corresponding memory cell MC on the bit line BL or complementary bit line BLB.

[0075] The precharge transistor MB4 is connected between the second node N2 and the output node OUT of the bit line sense amplifier circuit 620, and can operate in response to the third control signal PS of the precharge transistor MB4. For example, one end of the precharge transistor MB4 can be connected to the second node N2, and the other end of the precharge transistor MB4 can be connected to the output node OUT of the bit line sense amplifier circuit 620. The gate of the precharge transistor MB4 can receive the third control signal PS.

[0076] The bit-line sensing amplifier circuit 620 may further include a capacitive component CSBL of the second node N2. The second node N2 may be connected to a pre-charge transistor MB4. The second node N2 may also be connected to a control transistor MB3. The capacitive component CSBL of the second node N2 can store charge based on the connectivity of the second node N2. Furthermore, the capacitive component CSBL of the second node N2 can transfer the stored charge based on the connectivity of the second node N2.

[0077] The column select line CSL is connected to the gate of the local transistor ML1, and the operation of the local transistor ML1 can be determined based on the potential of the column select line CSL. For example, the local transistor ML1 can be turned on when the column select line CSL is a logic high voltage, and the local transistor ML1 can be turned off when the column select line CSL is a logic low voltage. The column select line CSL can be referred to as the fourth control signal. The local transistor ML1 can transmit data sensed by the bit line sense amplifier circuit 620 to the local I / O line LIO. The voltage of the bit line BL can be changed when the charge is shared by the local I / O line. In some embodiments, when the fourth control signal CSL at an active level (e.g., high level) is applied, the third control signal PS can be maintained at an inactive level (e.g., low level) to prevent the data value sensed by the disclosed bit line sense amplifier circuit 620 from spuriously changing in response to the fourth control signal CSL becoming active.

[0078] The local sense amplifier circuit 630 can amplify the voltage of the local I / O line LIO in response to a sixth control signal PL and transmit it to the global I / O line GIO. The local sense amplifier circuit 630 may include transistors ML2 and ML3 connected in series. Transistor ML2 can be connected to transistor ML3 and the local I / O line control transistor ML4. The LIO line can be applied as a control signal to transistor ML2. Transistor ML3 can be connected to transistor MN2 and ground. The control signal PL can be applied to transistor ML3.

[0079] The local I / O line control transistor ML4 can control the connection between the local I / O line LIO and the global I / O line GIO in response to the seventh control signal PM.

[0080] For example, when the sixth control signal PL is high and the seventh control signal PM is low, the local sense amplifier circuit 630 is activated, and the local I / O line control transistor ML4 can isolate the connection between the local I / O line LIO and the global I / O line GIO.

[0081] For example, when the sixth control signal PL is low and the seventh control signal PM is high, the local sense amplifier circuit 630 is inactive, and the local I / O line control transistor ML4 can provide the connection between the local I / O line LIO and the global I / O line GIO.

[0082] Figure 7 It is used for explanation Figure 6 An exemplary timing diagram 700 of the first operation of the sensing amplifier circuit is shown. Besides the voltage Vtg of the fifth control signal PTG, Figure 7The high (H) and low (L) levels of the signals depicted can correspond to logic high voltages (e.g., VDD) and logic low voltages (e.g., VSS), respectively. As described below, the voltage level of Vtg can be slightly higher than the logic low voltage.

[0083] The first operation OP1 of the sensing amplifier circuit 610 can sequentially execute the pre-charge operation PCG, offset compensation operation OC, charge sharing operation CS, charge transfer operation CT, sensing operation SEN, and recovery operation RST. Data "1" or data "0" can be stored... Figure 7 In the memory unit MC.

[0084] refer to Figure 6 and Figure 7 The sensing amplifier circuit 610 can perform a precharge operation PCG to precharge bit line BL, complementary bit line BLB, first node N1, second node N2 and output node OUT with ground voltage VSS.

[0085] Specifically, during the precharge operation (PCG), the first transistor (MD3) can be turned on based on a control signal PE with an effective level (e.g., a high level). Therefore, the first transistor (MD3) can connect the ground voltage VSS to the second node N2 and precharge the second node N2 to the ground voltage VSS. At this time, the second transistor can be turned off.

[0086] Additionally, during the pre-charge operation PCG period, a fifth control signal PTG at an effective level (e.g., high level) is applied to the gate of control transistor MB3, and control transistor MB3 can be turned on. Therefore, the first node N1 can be pre-charged with ground voltage VSS by connecting the second node N2 to the first transistor (MD3) connected to ground voltage VSS.

[0087] During the precharge operation PCG period, bit line transistor MB1 and complementary bit line transistor MB2 can be turned on based on the first control signal RB and the second control signal LB at an effective level (e.g., high level). Therefore, bit line BL and complementary bit line BLB can be precharged with ground voltage VSS through the first node N1. The capacitive component CBL present in bit line BL is thus precharged with ground voltage VSS.

[0088] During the precharge operation PCG period, the precharge transistor MB4 can be turned on based on the third control signal PS at an active level (e.g., high level). Therefore, the output node OUT can also be precharged to ground voltage VSS.

[0089] refer to Figure 6 and Figure 7 The sense amplifier circuit can perform offset compensation operation OC. The sense amplifier circuit can perform offset compensation operation OC by connecting bit line BL and the second node N2 through control transistor MB3 to store the offset information of the first control transistor MB3.

[0090] Specifically, during the offset compensation operation (OC), the second transistor (MD4) can be turned on based on a control signal PI with an active level (e.g., high level), and the first transistor (MD3) can be turned off based on a control signal PE with an inactive level. Therefore, the precharge voltage Vpc can be precharged to the second node N2 via the second transistor (MD4). The precharge voltage Vpc can be higher than the supply voltage Vinta (reference). Figure 8 ).

[0091] The control transistor MB3, to which the fifth control signal PTG is applied, can be in a weakly conducting state. The fourth transistor MD2 can be turned on based on the effective level (e.g., high level) control signal PC, and the third transistor MD1 can be turned off based on the ineffective level (e.g., high level) control signal PR. Therefore, a bias voltage Vb can be applied to the gate of the control transistor MB3 as the control signal PTG. The bias voltage Vb can be a voltage between a high level used as the effective level and a low level used as the ineffective level, and can be higher than the threshold voltage Vth of the complementary bit line transistor MB2. However, the bias voltage Vb can be lower than the supply voltage VDD. In some embodiments, the bias voltage Vb can be set by considering charge transfer in the charge transfer operation CT described below.

[0092] Therefore, current can flow from the second node N2, which is pre-charged, to the first node N1 (which is at ground voltage VSS during the start of the offset compensation operation OC), and the voltage of the first node N1 can increase. As the voltage of the first node N1 increases, it can reach a level that turns off the control transistor MB3. Specifically, if the difference between the voltage of the first node N1 (connected to the source of the control transistor MB3) and the voltage Vtg of the fifth control signal PTG is less than the threshold voltage Vth of the control transistor MB3, then the control transistor MB3 is turned off. Therefore, the voltage of the first node N1 increases until the voltage at the first node N1 equals Vtg - Vth. MB3 (where Vth) MB3 This refers to the threshold voltage Vth of the control transistor MB3. Furthermore, during the offset compensation operation OC, the bit line BL is connected to the first node N1 via transistor MB1 (which is turned on due to the active state (e.g., high) of RB) and is charged to the same value as the first node N1 (Vtg-Vth). MB3Therefore, during the offset compensation operation OC, the voltages of the first node N1 and bit line BL are increased and set to a value (Vtg-Vth) corresponding to the threshold voltage of the control transistor MB3 (and inherently including information about the threshold voltage of the control transistor MB3). MB3 Therefore, control transistor MB3 can be turned on until the difference between the voltage at the first node N1 and the voltage Vtg applied to the gate of the first control transistor MB3 reaches the threshold voltage of the first control transistor MB3. During offset compensation operation OC, bit line BL, which is only connected to one end of the bit line (already electrically connected to node N1 only via transistor MB1), can be in the form of an electrical stub. Therefore, offset compensation operation OC can provide and store a voltage corresponding to the threshold voltage of the first control transistor MB3 on bit line BL.

[0093] During the offset compensation operation OC period, complementary bit line transistor MB2 and precharge transistor MB4 can be turned off based on the second control signal LB and the third control signal PS being at an invalid level (e.g., low level). Bit line transistor MB1 can be kept on based on the first control signal RB being at an active level (e.g., high level). In some examples, the disclosed input sense amplifier can operate only one of the bit line BL or complementary bit line BLB to perform sensing, which can reduce power consumption. For example, both bit line BL and complementary bit line BLB can be selectively electrically connected to the first node N1 (e.g., the input node of bit line sense amplifier circuit 620) in a single-ended configuration, and therefore only one of them can be sensed at a time. Thus, one of the first control signal RB or the second control signal LB can be changed to an invalid level (e.g., low level) to prepare for the sensing operation SEN. In this example, during the offset compensation operation OC period, the first control signal RB is maintained at an active level (connecting bit line BL to node N1) and the second control signal LB is changed to an invalid level (keeping the complementary bit line BLB disconnected from node N1).

[0094] Therefore, the precharge voltage applied to the second node N2 can be connected to the bit line BL via the control transistor MB3, the first node N1, and the bit line transistor MB1, such that the voltage applied to the bit line BL corresponds to a precharge voltage that at least reduces the threshold voltage of the control transistor MB3.

[0095] The precharge voltage Vpc can be connected to the bit line BL until the difference between the voltage PTG and the voltages of the first node N1 and the second node N2 reaches the threshold voltage Vth of the control transistor MB3. It should be understood that the bit line BL will not be charged to the full precharge voltage Vpc due to the voltage drop applied to the precharge voltage Vpc signal from node N2 to the bit line BL (such as the voltage drop provided by the threshold voltage VthMB3 of the control transistor MB3), and references herein to connecting the precharge voltage Vpc to the bit line BL will be understood to include such a voltage drop (i.e., such a connection does not necessarily result in the full voltage being transmitted).

[0096] The voltage of bit line BL can be controlled by the threshold voltage Vth of transistor MB3. MB3 Confirmed. When bit line BL does not require a threshold voltage Vth for controlling transistor MB3. MB3 When performing compensation, the offset compensation operation OC can be omitted.

[0097] refer to Figure 6 and 7 The sense amplifier circuit can perform a charge-sharing operation CS, which shares charge between the bit line BL and the memory cell MC. At this time, the word line WL i connected to the gate of the memory cell MC can be activated, thereby turning on the transistor TR of the memory cell MC to connect the memory cell capacitor CS to the bit line BL.

[0098] During the charge-sharing operation CS period, bit line transistor MB1 can be turned off based on a first control signal RB at an invalid level (e.g., low level). Since bit line transistor MB1 is off, bit line BL can be electrically isolated from the first node N1 and the second node N2.

[0099] Because the transistor TR of the memory cell MC is turned on by the activation of the word line WL i connected to the gate of the memory cell MC, charge can be shared between the capacitor CS of the memory cell MC and the capacitive component CBL of the bit line. When the data "1" is stored in the memory cell MC, charge (e.g., electrons) can be transferred from the bit line BL to the capacitor CS, and the voltage of the bit line BL can be slightly increased to above Vtg-Vth. MB3 When the data "0" is stored in the memory cell MC, charge (e.g., electrons) can be transferred from the capacitor CS to the bit line BL, and the voltage of the bit line BL can be slightly reduced to below Vtg-Vth. MB3 .

[0100] The data "1" is stored and the bit line BL is precharged to a voltage closer to ground voltage VSS during the offset compensation operation OC period (e.g., precharged to Vtg-Vth in this example). MB3In the case of precharging bit line BL with an intermediate voltage between high and low levels during the precharge operation PCG, the voltage of bit line BL can be increased by a larger amount. Therefore, the voltage value of the control signal PTG applied to the control transistor MB3 can be set (during the offset compensation operation OC period) to provide a precharge voltage Vtg close to ground voltage to bit line BL. Vtg can be higher than the expected threshold voltage Vth of the control transistor MB3. MB3 A voltage with a small predetermined offset (e.g., in the range of 0.1 to 0.3 volts) (i.e., Vtg = expected Vth) MB3 +Voffset (where Voffset = 0.1V to 0.3V)). The expected threshold voltage VthMB3 can be the threshold voltage of the control transistor MB3 (i.e., expected from the design of memory device 100), but can differ from the actual threshold voltage Vth of the control transistor MB3 due to typical variations that can occur during the manufacture of memory device 100. MB3 Therefore, the voltage of bit line BL can be charged to Vtg-VthMB3 during the offset compensation operation OC period. The voltage of bit line BL can therefore have a voltage corresponding to Voffset (e.g., corresponding to 0.1 V to 0.3 V, as can be changed by any difference between the expected and actual threshold voltage of control transistor MB3), and thus the voltage of bit line BL can have a voltage close to ground voltage VSS.

[0101] During the charge-sharing operation CS period, the control signal PI applied to the gate of the second transistor can remain at an active level (e.g., high level), and therefore the second transistor can remain on. Thus, the pre-charge voltage Vpc can be continuously applied to the second node N2 during the charge-sharing operation CS period, and the second node N2 can be pre-charged to the pre-charge voltage Vpc.

[0102] Furthermore, since bit line transistor MB1 and complementary bit line transistor MB2 are turned off, the voltage at node N1 is floating and remains at the voltage obtained during offset compensation operation OC, which is high enough to keep MB3 in the off state (e.g., node N1 remains at Vtg-Vth). MB3 Therefore, no current flows through the control transistor MB3.

[0103] refer to Figure 6 and Figure 7 The sensing amplifier circuit can perform a charge transfer operation CT that connects bit line BL and the second node N2 to transfer charge between bit line BL and the second node N2.

[0104] During the charge transfer operation CT, the second transistor can be turned off based on the control signal PI, which is at an invalid level (e.g., low level). Therefore, the pre-charge voltage Vpc can be applied to the second node N2 without passing through the second transistor. However, the second node N2 will at least initially begin the charge transfer operation CT with the pre-charge voltage Vpc (the second node N2 has already been pre-charged to voltage Vpc during the charge sharing operation CS), and therefore the voltage of the second node N2 can be greater than the voltage of the first node N1 at the start of the charge transfer operation CT.

[0105] During the charge transfer operation CT, bit line transistor MB1 can be turned on based on a first control signal RB at an effective level (e.g., high). Therefore, the first node N1 can be electrically connected to bit line BL. Vtg continues to be applied to the gate of control transistor MB3. As discussed in more detail below, during the charge transfer operation CT, node N2 will remain substantially at Vpc when data "1" has been stored, and will drop to a voltage substantially at or near Vtg when data "0" has been stored. Vpc can correspond to (be interpreted as) logic "high" and Vtg can correspond to (be interpreted as) logic "low" (it should be understood that these voltages do not need to be the same as VDD and VSS).

[0106] When the data "1" has been stored by the memory cell MC, the voltage on the bit line BL increases slightly during the charge-sharing operation CS (e.g., from Vtg to Vth). MB3 Slightly increase to Vtg-Vth MB3 +delta i Therefore, when node N1 is connected to bit line BL during charge transfer operation CT (due to bit line transistor MB1 being turned on), node N1 also increases slightly (e.g., from Vtg to Vth). MB3 Slightly increase to Vtg-Vth MB3 +delta i In this case, because the voltage difference between the gate of control transistor MB3 and the voltage at node N1 is less than the threshold voltage Vth of control transistor MB3. MB3 Therefore, the control transistor MB3 remains off, and node N2 continues to maintain its floating state and its pre-charge voltage Vpc (or essentially the same - because a small current leakage may occur, and the voltage of node N2 may drop slightly during the charge transfer operation CT).

[0107] When the data "0" has been stored by the memory cell MC, the voltage on the bit line BL decreases slightly during the charge-sharing operation CS (e.g., from Vtg to Vth). MB3 Slightly reduced to Vtg-Vth MB3 -deltad Therefore, when node N1 is connected to bit line BL during charge transfer operation CT (due to bit line transistor MB1 being turned on), node N1 also decreases slightly (e.g., from Vtg to Vth). MB3 Slightly reduced to Vtg-Vth MB3 -delta d In this case, because the voltage difference between the gate of control transistor MB3 and the voltage at node N1 is greater than the threshold voltage Vth of control transistor MB3. MB3 Therefore, control transistor MB3 is turned on and node N2 is connected to N1. With control transistor MB3 on, the voltage of N2 drops to approximately the voltage of node N1 and bit line BL (dropped to approximately Vtg-Vth). MB3 -delta d Specifically, nodes N2, N1, and bit line BL are connected together as a single node via a charge-sharing operation CS when data "0" has been stored, and thus share charge to equalize their voltage levels—this can continue until nodes N2, N1, and bit line BL reach the same voltage level or the charge transfer operation CT terminates and the sensing operation SEN begins. Because the capacitance of bit line BL is substantially greater than that of node N2 (and node N1), the higher voltage Vpc on node N2 has minimal impact on the voltage of bit line BL, while the lower voltage of bit line BL significantly affects the voltage on node N2 to reduce the voltage of N2 to close to Vtg - Vth. MB3 delta d ’ The value of . Since the capacitance component CSBL of the second node N2 is less than the capacitance component CBL of the bit line BL, the voltage drop of the second node N2 can be less than the voltage increase of the bit line BL.

[0108] In the case of data "0", due to the threshold voltage Vth used in the offset compensation operation OC. MB3 A defined voltage is applied to charge the bit line BL (e.g., to Vtg-Vth). MB3 Therefore, it can be ensured that a threshold voltage Vth slightly higher than that of the control transistor MB3 is provided. MB3 (Vth) MB3The gate-to-source voltage of the control transistor MB3 (i.e., the difference between the gate voltage Vtg of the control transistor MB3 and the source voltage of MB3 (at node N1)) is charged to ensure that the control transistor MB3 is turned on, thereby allowing the drain at node N2 to reduce its voltage to a logic low level. Similarly, in the case of data "1", this charging of the bit line BL also ensures that the control transistor MB3 remains off, because the gate-to-source voltage of the control transistor MB3 does provide a voltage slightly less than the threshold voltage Vth of the control transistor MB3. MB3 (Vth) MB3 (That is, the difference between the gate voltage Vtg of control transistor MB3 and the source voltage of MB3 (at node N1).) It should be understood that process changes may affect the actual threshold voltage Vth. MB3 Changes (from the design threshold voltage and / or from device to device), but such changes are naturally addressed by operation OP1 (e.g., by pre-charging the bit line BL to Vtg-Vth during offset compensation operation OC). MB3 ).

[0109] refer to Figure 6 and Figure 7 The sensing amplifier circuit can perform the sensing operation SEN of the voltage at the output node OUT.

[0110] During the SEN (sensing) operation cycle, a power supply voltage is provided to the first inverter IN1 and the second inverter IN2 to sense and amplify the voltage at node N2. In the case of data "1", node N2 has a voltage corresponding to logic high (the voltage of Vpc), and therefore the first inverter IN1 outputs logic low to the second inverter IN2, and the second inverter IN2 outputs logic high at the output node OUTPUT. In the case of data "0", node N2 has a voltage corresponding to logic low (e.g., a voltage below Vtg, such as approximately Vtg-VthMB3), and therefore the first inverter IN1 outputs logic high to the second inverter IN2, and the second inverter IN2 outputs logic low at the output node OUTPUT.

[0111] refer to Figure 6 and 7 The sensing amplifier circuit can perform the recovery operation RST to restore the voltage of the memory cell MC.

[0112] During the recovery operation RST, the control transistor MB3 receives a fifth control signal PTG with an effective level (e.g., high level), causing the control transistor MB3 to be fully turned on.

[0113] During the recovery operation RST, the precharge transistor MB4 can be turned on based on the third control signal PS at an effective level (e.g., high level), connecting inverters IN1 and IN2 as a cross-coupled latch. Therefore, the output node OUTPUT (reflecting the data value of node N2 sensed during the sensing operation SEN) is connected to the bit line via control transistors MB3 and MB1, and thus the sensed data is restored to the memory cell MC (capacitor CS is connected to the output node OUTPUT via the bit line BL to restore the corresponding charge in capacitor CS (based on the logic level of the output node OUTPUT), to represent data "1" or data "0" as appropriate).

[0114] Furthermore, during the recovery operation RST, the control transistor ML1 is logic high due to the control signal CSL, and the data sensed by the sense amplifier circuit 620 (the logic value represented on the output node OUTPUT) is transmitted to the local I / O line LIO and the local sense amplifier circuit 630. The sensed data can also be transmitted to the global I / O line GIO for output (e.g., to an interface to the memory device 100 for transmission to a device outside the memory device 100).

[0115] In some embodiments, when data "0" is stored in memory cell MC, control signals PTG, LB, RB, PS, and WL can have the same characteristics as the reference signal. Figure 7 The control signals PTG, LB, RB, PS, and WL have the same timing sequence. Therefore, it can be referred to as... Figure 7 The pre-charge operation PC and offset compensation operation OC are performed as described.

[0116] During the charge-sharing operation CS, the data "0" is stored in the capacitor of the memory cell MC, and thus the voltage of the bit line BL can be reduced through charge sharing between the memory cell MC and the bit line BL.

[0117] During the charge transfer operation CT, charge (e.g., electrons) can be transferred from the bit line BL to the second node N2, and therefore the voltage of the second node N2 can decrease. In this case, since the voltage of the bit line BL is close to the ground voltage, it is related to... Figure 7 In contrast, the voltage at the second node N2 may be significantly lower. Additionally, charge (e.g., electrons) can be transferred from the bit line BL to the second node N2, and therefore the voltage at the bit line BL can be increased.

[0118] However, since the capacitance component of the second node N2 is greater than the capacitance component CBL of the bit line BL, the voltage drop of the second node N2 can be less than the voltage increase of the bit line BL.

[0119] During the sensing operation SEN, the voltage at output node OUT can be reduced to ground voltage VSS through the operation of the first inverter IN1 and the second inverter IN2. The sensing amplifier circuit can sense that data with a low level (i.e., "0") is stored in memory cell MC by sensing the logic level of the second node N2 (as described above).

[0120] Because of the relatively large supply voltage difference at the second node N2 via the charge-sharing operation CS and / or the charge-transfer operation CT, accurate sensing can be performed. In this case, the supply voltage difference can be amplified by the ratio of the capacitive component CBL of the bit line BL to the capacitive component CSBL of the second node N2.

[0121] During the recovery operation RST, the precharge transistor MB4 can be turned on based on a third control signal PS at an effective level (e.g., high level). Furthermore, charge (e.g., electrons) can be transferred from the output node OUT to the capacitor CS of the memory cell MC via the bit line transistor MB1, the first node N1, the control transistor MB3, the second node N2, and the precharge transistor MB4. Therefore, the voltage at the output node OUT can rise, and the data "0" can be recovered from the memory cell MC.

[0122] Figure 8 This is an exemplary circuit diagram 800 illustrating a sense amplifier circuit in a memory device according to some embodiments. For ease of explanation, the main explanation will be related to... Figure 6 The differences in content.

[0123] refer to Figure 8 Each of the first inverter IN1 and the second inverter IN2 in the bit line sense amplifier circuit 620 may include a p-type transistor and an n-type transistor. For example, each of the first inverter IN1 and the second inverter IN2 may be a complementary MOS (CMOS) configuration of NOT gates or inverters.

[0124] Therefore, in some embodiments, the first inverter IN1 may include a first p-type transistor MP1 connected to the internal power supply Vinta of the bit line sense amplifier circuit 620, and a first n-type transistor MN1 connected to the ground power supply, such as Figure 8 As shown. The second inverter IN 2 may include a second p-type transistor MP2 connected to the internal power supply Vinta and the output node OUT of the bit line sense amplifier circuit 620, and a second n-type transistor MN 2 connected to the ground power supply, as shown.

[0125] The first p-type transistor MP1, the first n-type transistor MN1, the second p-type transistor MP2, and the second n-type transistor MN2 can perform a sensing operation SEN in the first operation OP1. For example, data transmitted via a bit line can be amplified.

[0126] In one example, high-level (e.g., "1") data can be stored in memory cell MC and amplified in sensing operation SEN. Therefore, the first n-type transistor MN1 can be turned on and the first p-type transistor MP1 can be turned off by the voltage at the second node N2. The voltage output from the first inverter IN1 can be reduced to ground voltage VSS by the turned-on first n-type transistor MN1. Furthermore, the second n-type transistor MN2 can be turned off and the second p-type transistor MP2 can be turned on by the output of the first inverter IN1 (responding to the voltage at the second node N2, and more specifically, responding to the output of the first inverter IN1 forming the input of the second inverter IN2 (the inverted voltage of the second node N2)). The voltage at output node OUT can be increased to the supply voltage VDD by the turned-on second p-type transistor MP2. Therefore, the sensing amplifier circuit can sense high-level (e.g., "1") data stored in memory cell MC. However, Figure 8 Only a sense amplifier circuit in a memory device according to some embodiments is shown, but this disclosure is not limited thereto.

[0127] refer to Figure 6 and 7 The sensing amplifier circuit can perform a recovery operation RST to restore the voltage of the memory cell MC at the end of the first operation OP1.

[0128] During the recovery operation RST period, the precharge transistor MB4 and control transistor MB3 can be turned on based on the third control signal PS and the fifth control signal PTG at an effective level (e.g., high level). Charge (e.g., electrons) can be transferred from the capacitor CS of the memory cell MC to the output node OUT through the bit line transistor MB1, the first node N1, the control transistor MB3, the second node N2, and the precharge transistor MB4. Therefore, the voltage of the output node OUT drops, and the data "1" can be recovered in the memory cell MC.

[0129] The sensing amplifier circuit according to this disclosure is a single-ended type where each of the bit line BL and the complementary bit line BLB is connected to a first node N1, and the single-ended sensing amplifier circuit can operate differently depending on the type ("0" or "1") of the data stored in the memory cell MC.

[0130] For example, if all the data stored in each of the multiple memory cells connected to the bit line BL is "0", then a single-ended sense amplifier circuit does not need to increase the voltage of the bit line BL.

[0131] Furthermore, when data "0" is stored in one half of the memory cells connected to bit line BL and data "1" is stored in the remaining memory cells, the voltage of bit line BL, where data "1" is stored, can be increased only. Additionally, the disclosed single-ended input sense amplifier circuit can be used during sensing operations and, more specifically, when performing operations related to... Figure 7 All operations described are connected to only one of the bit lines BL or complementary bit lines BLB (note, regarding...). Figure 7 The described sensing operation can alternatively keep LB at low throughout the entire operation (including during PCG).

[0132] In contrast, a differential sense amplifier circuit, where the bit line and complementary bit line are connected to the two ends of the sense amplifier circuit, can amplify the voltage difference between the bit line BL and the complementary bit line BLB during data reading from the memory cell. The differential sense amplifier circuit can increase the voltage of one line and decrease the voltage of the other line to amplify the voltage difference between the bit line and the complementary bit line.

[0133] Therefore, single-ended sense amplifier circuits can be driven with lower power than differential sense amplifier circuits.

[0134] Figure 9 It is used for explanation Figure 6 An exemplary timing diagram of the second operation OP2 of the sense amplifier circuit is shown. Figure 9 As shown and discussed above, the second operation OP2 can occur between two repetitions of the first operation OP1. Figures 10 to 13 This is a circuit diagram of the sense amplifier circuit that performs the second operation.

[0135] refer to Figure 9 The second operation OP2 of the sensing amplifier circuit 610 can be performed between repeated first operations OP1. For example, the second operation OP2 of the sensing amplifier circuit 610 can be performed between the recovery (e.g., last) operation RST of the first operation OP1 and the precharge (e.g., first) operation PCG of repeated first operations OP1. For example, the second operation OP2 can be a read operation for reading data stored in the memory cell MC.

[0136] refer to Figure 9 and Figure 10An invalid level (e.g., low level) first control signal RB can be applied to bit line transistor MB1. Based on the invalid level of the first control signal RB, bit line transistor MB1 can be turned off. Therefore, the electrical connection between bit line BL and control transistor MB3 can be broken. Although Figure 9 The diagram shows that the first control signal RB applied to bit line transistor MB1 is switched to an invalid level, but in some embodiments, the second control signal LB applied to complementary bit line transistor MB2 can be switched to an invalid level.

[0137] refer to Figure 9 and Figure 11 A third control signal PS at an invalid level (e.g., low level) can be applied to the precharge transistor MB4. Based on the invalid level of the third control signal PS, the precharge transistor MB4 can be turned off.

[0138] refer to Figure 9 and Figure 12 A fourth control signal CSL at an effective level (e.g., high level) can be applied to the local transistor ML1. Based on the effective level of the fourth control signal CSL, the local transistor ML1 can be turned on. Therefore, the local transistor ML1 can transmit the data sensed by the bit line sense amplifier circuit 620 to the local I / O line LIO.

[0139] While the local transistor ML1 is on, the precharge transistor MB4 and the bit line transistor MB1 can be off. Therefore, while the local transistor ML1 is transmitting data from the output node OUT to the local I / O line LIO, the data value of the bit line sense amplifier circuit 620 can remain unchanged.

[0140] In some embodiments, the capacitance of the capacitive component CSBL of the bit line sensing amplifier circuit 620 can be relatively small. Therefore, the sensed data value of the bit line sensing amplifier circuit 620 is highly likely to change when the local transistor ML1 is turned on. By keeping the precharge transistor MB4 and the bit line transistor MB1 off while the local transistor ML1 is on, the accuracy of the operation of the bit line sensing amplifier circuit 620 can be improved. Furthermore, changes in the value of the data stored in the bit line BL can be prevented.

[0141] refer to Figure 9 and Figure 13 A fourth control signal CSL, at an invalid level (e.g., low), can be applied to local transistor ML1. A third control signal PS, at an active level (e.g., high), can be applied to precharge transistor MB4. A first control signal RB, at an active level (e.g., high), can be applied to bit-line transistor MB1. Therefore, the sense amplifier circuit 610 can perform the first operation again.

[0142] In some embodiments, the invalid fourth control signal CSL, the valid third control signal PS, and the valid (e.g., high) first control signal RB can be applied sequentially. In another embodiment, the invalid fourth control signal CSL and the valid third control signal PS can be applied simultaneously, and then the valid (e.g., high) first control signal RB can be applied. In yet another embodiment, the invalid fourth control signal CSL, the valid third control signal PS, and the valid (e.g., high) first control signal RB can be applied simultaneously.

[0143] Refer again Figure 9 After a first time interval following the application of the invalid first control signal RB to bit-line transistor MB1, the valid first control signal RB can be applied. Switching the first control signal RB from valid to invalid and back to valid during the second operation OP2 is referred to as the first pulse P1. After a second time interval following the application of the invalid third control signal PS to pre-charge transistor MB4, the valid third control signal PS can be applied. Switching the third control signal PS from valid to invalid and back to valid during the second operation OP2 is referred to as the second pulse P2. After a third time interval following the application of the valid fourth control signal CSL, the invalid fourth control signal CSL can be applied to local transistor ML1. Switching the fourth control signal CSL from invalid to valid and back to invalid during the second operation OP2 is referred to as the third pulse P3.

[0144] In some embodiments, the first and second times may be greater than the third time. For example, in some embodiments, when a fourth control signal CSL at an active level (e.g., high level) is applied, the third control signal PS may remain at an inactive level (e.g., low level) to prevent the data value sensed by the disclosed bit-line sense amplifier circuit 620 from spuriously changing in response to the fourth control signal CSL becoming active. Therefore, the third time (during which the fourth control signal CSL at an active level is applied) may be a subset of the second time (during which the third control signal PS remains inactive). In some embodiments, the first and second times may be the same. In some embodiments, the first time may be greater than the second time. In some embodiments, the second time may be greater than the first time.

[0145] Therefore, in some embodiments, the width (e.g., duration) (e.g., first time) of the first pulse P1 can be greater than or equal to the width (e.g., second time) of the second pulse P2. In some embodiments, the width (e.g., third time) of the third pulse P3 can be less than the width of the first pulse P1 and the second pulse P2. For example, the first, second, and third times and / or the timing of these pulses can be controlled by control logic circuitry 120, such as... Figure 1 As described in the example.

[0146] Figure 14 It is used for explanation Figure 6 An exemplary timing diagram of the third operation OP3 of the sense amplifier circuit is shown. For example, the third operation OP3 of the sense amplifier circuit 610 can be performed between the recovery (e.g., last) operation RST of the first operation OP1 and the precharge (e.g., first) operation PCG of repeating the first operation OP1. For example, the third operation OP3 can be a read operation for reading data stored in the memory cell MC. For ease of explanation, the main focus will be on... Figures 9 to 13 The differences in content.

[0147] refer to Figure 14 An invalid level (e.g., low level) first control signal RB can be applied to bit line transistor MB1. Based on the invalid level first control signal RB, bit line transistor MB1 can be turned off.

[0148] Next, an invalid level (e.g., low level) third control signal PS can be applied to the precharge transistor MB4. Based on the invalid level of the third control signal PS, the precharge transistor MB4 can be turned off.

[0149] Next, a fourth control signal CSL at an effective level (e.g., high level) can be applied to the local transistor ML1. Based on the effective level of the fourth control signal CSL, the local transistor ML1 can be turned on.

[0150] Next, an invalid level (e.g., low level) fourth control signal CSL can be applied to local transistor ML1. Based on the invalid level of the fourth control signal CSL, local transistor ML1 can be turned off. For example, the third operation OP3 of the sense amplifier circuit 610 can apply the invalid level (e.g., low level) fourth control signal CSL to local transistor ML1 while bit line transistor MB1 and precharge transistor MB4 are turned off. Therefore, based on the invalid level of the fourth control signal CSL, local transistor ML1 can be turned off.

[0151] Next, a fourth control signal CSL at an effective level (e.g., high level) can be applied to the local transistor ML1. Based on the effective level of the fourth control signal CSL, the local transistor ML1 can be turned on. For example, the third operation OP3 of the sense amplifier circuit 610 can apply the fourth control signal CSL at an effective level (e.g., high level) to the local transistor ML1 while the bit line transistor MB1 and the precharge transistor MB4 are off. Therefore, based on the effective level of the fourth control signal CSL, the local transistor ML1 can be turned on. Thus, the operation of turning on the local transistor ML1 can be performed twice.

[0152] Finally, an invalid level (e.g., low level) fourth control signal CSL is applied to local transistor ML1, and local transistor ML1 can be turned off. An valid level (e.g., high level) third control signal PS is applied to precharge transistor MB4, and precharge transistor MB4 can be turned on. An valid level (e.g., high level) first control signal RB is applied to bit line transistor MB1, and bit line transistor MB1 can be turned on. Therefore, the sense amplifier circuit 610 can perform the first operation again.

[0153] As in Figure 14 In the example, in the third operation OP3, the first pulse P1 may include switching the first control signal RB from an active level to an inactive level and then back to an active level, and the second pulse P2 may include switching the third control signal PS from an active level to an inactive level and then back to an active level. Although Figure 14 The illustration shows the fourth control signal CSL repeating a fourth pulse P4 twice during the third operation OP3, switching from an invalid level to an active level and then back to an invalid level. However, this disclosure is not limited thereto. The fourth control signal CSL may include two or more fourth pulses P4.

[0154] Figure 15 It is used for explanation Figure 6 An exemplary timing diagram of the fourth operation of the sense amplifier circuit shown.

[0155] refer to Figure 15 The fourth operation OP4 of the sense amplifier circuit 610 can be performed between repeated first operations OP1. For example, the fourth operation OP4 of the sense amplifier circuit 610 can be performed between the recovery (e.g., last) operation RST of the first operation OP1 and the precharge (e.g., first) operation PCG of repeated first operations OP1. For example, the fourth operation OP4 can be a read operation for reading data stored in the memory cell MC.

[0156] For example, the fourth operation OP4 can also be the operation of the second operation OP2 repeated multiple times between the recovery operation RST and the precharge operation PCG of the repeated first operation OP1.

[0157] refer to Figure 15 In the fourth operation OP4, switching the fourth control signal CSL from an invalid level to an active level and from an active level to an invalid level is referred to as the fifth pulse P5. For example, the fourth pulse P4 of the third operation OP3 may include two or more pulses that cumulatively form a subset of the second pulse P2, while in this example, the fifth pulse P5 of the fourth operation OP4 may include two or more pulses that correspond to two or more of the second pulses P2 respectively.

[0158] In some embodiments, the width (e.g., duration) of the first pulse P1 may be greater than or equal to the width of the second pulse P2. In some embodiments, the width of the fifth pulse P5 may be less than the widths of the first pulse P1 and the second pulse P2. For example, in some embodiments, the third control signal PS may maintain an invalid level (e.g., low level) while the fourth control signal CSL is applied at an active level (e.g., high level), thereby preventing the data value sensed by the bit line sense amplifier circuit 620 from spuriously changing in response to a change in the fourth control signal CSL. Therefore, the duration of each fifth pulse P5 (during which the fourth control signal CSL is applied at an active level) may be a subset of the duration of each corresponding second pulse P2 (during which the third control signal PS remains invalid). In some examples, the timing of these pulses may be controlled by the control logic circuit 120, such as... Figure 1 As described in the example.

[0159] Figure 16 It is used for explanation Figure 6 An exemplary timing diagram of the fifth operation OP5 of the sense amplifier circuit is shown. For example, the fifth operation OP5 of the sense amplifier circuit 610 can be performed between the recovery (e.g., last) operation RST of the first operation OP1 and the pre-charge (e.g., first) operation PCG of repeating the first operation OP1. For ease of explanation, the main explanation will be related to... Figures 9 to 14 The differences in content.

[0160] The sensing amplifier circuit 610 can operate differently depending on the frequency level of the fourth control signal CSL. For example, if the frequency of the fourth control signal CSL is high (e.g., above a threshold frequency, such as 50Hz, 100Hz, 500Hz, 1kHz, 100kHz, 1MHz, 10MHz, or 100MHz), then the bit line transistor MB1 and the precharge transistor MB4 can remain open between the recovery operation RST and the precharge operation PCG of the first operation OP1. If the frequency of the fourth control signal CSL is low, then the bit line transistor MB1 and the precharge transistor MB4 can be closed between the recovery operation RST and the precharge operation PCG of the first operation OP1.

[0161] For example, refer to Figure 16 During the fifth operation OP5, the switching of the fourth control signal Hf CSL, which has a high frequency, from an invalid level to an active level and from an active level to an invalid level is referred to as the sixth pulse P6. During the fifth operation OP5, the switching of the fourth control signal Lf CSL, which has a low frequency, from an invalid level to an active level and from an active level to an invalid level is referred to as the seventh pulse P7.

[0162] For example, when the frequency of the fourth control signal CSL is high, the width (e.g., duration) of the sixth pulse P6 can be much smaller than the width of the first pulse P1 or the second pulse P2. For example, because the duration of shared charge with the local I / O line LIO is very short, the voltage of the bit line BL is unlikely to fluctuate. Therefore, when the frequency of the fourth control signal CSL is high, the bit line transistor MB1 and the precharge transistor MB4 may not be turned off between the recovery operation RST and the precharge operation PCG of the first operation OP1. In some embodiments, when the frequency of the fourth control signal CSL is high, the fifth operation OP5 may differ from the second operation OP2 and the third operation OP3.

[0163] In another example, when the frequency of the fourth control signal CSL is low (e.g., below a threshold frequency, such as 50Hz, 100Hz, 500Hz, 1kHz, 100kHz, 1MHz, 10MHz, or 100MHz), the width (e.g., duration) of the seventh pulse P7 can be similar to the width of the first pulse P1 or the second pulse P2. For example, the voltage of the bit line BL may fluctuate while the charge is shared with the local I / O line LIO. Therefore, when the frequency of the fourth control signal CSL is low, the bit line transistor MB1 and the precharge transistor MB4 can be turned off between the recovery operation RST and the precharge operation PCG of the first operation OP1. In some embodiments, when the frequency of the fourth control signal CSL is low, the fifth operation OP5 can be the same as the second operations OP2 through the fourth operations OP4.

[0164] For example, in some embodiments, the third control signal PS can remain at an invalid level while the fourth control signal CSL, which is at an active level, is applied, thereby preventing the data value sensed by the bit line sense amplifier circuit 620 from spuriously changing in response to a change in the fourth control signal CSL. Therefore, the cumulative duration of the sixth pulse P6 and the duration of the seventh pulse P7 can each be a subset of the duration of the second pulse P2.

[0165] In some embodiments, the sensing amplifier circuit 610 may operate selectively in the fifth operation OP5 according to the frequency magnitude of the fourth control signal CSL.

[0166] Figure 17 This is a graph showing the sensing data of the internal power supply of a sensing amplifier circuit in a memory device according to some embodiments.

[0167] refer to Figure 17 The sensing amplifier circuit 610 can perform the first operation OP1 and the second operation OP2. Figure 17 The graph illustrates the changes in data for bit line BL, second node N2, and output node OUT based on the first operation OP1 and the second operation OP2. For example, the sensed data for output node OUT can change as the internal power supply Vinta of the bit line sense amplifier circuit 620 changes.

[0168] In the first operation OP1, the bit line sensing amplifier circuit 620 can sense the data transmitted via the bit line BL. Even when the internal power supply Vinta is low, the sensing amplifier circuit 610 according to this disclosure can perform the sensing operation.

[0169] Furthermore, by keeping the pre-charge transistor MB4 and the bit line transistor MB1 off while the local transistor ML1 is on, data changes due to the operation of the local transistor ML1 can be prevented. For example, data changes in the bit line sense amplifier circuit 620 and the bit line BL can be prevented. Therefore, the accuracy of the operation of the sense amplifier circuit 610 can be improved. During the period when the second operation OP2 is performed in the sense amplifier circuit 610, there is almost no data change in the bit line BL and the second node N2.

[0170] Figure 18 This is a graph illustrating sensing data from a sensing amplifier circuit in a memory device according to some embodiments. (Reference) Figure 18 The sensing amplifier circuit 610 can perform the first operation OP1 and the sixth operation OP6.

[0171] The sixth operation OP6 involves turning the local transistor ML1 on and off while the precharge transistor MB4 and bit line transistor MB1 are kept in the on state. During the execution of the sixth operation OP6 by the sense amplifier circuit 610, the data values ​​of the output node OUT and the second node N2 may change due to data interference caused by the on-state local transistor ML1. Furthermore, the charge amount of the capacitive component CSBL of the bit line sense amplifier circuit 620 may also change. The data value stored in the bit line BL may also change. Due to the changes in the data values ​​of the sense amplifier circuit 610 and the bit line, the accuracy of the sense amplifier circuit 610 may decrease when the sixth operation OP6 is executed. Therefore, the accuracy of the sense amplifier circuit 610 can be improved when it is operated according to the second through fifth operations.

[0172] Figure 19 This is a block diagram illustrating a computer device including a memory device according to some embodiments.

[0173] refer to Figure 19 The computing device 2000 includes a processor 2010, a memory 2020, a memory controller 2030, a storage device 2040, a communication interface 2050, and a bus 2060. The computing device 2000 may also include other general-purpose components.

[0174] The processor 2010 controls the overall operation of each component of the computing device 2000. The processor 2010 can be implemented as at least one of various processing units such as a central processing unit (CPU), an application processor (AP), and a graphics processing unit (GPU).

[0175] The memory 2020 stores various types of data and instructions. The memory 2020 can be implemented as a reference. Figures 1 to 16 The memory device is explained. The memory controller 2030 controls the transfer of data or instructions to and from the memory 2020. In some embodiments, the memory controller 2030 may be provided as a separate chip from the processor 2010. In some embodiments, the memory controller 2030 may be provided as an internal configuration of the processor 2010.

[0176] Storage device 2040 stores programs and data non-transitory. In some embodiments, storage device 2040 may be implemented as non-volatile memory. Communication interface 2050 supports wired and wireless Internet communication of computing device 2000. Furthermore, communication interface 2050 may support various communication methods other than Internet communication. Bus 2060 provides communication functionality between components of computing device 2000. Depending on the communication protocol between components, bus 2060 may include at least one type of bus.

[0177] In summarizing the detailed description, those skilled in the art will understand that many changes and modifications can be made to the preferred embodiments without substantially departing from the principles of this disclosure. Therefore, the preferred embodiments of this disclosure are used in a general and descriptive sense only and not for limiting purposes.

Claims

1. A memory device, comprising: The first memory cell is connected to the first bit line; The second memory cell is connected to the second bit line; A first transistor is connected to the first bit line, and the first transistor is configured to transmit a first data signal based on first data stored in the first memory cell to the input node of the bit line sense amplifier. A second transistor, connected to the second bit line, is configured to transmit a second data signal based on second data stored in the second memory cell to the input node of the bit line sense amplifier; The bit line sense amplifier is connected to the input node and is configured to amplify one of the first data signal or the second data signal provided to the input node to output a first amplified signal. A local transistor is connected to the output node of the bit-line sense amplifier; and A local sensing amplifier, connected to the local transistor, is configured to amplify the first amplified signal to output a second amplified signal.

2. The memory device according to claim 1, in, The bit-line sensing amplifier includes a pre-charge transistor connected to the local transistor and controls amplification of either the first data signal or the second data signal.

3. The memory device according to claim 2, wherein: The bit line sensing amplifier further includes a first inverter having a first inverter input and a first inverter output, and a second inverter having a second inverter input and a second inverter output. The first inverter input is configured to receive either the first data signal or the second data signal. The output of the first inverter is connected to the input of the second inverter, and The output of the second inverter is connected to the precharge transistor and the local transistor.

4. The memory device according to claim 2, It also includes control logic circuitry configured to output the first amplified signal to the local sense amplifier, which includes turning on the local transistor and turning off the precharge transistor.

5. The memory device according to claim 4, in, Outputting the first amplified signal to the local sensing amplifier includes the control logic circuit turning on the local transistor for a first duration and turning off the precharge transistor for a second duration, and The first duration is shorter than the second duration.

6. The memory device according to claim 5, in, Outputting the first amplified signal to the local sensing amplifier includes the control logic circuit being turned on for a third duration, and Wherein, the first duration is shorter than the third duration.

7. The memory device according to claim 2, in, The bit-line sensing amplifier further includes a control transistor connected to the first transistor and the second transistor, and connected to the input of the first inverter.

8. The memory device according to claim 2, further comprising control logic circuitry, in, In response to a first control signal for controlling the local transistor having a frequency higher than a threshold frequency, the control logic circuit turns on the local transistor and turns off the precharge transistor. In response to the frequency of the first control signal used to control the local transistor being lower than the threshold frequency, the local transistor is independently turned on.

9. The memory device of claim 1, further comprising control logic circuitry configured to selectively turn on the first transistor and the second transistor.

10. A memory device, comprising: A first memory cell is connected to the first bit line and configured to store first data; A first transistor includes a first terminal connected to the first bit line, the first transistor being configured to transmit a first data signal based on stored first data to a second terminal; A bit-line sense amplifier is connected to the first transistor, and the bit-line sense amplifier is configured to amplify the first data signal to output the first amplified signal to the output node via a pre-charged transistor. A local transistor includes a first local terminal connected to the output node of the bit line sense amplifier and a second local terminal connected to the local sense amplifier, the local sense amplifier being configured to amplify the first amplified signal to output a second amplified signal; as well as The control logic circuit is configured to control the transmission of the first amplified signal to the local sense amplifier by controlling the local transistor to be in an on state and controlling the precharge transistor to be in an off state.

11. The memory device according to claim 10, in, The control logic circuit turns on the local transistor multiple times while keeping the precharge transistor in the off state.

12. The memory device according to claim 10, in, The control logic circuit's transmission of the first amplified signal to the local sense amplifier includes the control logic circuit maintaining the first transistor in the off state and turning on the local transistor to transmit the first amplified signal at the output of the bit line sense amplifier to the local sense amplifier.

13. The memory device according to claim 12, in, The control logic circuit's transmission of the first amplified signal to the local sensing amplifier includes the control logic circuit turning off the precharge transistor and the first transistor.

14. The memory device of claim 10, further comprising: A second memory cell, connected to a second bit line and configured to store second data, and a second transistor, selectively connecting the second bit line to the bit line sensing amplifier.

15. The memory device according to claim 14, in, The control logic circuit is configured to selectively turn on the first transistor and the second transistor.

16. The memory device according to claim 10, in, In response to a first control signal for controlling the local transistor having a frequency higher than a threshold frequency, the control logic circuit turns on the local transistor and turns off the precharge transistor. In response to the frequency of the first control signal used to control the local transistor being lower than the threshold frequency, the local transistor is independently turned on.

17. The memory device according to claim 10, in, The bit line sense amplifier further includes a control transistor connected to the first transistor and the bit line sense amplifier to provide the stored first data to the bit line sense amplifier.

18. A method for driving a memory device, the memory device comprising a first memory cell connected to a first bit line and storing data, a first transistor connected to the first bit line, a bit line sense amplifier connected to the first transistor and including a precharge transistor, and a local transistor connected to the bit line sense amplifier and a local sense amplifier, the method comprising: When the first transistor is turned on, a first data signal based on the stored data is provided to the bit line sense amplifier; The bit-line sensing amplifier amplifies the first data signal to obtain a first amplified signal; When the precharge transistor is turned on, the first amplified signal is provided to the output node of the bit line sense amplifier; as well as When the local transistor is in the on state and the precharge transistor is in the off state, the output of the bit line sense amplifier is provided to the local sense amplifier to provide the first amplified signal from the output node of the bit line sense amplifier to the local sense amplifier.

19. The method for driving the memory device according to claim 18, in, When the first amplified signal is provided to the local sense amplifier from the output node of the bit line sense amplifier, the first transistor is in a cutoff state, while the local transistor is in a conduction state.

20. The method for driving the memory device according to claim 18, in, When the first amplified signal is provided to the local sense amplifier from the output node of the bit line sense amplifier, the local sense amplifier is turned on multiple times while the precharge transistor remains off.

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