Decoding logic derivation method, failed memory cell location method, and related devices

Abstract

The embodiment of the application discloses a decoding logic derivation method, a failed storage particle positioning method and related equipment, comprising: collecting all first error physical addresses generated by testing a same failed storage particle in a first physical slot to form a first error physical address set; collecting all second error physical addresses generated by testing the same failed storage particle in a second physical slot to form a second error physical address set; searching the first error physical address set and the second error physical address set to find k address bits, or a logical combination thereof, which is always a same value in binary logic values of all the first error physical addresses and is always an opposite value of the same value in binary logic values of all the second error physical addresses; and generating a Boolean function of the k address bits or the logical combination thereof as decoding logic. The application can automatically restore hidden physical address decoding logic and realize automatic, accurate and efficient positioning of the physical position of the failed storage particle.

Description

Technical Field

[0001] This application relates to the field of memory testing, and in particular to a method for deducing the error physical address decoding logic of a memory chip, a method for locating faulty memory chips, testing equipment, and computer program products. Background Technology

[0002] As computing systems increasingly demand higher memory capacity and performance, storage system topologies are becoming more complex. Multi-channel, multi-socket, high-density memory modules have become standard in servers, workstations, and high-performance computing platforms. In such systems, the central processing unit (CPU) maps the system's physical address space to specific storage particles distributed across multiple physical slots through its integrated memory controller (IMC). This mapping process typically involves complex address decoding logic, which may include address interleaving, chip select combinations, etc., to achieve bandwidth optimization and load balancing.

[0003] Storage modules typically contain multiple storage chips distributed across different physical slots. When the system detects a failure in a storage chip, it reports an error physical address. However, this address is usually a logical address and does not directly correspond to the physical slot or storage chip location. Since the address mapping logic can vary significantly across different platforms (CPU, motherboard, BIOS combination) and is typically not disclosed to the user, at the system level, it's impossible to directly determine which specific storage chip is faulty from the list of error physical addresses of the failed chips. Existing methods for locating faulty chips rely on manual analysis, which is inefficient and prone to errors. Summary of the Invention

[0004] This application provides a decoding logic derivation method, a failed memory chip location method, a testing device, and a computer program product to automatically restore the hidden physical address decoding logic and achieve automatic, accurate, and efficient location of the physical location of failed memory chips.

[0005] In a first aspect, embodiments of this application provide a decoding logic derivation method, applied to decoding the erroneous physical address of a failed storage particle in a storage module having multiple storage particles, the method comprising:

[0006] Collect all first-error physical addresses generated when the same failed memory chip is tested in the first physical slot, forming a first-error physical address set;

[0007] Collect all second-error physical addresses generated when the same failed memory chip is tested in a second physical slot, forming a set of second-error physical addresses;

[0008] Search the first set of erroneous physical addresses and the second set of erroneous physical addresses to find k address bits, where the binary logical value of the k address bits or their logical combination is always the same value in all the first set of erroneous physical addresses, and the binary logical value of the same value is always the inverse value in all the second set of erroneous physical addresses.

[0009] A Boolean function is generated to form the k address bits or their logical combinations, which serves as the decoding logic for mapping the erroneous physical address of the failed memory chip to the physical slot identifier.

[0010] Where k is a natural number, and 1 ≤ k ≤ the number of bits in the address.

[0011] By implementing the embodiments of this application, the system can automatically find address bit combinations with stable logical differences from the set of error addresses generated when the same failed memory chip is tested in different physical slots, and deduce the decoding logic. Without manual intervention or a preset mapping table, automatic mapping from system error addresses to physical slots can be achieved, which significantly improves the efficiency and accuracy of the location.

[0012] In at least one possible implementation, the step of searching the first set of erroneous physical addresses and the second set of erroneous physical addresses to find k address bits specifically includes:

[0013] Let k=1;

[0014] Search the first set of erroneous physical addresses and the second set of erroneous physical addresses to find one address bit. This address bit has the same binary logical value in all the first set of erroneous physical addresses, and has the same inverse value in all the second set of erroneous physical addresses.

[0015] If the specified address bit is not found, the following search steps are performed iteratively until the specified k address bits are found, or the value of k exceeds a preset limit:

[0016] Increment the value of k by 1;

[0017] Continue searching the first set of erroneous physical addresses and the second set of erroneous physical addresses to find k address bits. The logical combination of these k address bits always has the same binary logical value in all the first set of erroneous physical addresses, and always has the inverse of the same binary logical value in all the second set of erroneous physical addresses.

[0018] Implementing the embodiments of this application employs an iterative search strategy from simple to complex, prioritizing the search for differences in individual address bits. If no such differences exist, the complexity of address bit combinations is gradually increased, ensuring both search efficiency and the accuracy and minimization of the decoding logic.

[0019] In at least one possible implementation, after finding the k address bits, the method further includes:

[0020] After replacing the same failed memory chip with another failed memory chip, repeat the above search steps until k address bits are found. If the same k address bits are found, the search results are verified to be correct.

[0021] By implementing the embodiments of this application and performing cross-validation by replacing failed memory chips, errors caused by randomness or chip characteristics can be eliminated, thereby improving the universality and reliability of the decoding logic.

[0022] In at least one possible implementation, if the k address bits are not found to be the same, the search result is verified as incorrect, and the following steps are performed:

[0023] After replacing the other failed memory chip, let the value of k start from the previous search result plus 1, and repeat the above search steps until k address bits are found.

[0024] By implementing the embodiments of this application, the search strategy is automatically adjusted when verification fails, avoiding getting trapped in local optima and improving the robustness of the method under complex or abnormal conditions.

[0025] In at least one possible implementation, in the Boolean function that generates the k address bits or their logical combinations:

[0026] The k address bits are determined to be the k address bits found for the first time; or

[0027] The k address bits are determined as the result of having the fewest address bits and the largest highest-order bit index among multiple found k address bits.

[0028] Implementing the embodiments of this application provides a variety of decoding logic optimization strategies, allowing users to select the simplest or most stable logic combination based on actual needs, thereby improving decoding efficiency and system compatibility.

[0029] In at least one possible implementation, the logical combination includes at least one of the following operations: AND, OR, NOT, XOR.

[0030] In at least one possible implementation, when k=1, the logical combination is the value of the one address bit or its logical NOT; and / or, when k≥2, the logical combination includes an XOR operation.

[0031] Implementing the embodiments of this application supports a variety of logical operation combinations, adapts to the address mapping rules of different storage architectures, and improves the applicability of the method.

[0032] In at least one possible implementation, the Boolean function is set to disjunctive normal form or conjunctive normal form.

[0033] Implementing the embodiments of this application uses standardized Boolean expressions, which facilitates integration into existing test systems or hardware logic, thereby improving system compatibility and maintainability.

[0034] Secondly, embodiments of this application provide a method for locating failed memory chips, applied to the location of failed memory chips in a storage module having multiple memory chips, the method comprising:

[0035] In response to the detection of a storage chip failure in the system, the erroneous physical address of the failed storage chip is converted into the corresponding faulty physical slot identifier according to the preset decoding logic;

[0036] Map the physical slot identifier to the physical location identifier of the failed memory chip;

[0037] The preset decoding logic is a Boolean function generated according to the method described in the first aspect.

[0038] By implementing the embodiments of this application, based on the derived decoding logic, automatic, fast, and accurate mapping from system error addresses to physical slots can be achieved, greatly improving the efficiency and accuracy of failure location.

[0039] In at least one possible implementation, mapping the physical slot identifier to the physical location identifier of the failed memory chip specifically includes:

[0040] Based on the column address bits in the erroneous physical address and the bit width configuration of the storage particle, the physical location identifier corresponding to the failed storage particle on the storage module is determined.

[0041] By implementing the embodiments of this application and combining column address and particle width information, the specific particle location can be further precisely located, supporting particle-level replacement and repair.

[0042] Thirdly, embodiments of this application provide a testing device including a processor and a memory, the memory being coupled to the processor, the memory being used to store computer program code, the computer program code including computer instructions, and when the processor reads the computer instructions from the memory, causing the processor to perform the steps of the method as described in the first or second aspect.

[0043] Fourthly, embodiments of this application provide a computer program product comprising: computer program code, which, when executed on a computer, causes the computer to perform the steps described in the first or second aspect.

[0044] The beneficial effects of this application are:

[0045] This application embodiment collects the set of erroneous addresses of the same failed memory chip in different physical slots, automatically searches for address bit combinations with stable logical differences, and generates corresponding Boolean functions as decoding logic. This achieves automatic and accurate mapping from erroneous physical addresses to physical slot locations, enabling automated, precise, and efficient location of failed memory chips. This results in rapid and accurate fault location without manual intervention, strong adaptability, and high location efficiency. Especially in large-scale storage testing or production environments, it enables rapid and accurate location of failed memory chips, significantly improving testing efficiency, reducing maintenance costs, and ensuring product quality. Attached Figure Description

[0046] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0047] Figure 1 This is a flowchart illustrating the decoding logic derivation method according to an embodiment of this application.

[0048] Figure 2 This is a flowchart illustrating the iterative search step in the decoding logic derivation method of this application embodiment.

[0049] Figure 3 This is a flowchart illustrating the method for locating failed storage particles according to an embodiment of this application.

[0050] Figure 4 This is a schematic diagram of the structure of the test equipment according to an embodiment of this application. Detailed Implementation

[0051] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions of this application will be described in detail below with reference to the accompanying drawings in the embodiments of this application. Obviously, the described embodiments are only some, not all, of the embodiments of this application. Unless otherwise specified, the embodiments and features in the embodiments of this application can be combined with each other. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0052] It should be noted that: throughout the accompanying drawings, the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions; in the description of this application, the terms "center," "longitudinal," "lateral," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on the scope of protection of this application; in the description of this application, "first," "second," etc., are only used to distinguish each other, and do not indicate their degree of importance or order, etc.

[0053] In the description of this application, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linkage" should be interpreted broadly. For example, they can refer to fixed connections, movable connections, or detachable connections; they can refer to mechanical connections or electrical connections; they can refer to direct connections or indirect connections through an intermediate medium; they can refer to the internal communication between two components, etc. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0054] In production testing and fault analysis of storage modules with multiple storage chips, when a storage chip fails, a list of erroneous physical addresses is typically reported at the system level. However, this address is a logical address from the controller's perspective and does not directly correspond to the physical slot or storage chip location. Especially in complex multi-channel, multi-slot storage systems, after complex address mapping (including Rank interleaving, Channel selection, and chip selection bits), the direct correspondence between the system-reported erroneous physical addresses and physical chips is hidden. Different platforms (CPU, motherboard, BIOS combination) may have drastically different address mapping logic, which is usually not disclosed to the user.

[0055] Existing memory chip testing methods typically rely on manual analysis, empirical rules, or pre-defined address mapping tables to locate failed memory chips. In advanced technologies such as multi-chip packaging and 3D stacking, address decoding logic must consider factors such as signal integrity, thermal distribution, and power consumption equalization, inevitably resulting in complex combinational logic. Existing location methods are inefficient, error-prone, and difficult to adapt to different memory architectures or configuration changes. Especially in large-scale memory testing or production environments, quickly and accurately locating failed memory chips is crucial for improving testing efficiency, reducing repair costs, and ensuring product quality.

[0056] In view of this, embodiments of this application provide a decoding logic derivation method and a failed memory chip location method, applied to the decoding of erroneous physical addresses of failed memory chips in a storage module with multiple memory chips. The aim is to automatically discover the logical pattern mapping the erroneous physical address of the failed memory chip obtained from the controller to the physical slot identifier, construct decoding logic, and automatically decode the physical slot location of the failed memory chip from the erroneous physical address. This enables automatic, accurate, and efficient location of the failed memory chip, thereby achieving fast and accurate fault location. Please refer to... Figure 1 The decoding logic derivation method includes:

[0057] In step S100, all first erroneous physical addresses generated when the same failed memory chip is tested in the first physical slot are collected to form a first erroneous physical address set;

[0058] In step S200, all second erroneous physical addresses generated when the same failed memory chip is tested in the second physical slot are collected to form a set of second erroneous physical addresses;

[0059] In step S300, the first set of erroneous physical addresses and the second set of erroneous physical addresses are searched to find k address bits, wherein the binary logical values ​​of the k address bits or their logical combinations are always the same value in all the first set of erroneous physical addresses, and the binary logical values ​​of the same value are always the inverse value in all the second set of erroneous physical addresses.

[0060] In step S400, a Boolean function of the k address bits or their logical combination is generated as the decoding logic for mapping the erroneous physical address of the failed memory chip to the physical slot identifier.

[0061] Where k is a natural number, and 1 ≤ k ≤ the number of bits in the address.

[0062] By implementing the embodiments of this application, the system can automatically find address bit combinations with stable logical differences from the set of error addresses generated when the same failed memory chip is tested in different physical slots, and deduce the decoding logic. Without manual intervention or a preset mapping table, automatic mapping from system error addresses to physical slots can be achieved, which significantly improves the efficiency and accuracy of the location.

[0063] A Boolean function is a logical rule whose input and output are both "yes / no" (1 / 0). It precisely describes how the physical address of a system determines the selection of a hardware unit (such as a memory slot): it is a mapping that takes multiple bits of the system's physical address as input and outputs a single logical value, and its output uniquely determines the physical memory slot accessed by that physical address.

[0064] Boolean functions may manifest as simple single-bit mappings or as combinations of multiple bits formed by logical operations (such as AND, OR, NOT, XOR). The adaptive iterative search algorithm of this application can automatically discover and determine the specific form of the function, deriving the address decoding logic from the bits of the system physical address.

[0065] In at least one possible implementation, the step of searching the first set of erroneous physical addresses and the second set of erroneous physical addresses to find k address bits specifically includes:

[0066] In step S301, let k=1;

[0067] In step S302, the first set of erroneous physical addresses and the second set of erroneous physical addresses are searched to find one address bit. The binary logical value of this address bit is always the same for all the first set of erroneous physical addresses, and the binary logical value of this address bit is always the inverse of the same value for all the second set of erroneous physical addresses.

[0068] In step S303, if the 1 address bit is not found, the following search steps are performed iteratively until the k address bits are found, or the value of k exceeds a preset limit:

[0069] In step S3031, the value of k is incremented by 1;

[0070] In step S3032, the search continues on the first set of erroneous physical addresses and the second set of erroneous physical addresses to find k address bits. The logical combination of these k address bits is always the same value in the binary logical value of all the first erroneous physical addresses, and is always the inverse of the same value in the binary logical value of all the second erroneous physical addresses.

[0071] The adaptive combinatorial search algorithm implemented in this application adopts an iterative search strategy that progresses from simple to complex, with increasing complexity:

[0072] Define the search space:

[0073] For a combination size k, the algorithm's search objective is to find a Boolean function F from all possible combinations of k address bits that operates on these k bits and can completely distinguish between two sets of erroneous addresses.

[0074] Perform iterative search:

[0075] The algorithm starts executing from k = 1.

[0076] When k = 1, the search space is all single-bit address bits. At this time, the "combination" degenerates into single-bit address bits, and the Boolean function F is usually in the form of the identity function (f(addr) = bit_i) or its inverse (f(addr) = ¬bit_i).

[0077] If no solution is found when k=1, then let k=k+1 (i.e., k=2) and enter the multi-bit combination search stage. At this time, the Boolean function F can be expanded to the logical combination of these bits, such as XOR, AND, etc.

[0078] Increment and Termination:

[0079] The value of k is increased successively, and an exhaustive or heuristic search is performed in the search space defined by each value of k until a Boolean function F that satisfies the distinguishing condition is found, or the preset limit k_max (such as 5) is reached and then the process terminates.

[0080] When k=1, the algorithm searches in the solution space of "all single-bit functions". This corresponds to the simplest and most direct address mapping rule, i.e., selection is controlled by a single address line. This stage is the efficient entry point of the algorithm, capable of quickly solving a large number of simple mapping scenarios.

[0081] When k ≥ 2, the algorithm enters the solution space of the 'multi-bit combination function'. This corresponds to the complex mapping rules used in reality to optimize performance, such as address interleaving (often manifested as an XOR function). The algorithm explores more complex and refined mapping possibilities by incrementing the value of k.

[0082] This search strategy, progressing from simple to complex, prioritizes finding differences in individual address bits. If none are found, it gradually increases the complexity of address bit combinations. This approach ensures both search efficiency and the accuracy and simplicity of the decoding logic. It guarantees that the algorithm attempts to solve the problem with minimal initial computational overhead, only investing resources to explore more complex hypotheses when necessary, thus achieving an optimal balance between efficiency and completeness.

[0083] In at least one possible implementation, after finding the k address bits, the method further includes:

[0084] In step S500, after replacing the same failed memory chip with another failed memory chip, the above search steps are repeated until k address bits are found. If the same k address bits are found, the search results are verified to be correct.

[0085] By implementing the embodiments of this application and performing cross-validation by replacing failed memory chips, errors caused by randomness or chip characteristics can be eliminated, thereby improving the universality and reliability of the decoding logic.

[0086] In at least one possible implementation, if the k address bits are not found to be the same, the search result is verified as incorrect, and the following steps are performed:

[0087] In step S600, after replacing the other failed memory chip again, the value of k is incremented by 1 from the previous search result, and the above search steps are repeated until k address bits are found.

[0088] Implementing the embodiments of this application automatically adjusts the search strategy when verification fails, avoiding getting trapped in local optima and improving the robustness of the search algorithm under complex or abnormal conditions. An upper limit can be set for k (e.g., k≤5) to avoid combinatorial explosion.

[0089] In another implementation, to improve the reliability of the decoding logic, after finding k address bits, the above steps can be repeated with another failed memory chip for verification. If the two results are consistent, the decoding logic is confirmed to be correct; if they are inconsistent, the value of k is adjusted and the search is repeated.

[0090] In at least one possible implementation, in the Boolean function that generates the k address bits or their logical combinations:

[0091] The k address bits are determined to be the k address bits found for the first time; or

[0092] The k address bits are determined as the result of having the fewest address bits and the largest highest-order bit index among multiple found k address bits.

[0093] The candidate logic combination with the larger highest-order bit index refers to a combination in which the largest bit sequence number of the address bits is greater than the largest bit sequence number of other candidate combinations. In system address decoding, high-order address lines (such as A31-A20) are typically used for coarse-grained selection (such as channel, slot, rank), while low-order address lines are used for fine-grained on-chip addressing (such as column address, burst order). Therefore, decoding logic used to distinguish physical slots is more likely to fall on high-order address lines. Prioritizing the checking of high-order combinations can lead to faster convergence to the true rules and reduce invalid searches.

[0094] Implementing the embodiments of this application provides a variety of decoding logic optimization strategies, allowing users to select the simplest or most stable logic combination based on actual needs, thereby improving decoding efficiency and system compatibility.

[0095] In at least one possible implementation, the logical combination includes at least one of the following operations: AND, OR, NOT, and XOR.

[0096] In at least one possible implementation, when k=1, the logical combination is the value of the 1 address bit or its logical NOT; and / or, when k≥2, the logical combination includes an XOR operation.

[0097] By implementing the embodiments of this application, the search process can support a combination of various logical operations such as AND, OR, NOT, and XOR, adapting to the address mapping rules of different storage architectures and improving the applicability of the method.

[0098] In advanced system design, the XOR operation is the most frequently used nonlinear mapping function due to its superior performance in implementing address interleaving and balancing access load. Furthermore, mapping rules may also manifest as other basic logical operations (such as AND, OR, NOT) and their combinations. The iterative search algorithm provided in this application can automatically identify and derive all these forms of Boolean functions.

[0099] In at least one possible implementation, the Boolean function is set to disjunctive normal form (DNF) or conjunctive normal form (CNF).

[0100] In implementing the embodiments of this application, the decoding logic adopts a standardized Boolean function expression form (DNF or CNF), which on the one hand can characterize any complex decoding logic; on the other hand, the standard output form greatly facilitates the readability verification, hardware simulation and integration with subsequent diagnostic tools of the rule, and is easy to integrate into existing test systems or hardware decoder logic, thereby improving system compatibility and maintainability.

[0101] For example, an XOR function, A17 XOR A15, can be equivalently expressed in Disjunctive Normal Form (DNF) as: (A17&!A15) | (!A17&A15). This DNF form directly corresponds to multiplexers in hardware description languages, realizing the transformation from fault data to understandable and reusable knowledge.

[0102] Please refer to Figure 3 Based on the decoding logic derived above, this application also provides a method for locating failed storage particles, applied to the location of failed storage particles in a storage module with multiple storage particles. The method includes:

[0103] In step S700, in response to detecting a memory chip failure, the erroneous physical address of the failed memory chip is converted into the corresponding faulty physical slot identifier according to a preset decoding logic;

[0104] In step S800, the physical slot identifier is mapped to the physical location identifier of the failed storage chip in the storage module;

[0105] The preset decoding logic is a Boolean function generated according to the decoding logic derivation method of the aforementioned embodiment.

[0106] By implementing the embodiments of this application, based on the derived decoding logic, an automatic, fast, and accurate mapping from the system error address to the physical location is achieved, which greatly improves the efficiency and accuracy of locating failed memory chips and significantly improves testing and maintenance efficiency.

[0107] In at least one possible implementation, mapping the physical slot identifier to the corresponding physical location identifier of the failed storage chip in the storage module specifically includes:

[0108] Based on the column address bits in the erroneous physical address and the bit width configuration of the storage particle, the physical location identifier (such as LPDDR number, particle row and column position) corresponding to the failed storage particle on the storage module is determined.

[0109] By implementing the embodiments of this application and combining column address and particle width information, the specific particle location can be further precisely located, supporting particle-level replacement and repair.

[0110] The following uses LPDDR (Low Power Double Data Rate SDRAM) as an example to exemplify the process of decoding logic derivation and faulty memory particle location in the embodiments of this application.

[0111] In production testing and fault analysis of LPDDR multi-chip systems, when stress testing software in a UEFI environment detects a memory error, it can only report the system physical address. This address is from the perspective of the CPU memory controller, and after complex address mapping (including Rank interleaving, Channel selection, chip selection bits, etc.), the direct correspondence between it and the physical chip is hidden. This leads to the following problems:

[0112] Unable to automatically locate failed storage chips:

[0113] When test engineers receive a list of incorrect physical addresses, they cannot directly determine which specific physical particle is faulty. This is the root cause of inefficiency in the production and maintenance processes.

[0114] Relying on inefficient manual troubleshooting methods:

[0115] The only current solution is the "replacement method": replace the suspected faulty chips one by one with known good chips, and repeat the lengthy stress test until the source of the fault is located. This method is time-consuming, labor-intensive, costly, and highly dependent on the experience of engineers.

[0116] Decoding information is missing or inaccurate:

[0117] Motherboard design (especially address / command line swapping caused by high-speed signal cabling) and memory controller configuration can disrupt the default address mapping, rendering the standard address decoding table ineffective. There is a lack of automated methods to rebuild or verify this specific board-specific mapping.

[0118] This example aims to address the technical challenge of directly and automatically locating failed physical memory chips in multi-chip LPDDR systems based on the physical addresses in UEFI test reports. It provides a method that can automatically and accurately parse the mapping relationship between system physical addresses and specific LPDDR chip physical identifiers from UEFI test error data, enabling fast and precise identification of failed memory chips. Key features include:

[0119] Automated address mapping resolution:

[0120] This paper provides a method that does not rely on preset knowledge and can automatically learn and establish the correspondence between "system physical address" and "physical particle select bit (Chip Select)".

[0121] Achieve granular-level fault location:

[0122] Based on the parsed mapping relationship, any erroneous physical address in the test report is translated into a specific failed storage particle identifier (such as Chip ID, CS#) in real time and accurately, and an intuitive location result is output.

[0123] Improve production and maintenance efficiency:

[0124] It completely replaces the inefficient manual replacement troubleshooting method, reducing fault location from the "hour / day" level to the "minute" level, significantly reducing testing and maintenance costs, and improving the speed and accuracy of product yield analysis.

[0125] To achieve the above objectives, this example provides an automated decoding logic derivation and faulty memory chip location method based on dual-socket (Socket) comparative analysis and iterative bit pattern search. Its core innovation lies in using two test sockets (Socket 0, Socket 1) with known physical locations as a "training ground." By analyzing the differences in error address patterns generated by the same faulty memory chip in two different physical socket locations, the decoding logic for selecting the critical address bits (i.e., the Chip Select bit) for LPDDR chips is automatically deduced.

[0126] The decoding logic derivation process is described in detail below.

[0127] Step S101: Obtain the target failed LPDDR chip.

[0128] In a UEFI (Unified Extensible Firmware Interface) environment, stress tests are performed on a batch of LPDDR chips (which may come from faulty modules or boards) to identify at least one target failed LPDDR chip with a known test result of "FAIL" and record its original test data (including a list of faulty physical addresses).

[0129] Step S102: Dual Socket Comparison Test and Data Collection.

[0130] The same failed LPDDR chip was inserted sequentially into two independent LPDDR slots (denoted as Socket A and Socket B) on the test platform, each with a known different physical address mapping, and the same stress test was run separately on each. This step is a critical prerequisite, ensuring that the failure characteristics of the LPDDR chip itself remain unchanged, and only its location in the system address space changes.

[0131] The system collects all first-error physical addresses generated during testing under Socket A, forming a set of first-error physical addresses {Addr_A}.

[0132] The system collects all second-error physical addresses generated during testing under Socket B, forming a set of second-error physical addresses {Addr_B}.

[0133] The difference in address patterns between these two sets directly contains the address decoding information that distinguishes these two sockets (i.e., distinguishes the physical location of the LPDDR chips).

[0134] Step S103: Address decoding logic derivation based on difference analysis (core algorithm).

[0135] The goal of this study is to perform automated binary bit pattern analysis on {Addr_A} and {Addr_B}, and to find a set of combination patterns of address bits that can distinguish the two sets {Addr_A} and {Addr_B} with 100% accuracy.

[0136] S1031: Binary conversion.

[0137] Convert all erroneous physical addresses to fixed-width binary strings.

[0138] S1032: Single-bit distinguishable search.

[0139] This is suitable for scenarios where selection is directly controlled by a single address line: Iterate through all address bits, searching for a specific bit i such that all bits in {Addr_A} are always 0 (or 1), while all bits in {Addr_B} are always 1 (or 0). That is:

[0140] For each address bit i = 0 to N-1, check if the following conditions are met:

[0141] (The bit_i of all {Addr_A} is 0 and the bit_i of all {Addr_B} is 1)

[0142] or

[0143] (The bit_i of all {Addr_A} is 1 and the bit_i of all {Addr_B} is 0)

[0144] If found, address bit i is one of the key granular selection bits, and f_decode = bit_i is the decoding logic. The process jumps to step S104.

[0145] S1033: Multi-bit combination search.

[0146] If a single bit cannot completely distinguish the granular selection logic, it indicates that the selection logic is determined by multiple address lines through logical combinations (such as selection controlled by the XOR relationship of two address lines, which is a common optimization design for address interleaving and load balancing). The system automatically performs a combined search.

[0147] Starting with a 2-bit combination, iterate through all possible address bit combinations (j, k) and calculate the value of bit_j XOR bit_k for each address.

[0148] Check if there exists a certain address bit combination whose XOR result is all 0 in {Addr_A} and all 1 in {Addr_B} (or vice versa).

[0149] If found, then (bit_j XOR bit_k) is the decoding logic, and the process jumps to step S104;

[0150] If not found, the number of address bits involved in the XOR operation is iteratively increased (3 bits, 4 bits, etc.) to continue the search until a minimum combination is found that can completely distinguish {Addr_A} and {Addr_B}. This minimum combination is the granular selection decoding function f_decode(addr) for "Socket A vs. Socket B". That is:

[0151] Iterate through all possible combinations of k bits, and for each combination, calculate the XOR value for each address:

[0152] xor_val = bit_{c1} XOR bit_{c2} XOR ... XOR bit_{ck};

[0153] Check if it meets the following requirements:

[0154] (xor_val == 0 for all {Addr_A} and xor_val == 1 for all {Addr_B}), or vice versa.

[0155] If found, then f_decode = XOR(bit_{c1}, ..., bit_{ck}) is the decoding logic, and the process jumps to step S104.

[0156] If the k value has reached the preset upper limit and the same address bit is still not found, it is determined that the current decoding logic derivation has failed. This indicates that the currently collected erroneous physical address samples may not be sufficient to reveal the address mapping rules of the system on this platform, or the mapping rules exceed the preset logical complexity model. At this time, it is necessary to adjust the upper limit of the k value, replace the training particles, or check the address mapping relationship between the two physical slots.

[0157] S1034: Boolean function generation.

[0158] The decoding logic found in step S1032 or S1033 is formalized into a Boolean function. For example:

[0159] Target failed memory chip = (A15 XOR A13) ? “Memory chip corresponding to Socket B”: “Memory chip corresponding to Socket A”. This Boolean function directly associates the address value with the physical location of the memory chip accessed by that address.

[0160] The process of locating failed memory chips is described in detail below.

[0161] Step S104: Decoding logic embedding and failure storage particle location.

[0162] The Boolean function f_decode(addr) derived in step S103 is embedded into the decoding module of the test system or a standalone location tool. When the tool receives any new erroneous physical address (addr_fail), it can immediately determine which socket (or address space) the LPDDR chip corresponds to by calculating f_decode(addr_fail). Combined with the known physical design (which chip is soldered to which socket's corresponding location), the physical identifier of the failed memory chip can be directly output (e.g., "U12 chip failed"). Specific details are as follows:

[0163] After obtaining the physical slot and LPDDR information to which the erroneous physical address belongs, granular-level precise positioning can be further performed. Specifically, based on the LPDDR's chip width configuration information (such as x4 or x8, which can be read from the SPD), the least significant bit of the corresponding column address in the erroneous physical address is extracted. By calculating the chip logical index represented by the least significant bit of the column address and querying a pre-stored memory chip location mapping table for this LPDDR model, the unique physical location identifier (such as U23) corresponding to the failed memory chip in the memory module can be obtained.

[0164] Assume the erroneous physical address determined by address decoding belongs to Socket 1, LPDDR_B1.

[0165] 1. Address Structure

[0166] A complete faulty physical address (such as 0x4E5D1AA30) is typically divided as follows:

[0167] | Bits used to select slot / channel (decoded by the Boolean function f(addr)) | Bank address bits | Row address bits | Column address bits |

[0168] The bits decoded by the Boolean function f(addr) are used to determine which socket it is; the remaining low bits (Column, Bank, Row) are used for addressing within the selected storage granule.

[0169] 2. The least significant bit (LSB) of the column address determines the specific storage granularity.

[0170] In an LPDDR, multiple memory chips work in parallel to provide a total bit width (e.g., 64 bits). The chip bit width (e.g., x4, x8, or x16) indicates how many bits of data a single memory chip provides at a time. The total LPDDR bit width (typically 64 bits) is provided by multiple memory chips. The lowest bits of the column address directly correspond to specific bits on the data bus, thus determining which memory chip is responsible for that access.

[0171] 3. Mapping Calculation (Example)

[0172] Assuming the target LPDDR is an x8 organization (i.e., each chip provides 8 bits of data), with a total bit width of 64 bits. The number of memory chips is calculated as: 64 bits / 8 bits / chip = 8 memory chips working in parallel.

[0173] Granule index calculation: The lowest log2(8) = 3 bits of the column address (i.e., C[2:0]) are used to select one of these 8 storage granules.

[0174] Extract C[2:0] from the fault address to obtain a value between 0 and 7, which is the logical sequence number of the storage chip on LPDDR.

[0175] 4. Physical location transformation:

[0176] The design drawings / silk screen diagrams of the motherboard or LPDDR will clearly indicate: "Logical chip 0" on LPDDR_B1 corresponds to physical location U20, "Logical chip 1" corresponds to U21, ..., "Logical chip 7" corresponds to U27.

[0177] Based on the calculated logical sequence number (e.g., 3), query this mapping table to obtain the final physical identifier: U23.

[0178] 5. For other bit widths (x4)

[0179] x4 bit width requires 64 / 4=16 storage particles. The lowest log2(16)=4 bits (C[3:0]) of the column address are used to select particles (0-15) and then mapped to physical locations (such as U20-U35).

[0180] The mapping relationship between address decoding derivation and failed memory particle location in this example is summarized as follows:

[0181] Error physical address → [Decoding logic (Boolean function f(addr))] → Target slot / LPDDR → Extract the low-order Column from the address → Calculate the chip logic number based on the chip bit width → Query the physical layout mapping table → Output the specific failed memory chip identifier (e.g., U23).

[0182] Step S105: Closed-loop verification and optimization.

[0183] Verification: Using other known failed storage particles, or by intentionally creating particle-level failures (such as heating / pressurizing a specific particle), collect new error addresses and locate them using the location method in this example to verify the accuracy of the location results.

[0184] Iterative optimization: If the verification fails, return to step S102, increase the number of test samples or use more complex granularity for training, and start searching from more complex bit combinations in the next round of analysis (e.g., starting from the number of bits used successfully last time + 1) to find more general decoding logic.

[0185] Step S106: Model solidification and application.

[0186] Once the decoding logic f_decode(addr) has passed verification on a sufficient number of samples, it is embedded into the test program configuration file or diagnostic firmware for that platform / module model. Subsequently, in any test on that platform, if an error occurs, the system can automatically output the information of the failed storage particle in real time, without manual intervention.

[0187] This example has been verified to achieve the following:

[0188] Significantly improve positioning efficiency

[0189] The process of locating failed storage particles has been transformed from relying on "manual replacement testing" (which takes hours to days) to "automatic software analysis" (completed in real time), improving efficiency by more than 100 times.

[0190] Achieving precision maintenance

[0191] It directly identifies the location of the failed memory chip, allowing the repair process to be more precise, reducing material costs and repair difficulty by shifting the focus from "replacing the entire memory module / motherboard" to "replacing a single specific chip".

[0192] Not relying on prior knowledge

[0193] It does not require precise knowledge of the switching details of the motherboard wiring or the complex configuration of the controller. It can automatically learn the actual address mapping relationship of the current system through data-driven methods, making it highly versatile.

[0194] Empowering automated production lines

[0195] It can be integrated with automated test equipment (ATE) to automate the entire process of testing, positioning, sorting / repair, which is a key technology for building smart factories and realizing intelligent manufacturing.

[0196] Reduce reliance on expert experience

[0197] This frees highly skilled engineers from repetitive and tedious address pattern analysis work, reducing personnel training costs and technical barriers.

[0198] Please refer to Figure 4 This application also provides a testing device, including a processor 100 and a memory 200. The memory 200 is coupled to the processor 100 and is used to store computer program code, which includes computer instructions. When the processor 100 reads the computer instructions from the memory 200, the processor 100 executes the steps of the method in any possible implementation of any of the foregoing embodiments.

[0199] This application also provides a computer program product, which includes computer program code that, when run on a computer, causes the computer to perform the steps of the method in any of the possible implementations of the foregoing embodiments.

[0200] Those skilled in the art will recognize that the functions described in the embodiments of this application in one or more of the above examples can be implemented using hardware, software, firmware, or any combination thereof. When implemented using software, these functions can be stored in a computer-readable medium or transmitted as one or more instructions or code on a computer-readable medium. Computer-readable media include computer storage media and communication media, wherein communication media include any medium that facilitates the transfer of a computer program from one place to another. Storage media can be any available medium that can be accessed by a general-purpose or special-purpose computer.

[0201] Note that the above are merely preferred embodiments and the technical principles employed in this application. Those skilled in the art will understand that this application is not limited to the specific embodiments described herein, and various obvious changes, readjustments, and substitutions can be made without departing from the scope of protection of this application. Therefore, although this application has been described in detail through the above embodiments, this application is not limited to the above embodiments, and may include many other equivalent embodiments without departing from the concept of this application, the scope of which is determined by the scope of the appended claims.

Claims

1. A decoding logic derivation method, applied to decoding the erroneous physical address of a failed storage particle in a storage module with multiple storage particles, characterized in that, The method includes: Collect all first-error physical addresses generated when the same failed memory chip is tested in the first physical slot, forming a first-error physical address set; Collect all second-error physical addresses generated when the same failed memory chip is tested in a second physical slot, forming a set of second-error physical addresses; Search the first set of erroneous physical addresses and the second set of erroneous physical addresses to find k address bits, where the binary logical value of the k address bits or their logical combination is always the same value in all the first set of erroneous physical addresses, and the binary logical value of the same value is always the inverse value in all the second set of erroneous physical addresses. A Boolean function is generated to form the k address bits or their logical combinations, which serves as the decoding logic for mapping the erroneous physical address of the failed memory chip to the physical slot identifier. Where k is a natural number, and 1 ≤ k ≤ the number of bits in the address.

2. The decoding logic derivation method according to claim 1, characterized in that, The step of searching the first set of erroneous physical addresses and the second set of erroneous physical addresses to find k address bits specifically includes: Let k=1; Search the first set of erroneous physical addresses and the second set of erroneous physical addresses to find one address bit. This address bit has the same binary logical value in all the first set of erroneous physical addresses, and has the same inverse value in all the second set of erroneous physical addresses. If the specified address bit is not found, the following search steps are performed iteratively until the specified k address bits are found, or the value of k exceeds a preset limit: Increment the value of k by 1; Continue searching the first set of erroneous physical addresses and the second set of erroneous physical addresses to find k address bits. The logical combination of these k address bits always has the same binary logical value in all the first set of erroneous physical addresses, and always has the inverse of the same binary logical value in all the second set of erroneous physical addresses.

3. The decoding logic derivation method according to claim 2, characterized in that, After finding k address bits, the process also includes: After replacing the same failed memory chip with another failed memory chip, repeat the above search steps until k address bits are found. If the same k address bits are found, the search results are verified to be correct.

4. The decoding logic derivation method according to claim 3, characterized in that, If the k address bits are not found to be the same, then the search result is verified as incorrect, and the following steps are performed: After replacing the other failed memory chip, let the value of k start from the previous search result plus 1, and repeat the above search steps until k address bits are found.

5. The decoding logic derivation method according to claim 4, characterized in that, In the Boolean function that generates the k address bits or their logical combinations: The k address bits are determined to be the k address bits found for the first time; or The k address bits are determined as the result of having the fewest address bits and the largest highest-order bit index among multiple found k address bits.

6. The decoding logic derivation method according to any one of claims 2-5, characterized in that, The logical combination includes at least one of the following operations: AND, OR, NOT, XOR.

7. The decoding logic derivation method as described in claim 6, characterized in that, When k=1, the logical combination is the value of the one address bit or its logical NOT; or, when k≥2, the logical combination includes an XOR operation.

8. The decoding logic derivation method as described in any one of claims 1-5, characterized in that, The Boolean function is set to disjunctive normal form or conjunctive normal form.

9. A method for locating failed memory chips, applied to the location of failed memory chips in a memory module having multiple memory chips, characterized in that, The method for locating failed storage particles includes: In response to the detection of a storage chip failure, the erroneous physical address of the failed storage chip is converted into the corresponding physical slot identifier according to a preset decoding logic; Map the physical slot identifier to the physical location identifier of the failed memory chip; The preset decoding logic is set as a Boolean function generated by the decoding logic derivation method according to any one of claims 1-8.

10. The method for locating failed storage particles according to claim 9, characterized in that, The process of mapping the physical slot identifier to the physical location identifier of the failed memory chip specifically includes: Based on the column address bits in the erroneous physical address and the bit width configuration of the storage particle, the physical location identifier corresponding to the failed storage particle on the storage module is determined.

11. A testing device, characterized in that, The method includes a processor and a memory coupled to the processor. The memory is used to store computer program code, which includes computer instructions. When the processor reads the computer instructions from the memory, the processor causes the processor to perform the steps of the method as described in any one of claims 1-10.

12. A computer program product, characterized in that, The computer program product includes: computer program code, which, when run on a computer, causes the computer to perform the steps of the method as described in any one of claims 1-10.

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