Multilayer ceramic capacitor

Abstract

The invention provides a laminated ceramic capacitor capable of moving lithium in a laminated body to an external electrode and improving high-temperature load service life. The laminated ceramic capacitor is provided with a laminated body, a first external electrode and a second external electrode. The dimension l in the first direction of the laminate is shorter than the dimension w in the second direction. The inner dielectric layer at least comprises Ca, Sr or Zr as a main component; and Li, in at least one of a square region having a side length of 30 [mu] m centered on a 1 / 2 dimension in the lamination direction and an interface between the laminated body and the first external electrode, and a square region having a side length of 30 [mu] m centered on a 1 / 2 dimension in the lamination direction and an interface between the laminated body and the second external electrode. Li segregation exists in the first external electrode and / or the second external electrode, and the size of the Li segregation in the first external electrode and / or the second external electrode is larger than the size of the Li segregation in the inner dielectric layer.

Description

TECHNICAL FIELD

[0001] The present application relates to a multilayer ceramic capacitor. BACKGROUND

[0002] In a multilayer ceramic capacitor for electronic equipment, a multilayer ceramic capacitor having a high dielectric constant system, and a multilayer ceramic capacitor for temperature compensation in which the change in electrostatic capacitance with respect to temperature change is linear, as described in Patent Literature 1, are known.

[0003] For example, in the multilayer ceramic capacitor described in Patent Literature 2, copper or an alloy containing copper is used for the internal electrode, and calcium zirconate is used as a main component for the dielectric layer. However, if copper is used for the internal electrode, since the melting point is low, in the process of sintering the dielectric, problems such as the internal electrode becoming over-sintered, the effective area of the internal electrode decreasing, the electrostatic capacitance decreasing, and the like sometimes occur. In Patent Literature 2, in order to lower the temperature at which the dielectric is sintered to as close to the temperature of copper as possible, a sintering aid that forms a liquid phase at the time of firing, such as lithium, silicon, and the like, is used as a sintering aid.

[0004] PRIOR ART DOCUMENTS

[0005] PATENT LITERATURE

[0006] Patent Literature 1: Japanese Patent Application Publication No. 2018-24542

[0007] Patent Literature 2: Japanese Patent Application Publication No. 2009-7209

[0008] Patent Literature 3: Japanese Patent Application Publication No. 2019-62177

[0009] However, if segregation of lithium (Li) occurs in the multilayer body in the firing process, lithium remains in the multilayer body, and the high-temperature load life of the multilayer ceramic capacitor can decrease. SUMMARY

[0010] PROBLEMS TO BE SOLVED BY THE INVENTION

[0011] Therefore, the main object of the present application is to provide a multilayer ceramic capacitor that can move lithium in the multilayer body to the external electrode and improve the high-temperature load life.

[0012] TECHNICAL SOLUTION TO THE PROBLEM

[0013] The present application relates to a multilayer ceramic capacitor, which is a multilayer ceramic capacitor including: a laminate having a first surface and a second surface opposite to each other in a stacking direction, a third surface and a fourth surface opposite to each other in a first direction orthogonal to the stacking direction, and a fifth surface and a sixth surface opposite to each other in a second direction orthogonal to the stacking direction and the first direction; a first external electrode disposed on the third surface of the laminate; and a second external electrode disposed on the fourth surface of the laminate, a dimension l in the first direction of the laminate is shorter than a dimension w in the second direction of the laminate, the laminate includes: a first internal electrode having one end exposed on the third surface; a second internal electrode having one end exposed on the fourth surface; and an inner dielectric layer in which the first internal electrode and the second internal electrode are disposed, the inner dielectric layer contains, as main components, at least: Ca, Sr, or Zr; and Li, segregation of Li exists in the first external electrode and / or the second external electrode in at least either of a region of a square of 30 μm in a side length, which is centered on a dimension of 1 / 2 in the stacking direction and an interface between the laminate and the first external electrode, and a region of a square of 30 μm in a side length, which is centered on a dimension of 1 / 2 in the stacking direction and an interface between the laminate and the second external electrode, and a size of the segregation of Li in the first external electrode and / or the second external electrode is larger than a size of the segregation of Li in the inner dielectric layer.

[0014] According to the present application, the dimension l in the first direction of the laminate is shorter than the dimension w in the second direction of the laminate, the inner dielectric layer contains, as main components, at least: Ca, Sr, or Zr; and Li, segregation of Li exists in the first external electrode and / or the second external electrode in at least either of a region of a square of 30 μm in a side length, which is centered on a dimension of 1 / 2 in the stacking direction and an interface between the laminate and the first external electrode, and a region of a square of 30 μm in a side length, which is centered on a dimension of 1 / 2 in the stacking direction and an interface between the laminate and the second external electrode, and a size of the segregation of Li in the first external electrode and / or the second external electrode is larger than a size of the segregation of Li in the inner dielectric layer, and thus high-temperature load reliability can be improved.

[0015] Effects of the Invention

[0016] According to the present application, a multilayer ceramic capacitor in which lithium in a laminate moves to an external electrode and high-temperature load life is improved can be provided.

[0017] The above objects, other objects, features, and advantages of the present application will become more clearly apparent from the following description of embodiments of the application taken in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS

[0018] Figure 1is an appearance perspective view showing one example of a multilayer ceramic capacitor to which an embodiment of the present application pertains.

[0019] Figure 2 is Figure 1 a cross-sectional view at line II-II of

[0020] Figure 3 is Figure 1 a cross-sectional view at line III-III of

[0021] Figure 4 is Figure 1 a cross-sectional view at line IV-IV of

[0022] Figure 5 is an appearance perspective view showing one example of a multilayer ceramic capacitor to which a modification 1 of an embodiment of the present application pertains.

[0023] Figure 6 is Figure 5 a cross-sectional view at line VI-VI of

[0024] Figure 7 is Figure 5 a cross-sectional view at line VII-VII of

[0025] Figure 8 is Figure 5 a cross-sectional view at line VIII-VIII of

[0026] Figure 9 is an appearance perspective view showing one example of a multilayer ceramic capacitor to which a modification 2 of an embodiment of the present application pertains.

[0027] Figure 10 is Figure 9 a cross-sectional view at line X-X of

[0028] Figure 11 is Figure 9 a cross-sectional view at line XI-XI of

[0029] Figure 12 is Figure 9 a cross-sectional view at line XII-XII of

[0030] Figure 13 is a cross-sectional view showing a modification 3 of an embodiment of the present application in a cross-sectional view shown in Figure 10

[0031] Explanation of Reference Numerals

[0032] 10, 10A, 10B, 10C: multilayer ceramic capacitor;

[0033] 12: multilayer body; ​

[0034] 12a: first surface

[0035] 12b: second surface

[0036] 12c: third surface

[0037] 12d: fourth surface

[0038] 12e: fifth surface

[0039] 12f: sixth surface

[0040] 14: dielectric layer

[0041] 14a: inner dielectric layer

[0042] 14b: outer dielectric layer

[0043] 16: internal electrode

[0044] 16a, 16a1, 16a2: first internal electrode

[0045] 16b, 16b1, 16b2: second internal electrode

[0046] 16A: pair of first internal electrodes

[0047] 16B: pair of second internal electrodes

[0048] 18: inner layer portion

[0049] 20a: outer layer portion on first surface side

[0050] 20b: outer layer portion on second surface side

[0051] 22: counter electrode portion

[0052] 22a: first counter electrode portion

[0053] 22b: second counter electrode portion

[0054] 24a: first lead electrode portion

[0055] 24b: second lead electrode portion

[0056] 25: dummy electrode

[0057] 25a, 25a1, 25a2: first dummy electrode

[0058] 25b, 25b1, 25b2: second dummy electrode

[0059] 25A: pair of dummy electrodes

[0060] 25B: pair of dummy electrodes

[0061] 26a, 26b: side portion

[0062] 27a, 27b: end portion

[0063] 30: external electrode

[0064] 30a: first external electrode

[0065] 30b: second external electrode

[0066] 32: base electrode layer

[0067] 32a: first base electrode layer

[0068] 32b: second base electrode layer

[0069] 34: plating layer

[0070] 34a: first plating layer

[0071] 34b: second plating layer

[0072] 36: lower plating layer

[0073] 36a: first lower plating layer

[0074] 36b: second lower plating layer

[0075] 38: upper plating layer

[0076] 38a: first upper plating layer

[0077] 38b: second upper plating layer

[0078] x: stacking direction

[0079] y: first direction

[0080] z: second direction DETAILED DESCRIPTION

[0081] 1. A laminated ceramic capacitor

[0082] An embodiment of the present application relates to a laminated ceramic capacitor.

[0083] Figure 1 is an appearance perspective view showing one example of a laminated ceramic capacitor to which an embodiment of the present application relates. Figure 2 is Figure 1 a cross-sectional view at line II-II of Figure 3 is Figure 1 a cross-sectional view at line III-III of Figure 4 is Figure 1A cross-sectional view at line IV-IV.

[0084] like Figures 1 to 3 As shown, the multilayer ceramic capacitor 10 includes a cuboid multilayer 12 and external electrodes 30 disposed at both ends of the multilayer 12.

[0085] (Layered structure)

[0086] The laminate 12 has a plurality of stacked dielectric layers 14 and a plurality of internal electrodes 16 stacked on the dielectric layers 14. Furthermore, the laminate 12 has a first surface 12a and a second surface 12b opposite each other in the stacking direction x, a third surface 12c and a fourth surface 12d opposite each other in a first direction y orthogonal to the stacking direction x, and a fifth surface 12e and a sixth surface 12f opposite each other in a second direction z orthogonal to the stacking direction x and the first direction y.

[0087] Furthermore, it is preferable that the first surface 12a and the second surface 12b, or one of them, are flat. If they are flat, the stress experienced by the nozzle picking up the multilayer ceramic capacitor 10 can be dispersed on the flat surface. As a result, the strength of the multilayer ceramic capacitor can be improved during installation.

[0088] In addition, the surface of the laminate 12 can also be roughened.

[0089] In this laminate 12, the corners and edges may also have rounded corners.

[0090] Furthermore, the portion where two of the first facet 12a, second facet 12b, third facet 12c, fourth facet 12d, fifth facet 12e, and sixth facet 12f intersect is called an edge portion, and the portion where three facets intersect is called a corner portion. The edge portions and corner portions are preferably rounded with a radius (R). By giving the edge portions and corner portions a radius (R), gaps and cracks can be prevented. When the edge portions and corner portions have a radius (R), the main surfaces of the faces other than the edge portions and corner portions can also be flat.

[0091] Here, the dimension of the laminate 12 in the first direction y is defined as dimension l, the dimension of the laminate 12 in the second direction z is defined as dimension w, and the dimension of the laminate 12 in the stacking direction x is defined as dimension t. The dimension l in the first direction y of the laminate 12 is shorter than the dimension w in the second direction z of the laminate 12. As a result, the current path can be shortened, and thus the ESL of the laminated ceramic capacitor 10 can be reduced.

[0092] like Figure 2 as well as Figure 3As shown, the laminate 12 has: an inner layer portion 18 in which the dielectric layers 14 and the internal electrodes 16 are alternately stacked in a stacking direction x in which the first face 12a and the second face 12b are joined to each other; a first face side outer layer portion 20a formed of a plurality of dielectric layers 14 provided between the internal electrode 16 located closest to the first face 12a side and the first face 12a; and a second face side outer layer portion 20b formed of a plurality of dielectric layers 14 provided between the internal electrode 16 located closest to the second face 12b side and the second face 12b.

[0093] (the inner layer portion)

[0094] The inner layer portion 18 includes a plurality of inner layer dielectric layers 14a among the plurality of dielectric layers 14. That is, the inner layer portion 18 is configured so that the plurality of internal electrodes 16 face each other with the inner layer dielectric layers 14a interposed therebetween.

[0095] The inner layer dielectric layer 14a includes, as main components, at least: Ca, Sr, or Zr; and Li. For example, as a dielectric component, CaZrO3 or SrZrO3 is included, and as a sintering aid, Li is included. In addition to these, Mn, Ti, or the like can also be included.

[0096] Regarding the main components of the inner layer dielectric layer 14a, the following can be observed.

[0097] That is, a cross section in the stacking direction x x the first direction y when the laminate ceramic capacitor 10 is ground to 1 / 2 of the size of W in the second direction z is exposed. Then, the exposed cross section is observed under the condition of a square of 30 μm in side length using TOF.SIM (manufactured by ION-TOF).

[0098] As shown in Figs. 1 and 2, the internal electrode 16 has a first internal electrode 16a and a second internal electrode 16b. The first internal electrode 16a and the second internal electrode 16b are alternately stacked with the inner layer dielectric layer 14a interposed therebetween. Figure 2 Figure 3 As shown in Figs. 1 and 2, the internal electrode 16 has a first internal electrode 16a and a second internal electrode 16b. The first internal electrode 16a and the second internal electrode 16b are alternately stacked with the inner layer dielectric layer 14a interposed therebetween.

[0099] The first internal electrode 16a is disposed on the plurality of dielectric layers 14 and is located inside the laminate 12. The first internal electrode 16a has a first facing electrode portion 22a facing the second internal electrode 16b, and a first lead electrode portion 24a located on the one end side of the first internal electrode 16a and extending from the first facing electrode portion 22a to the third face 12c of the laminate 12. Regarding the first lead electrode portion 24a, the end portion thereof is led out to the surface of the third face 12c and is exposed from the laminate 12. That is, the end portion of the first lead electrode portion 24a is not exposed on the first face 12a and the second face 12b, the fourth face 12d and the fifth face 12e, and the sixth face 12f. In detail, the end portion of the first internal electrode 16a is slightly retracted from the fourth face 12d.​

[0100] The shape of the first opposing electrode portion 22a of the first internal electrode 16a is not particularly limited, but is preferably rectangular in plan view. However, the corner portions can be formed with rounded corners in plan view, or the corner portions can be formed so as to be inclined (tapered) in plan view. Further, it can be tapered in plan view with an inclination toward somewhere.

[0101] The shape of the first lead-out electrode portion 24a of the first internal electrode 16a is not particularly limited, but is preferably rectangular in plan view. However, the corner portions can be formed with rounded corners in plan view, or the corner portions can be formed so as to be inclined (tapered) in plan view. Further, it can be tapered in plan view with an inclination toward somewhere.

[0102] The width of the first opposing electrode portion 22a of the first internal electrode 16a and the width of the first lead-out electrode portion 24a of the first internal electrode 16a can be formed with the same width, or the width of either one can be formed to be narrower.

[0103] The second internal electrode 16b is disposed on the plurality of dielectric layers 14 and is located inside the stacked body 12. The second internal electrode 16b has a second opposing electrode portion 22b that opposes the first internal electrode 16a, and a second lead-out electrode portion 24b that is located on the one end side of the second internal electrode 16b and extends from the second opposing electrode portion 22b to the fourth surface 12d of the stacked body 12. The end portion of the second lead-out electrode portion 24b is led out to the surface of the fourth surface 12d and is exposed from the stacked body 12. That is, the end portion of the second lead-out electrode portion 24b is not exposed from the first surface 12a and the second surface 12b, the third surface 12c, and the fifth surface 12e and the sixth surface 12f. In detail, the end portion of the second internal electrode 16b is slightly recessed from the third surface 12c.

[0104] The shape of the second opposing electrode portion 22b of the second internal electrode 16b is not particularly limited, but is preferably rectangular in plan view. However, the corner portions can be formed with rounded corners in plan view, or the corner portions can be formed so as to be inclined (tapered) in plan view. Further, it can be tapered in plan view with an inclination toward somewhere.

[0105] The shape of the second lead-out electrode portion 24b of the second internal electrode 16b is not particularly limited, but is preferably rectangular in plan view. However, the corner portions can be formed with rounded corners in plan view, or the corner portions can be formed so as to be inclined (tapered) in plan view. Further, it can be tapered in plan view with an inclination toward somewhere.

[0106] The width of the second opposing electrode portion 22b of the second internal electrode 16b and the width of the second lead electrode portion 24b of the second internal electrode 16b can be formed with the same width, or the width of either can be formed to be narrower.

[0107] As shown in FIG. 1, the laminated body 12 includes a side portion 26a of the laminated body 12 formed between the first opposing electrode portion 22a and the fifth surface 12e in the second direction z of the first opposing electrode portion 22a and the second opposing electrode portion 22b, and a side portion 26b of the laminated body 12 formed between the second opposing electrode portion 22b and the sixth surface 12f in the second direction z of the first opposing electrode portion 22a and the second opposing electrode portion 22b. Figure 3

[0108] Further, as shown in FIG. 1, the laminated body 12 includes an end portion 27a of the laminated body 12 formed between the end portion of the first internal electrode 16a on the opposite side of the first lead electrode portion 24a and the fourth surface 12d, and an end portion 27b of the laminated body 12 formed between the end portion of the second internal electrode 16b on the opposite side of the second lead electrode portion 24b and the third surface 12c. Figure 2

[0109] The internal electrode 16 has Cu as a main component, for example. Thus, the resistance of the internal electrode 16 can be reduced, and the ESR can be decreased. In addition to this, by making the main component of the internal electrode 16 Cu, the internal electrode 16 can be formed with inexpensive materials.

[0110] Regarding the main component of the internal electrode 16, observation can be performed as follows.

[0111] That is, a cross section in the lamination direction x x the first direction y when the laminated ceramic capacitor 10 is polished to 1 / 2 of the size of W in the second direction z is exposed. Then, the exposed cross section is observed using TOF.SIM (manufactured by ION-TOF) under the condition of a square of 30 μm on a side.

[0112] The thickness of the internal electrode 16 is preferably 0.5 μm or more and 3.5 μm or less. In addition, the number of pieces of the first internal electrode 16a and the second internal electrode 16b is preferably two or more and 30 or less in total.

[0113] (First surface side outer layer portion, second surface side outer layer portion)

[0114] The first surface side outer layer portion 20a is on the first surface 12a side of the laminated body 12, and is a collection of the plurality of dielectric layers 14, i.e., the plurality of outer layer dielectric layers 14b, between the first surface 12a and the internal electrode 16 closest to the first surface 12a.

[0115] ​​The second-side outer layer 20b is located on the second surface 12b side of the laminate 12, and is an assembly of multiple dielectric layers 14, i.e. multiple outer dielectric layers 14b, located between the second surface 12b and the inner electrode 16 closest to the second surface 12b.

[0116] The area sandwiched between the first outer layer 20a and the second outer layer 20b is the inner layer 18.

[0117] The first-side outer layer 20a and the second-side outer layer 20b are each formed of an insulating material. When the first-side outer layer 20a and the second-side outer layer 20b are formed of the same type of dielectric material as the inner dielectric layer 14a, each outer layer 20a, 20b can be composed of multiple outer dielectric layers 14b or a single outer dielectric layer 14b.

[0118] (External electrode)

[0119] like Figures 1 to 3 As shown, external electrodes 30 are disposed on the third surface 12c side and the fourth surface 12d side of the laminate 12.

[0120] The external electrode 30 includes: a base electrode layer 32 comprising a metallic component and glass; and a plating layer 34 disposed on the surface of the base electrode layer 32.

[0121] The external electrode 30 has a first external electrode 30a and a second external electrode 30b.

[0122] The first external electrode 30a is connected to the first internal electrode 16a and is disposed at least on the surface of the third surface 12c. Furthermore, the first external electrode 30a preferably extends from the third surface 12c of the laminate 12 and is also disposed on a portion of the first surface 12a, a portion of the second surface 12b, a portion of the fifth surface 12e, and a portion of the sixth surface 12f. The first external electrode 30a is electrically connected to the first lead-out electrode portion 24a of the first internal electrode 16a.

[0123] The second external electrode 30b is connected to the second internal electrode 16b and is disposed at least on the surface of the fourth surface 12d. Furthermore, the second external electrode 30b preferably extends from the fourth surface 12d of the laminate 12 and is also disposed on a portion of the first surface 12a, a portion of the second surface 12b, a portion of the fifth surface 12e, and a portion of the sixth surface 12f. The second external electrode 30b is electrically connected to the second lead-out electrode portion 24b of the second internal electrode 16b.

[0124] In the multilayer body 12, the first opposing electrode portion 22a of the first internal electrode 16a and the second opposing electrode portion 22b of the second internal electrode 16b oppose each other via the dielectric layer 14, thereby forming a static capacitance. Thus, a static capacitance can be obtained between the first external electrode 30a connected to the first internal electrode 16a and the second external electrode 30b connected to the second internal electrode 16b, thereby embodying the characteristics of a capacitor.

[0125] The base electrode layer 32 has a first base electrode layer 32a and a second base electrode layer 32b.

[0126] The first base electrode layer 32a is connected to the first internal electrode 16a and is disposed on the surface of the third face 12c. Further, the first base electrode layer 32a preferably extends from the third face 12c and is also disposed on a part of the first face 12a and a part of the second face 12b and a part of the fifth face 12e and a part of the sixth face 12f. The first base electrode layer 32a is electrically connected to the first lead-out electrode portion 24a of the first internal electrode 16a.

[0127] The second base electrode layer 32b is connected to the second internal electrode 16b and is disposed on the surface of the fourth face 12d. Further, the second base electrode layer 32b preferably extends from the fourth face 12d and is also disposed on a part of the first face 12a and a part of the second face 12b and a part of the fifth face 12e and a part of the sixth face 12f. The second base electrode layer 32b is electrically connected to the second lead-out electrode portion 24b of the second internal electrode 16b.

[0128] The base electrode layer 32 has Cu as a main component. The base electrode layer 32 contains a glass component in addition to Cu as the main component. The base electrode layer 32 can lower the ESR of the multilayer ceramic capacitor 10 by containing Cu having a low specific resistance as the main component. Further, the base electrode layer 32 can improve the sinterability of the base electrode layer 32 by containing a glass component. As the glass component, for example, Na, B, Si, Zn, Ba, and the like can be contained.

[0129] In the present embodiment, if the Cu particle diameter becomes small, the number of interfaces of the Cu particles increases, and thus the ESR increases. Therefore, the D50 of the Cu particles of Cu contained in the base electrode layer 32 is preferably 1.5 μm or more and 3.5 μm or less.

[0130] Further, regarding the base electrode layer 32, in a region of a square of 30 μm on a side with the interface between the laminated body 12 and the external electrode 30 at the center in the laminating direction x, segregation of Li was present, and was greater than the segregation of Li contained in the inner dielectric layer 14a. Further, in the region of the square of 30 μm on a side with the interface between the laminated body 12 and the external electrode 30 at the center in the laminating direction x, the size of the segregation of Li was preferably 1.0 μm or less 2 above and 30.2 μm 2 below.

[0131] Further, in the cross section in the laminating direction x x the first direction y when the laminated ceramic capacitor 10 was polished to 1 / 2 of the size of W in the second direction z, regarding the base electrode layer 32 located at the center in the laminating direction x, using TOF.SIMS, under the condition of a square of 30 μm on a side, and with the interface between the laminated body 12 and the base electrode layer 32 as the center of the observation image, the size of the segregation of Li in the base electrode layer 32 was defined by the presence of Li at that time.

[0132] Further, the size of the segregation of Li in the base electrode layer 32 and the size of the segregation of Li in the inner dielectric layer 14a can be measured by TOF.SIMS (Time-of-Flight Secondary Ion Mass Spectrometry). The measurement conditions using this TOF.SIMS are as follows.

[0133] • Apparatus name: TOF.SIMS (manufactured by ION-TOF Corporation)

[0134] • Primary ions: Bi +

[0135] • Acceleration voltage: 25 kV

[0136] • Secondary ion polarity: Positive

[0137] • Number of scans: 32

[0138] • Number of pixels: 256 pixels x 256 pixels

[0139] • Measurement area: 30 μm x 30 μm

[0140] Further, regarding the size of the segregation of Li, among the 256 pixels x 256 pixels, the pixels in which the intensity of Li was 1.0 or more were counted as Li. Regarding the size of the segregation of Li, 0.50 μm or less 2The above areas are counted. For example, in a case where there are three Li segregations, the segregation having the largest size among them is set as the size of Li.

[0141] The thickness of the first direction y linking the third face 12c and the fourth face 12d at the central portion of the third face 12c in the stacking direction x of the first base electrode layer 32a is, for example, preferably in the order of 19 μm or more and 24 μm or less.

[0142] The thickness of the first direction y linking the third face 12c and the fourth face 12d at the central portion of the fourth face 12d in the stacking direction x of the second base electrode layer 32b is, for example, preferably in the order of 19 μm or more and 24 μm or less.

[0143] Next, the first plated layer 34a and the second plated layer 34b provided on the base electrode layer 32 will be described with reference to Figure 2 and Figure 3 to the drawings.

[0144] The first plated layer 34a and the second plated layer 34b contain, for example, at least one selected from Cu, Ni, Sn, Ag, Pd, Ag-Pd alloy, Au, and the like.

[0145] The first plated layer 34a is provided so as to completely cover the first base electrode layer 32a.

[0146] The second plated layer 34b is provided so as to completely cover the second base electrode layer 32b.

[0147] The first plated layer 34a and the second plated layer 34b can also be formed of a plurality of layers. In this case, the plated layer 34 is preferably a two-layer structure of a lower plated layer (Ni plated layer) formed of Ni plating provided on the base electrode layer 32 and an upper plated layer (Sn plated layer) formed of Sn plating provided on the lower plated layer.

[0148] That is, in this case, the first plated layer 34a has a first lower plated layer 36a and a first upper plated layer 38a provided on the surface of the first lower plated layer 36a.

[0149] Further, the second plated layer 34b has a second lower plated layer 36b and a second upper plated layer 38b provided on the surface of the second lower plated layer 36b.

[0150] The lower plated layer 36 formed of Ni plating serves to prevent the base electrode layer 32 from being corroded by solder when the multilayer ceramic capacitor 10 is mounted, and the upper plated layer 38 formed of Sn plating serves to improve the wettability of solder when the multilayer ceramic capacitor 10 is mounted, so that the mounting can be easily performed.

[0151] The thickness of each of the lower plating layer 36 and the upper plating layer 38 is preferably 1.0 μm or more and 15.0 μm or less.

[0152] The dimension in the first direction y of the stacked ceramic capacitor 10, which includes the laminate 12, the first external electrode 30a, and the second external electrode 30b, is set as dimension L. The dimension in the stacking direction x of the stacked ceramic capacitor 10, which includes the laminate 12, the first external electrode 30a, and the second external electrode 30b, is set as dimension T. The dimension in the second direction z of the stacked ceramic capacitor 10, which includes the laminate 12, the first external electrode 30a, and the second external electrode 30b, is set as dimension W.

[0153] Regarding the dimensions of the multilayer ceramic capacitor 10, the L dimension in the first direction y is 0.2 mm or more and 0.5 mm or less, the W dimension in the second direction z is 0.4 mm or more and 1.0 mm or less, and the T dimension in the stacking direction x is 0.15 mm or more and 0.35 mm or less. Furthermore, the dimensions of the multilayer ceramic capacitor 10 can be measured using a microscope.

[0154] exist Figure 1 In the multilayer ceramic capacitor 10 shown, the dimension l in the first direction y of the multilayer 12 is shorter than the dimension w in the second direction z of the multilayer 12. The inner dielectric layer 14a of the multilayer 12 contains at least Ca, Sr or Zr and Li as the main components. In a square region with a side length of 30 μm centered on 1 / 2 of the multilayer direction x and the interface between the multilayer 12 and the outer electrode 30, the base electrode layer 32 has Li segregation, which is larger than the Li segregation contained in the inner dielectric layer. Therefore, the reliability under high temperature load can be improved.

[0155] Furthermore, in Figure 1 In the multilayer ceramic capacitor 10 shown, in a square region with a side length of 30 μm centered on the halfway point in the stacking direction x and the interface between the multilayer body 12 and the external electrode 30, if the size of the Li segregation is 1.0 μm... 2 Above and 30.2μm 2 The following steps can further improve the reliability of high-temperature loads.

[0156] 2. Variations

[0157] (1) Variation Example 1

[0158] Next, an example of a multilayer ceramic capacitor 10A according to a variation of this embodiment will be described. Figure 5 This is a perspective view showing an example of a multilayer ceramic capacitor according to a modified example 1 of an embodiment of the present invention. Figure 6 yes Figure 5a cross-sectional view taken along line VI-VI of FIG. 10. Figure 7 a cross-sectional view taken along line VII-VII of FIG. 11. Figure 5 a cross-sectional view taken along line VIII-VIII of FIG. 12. Figure 8 For structures identical or equivalent to those of Figure 5 , the same reference numerals are applied, and detailed description is omitted. Figures 1 to 4

[0159] A stacked ceramic capacitor 10A according to Embodiment 1 of the present application includes a rectangular parallelepiped-shaped stacked body 12A and external electrodes 30 arranged at both end portions of the stacked body 12A.

[0160] The stacked body 12A has a plurality of dielectric layers 14 stacked. Further, the stacked body 12A has a first surface 12a and a second surface 12b opposed in a stacking direction x, a third surface 12c and a fourth surface 12d opposed in a first direction y orthogonal to the stacking direction x, and a fifth surface 12e and a sixth surface 12f opposed in a second direction z orthogonal to the stacking direction x and the first direction y.

[0161] In the stacked body 12A, as shown in FIG. 13, the first internal electrode 16a and the second internal electrode 16b are arranged on the same internal dielectric layer 14a with a given interval in the internal layer portion 18. Figure 6 Figure 8 That is, the first internal electrode 16a and the second internal electrode 16b are opposed to each other in the first direction y.

[0162] The stacked ceramic capacitor 10A according to Embodiment 1 of the present application achieves the same effects as the stacked ceramic capacitor 10. Figure 5 Figure 1 (2) Embodiment 2

[0163] Next, one example of a stacked ceramic capacitor 10B according to Embodiment 2 of the present application will be described. is an external perspective view showing one example of a stacked ceramic capacitor according to Embodiment 2 of the present application.

[0164] is a cross-sectional view taken along line X-X of FIG. 14. Figure 9 is a cross-sectional view taken along line XI-XI of FIG. 15. Figure 10 is a cross-sectional view taken along line XII-XII of FIG. 16. For structures identical or equivalent to those of Figure 9 , the same reference numerals are applied, and detailed description is omitted. Figure 11 Figure 9 Figure 12 Figure 9 Figures 1 to 4

[0165] ​​​​​​​A variant 2 of the present embodiment relates to a multilayer ceramic capacitor 10B including a rectangular parallelepiped-shaped multilayer body 12B and external electrodes 30 arranged at both end portions of the multilayer body 12B.

[0166] The multilayer body 12B has a plurality of dielectric layers 14 stacked. Further, the multilayer body 12B has a first surface 12a and a second surface 12b opposing in the stacking direction x, a third surface 12c and a fourth surface 12d opposing in a first direction y orthogonal to the stacking direction x, and a fifth surface 12e and a sixth surface 12f opposing in a second direction z orthogonal to the stacking direction x and the first direction y.

[0167] As shown in FIG. 6, the multilayer body 12B has the first internal electrode 16a and the second internal electrode 16b as internal electrodes 16. Figures 10 to 12

[0168] The first internal electrode 16a is electrically connected to the first external electrode 30a.

[0169] The second internal electrode 16b is electrically connected to the second external electrode 30b.

[0170] Further, the first dummy electrode 25a is arranged at the end portion (L gap) 27b of the multilayer body 12B so as to be exposed at the third surface 12c. Further, the second dummy electrode 25b is arranged at the end portion (L gap) 27a of the multilayer body 12B so as to be exposed at the fourth surface 12d.

[0171] The first dummy electrode 25a is preferably arranged on the same plane as the second internal electrode 16b and has the same thickness as the second internal electrode 16b.

[0172] The second dummy electrode 25b is preferably arranged on the same plane as the first internal electrode 16a and has the same thickness as the first internal electrode 16a.

[0173] The first dummy electrode 25a and the second dummy electrode 25b can also be arranged at the first surface side outer layer portion 20a and the second surface side outer layer portion 20b. In this case, it is preferable to be arranged at a portion corresponding to a place where the end portions (L gaps) 27a, 27b of the multilayer body 12B are moved in parallel in the stacking direction x. By being provided like this, it becomes easy to form a plating layer in the case where the plating layer is provided without providing the base electrode layer 32.

[0174] Further, in the case where the first dummy electrode 25a and the second internal electrode 16b are arranged on the same plane, by printing the first dummy electrode 25a together with the second internal electrode 16b when the second internal electrode 16b is printed, it is possible to arrange the first dummy electrode 25a and the second internal electrode 16b on the same plane.

[0175] ​Further, in a case where the second dummy electrode 25b and the first internal electrode 16a are provided on the same plane, the second dummy electrode 25b can be printed together with the first internal electrode 16a when the first internal electrode 16a is printed.

[0176] According to Figure 9 the modified example 2 shown in FIG. 10B, the same effects as the multilayer ceramic capacitor 10 shown in FIG. 1A are achieved. Figure 1

[0177] (3) Modified Example 3

[0178] Next, one example of the multilayer ceramic capacitor 10C according to the modified example 3 of the present embodiment will be described. Figure 13 is Figure 10 is a cross-sectional view showing the modified example 3 of the present embodiment. In the cross-sectional view, the same reference numerals are assigned to the same or equivalent structures as those of the multilayer ceramic capacitor 10 shown in FIG. 1A, and detailed description will be omitted. Figures 1 to 4

[0179] As shown in FIG. 10C, the multilayer ceramic capacitor 10C according to the modified example 3 of the present embodiment has a pair of first internal electrodes 16A and a pair of second internal electrodes 16B as internal electrodes 16. Figure 13 The pair of first internal electrodes 16A is composed of two pieces of first internal electrodes 16al, 16a2 that are continuous and adjacent in the stacking direction x. The pair of first internal electrodes 16A is electrically connected to the first external electrode 30a.

[0180] The pair of second internal electrodes 16B is composed of two pieces of second internal electrodes 16bl, 16b2 that are continuous and adjacent in the stacking direction x. The pair of second internal electrodes 16B is electrically connected to the second external electrode 30b.

[0181] Further, a pair of first dummy electrodes 25A is arranged at the end portion (L-gap) 27b of the multilayer body 12C so as to be exposed on the third surface 12c. Further, a pair of second dummy electrodes 25B is arranged at the end portion (L-gap) 27a of the multilayer body 12C so as to be exposed on the fourth surface 12d.

[0182] The pair of first dummy electrodes 25A is composed of two pieces of first dummy electrodes 25al, 25a2 that are continuous and adjacent in the stacking direction x. The first dummy electrodes 25al, 25a2 that constitute the pair of first dummy electrodes 25A are each preferably arranged on the same plane as each of the second internal electrodes 16bl, 16b2 that constitute the pair of second internal electrodes 16B, and has the same thickness as each of the second internal electrodes 16bl, 16b2.

[0183]

[0184] ​​​A pair of the second dummy electrodes 25B is composed of two pieces of the second dummy electrodes 25bl, 25b2 which are continuous and adjacent in the stacking direction x. The second dummy electrodes 25bl, 25b2 which compose the pair of the second dummy electrodes 25B are each preferably arranged on the same plane as each of the first internal electrodes 16al, 16a2 which compose the pair of the first internal electrodes 16A, and have the same thickness as each of the first internal electrodes 16al, 16a2.

[0185] According to Figure 13 The modification 3 shown in FIG. 10 relates to the multilayer ceramic capacitor 10C which achieves the same effect as the multilayer ceramic capacitor 10 shown in FIG. 1. Figure 1

[0186] 3. Method for manufacturing multilayer ceramic capacitor

[0187] Next, one example of the method for manufacturing the multilayer ceramic capacitor according to the present embodiment will be described.

[0188] (Step of preparing ceramic green sheet)

[0189] First, a ceramic green sheet for a dielectric layer and a conductive paste for an internal electrode are prepared. The ceramic green sheet and the conductive paste for an internal electrode contain a binder and an organic solvent. The binder and the organic solvent can be publicly known ones.

[0190] At this time, the ceramic green sheet for the inner dielectric layer region is formed of, for example, a dielectric paste containing Li in CaZr03. In more detail, the dielectric paste contains at least: Ca, Sr, or Zr; and Li as main components. For example, as a dielectric component, CaZr03or SrZr03is contained, and as a sintering aid, Li is contained. In addition to these, Mn, Ti, or the like can also be contained.

[0191] In addition, the dielectric paste for forming the ceramic green sheet for the inner dielectric layer region contains a glass component in an amount of 2 wt% or more and 4 wt% or less with respect to CaZr03when CaZr03is used as a main component. At this time, the amount of Li contained in the glass component can be set to 3 wt% or more and 4 wt% or less.

[0192] Then, the conductive paste for an internal electrode is printed on the ceramic green sheet for the inner dielectric layer region in a given pattern by, for example, screen printing, gravure printing, or the like. Thus, a ceramic green sheet on which a pattern of a first internal electrode is formed and a ceramic green sheet on which a pattern of a second internal electrode is formed are prepared.

[0193] (Step of obtaining a laminated sheet)

[0194] ​Next, ceramic green sheets for the outer layer of the pattern of the unprinted internal electrode are stacked in a given number of sheets, thereby forming a portion that becomes the 2nd surface side outer layer portion of the 2nd surface side. Then, ceramic green sheets in which the pattern of the 1st internal electrode is printed and ceramic green sheets in which the pattern of the 2nd internal electrode is printed are stacked in order on the portion that becomes the 2nd surface side outer layer portion, so as to become the configuration of the present application, thereby forming a portion that becomes the inner layer portion. Ceramic green sheets for the outer layer of the pattern of the unprinted internal electrode are stacked in a given number of sheets on the portion that becomes the inner layer portion, thereby forming a portion that becomes the 1st surface side outer layer portion of the 1st surface side. Thus, a stacked sheet is produced.

[0195] (Procedure for obtaining a stacked block)

[0196] Next, the stacked sheet is pressed in the stacking direction by means of isostatic pressing or the like, thereby producing a stacked block.

[0197] (Procedure for obtaining a stacked chip)

[0198] Then, the stacked block is cut to a given size, thereby cutting out a stacked chip.

[0199] (Procedure for obtaining a fired body chip)

[0200] Next, the stacked chip is fired, thereby producing a fired body chip. Specifically, after heating at 200°C or higher and 300°C or lower, firing is performed at a temperature rise of 3.33°C / minute or higher and 200°C / minute or lower and a maximum firing temperature of 900°C or higher and 1040°C or lower in a non-oxidizing atmosphere, thereby forming the fired body chip.

[0201] Next, a conductive paste for a base electrode layer including a metal component and a glass component is prepared.

[0202] (Procedure for forming an external electrode)

[0203] The conductive paste prepared so as to become a base electrode layer is applied to the surfaces of the fired body chip corresponding to the respective surfaces of the 3rd surface and the 4th surface, thereby forming a base electrode layer. In applying the conductive paste to the surfaces of the fired body chip corresponding to the 3rd surface and the 4th surface, for example, a method such as dipping can be used. For example, in the conductive paste that becomes a base electrode layer, as a metal component, Cu can be used as a main component, and a glass component can be contained at a content of 10 vol% or more and 20 vol% or less. At this time, with respect to the particles of Cu, for particles of Cu in which the shape of the particles is flat, particles of Cu in which D50 is 2 μm or more and 4 μm or less are used, and for particles of Cu in which the shape of the particles is spherical, particles of Cu in which D50 is 0.3 μm or more and 0.5 μm or less are used.

[0204] Next, the fired body piece to which the conductive paste is applied is fired, thereby forming a fired body piece with a base electrode layer. At this time, it is preferable to adjust the firing conditions under conditions in which an appropriate amount of Li is contained in the base electrode layer after the conductive paste is fired. If firing is performed under conditions in which Li is not contained in the base electrode layer, densification of the base electrode layer cannot be promoted, and it is likely that invasion of plating solution will occur in the plating process described later, or the interface between the internal electrode and the internal dielectric layer will separate, and it is likely that many failures will occur in the high-temperature load test. Furthermore, if segregation of Li scattered into the base electrode layer is large or the amount of Li is excessive, the proportion of glass components increases, and it is likely that moisture resistance will decrease. With respect to the firing conditions for the fired body piece, for example, firing can be performed under conditions in which the temperature is 850°C or higher and 900°C or lower and the time is 0.3 hours or longer and 0.5 hours or shorter in a reducing atmosphere.

[0205] In addition, in a capacitor in which the W dimension of the laminated ceramic capacitor 10 is larger than the L dimension as in the present embodiment, the contact surface of the laminated body 12 and the external electrode 30 is large, and thus lithium in the laminated body 12 is more likely to be scattered into the external electrode 30 in the external electrode firing process. Therefore, the paste used to form the external electrode 30 and the atmosphere used for firing of the external electrode are set to an appropriate range.

[0206] Next, plating is performed on the surface of the base electrode layer as necessary to form a plated layer. In the present embodiment, two layers of plated layers are formed on the surface of the base electrode layer. Specifically, a Ni plated layer and a Sn plated layer are formed on the base electrode layer. As the plating process, electrolytic plating is preferably used. The Ni plated layer and the Sn plated layer are formed in this order, for example, by a barrel plating method.

[0207] The laminated ceramic capacitor 10 according to the present embodiment is manufactured as described above.

[0208] 3. Experimental Example

[0209] Next, in order to confirm the effects of the laminated ceramic capacitor according to the present embodiment described above, laminated ceramic capacitors in which the size of segregation of Li contained in the base electrode layer was changed were produced as test samples of an experimental example according to the production method described above, and moisture resistance tests and high-temperature load reliability tests were performed.

[0210] (1) Specifications of the laminated ceramic capacitors produced as test samples of an experimental example

[0211] Laminated ceramic capacitors were produced as test samples of Test Sample No. 1 to Test Sample No. 7 using the production method according to the above-described embodiment.

[0212] • Configuration of the laminated ceramic capacitor: Figure 1 The laminated ceramic capacitor

[0213] • Size in the 1st direction of the multilayer ceramic capacitor: 300 μm

[0214] • Size in the 2nd direction of the multilayer ceramic capacitor: 600 μm

[0215] • Size in the stacking direction of the multilayer ceramic capacitor: 200 μm

[0216] • Main component of the internal electrode: Cu

[0217] • Main component of the internal dielectric layer: CaZr03

[0218] • Main component of the base electrode layer: Cu

[0219] • Thickness of the base electrode layer in the center in the stacking direction x of 1 / 2 of the W size in the 2nd direction z of the multilayer ceramic capacitor: 20 μm

[0220] • Plating layer

[0221] Two layers of Ni plating layer and Sn plating layer are formed

[0222] • Ni plating layer thickness: about 3 μm

[0223] • Sn plating layer thickness: about 5 μm

[0224] (2) Measurement method of the size of segregation of Li

[0225] In the cross section in the stacking direction x x the 1st direction y when polishing to 1 / 2 of the W size in the 2nd direction z in the 2nd direction z of the multilayer ceramic capacitor involved in each sample, for the base electrode layer in the center in the stacking direction x, using TOF.SIMS, under the condition of a square of 30 μm on a side, and setting the interface of the stack and the base electrode layer as the center of the observation image, the size of segregation of Li in the base electrode layer was defined by the presence of Li at that time. The measurement conditions using this TOF.SIMS were set as follows.

[0226] • Apparatus name: TOF.SIMS (manufactured by ION-TOF Corporation)

[0227] • Primary ion: Bi +

[0228] • Acceleration voltage: 25 kV

[0229] • Secondary ion polarity: Positive

[0230] • Number of scans: 32

[0231] • Number of pixels: 256 pixels x 256 pixels

[0232] • Measurement area: square of 30 μm x 30 μm

[0233] Further, regarding the size of the segregation of Li, the area of the largest segregation of Li was measured in the 0.5 μm 2 The area above was counted. For example, in the case where there were three sites where Li was segregated, the site where Li was segregated having the largest size was determined, and the site where Li was segregated was set as the size of Li.

[0234] (3) Method of the moisture resistance test

[0235] First, the insulation resistance values of the multilayer ceramic capacitors relating to each of the test samples were measured with the multilayer ceramic capacitors relating to each of the test samples mounted on a wiring substrate using solder. At this time, the multilayer ceramic capacitors relating to each of the test samples mounted on the wiring substrate were put into a high-temperature high-humidity tank, and a moisture resistance test was performed by maintaining the state where a direct current of 200 V was applied to the external electrodes of the multilayer ceramic capacitors relating to each of the test samples in an environment of 85°C and a relative humidity of 85% RH for 2000 hours. Then, the insulation resistance values of the multilayer ceramic capacitors relating to each of the test samples after the moisture resistance test were measured. The case where the insulation resistance value after the moisture resistance test decreased by one or more digits from the insulation resistance value before the moisture resistance test was set as NG (defective). The number of each of the test samples was set to 100.

[0236] (4) High-temperature load reliability test

[0237] First, the insulation resistance values of the multilayer ceramic capacitors relating to each of the test samples were measured with the multilayer ceramic capacitors relating to each of the test samples mounted on a wiring substrate using solder. At this time, the multilayer ceramic capacitors relating to each of the test samples mounted on the wiring substrate were put into a tank, and a high-temperature load test was performed by maintaining the state where a direct current of 200 V was applied to the external electrodes of the multilayer ceramic capacitors relating to each of the test samples in an environment of 150°C for 2000 hours. Then, the insulation resistance values of the multilayer ceramic capacitors relating to each of the test samples after the high-temperature load test were measured. The case where the insulation resistance value after the high-temperature load test decreased by one or more digits from the insulation resistance value before the high-temperature load test was set as NG (defective). The number of each of the test samples was set to 100.

[0238] (5) Results

[0239] In Table 1, the results of the moisture resistance test and the high-temperature load reliability test are shown when the size of the segregation of Li included in the base electrode layer was changed in the multilayer ceramic capacitors of each of the test samples according to Test Sample No. 1 to Test Sample No. 7.

[0240] In addition, for the sample No. 7, it was assumed that Li was not contained in the base electrode layer but was contained in the laminate. On the other hand, for the sample No. 1 to the sample No. 6, it was assumed that Li was contained in the base electrode layer as well as in the laminate, but the segregation of Li in the base electrode layer was larger than the segregation of Li contained in the laminate.

[0241] [Table 1]

[0242]

[0243] According to Table 1, the segregation of Li contained in the base electrode layer became larger from the sample No. 1 to the sample No. 6. Therefore, the difference between the segregation of Li contained in the laminate and the segregation of Li contained in the base electrode layer became larger from the sample No. 1 to the sample No. 6 with respect to the segregation of Li contained in the base electrode layer.

[0244] As a result, it was confirmed that, as the segregation of Li contained in the base electrode layer became larger, the number of samples that became NG (defective) as a result of the high-temperature load test decreased.

[0245] On the other hand, in the sample of the sample No. 7, there was no segregation of Li in the base electrode layer, and therefore, as a result of the high-temperature load test, the number of samples that became NG (defective) was relatively large, and there were 10 out of 100.

[0246] When the segregation of Li in the samples assumed to be the sample No. 1 to the sample No. 3 was large, as a result of the humidity resistance test, there were no samples that became NG (defective), and a good result was obtained.

[0247] On the other hand, when the segregation of Li in the samples assumed to be the sample No. 4 to the sample No. 6 was large, as a result of the humidity resistance test, there were samples that became NG (defective) although they were a small number.

[0248] According to the above results, it was confirmed that, in the present application, the larger the segregation of Li contained in the base electrode layer, the better the result of the high-temperature load reliability test. In addition, it was confirmed that, if the segregation of Li was 1.0 μm 2 and 30.2 μm 2 When the segregation of Li was in the above range, the result of the humidity resistance test was also relatively good.

[0249] In addition, as described above, the embodiment of the present application has been disclosed by the above description, but the present application is not limited thereto.

[0250] That is, various changes can be made to the embodiments described above in terms of the mechanism, shape, material, number, position, or arrangement, and the like, without departing from the scope of the technical idea and the objects of the present application, and these are included in the present application.

Claims

1. A multilayer ceramic capacitor, comprising: The laminate has a first and a second surface opposite to each other in the lamination direction, a third and a fourth surface opposite to each other in the first direction orthogonal to the lamination direction, and a fifth and a sixth surface opposite to each other in the second direction orthogonal to both the lamination direction and the first direction; A first external electrode is disposed on the third surface of the laminate; and The second external electrode is disposed on the fourth surface of the laminate. The dimension l in the first direction of the laminate is shorter than the dimension w in the second direction of the laminate. The laminate has: The first internal electrode has one end exposed on the third surface; The second internal electrode, one end of which is exposed on the fourth surface; and An inner dielectric layer is provided with the first internal electrode and the second internal electrode. The inner dielectric layer, as a main component, contains at least: Ca, Sr, or Zr; and Li, In at least one of the following regions, a square region with a side length of 30 μm centered on half the dimension in the stacking direction and the interface between the stack and the first external electrode, and a square region with a side length of 30 μm centered on half the dimension in the stacking direction and the interface between the stack and the second external electrode, Li segregation exists in the first external electrode and / or the second external electrode, and the magnitude of Li segregation in the first external electrode and / or the second external electrode is greater than the magnitude of Li segregation in the inner dielectric layer.

2. The multilayer ceramic capacitor according to claim 1, wherein, The size of the Li segregation in at least one of the first external electrode and the second external electrode is 1.0 μm. 2 Above and 30.2μm 2 the following.

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