Half-bridge drive interlocking circuit

Abstract

The invention provides a half-bridge drive interlocking circuit, and a logic circuit is provided with a logic gate. Two input ends of the logic circuit respectively receive two control signals; the two control signals are in one-to-one correspondence with two switch tubes in the half-bridge circuit; when the two control signals are turn-on signals, the two output ends of the logic circuit output turn-off signals. A first output end of the logic circuit is connected with a control end of a first switching tube in the half-bridge circuit through a first driving circuit; a second output end of the logic circuit is connected with a control end of a second switching tube in the half-bridge circuit through a second driving circuit; namely, the logic circuit is built through the logic gate, the phenomenon of high-temperature attenuation caused by the adoption of an optical device is avoided, the logic circuit is not affected by the high-temperature environment, good performance stability can still be kept in the high-temperature environment, the signal transmission efficiency is high, and the driving accuracy and the reliability and safety of the system are improved.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of power electronics, and more particularly relates to a half-bridge drive interlocking circuit. BACKGROUND

[0002] With the acceleration of global energy transformation and the full arrival of the electrification era, high-power converters, as the key link between clean energy and terminal applications, are becoming increasingly important. New energy electric drive, port shore power and future multi-electric aircraft require higher power and more intelligent high-power converters. As the core of high-power intelligent power modules, they not only need to carry strong driving capability, but also need to integrate perfect protection mechanisms to ensure efficient and stable operation of the system. Currently, high-voltage power supply and high-frequency operation strategy are used to improve conversion efficiency, and silicon carbide (SiC) switching tubes with low resistance and high frequency characteristics are preferred. However, efficient driving of SiC switching tubes, especially at high bus voltage, requires the design of an isolated drive circuit to prevent bridge arm shoot-through and ensure system safety.

[0003] Currently, the use of primary-side optocoupler interlocking function solves the problem of complementary and shoot-through prevention of the drive signal in a high-power converter. The complementary control of the signal is realized by connecting two optocouplers in series. Specifically, the low end of optocoupler 1 is connected to the high end of optocoupler 2 to form an interlocking link. When only one of PWM signal 1 and PWM signal 2 is high, the corresponding optocoupler will be activated and turned on, thereby ensuring that the upper and lower switching tubes of the same bridge arm will not be turned on at the same time, effectively preventing the occurrence of shoot-through phenomenon.

[0004] Although this method can achieve the expected complementary effect of the drive signal, the use of optocouplers in a high-temperature environment for a long time has poor performance stability, resulting in a decrease in signal transmission efficiency and even attenuation, which may eventually cause drive failure and affect the reliability and safety of the entire system. SUMMARY

[0005] Therefore, the purpose of the present application is to provide a half-bridge drive interlocking circuit for improving the driving accuracy, reliability and safety of the system.

[0006] The present application discloses a half-bridge drive interlocking circuit, comprising: a logic circuit, a first drive circuit, a second drive circuit and a half-bridge circuit.

[0007] The logic circuit is provided with a logic gate;

[0008] Two input ends of the logic circuit receive two control signals respectively; the two control signals correspond one-to-one to two switching tubes in the half-bridge circuit; when both control signals are on signals, both output ends of the logic circuit output off signals;

[0009] a first output terminal of the logic circuit is connected with a control terminal of a first switch tube in the half-bridge circuit through the first driving circuit;

[0010] a second output terminal of the logic circuit is connected with a control terminal of a second switch tube in the half-bridge circuit through the second driving circuit.

[0011] Optionally, the logic circuit comprises a first logic sub-circuit and a second logic sub-circuit.

[0012] a first input terminal of the first logic sub-circuit and a first input terminal of the second logic sub-circuit respectively receive a first control signal;

[0013] a second input terminal of the first logic sub-circuit and a second input terminal of the second logic sub-circuit respectively receive a second control signal;

[0014] an output terminal of the first logic sub-circuit is connected with a third input terminal of the second logic sub-circuit;

[0015] two output terminals of the second logic sub-circuit are respectively two output terminals of the logic circuit;

[0016] the first logic sub-circuit adopts OR logic, and the second logic sub-circuit adopts XOR logic.

[0017] Optionally, the first logic sub-circuit comprises a logic OR gate.

[0018] a first input terminal of the logic OR gate is a first input terminal of the first logic sub-circuit;

[0019] a second input terminal of the logic OR gate is a second input terminal of the second logic sub-circuit;

[0020] an output terminal of the logic OR gate is an output terminal of the first logic sub-circuit.

[0021] Optionally, the second logic sub-circuit comprises a first logic XOR gate and a second logic XOR gate.

[0022] a first input terminal of the first logic XOR gate is a first input terminal of the second logic sub-circuit;

[0023] a first input terminal of the second logic XOR gate is a second input terminal of the second logic sub-circuit;

[0024] a second input terminal of the first logic XOR gate and a second input terminal of the second logic XOR gate are connected, and a connection point is a third input terminal of the second logic sub-circuit;

[0025] The output end of the first logic exclusive OR gate is the first output end of the second logic sub-circuit;

[0026] The output end of the second logic exclusive OR gate is the second output end of the second logic sub-circuit.

[0027] Optionally, the circuit further comprises a pull-up circuit;

[0028] Both input ends of the logic circuit are connected to the power supply through the pull-up circuit.

[0029] Optionally, the pull-up circuit comprises a first pull-up resistor and a second pull-up resistor;

[0030] The first input end of the logic circuit is connected to the power supply through the first pull-up resistor;

[0031] The second input end of the logic circuit is connected to the power supply through the second pull-up resistor.

[0032] Optionally, the circuit further comprises a filter circuit;

[0033] The filter circuit is arranged at the two input ends of the logic circuit.

[0034] Optionally, the filter circuit comprises a first filter sub-circuit and a second filter sub-circuit;

[0035] The first filter sub-circuit is arranged between the first input end of the first logic sub-circuit and the first input end of the second logic sub-circuit in the logic circuit;

[0036] The second filter sub-circuit is arranged between the second input end of the first logic sub-circuit and the second input end of the second logic sub-circuit in the logic circuit.

[0037] Optionally, the first filter sub-circuit comprises a first filter capacitor and a first filter resistor;

[0038] One end of the first filter resistor is connected to the first input end of the first logic sub-circuit;

[0039] One end of the first filter capacitor and the other end of the first filter resistor are connected, and the connection point is connected to the first input end of the second logic sub-circuit;

[0040] The other end of the first filter capacitor is grounded.

[0041] Optionally, the second filter sub-circuit comprises a second filter capacitor and a second filter resistor;

[0042] One end of the second filter resistor is connected to the second input end of the first logic sub-circuit;

[0043] One end of the second filter capacitor is connected with the other end of the second filter resistor, and the connection point is connected with the second input end of the second logic sub-circuit;

[0044] The other end of the second filter capacitor is grounded.

[0045] From the above technical solution, the application provides a half-bridge drive interlocking circuit, wherein a logic gate is arranged in the logic circuit; two input ends of the logic circuit receive two control signals respectively; the two control signals correspond to two switch tubes in the half-bridge circuit one by one; when the two control signals are both on signals, two output ends of the logic circuit output off signals; a first output end of the logic circuit is connected with a control end of a first switch tube in the half-bridge circuit through a first drive circuit; a second output end of the logic circuit is connected with a control end of a second switch tube in the half-bridge circuit through a second drive circuit; that is, the logic circuit is built by the logic gate, the decay phenomenon caused by high temperature is avoided due to the use of optical devices, the logic circuit is not affected by the high temperature environment, and the performance stability is still good in the high temperature environment, the signal transmission efficiency is high, the driving accuracy, the reliability and the safety of the system are improved. BRIEF DESCRIPTION OF DRAWINGS

[0046] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or the prior art description. Obviously, the drawings in the following description are some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without creative labor.

[0047] Figure 1 is a schematic diagram of a half-bridge drive interlocking circuit provided by an embodiment of the present application;

[0048] Figure 2 is a schematic diagram of another half-bridge drive interlocking circuit provided by an embodiment of the present application;

[0049] Figure 3 is a schematic diagram of another half-bridge drive interlocking circuit provided by an embodiment of the present application. DETAILED DESCRIPTION

[0050] In order to make the purpose, technical solutions and advantages of the embodiments of the present application more clear, the technical solutions in the embodiments of the present application will be described clearly and completely in the following with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are some embodiments of the present application, not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor are within the protection scope of the present application.

[0051] In this application, the terms "comprising," "including," or any other variations thereof are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element. Furthermore, the terms "first," "second," "third," "fourth," etc. (if present) in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a particular order or sequence. It should be understood that such data used can be interchanged where appropriate so that embodiments of this application described herein can be implemented, for example, in orders other than those illustrated or described herein.

[0052] This application provides a half-bridge drive interlock circuit to solve the problem that in the prior art, the performance stability of optocouplers is poor when they work in high-temperature environments for a long time, which leads to a decrease in signal transmission efficiency and even attenuation, which may eventually cause drive failure and affect the reliability and safety of the entire system.

[0053] See Figure 1 The half-bridge drive interlock circuit includes: logic circuit 10, first drive circuit 20, second drive circuit 30 and half-bridge circuit 40.

[0054] The logic circuit 10 includes logic gates. Logic gates are hardware devices, meaning that the logic circuit 10 can be constructed using appropriate logic gates. Commonly used logic gates include AND gates, OR gates (U1), NOT gates, XOR gates, and XNOR gates, etc., which will not be elaborated here. The choice depends on the specific circumstances and is within the scope of protection of this application.

[0055] The two input terminals of logic circuit 10 receive two control signals respectively.

[0056] The two control signals correspond one-to-one with the two switching transistors in the half-bridge circuit 40.

[0057] Specifically, the first input end of the logic circuit 10 receives a first control signal PWM1, which is used to control the on-off of the second switch tube Q2 in the half-bridge circuit 40; the second input end of the logic circuit 10 receives a second control signal PWM2, which is used to control the on-off of the first switch tube Q1 in the half-bridge circuit 40; the first switch tube Q1 can be an upper tube; and the second switch tube Q2 can be a lower tube. The first control signal PWM1 and the second control signal PWM2 can both be PWM (Pulse Width Modulation) signals, for example, the first control signal PWM1 is a PWM signal 1; and the second control signal PWM2 is a PWM signal 2.

[0058] In the half-bridge circuit 40, one end of the first switch tube Q1 is connected to the power supply VDD; the control end of the first switch tube Q1 serves as the first control end of the half-bridge circuit 40 and is connected to the output end of the first driving circuit 20; the other end of the first switch tube Q1 is connected to one end of the second switch tube Q2; the other end of the second switch tube Q2 is grounded; and the control end of the second switch tube Q2 serves as the second control end of the half-bridge circuit 40.

[0059] When both control signals are on signals, both output ends of the logic circuit 10 output off signals.

[0060] That is to say, when both control signals are on signals, if the upper and lower tubes of the half-bridge circuit 40 are turned on according to the control signals, the upper and lower tubes of the half-bridge circuit 40 will be directly connected, that is, the bridge arm is directly connected, which will cause damage or failure of the system; therefore, when both control signals are on signals, the logic circuit 10 changes the control signals and outputs off signals, so that the upper and lower tubes of the half-bridge circuit 40 are both turned off, avoiding the situation of bridge arm direct connection.

[0061] The first output end of the logic circuit 10 is connected to the control end of the first switch tube Q1 in the half-bridge circuit 40 through the first driving circuit 20; specifically, the first output end of the logic circuit 10 is connected to one end of the first driving circuit 20, and the other end of the first driving circuit 20 is connected to the control end of the first switch tube Q1.

[0062] The second output end of the logic circuit 10 is connected to the control end of the second switch tube Q2 in the half-bridge circuit 40 through the second driving circuit 30; specifically, the second output end of the logic circuit 10 is connected to one end of the second driving circuit 30, and the other end of the second driving circuit 30 is connected to the control end of the second switch tube Q2.

[0063] Specifically, when two control signals are not conductive signals, the signal output from the output end of the logic circuit 10 is consistent with the signal output from the input end, that is, the output signal tracks the input signal. For example, the signal output from the first output end of the logic circuit 10 is named as the first output signal, and the signal output from the second output end of the logic circuit 10 is named as the second output signal. When two control signals are not conductive signals, the first output signal tracks the second control signal PWM2, and the first output signal and the second control signal PWM2 remain consistent; the second output signal tracks the first control signal PWM1, and the second output signal and the first control signal PWM1 remain consistent. The specific logic of the logic circuit 10 is shown in Table 1:

[0064] Table 1: Input and output logic of the logic circuit 10

[0065]

[0066] Wherein, 1 represents a conductive signal, that is, a high-level conduction, and 0 represents an off signal, that is, a low-level off. That is, when the upper and lower tube pulse signals are high at the same time, the upper and lower tubes are interlocked through the logic operation of the logic circuit 10, and the protection function is achieved.

[0067] The half-bridge drive interlocking circuit can be applied to occasions where the bus voltage is relatively high and the working power is required to be relatively high, for example, applied to a high-power converter, to solve the drive circuit occasion where the upper and lower tubes of the same bridge arm of the high-power converter exist shoot-through phenomenon. Of course, it is not excluded to be applied to other fields, which will not be described one by one here.

[0068] In the embodiment, the logic circuit 10 is provided with a logic gate; two input ends of the logic circuit 10 receive two control signals respectively; the two control signals correspond to two switching tubes in the half-bridge circuit 40 one by one; when the two control signals are conductive signals, the two output ends of the logic circuit 10 output off signals; the first output end of the logic circuit 10 is connected with the control end of the first switching tube Q1 in the half-bridge circuit 40 through the first drive circuit 20; the second output end of the logic circuit 10 is connected with the control end of the second switching tube Q2 in the half-bridge circuit 40 through the second drive circuit 30; that is, the logic circuit 10 is built by the logic gate, avoiding the attenuation phenomenon caused by high temperature when the optical device is used, the logic circuit 10 is not affected by the high temperature environment, and can still maintain good performance stability in the high temperature environment, the signal transmission efficiency is relatively high, the driving accuracy, the reliability and the safety of the system are improved.

[0069] It should be noted that the prior art relies on two optical couplings to realize signal isolation and interlocking, which increases the complexity and cost of the system. Moreover, each optical coupling needs sufficient driving capability to work normally, which further increases the design difficulty of the drive circuit.

[0070] In the embodiment, the isolation and interlocking can be realized by using the logic gate and the driving circuit, the complexity and cost of the system are reduced, the driving circuit does not need large driving capacity, the conventional driving signal can realize the driving, and the design difficulty of the driving circuit is reduced.

[0071] Optionally, referring to Figure 2 The logic circuit 10 includes a first logic sub-circuit 11 and a second logic sub-circuit 12.

[0072] The first input end of the first logic sub-circuit 11 and the first input end of the second logic sub-circuit 12 respectively receive the first control signal PWM1.

[0073] Specifically, the first input end of the first logic sub-circuit 11 and the first input end of the second logic sub-circuit 12 are connected, and the connection point is used as the first input end of the logic circuit 10 to receive the first control signal PWM1.

[0074] The second input end of the first logic sub-circuit 11 and the second input end of the second logic sub-circuit 12 respectively receive the second control signal PWM2.

[0075] Specifically, the second input end of the first logic sub-circuit 11 and the second input end of the second logic sub-circuit 12 are connected, and the connection point is used as the second input end of the logic circuit 10 to receive the second control signal PWM2.

[0076] The output end of the first logic sub-circuit 11 is connected with the third input end of the second logic sub-circuit 12; that is, the output signal of the first logic sub-circuit 11 affects the output signal of the second logic sub-circuit 12.

[0077] The two output ends of the second logic sub-circuit 12 are respectively used as the two output ends of the logic circuit 10; specifically, the first output end of the second logic sub-circuit 12 is used as the first output end of the logic circuit 10 and is connected with the control end of the first switch tube Q1 through the first driving circuit 20; the second output end of the second logic sub-circuit 12 is used as the second output end of the logic circuit 10 and is connected with the control end of the second switch tube Q2 through the second driving circuit 30.

[0078] The first logic sub-circuit 11 adopts OR logic, and the second logic sub-circuit 12 adopts XOR logic.

[0079] That is, when at least one of the first control signal PWM1 and the second control signal PWM2 is a conduction signal, the first logic sub-circuit 11 outputs a conduction signal. In the second logic sub-circuit 12, the signal of the first output end is obtained by performing XOR operation on the first control signal PWM1 and the signal output by the first logic sub-circuit 11; and the signal of the second output end is obtained by performing XOR operation on the second control signal PWM2 and the signal output by the first logic sub-circuit 11.

[0080] Specifically, the logic of the first logic sub-circuit 11 is shown in Table 2:

[0081] Table 2: Input and output logic of the first logic sub-circuit 11

[0082]

[0083] Specifically, the logic of the second logic sub-circuit 12 is shown in Table 3:

[0084] Table 3: Input and output logic of the second logic sub-circuit 12

[0085]

[0086] That is, the output signal of the second logic sub-circuit 12 tracks the control signal.

[0087] Optionally, referring to Figure 3 , the first logic sub-circuit 11 includes a logic OR gate U1.

[0088] The first input end of the logic OR gate U1 serves as the first input end of the first logic sub-circuit 11 and receives the first control signal PWM1. The second input end of the logic OR gate U1 serves as the second input end of the second logic sub-circuit 12 and receives the second control signal PWM2. The output end of the logic OR gate U1 serves as the output end of the first logic sub-circuit 11 and is connected to the third input end of the second logic sub-circuit 12.

[0089] Specifically, in the logic OR gate U1: when one of the input ends is 1, the output is 1, and only when all the input ends are 0, the output is 0, which realizes the logic OR function. Its logic formula is: Y1=A1+B1; wherein Y1 is the output signal of the logic OR gate U1; A1 is one of the input signals of the logic OR gate U1, which can be the first control signal PWM1; B1 is the other input signal of the logic OR gate U1, which can be the second control signal PWM2.

[0090] The truth table of the logic OR gate U1 is shown in Table 4:

[0091] Table 4: Truth table of the logic OR gate U1

[0092]

[0093] That is, the specific logic of Table 4 and Table 2 is the same.

[0094] Optionally, referring to Figure 3 , the second logic sub-circuit 12 includes: a first logic XOR gate U2 and a second logic XOR gate U3.

[0095] The first input end of the first logic exclusive-OR gate U2 is connected to the first input end of the second logic sub-circuit 12 and receives the first control signal PWM1.

[0096] The first input end of the second logic exclusive-OR gate U3 is connected to the second input end of the second logic sub-circuit 12 and receives the second control signal PWM2.

[0097] The second input end of the first logic exclusive-OR gate U2 is connected to the second input end of the second logic exclusive-OR gate U3, and the connection point is connected to the third input end of the second logic sub-circuit 12 and receives the output signal of the first logic sub-circuit 11.

[0098] The output end of the first logic exclusive-OR gate U2 is connected to the first output end of the second logic sub-circuit 12 and is connected to the control end of the first switch tube Q1 through the first driving circuit 20.

[0099] The output end of the second logic exclusive-OR gate U3 is connected to the second output end of the second logic sub-circuit 12 and is connected to the control end of the second switch tube Q2 through the second driving circuit 30.

[0100] That is, the second logic sub-circuit 12 includes two logic chips, and the functions of the two logic chips are the same; specifically, for any one logic chip in the second logic sub-circuit 12, if the logic states of the two input ends are different, the output end outputs high; if the logic states of the two input ends are the same, for example, both high or both low, the output is 0 (low). The logic formula is:

[0101]

[0102] Wherein, Y1 is the output signal of the logic OR gate U1; A1 is the first control signal PWM1, the signal after the first control signal PWM1 is logically negated; B1 is the second control signal PWM2; the signal after the second control signal PWM2 is logically negated; Y2 is the output signal of the first logic exclusive-OR gate U2; Y3 is the output signal of the second logic exclusive-OR gate U3.

[0103] In this embodiment, the logic gate is used so that the digital logic circuit 10 processes the signal, and the two output ends of the logic circuit 10 drive the switch tubes through two driving circuits, that is, the driving signals of the two switch tubes are isolated through different driving circuits. The digital isolator with capacitive isolation can be used for isolation in the driving circuit, avoiding the use of optical devices. There is no attenuation phenomenon of optical devices under high temperature, which increases the reliability of the driving circuit working in a complex environment, thereby improving the stability of the entire system.

[0104] The following will be described according to Figure 3The circuit diagram shows the working process of the half-bridge drive interlocking circuit.

[0105] When the first control signal PWM1 is high and the second control signal PWM2 is low, Y1 is high through the logic formula Y1=A1+B1, and since Therefore, Y2=0, and the first switch tube Q1 is off, and since Therefore, Y3=1, and the second switch tube Q2 is on.

[0106] When the first control signal PWM1 is low and the second control signal PWM2 is high, Y1 is high through the logic formula Y1=A1+B1, and since Therefore, Y2=1, and Q1 is on, and since Therefore, Y3=0, and Q2 is off.

[0107] When the first control signal PWM1 is high and the second control signal PWM2 is high, Y1 is high through the logic formula Y1=A1+B1, and since Therefore, Y2=0, and the first switch tube Q1 is off, and since Therefore, Y3=0, and the second switch tube Q2 is off.

[0108] When the first control signal PWM1 is low and the second control signal PWM2 is low, Y1 is low through the logic formula Y1=A1+B1, and since Therefore, Y2=0, and the first switch tube Q1 is off, and since Therefore, Y3=0, and the second switch tube Q2 is off.

[0109] Optionally, the pull-up circuit is further included.

[0110] Both input ends of the logic circuit 10 are connected to the power supply VCC through the pull-up circuit.

[0111] Specifically, the first input end of the logic circuit 10 is connected to the first end of the pull-up circuit, and the second end of the pull-up circuit is connected to the power supply VCC; the second input end of the logic circuit 10 is connected to the third end of the pull-up circuit, and the fourth end of the pull-up circuit is connected to the power supply VCC.

[0112] Optionally, referring to Figure 3 The pull-up circuit includes a first pull-up resistor R1 and a second pull-up resistor R2.

[0113] The first input end of the logic circuit 10 is connected to the power supply VCC through the first pull-up resistor R1; specifically, the first input end of the logic circuit 10 is connected to one end of the first pull-up resistor R1, and the other end of the first pull-up resistor R1 is connected to the power supply VCC.

[0114] The second input end of the logic circuit 10 is connected to the power supply VCC through the second pull-up resistor R2; specifically, the second input end of the logic circuit 10 is connected to one end of the second pull-up resistor R2, and the other end of the second pull-up resistor R2 is connected to the power supply VCC.

[0115] The first pull-up resistor R1 and the second pull-up resistor R2 play a pull-up role, mainly to prevent the switch tube from being misdirected on when there are interference signals in the input of the first control signal PWM1 and the second control signal PWM2; the two pull-up resistors can be small power resistors with a resistance value of 5k to 10k, of course, resistors with other resistance values are not excluded.

[0116] Optionally, it further includes a filter circuit.

[0117] The filter circuit is arranged at the two input ends of the logic circuit 10. The filter circuit is used to filter out interference of the two control signals of the logic circuit 10.

[0118] The functions of the filter circuit are reflected in the following aspects:

[0119] Noise removal: The filter circuit can effectively filter out noise components in the signal, which may come from power supply fluctuations, electromagnetic interference, crosstalk in the signal transmission process, etc. By filtering out these noises, the filter circuit can significantly improve the signal-to-noise ratio of the signal, so that the subsequent circuit can more accurately process and analyze the signal.

[0120] Signal shaping: In some cases, the signal may be distorted due to transmission path or source signal itself. The filter circuit can shape the signal through its specific frequency response characteristics, so that it restores to a shape closer to the original signal, thereby ensuring the integrity and accuracy of the signal.

[0121] Frequency selection: The filter circuit has the function of frequency selection, which can selectively pass or block signals in a specific frequency range as needed. This is particularly important for signal separation, frequency band division, etc., so that signals of different frequencies can be processed or transmitted in a predetermined manner.

[0122] Protection circuit: In some cases, the filter circuit can also act as a protection circuit. For example, by adding a filter circuit at the power input, high-frequency noise and surge voltage in the power supply can be filtered out, protecting the subsequent circuit from damage.

[0123] Improve system performance: By reasonably designing the filter circuit, the performance of the entire electronic system can be optimized. For example, in a communication system, by accurately controlling the bandwidth and attenuation characteristics of the filter circuit, the transmission efficiency and reception quality of the signal can be improved; in a control system, the filter circuit can ensure the stability and accuracy of the control signal, thereby improving the control accuracy and response speed of the system.

[0124] The setting of the filter circuit ensures that the logic circuit 10 can receive pure and stable signal input, thereby effectively avoiding the adverse effects of external noise or signal distortion on the performance of the circuit, and ensuring the stable operation and accurate judgment of the logic circuit 10.

[0125] Optionally, the filter circuit comprises a first filter sub-circuit and a second filter sub-circuit.

[0126] The first filter sub-circuit is arranged between the first input end of the first logic sub-circuit 11 and the first input end of the second logic sub-circuit 12 in the logic circuit 10.

[0127] Specifically, one end of the first filter sub-circuit is connected to the first input end of the first logic sub-circuit 11, and the other end of the first filter sub-circuit is connected to the first input end of the second logic sub-circuit 12.

[0128] The second filter sub-circuit is arranged between the second input end of the first logic sub-circuit 11 and the second input end of the second logic sub-circuit 12 in the logic circuit 10.

[0129] Specifically, one end of the second filter sub-circuit is connected to the second input end of the first logic sub-circuit 11, and the other end of the second filter sub-circuit is connected to the second input end of the second logic sub-circuit 12.

[0130] That is, the first filter sub-circuit and the second filter sub-circuit respectively filter the first control signal PWM1 and the second control signal PWM2.

[0131] Optionally, referring to Figure 3 , the first filter sub-circuit comprises a first filter capacitor C1 and a first filter resistor R3.

[0132] One end of the first filter resistor R3 is connected to the first input end of the first logic sub-circuit 11.

[0133] One end of the first filter capacitor C1 and the other end of the first filter resistor R3 are connected, and the connection point is connected to the first input end of the second logic sub-circuit 12.

[0134] The other end of the first filter capacitor C1 is grounded.

[0135] That is, the first filter resistor R3 and the first filter capacitor C1 form a first RC filter network, which mainly eliminates interference signals in the driving signal (control signal) to ensure the purity and stability of the signal.

[0136] Optionally, referring to Figure 3 , the second filter sub-circuit comprises a second filter capacitor C2 and a second filter resistor R4.

[0137] One end of the second filter resistor R4 is connected with the second input end of the first logic sub-circuit 11.

[0138] One end of the second filter capacitor C2 and the other end of the second filter resistor R4 are connected, and the connection point is connected with the second input end of the second logic sub-circuit 12.

[0139] The other end of the second filter capacitor C2 is grounded.

[0140] That is, the second filter resistor R4 and the second filter capacitor C2 form a second RC filter network, which mainly eliminates the interference signal in the driving signal (control signal), ensures the purity and stability of the signal, and provides more clear and reliable signal input for the system.

[0141] The features described in each of the embodiments in the specification can be replaced with each other or combined, and the same or similar parts between each of the embodiments can be referred to each other, and each of the embodiments mainly describes the difference from other embodiments. Especially, for the system or system embodiments, since it is basically similar to the method embodiments, it is described more simply, and the related parts can refer to the part of the method embodiments. The above described system and system embodiments are only illustrative, wherein the units described as separate components can be or can not be physically separated, and the components displayed as units can be or can not be physical units, that is, they can be located in one place, or can be distributed on multiple network units. According to the actual needs, part or all of the modules can be selected to achieve the purpose of the embodiment scheme. Those skilled in the art can understand and implement without creative labor.

[0142] The skilled person can further realize that the units and algorithm steps of each example described in combination with the embodiments disclosed in the present text can be realized in electronic hardware, computer software or combination of both. In order to clearly show the interchangeability of hardware and software, the composition and steps of each example have been described in the above description. Whether the functions are realized in hardware or software depends on the specific application and design constraints of the technical scheme. The skilled person can use different methods to realize the described functions for each specific application, but such implementation should not be considered beyond the scope of the present application.

[0143] The foregoing description of the disclosed embodiments enables a person skilled in the art to make or use the application. Modifications of these embodiments will occur to persons of skill in the art, and that the appended claims are intended to cover all such modifications that do not depart from the true spirit and scope of the application. Therefore, the application is not limited to the embodiments shown but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A half-bridge drive interlock circuit, characterized in that, include: Logic circuit, first driver circuit, second driver circuit, and half-bridge circuit; The logic circuit is equipped with logic gates; The two input terminals of the logic circuit receive two control signals respectively; the two control signals correspond one-to-one with the two switching transistors in the half-bridge circuit; when both control signals are on signals, the two output terminals of the logic circuit output off signals. The first output terminal of the logic circuit is connected to the control terminal of the first switching transistor in the half-bridge circuit through the first driving circuit. The second output terminal of the logic circuit is connected to the control terminal of the second switching transistor in the half-bridge circuit through the second driving circuit.

2. The half-bridge drive interlock circuit according to claim 1, characterized in that, The logic circuit includes: a first logic sub-circuit and a second logic sub-circuit; The first input terminal of the first logic sub-circuit and the first input terminal of the second logic sub-circuit respectively receive the first control signal; The second input terminal of the first logic sub-circuit and the second input terminal of the second logic sub-circuit respectively receive the second control signal; The output terminal of the first logic sub-circuit is connected to the third input terminal of the second logic sub-circuit; The two output terminals of the second logic sub-circuit are respectively used as the two output terminals of the logic circuit; The first logic sub-circuit uses OR logic, and the second logic sub-circuit uses XOR logic.

3. The half-bridge drive interlock circuit according to claim 2, characterized in that, The first logic sub-circuit includes a logic OR gate; The first input terminal of the logic OR gate serves as the first input terminal of the first logic sub-circuit. The second input terminal of the OR gate serves as the second input terminal of the second logic sub-circuit. The output of the OR gate serves as the output of the first logic sub-circuit.

4. The half-bridge drive interlock circuit according to claim 2, characterized in that, The second logic sub-circuit includes: a first logic XOR gate and a second logic XOR gate; The first input terminal of the first logic XOR gate is used as the first input terminal of the second logic sub-circuit. The first input terminal of the second logic XOR gate serves as the second input terminal of the second logic sub-circuit; The second input terminal of the first logic XOR gate is connected to the second input terminal of the second logic XOR gate, and the connection point serves as the third input terminal of the second logic sub-circuit. The output of the first logic XOR gate is used as the first output of the second logic sub-circuit. The output of the second logic XOR gate serves as the second output of the second logic sub-circuit.

5. The half-bridge drive interlock circuit according to claim 1, characterized in that, It also includes pull-up circuits; Both inputs of the logic circuit are connected to the power supply via the pull-up circuit.

6. The half-bridge drive interlock circuit according to claim 5, characterized in that, The pull-up circuit includes: a first pull-up resistor and a second pull-up resistor; The first input terminal of the logic circuit is connected to the power supply through the first pull-up resistor; The second input terminal of the logic circuit is connected to the power supply through the second pull-up resistor.

7. The half-bridge drive interlock circuit according to claim 1, characterized in that, Also includes: Filtering circuit; The filter circuit is located at both input terminals of the logic circuit.

8. The half-bridge drive interlock circuit according to claim 7, characterized in that, The filtering circuit includes: a first filtering sub-circuit and a second filtering sub-circuit; The first filter sub-circuit is disposed between the first input terminal of the first logic sub-circuit and the first input terminal of the second logic sub-circuit in the logic circuit; The second filter sub-circuit is disposed between the second input terminal of the first logic sub-circuit and the second input terminal of the second logic sub-circuit in the logic circuit.

9. The half-bridge drive interlock circuit according to claim 8, characterized in that, The first filter sub-circuit includes: a first filter capacitor and a first filter resistor; One end of the first filter resistor is connected to the first input terminal of the first logic sub-circuit; One end of the first filter capacitor is connected to the other end of the first filter resistor, and the connection point is connected to the first input terminal of the second logic sub-circuit. The other end of the first filter capacitor is grounded.

10. The half-bridge drive interlock circuit according to claim 8, characterized in that, The second filter sub-circuit includes: a second filter capacitor and a second filter resistor; One end of the second filter resistor is connected to the second input terminal of the first logic sub-circuit; One end of the second filter capacitor is connected to the other end of the second filter resistor, and the connection point is connected to the second input terminal of the second logic sub-circuit. The other end of the second filter capacitor is grounded.

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