Voltage-sharing control method and device, electronic equipment and storage medium
By employing two independent control units in the half-bridge circuit to generate duty cycle signals for the switching devices, the problems of circuit oscillation and insufficient current control in the prior art are solved, achieving stable and efficient voltage equalization regulation and circuit protection.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2022-11-28
- Publication Date
- 2026-03-27
AI Technical Summary
In the prior art, single-phase unbalanced bridge arm control is prone to circuit oscillation during voltage equalization regulation and cannot effectively control the current, resulting in damage to circuit components and failing to maintain superior performance during short-term overpower regulation and start-up regulation.
By employing two independent control units in the half-bridge circuit to generate duty cycle signals for the switching devices, and determining the given current for each control unit based on the DC bus voltage difference, voltage difference reference value, and reference current range, the ripple generation of the switching devices is independently controlled, thereby achieving stable and efficient voltage regulation.
It enables independent control and regulation of the half-bridge circuit, avoids back-and-forth oscillations during voltage equalization regulation, protects circuit components, allows short-term over-power regulation, and ensures the circuit's voltage regulation performance in normal steady state and instantaneous over-power.
Smart Images
Figure CN121749708A_ABST
Abstract
Description
[0001] This application is a divisional application of the invention patent application filed on November 28, 2022, with application number 2022115055317 and title "Equalizing Pressure Control Method, Device, Electronic Equipment and Storage Medium". Technical Field
[0002] This application relates to the field of power electronics technology, and more specifically, to a voltage equalization control method, device, electronic device, and storage medium. Background Technology
[0003] For voltage equalization control of converters, multi-stage capacitors or converter modules are generally connected in series to achieve voltage equalization in the system corresponding to the converter. The series capacitors or series converter modules need to consider voltage equalization control under various operating conditions.
[0004] In the existing technology, single-phase unbalanced bridge arm control is used for voltage equalization control. Although this method is based on the voltage difference for voltage equalization control, adjusting solely based on the voltage difference can easily cause circuit oscillation during the voltage equalization adjustment process, and the current in the circuit cannot be controlled, making the circuit components prone to damage. Summary of the Invention
[0005] The purpose of this application is to address the shortcomings of the prior art by providing a pressure equalization control method, device, electronic equipment, and storage medium to achieve stable and efficient pressure regulation.
[0006] To achieve the above objectives, the technical solutions adopted in the embodiments of this application are as follows: In a first aspect, embodiments of this application provide a pressure equalization control method, the method comprising: Obtain the DC bus voltage difference in the half-bridge circuit; Based on the DC bus voltage difference, a duty cycle signal for a first switching device in the first control unit is generated based on the first control unit; based on the DC bus voltage difference, a duty cycle signal for a second switching device in the second control unit is generated based on the second control unit. The half-bridge circuit is subjected to voltage equalization control based on the duty cycle signals of the first and second switching devices. The step of generating a duty cycle signal for a first switching device in a first control unit based on the DC bus voltage difference, and generating a duty cycle signal for a second switching device in a second control unit based on a second control unit, includes: The given current of the first control unit is determined based on the DC bus voltage difference, the voltage difference reference value, and the reference current range; the given current of the second control unit is determined based on the DC bus voltage difference, the voltage difference reference value, and the reference current range. Based on the given current of the first control unit, the inductor current loop on the first control unit is controlled to output a corresponding first electrical signal, and the duty cycle signal of the first control unit is generated based on the first electrical signal. Based on the limiting current of the second control unit, the inductor current loop on the second control unit is controlled to output a corresponding second electrical signal. Based on the second electrical signal, an initial duty cycle signal of the second control unit is generated, and the initial duty cycle signal is inverted to generate the duty cycle signal of the second control unit. The duty cycle signal of the first control unit is input to the first control unit to control the first switching device to block or transmit a wave, and the duty cycle signal of the second control unit is input to the second control unit to cause the second switching device to block or transmit a wave.
[0007] Optional, also includes: Determine the target given current based on the given currents of the first control unit and the second control unit; Based on the target given current, control the target inductor current loop to output the corresponding third electrical signal, and generate the target duty cycle signal based on the third electrical signal; Based on the target duty cycle signal, the duty cycle signals of the first control unit and the second control unit are generated respectively.
[0008] Optionally, generating the duty cycle signal of the first control unit and the duty cycle signal of the second control unit based on the target duty cycle signal includes: The target duty cycle signal is used as the duty cycle signal of the first control unit; The inverted target duty cycle signal is used as the duty cycle signal of the second control unit.
[0009] Secondly, embodiments of this application also provide a pressure equalization control device, the device comprising: The acquisition module is used to acquire the DC bus voltage difference in the half-bridge circuit; The generation module is used to generate a duty cycle signal of a first switching device in the first control unit based on the DC bus voltage difference and a first control unit, and to generate a duty cycle signal of a second switching device in the second control unit based on the DC bus voltage difference and a second control unit. The control module is used to perform voltage equalization control on the half-bridge circuit based on the duty cycle signal of the first switching device and the duty cycle signal of the second switching device. The generation module is specifically used for: The given current of the first control unit is determined based on the DC bus voltage difference, the voltage difference reference value, and the reference current range; the given current of the second control unit is determined based on the DC bus voltage difference, the voltage difference reference value, and the reference current range. Based on the given current of the first control unit, the inductor current loop on the first control unit is controlled to output a corresponding first electrical signal, and the duty cycle signal of the first control unit is generated based on the first electrical signal. Based on the limiting current of the second control unit, the inductor current loop on the second control unit is controlled to output a corresponding second electrical signal. Based on the second electrical signal, an initial duty cycle signal of the second control unit is generated, and the initial duty cycle signal is inverted to generate the duty cycle signal of the second control unit. The duty cycle signal of the first control unit is input to the first control unit to control the first switching device to block or transmit a wave, and the duty cycle signal of the second control unit is input to the second control unit to cause the second switching device to block or transmit a wave.
[0010] Optionally, the generation module is specifically used for: Determine the target given current based on the given currents of the first control unit and the second control unit; Based on the target given current, control the target inductor current loop to output the corresponding third electrical signal, and generate the target duty cycle signal based on the third electrical signal; Based on the target duty cycle signal, the duty cycle signals of the first control unit and the second control unit are generated respectively.
[0011] Optionally, the generation module is specifically used for: The target duty cycle signal is used as the duty cycle signal of the first control unit; The inverted target duty cycle signal is used as the duty cycle signal of the second control unit.
[0012] Thirdly, embodiments of this application also provide an electronic device, including: a processor, a storage medium, and a bus, wherein the storage medium stores program instructions executable by the processor, and when the application runs, the processor communicates with the storage medium via the bus, and the processor executes the program instructions to perform the steps of the voltage equalization control method described in the first aspect.
[0013] Fourthly, embodiments of this application also provide a computer-readable storage medium storing a computer program, which is read and executes the steps of the voltage equalization control method described in the first aspect.
[0014] The beneficial effects of this application are: This application provides a voltage equalization control method, device, electronic device, and storage medium, which acquires the DC bus voltage difference in a half-bridge circuit; generates a duty cycle signal of a first switching device in a first control unit based on the DC bus voltage difference; generates a duty cycle signal of a second switching device in a second control unit based on the DC bus voltage difference; and performs voltage equalization on the half-bridge circuit based on the duty cycle signals of the first and second switching devices. This system allows for independent control of the switching devices in each control unit via two separate control units. This enables independent control and regulation of the voltage equalization in the half-bridge circuit, avoiding oscillations during voltage equalization and achieving stable and efficient voltage regulation. Furthermore, by determining the setpoint current for each control unit based on the DC bus voltage difference, voltage difference reference value, and reference current range, the current in each control unit is controlled, allowing for short-term overpower regulation and protecting the circuit components from damage. The system also generates duty cycle signals for each control unit based on its setpoint current, and each unit performs voltage equalization according to these signals. This independent control and regulation of each control unit further prevents oscillations during voltage equalization, achieving stable and efficient voltage regulation. Attached Figure Description
[0015] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.
[0016] Figure 1 A schematic diagram of a half-bridge balanced circuit provided in an embodiment of this application; Figure 2 This is a schematic diagram of an independent control loop architecture provided in the embodiments of this application; Figure 3 A schematic flowchart of a pressure equalization control method provided in an embodiment of this application; Figure 4 A flowchart illustrating another pressure equalization control method provided in this application embodiment; Figure 5An inductor current given amplitude time limiting curve provided in an embodiment of this application; Figure 6 This is a block diagram of a dual outer loop competition and switching logic loop according to an embodiment of this application; Figure 7 A schematic diagram of a process for generating a duty cycle signal is provided for an embodiment of this application; Figure 8 A pressure equalization control device provided in the embodiments of this application; Figure 9 This is a structural block diagram of an electronic device provided in an embodiment of this application. Detailed Implementation
[0017] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. It should be understood that the accompanying drawings in this application are for illustrative and descriptive purposes only and are not intended to limit the scope of protection of this application. Furthermore, it should be understood that the schematic drawings are not drawn to scale. The flowcharts used in this application illustrate operations implemented according to some embodiments of this application. It should be understood that the operations in the flowcharts may not be implemented in sequence, and steps without logical contextual relationships may be reversed or implemented simultaneously. In addition, those skilled in the art, guided by the content of this application, may add one or more other operations to the flowcharts, or remove one or more operations from the flowcharts.
[0018] Furthermore, the described embodiments are merely some, not all, of the embodiments of this application. The components of the embodiments of this application described and illustrated herein can typically be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.
[0019] It should be noted that the term "comprising" will be used in the embodiments of this application to indicate the presence of the features declared thereafter, but does not exclude the addition of other features.
[0020] For the high-voltage input or output terminals of the converter, multi-stage capacitors or converter modules are connected in series. The series capacitors or modules all require voltage equalization control under various operating conditions. Current technologies generally employ hardware or software, or a combination of both, for voltage equalization control. Hardware solutions include self-equalizing coupling topologies, external auxiliary power supplies, equalizing resistors, clamping regulators, or additional voltage equalization modules or converters. Software solutions use relevant control algorithms to adjust output power, or inject zero-sequence or DC components to regulate the energy of the upper and lower bus capacitors.
[0021] However, hardware voltage equalization solutions suffer from high losses, are bulky, and require additional control, while software voltage equalization solutions are less effective under special conditions such as light loads and half-wave loads.
[0022] Meanwhile, existing technical solutions also include voltage equalization schemes using half-bridge circuit control algorithms. In the control algorithm of the half-bridge module, the voltage difference is used to adjust the transmission duty cycle to achieve voltage equalization regulation. However, the voltage equalization control regulation of the existing technology only sends the corresponding duty cycle signal to perform voltage equalization regulation when the voltage difference is relatively large. When the voltage difference is small, no duty cycle signal is sent for voltage equalization regulation. Furthermore, the existing half-bridge module algorithm technology does not consider the current control problem in the circuit, and cannot protect the inductor current or circuit devices such as switches. At the same time, it cannot bring out the superior performance of the converter, such as being controlled during short-term overpower regulation or when starting the regulation circuit.
[0023] Therefore, this application provides a voltage equalization control method based on a half-bridge voltage equalization circuit. Each control loop independently performs voltage equalization adjustment, and a suitable voltage difference setpoint and limit value setting strategy is configured to control the circuit current, allow short-term over-power adjustment, fully meet the performance requirements of normal steady-state voltage regulation and instantaneous over-power voltage regulation, and the voltage equalization function is not activated within the normal fluctuation range. If the fluctuation range is exceeded, it can be automatically controlled to make the voltage equalization adjustment stable.
[0024] Figure 1 This is a schematic diagram of a half-bridge balancing circuit provided in an embodiment of this application. The voltage equalization control method in this application is based on this half-bridge balancing circuit, and controls the output duty cycle of the power switching devices in the half-bridge balancing circuit respectively. The power switching devices are as follows: Figure 1 The field-effect transistors Q1 and Q2 in the diagram; specifically, such as... Figure 2 The diagram shown is a schematic of a control unit architecture provided in an embodiment of this application, in which each control unit controls, for example... Figure 1Specifically, Q1 and Q2 in this application are driven by the equalization control method of this application. Each control unit outputs the duty cycle signal for driving Q1 and Q2 respectively. Q1 and Q2 generate waves through the duty cycle signal output by each control unit to achieve equalization regulation.
[0025] like Figure 1 In this circuit, Vdc represents the DC input voltage or equivalent voltage regulation effect. Capacitors C1 and C2 are connected in series to form a bus. The voltage across capacitor C1 can be Vdc1, and the voltage across capacitor C2 can be Vdc2. Resistors R1 and R2 are equivalent resistances. If R1 and R2 are the same, it means that the upper and lower capacitors have the same output power and there is no bias voltage problem. Q1 and Q2 form a half-bridge, and L1 is the topological inductor.
[0026] Figure 1 The principle of voltage equalization is as follows: If R1 and R2 are not equal, then the energy consumption of C1 and C2 will be different. The final voltage equalization is determined by the ratio of the resistance values of R1 and R2. For example, if R1 is greater than R2, the energy consumption of C1 is less than that of C2. If the direction of the inductor current IL1 in inductor L1 is made positive (as shown in the diagram), then the energy consumed by R2 can be supplemented by IL1, or the energy of C1 can be transferred and consumed. Therefore, by adjusting the magnitude and direction of IL1, voltage equalization or limiting voltage difference can be achieved.
[0027] When there is an unbalanced load, especially when the bus end is connected to the neutral line, the capacitor voltage fluctuates significantly at low frequencies. If the low-frequency ripple current is adjusted in real time, it will be transferred to the voltage equalization circuit, resulting in a large voltage equalization circuit size. If low loop parameters or large filtering are used to ignore low-frequency fluctuations for control, it is difficult to withstand the ripple when the real-time control voltage difference is 0V. Therefore, in the embodiments of this application, the voltage equalization is not started within the normal fluctuation range, and the adjustment is started only when the voltage difference threshold is exceeded, which can achieve efficient and automatic stable control outside the voltage difference.
[0028] Figure 3 This is a flowchart illustrating a pressure equalization control method provided in an embodiment of this application, as shown below. Figure 3 As shown, the method may include: S101. Obtain the DC bus voltage difference in the half-bridge circuit.
[0029] The DC bus voltage difference refers to, for example, Figure 1 The difference between the voltage across the upper capacitor C1 and the voltage across the lower capacitor C2 shown in the figure is Vdc1 - Vdc2. The voltage across the upper capacitor C1 can be represented by Vdc1, and the voltage across the lower capacitor C2 can be represented by Vdc2.
[0030] S102. Based on the DC bus voltage difference, generate the duty cycle signal of the first switching device in the first control unit based on the first control unit, and generate the duty cycle signal of the second switching device in the second control unit based on the DC bus voltage difference based on the second control unit.
[0031] Optionally, the first control unit mentioned above refers to, for example, Figure 2 The diagram shows a combination of a first deviation feedback module, a voltage equalization control module, a current limiting module, an inductor current loop, a duty cycle limiting module, and a first wave generation module. The voltage equalization control refers to... Figure 2 The VR shown; the second control unit mentioned above refers to, as Figure 2 The diagram shown consists of a second deviation feedback module, a voltage equalization control module, a current limiting module, an inductor current loop, a duty cycle limiting module, and a second wave generation module.
[0032] In this context, both the first and second switching devices can be, for example, field-effect transistors.
[0033] Optionally, the first control unit can send a duty cycle signal generated based on the DC bus voltage difference to the first switching device, and the first switching device can generate a waveform based on the received duty cycle signal; the second control unit can send a duty cycle signal generated based on the DC bus voltage difference to the second switching device, and the second switching device can generate a waveform based on the received duty cycle signal, so that each switching device can generate a waveform based on the duty cycle signal generated by its corresponding control unit without affecting each other, and the voltage equalization modulation of the half-bridge circuit can be achieved through independent control units.
[0034] S103. Equalize the voltage of the half-bridge circuit according to the duty cycle signal of the first switching device and the duty cycle signal of the second switching device.
[0035] Optionally, the first switching device can generate a wave based on the duty cycle signal generated by the first control unit; the second switching device can generate a wave based on the duty cycle signal generated by the second control unit. The wave generation of the first switching device and the wave generation of the second switching device can be used to equalize the voltage of the half-bridge circuit.
[0036] In this embodiment, the DC bus voltage difference in the half-bridge circuit is acquired. Based on the DC bus voltage difference, a duty cycle signal for the first switching device in the first control unit is generated using the first control unit. Based on the DC bus voltage difference, a duty cycle signal for the second switching device in the second control unit is generated using the second control unit. Voltage equalization is then performed on the half-bridge circuit based on the duty cycle signals of the first and second switching devices. This allows for independent control of the waveform generation of the switching devices in each control unit by two sets of control units, thereby achieving independent control and adjustment of voltage equalization in the half-bridge circuit, avoiding back-and-forth oscillations during voltage equalization adjustment, and achieving stable and efficient voltage regulation.
[0037] Figure 4 A schematic flowchart of another pressure equalization control method provided in this application embodiment is shown below. Figure 4 As shown, in step S102 above, generating the duty cycle signal of the first switching device in the first control unit based on the DC bus voltage difference and the second switching device in the second control unit based on the second control unit may include: S201. Determine the given current of the first control unit based on the DC bus voltage difference, voltage difference reference value, and reference current range. Determine the given current of the second control unit based on the DC bus voltage difference, voltage difference reference value, and reference current range.
[0038] The reference current range refers to the reference current range of the given current amplitude of each control unit. In other words, the magnitude of the given current of each control unit is determined to be within the reference current range, which can be represented by (IL_max, IL_min).
[0039] The voltage reference value can be represented by ΔVdc ref, which refers to the reference value of the absolute value of the voltage difference. In other words, the voltage difference reference value is a value greater than 0.
[0040] Specifically, based on the DC bus voltage difference, voltage difference reference value, and reference current range obtained above, the given current of each control unit can be determined using a preset method. This given current is the given current amplitude of the inductor current loop in each control unit, and the upper and lower amplitudes of this given current amplitude are limited. For the current in each control unit, which includes forward current and reverse current, the maximum amplitude of the forward current can be limited to IL_max, and the maximum amplitude of the reverse current can be limited to -IL_max.
[0041] For example, for the first control unit mentioned above, the given current on the first control unit can be determined by a preset method based on the obtained DC bus voltage difference Vdc1-Vdc2, where Vdc1-Vdc2 can also be represented by ΔVdc, the voltage reference value ΔVdc ref, and the reference current range (IL_max, IL_min). This given current refers to the given current of the inductor current loop in the first control unit, and the given current can refer to the value of any current in the reference current range.
[0042] In another example, for the second control unit mentioned above, the given current on the second control unit can be determined using a preset method based on the negative feedback Vdc2-Vdc1 of the obtained DC bus voltage difference, where Vdc2-Vdc1 can be represented by -ΔVdc, the voltage reference value ΔVdc ref, and the reference current range (IL_max, IL_min). This given current refers to the given current of the inductor current loop in the second control unit, and this given current can refer to the value of any current in the reference current range.
[0043] Optionally, when the DC bus voltage difference is outside the bias range, the first control unit and the second control unit participate in voltage equalization regulation; when the DC bus voltage difference is within the bias range, the first control unit and the second control unit do not participate in voltage equalization regulation, that is, the first control unit and the second control unit can be locked out, wherein the bias range is the voltage reference value ΔVdc ref mentioned above.
[0044] In this configuration, one of the first control unit and the second control unit can be a positive deviation, while the other control unit can be a negative deviation.
[0045] S202. Generate the duty cycle signal of the first control unit according to the given current of the first control unit, and generate the duty cycle signal of the second control unit according to the given current of the second control unit.
[0046] Optionally, in each control unit, a duty cycle signal for each control unit can be generated using a preset method based on the given current of each control unit determined above. The duty cycle signal can be, for example, a signal with a negative saturation duty cycle of 0, a signal with a positive saturation duty cycle of 0, a modulation signal with a duty cycle of 30%, a modulation signal with a duty cycle of 10%, etc.
[0047] For example, for the first control unit, a duty cycle signal of the first control unit can be generated using a preset method based on the given current of the first control unit; for the second control unit, a duty cycle signal of the second control unit can be generated using a preset method based on the given current of the second control unit.
[0048] S203. Input the duty cycle signal of the first control unit to the first control unit to control the first switching device to block or generate a wave, and input the duty cycle signal of the second control unit to the second control unit to cause the second switching device to block or generate a wave.
[0049] Optionally, the duty cycle signals of each control unit generated above are input to each control unit. Specifically, the duty cycle signals of each control unit are input to the switching devices in each control unit to drive the switching devices in each control unit to turn off or on, so that each control unit achieves voltage equalization.
[0050] For example, for the first control unit, the duty cycle signal of the control unit is input to the first switching device Q1, so that Q1 blocks or turns on according to the received duty cycle signal; for the second control unit, the duty cycle signal of the second control unit is input to the second switching device Q2, so that Q2 blocks or turns on according to the received duty cycle signal.
[0051] In this embodiment, each control unit determines its given current based on the DC bus voltage difference, voltage difference reference value, and reference current range. This allows for current control within each control unit, enabling short-term overpower regulation and protecting circuit components from damage. Furthermore, by generating duty cycle signals for each control unit based on its given current, and by performing voltage equalization based on these signals, independent control and regulation of each unit can be achieved. This avoids back-and-forth oscillations during voltage equalization, resulting in stable and efficient voltage regulation.
[0052] Optionally, in step S201 above, determining the given current of the first control unit based on the DC bus voltage difference, the voltage difference reference value, and the reference current range, and determining the given current of the second control unit based on the DC bus voltage difference, the voltage difference reference value, and the reference current range, may include: Optionally, if the DC bus voltage difference is less than the voltage difference reference value, the given current of the first control unit is determined to be the negative maximum current of the reference current range, and the given current of the second control unit is determined to be the positive maximum current of the reference current range.
[0053] Optionally, if the DC bus voltage difference Vdc1-Vdc2, i.e. ΔVdc, is a positive deviation, then the DC bus difference is greater than 0. The first control unit controls the DC bus voltage difference based on the positive feedback value. Specifically, the first control unit performs voltage equalization control of -VR based on the positive feedback value of the DC bus voltage difference. When the positive feedback value of the DC bus voltage difference is less than the voltage difference reference value, the limiting current of the first control unit is determined to be the negative maximum current in the reference current range. That is, when ΔVdc < ΔVdc ref, the given current of the first control unit is determined to be -IL_max. If the DC bus voltage difference is less than the voltage difference reference value, i.e., the DC bus voltage difference is within the deviation range, the first control unit can lock out the voltage equalization regulation.
[0054] Optionally, the second control unit performs control based on the negative feedback value of the DC bus voltage difference, i.e., -ΔVdc. Specifically, the second control unit performs VR equalization control on the negative feedback value of the DC bus voltage difference. When the DC bus voltage difference is less than the voltage difference reference value, the given current of the second control unit is determined to be the maximum positive current in the reference range. When -ΔVdc < ΔVdc ref, the given current of the second control unit is determined to be IL_max. If the DC bus voltage difference is less than the voltage difference reference value, that is, the DC bus voltage difference is within the deviation range, the second control unit can be locked and does not participate in the equalization regulation.
[0055] Optionally, if the DC bus voltage difference is greater than the voltage difference reference value, the given current of the first control unit and the given current of the second control unit are determined based on the current time, the reference current range, and the target curve.
[0056] Specifically, when the DC bus voltage difference is greater than the voltage difference reference value, that is, when the DC bus voltage difference exceeds the deviation range.
[0057] Optionally, if the DC bus voltage difference is greater than the voltage difference reference value, the first control unit can determine the transition from negative saturation to positive current based on the positive feedback value of the DC bus voltage difference, that is, when ΔVdc>ΔVdc ref. When the bias energy is stable, the given current of the first control unit can be determined based on the current time and the target curve. The amplitude of the given current is less than IL_max and greater than 0. At the same time, under this condition, the given current of the second closed-loop circuit control unit is the maximum positive current.
[0058] Optionally, based on the negative feedback value of the DC bus voltage difference and voltage equalization control, the second control unit can determine that when the negative feedback value of the DC bus voltage difference -ΔVdc>ΔVdcref, the second control unit transitions from positive saturation to negative current. When the bias energy in the circuit is stable, the given current of the second control unit can be determined based on the current time and the target curve. The amplitude of this given current is less than 0 and greater than -IL_max. At the same time, under this condition, the limiting current of the first control unit is the maximum negative current.
[0059] In this embodiment, when the DC bus voltage difference is outside the voltage reference range, the loop can be automatically selected to intercept the voltage difference, the inductor current can automatically run bidirectionally, and by limiting it in the positive and negative ranges, the limiting current can automatically run in the limiting range without the need for logic switching, making it convenient to use.
[0060] Optionally, the target curve described above is used to characterize the mapping relationship between a given current and a reference current range and time.
[0061] Optionally, if the current time is within a first preset time period, the given current is the maximum current value in the reference current range; if the current time is within a second preset time period, the given current is the current value between the maximum and minimum current values in the reference current range; if the current time is within a third preset time period, the given current is the minimum current value in the reference current range, specifically as follows: Figure 5 As shown.
[0062] Figure 5 This application provides an embodiment of an inductor current given amplitude time limiting curve, wherein the given current is the given current of the inductor current loop in each control unit, such as... Figure 5 As shown, the horizontal axis represents time t, and the vertical axis represents the amplitude of the given current, represented by IL_ref. The amplitude of the given current can be adjusted according to the time limit, so that the absolute value of the given current amplitude varies within the current range (IL_max, IL_min) over time. This allows for short-term overload operation for voltage equalization regulation while ensuring the thermal stability of the circuit. Figure 4 As can be seen, when the current amplitude is too large, the allowable operating time is shorter, and when the current amplitude is small, the operation time can be longer. By setting the reference current range, overpower operation can be allowed for a short period of time.
[0063] Optionally, in step S202 above, generating the duty cycle signal of the first control unit based on the given current of the first control unit, and generating the duty cycle signal of the second control unit based on the given current of the second control unit, may include: Optionally, based on the given current limit of the first control unit, the inductor current loop on the first control unit is controlled to output a corresponding first electrical signal, and the duty cycle signal of the first control unit is generated based on the first electrical signal.
[0064] In the first control unit, the pulse width modulation (PWM) is positive logic. This positive logic means that when the modulated wave is greater than the carrier wave, the switching device in the control unit is turned on, so that the control unit participates in voltage equalization modulation.
[0065] The given current of the first control unit is the given current of the inductor current loop on the first control unit. The current inductor loop on the first control unit outputs a first electrical signal according to the given current. This first electrical signal can represent an electrical signal with a duty cycle. By limiting the duty cycle of the first electrical signal, the pulse width modulation outputs the corresponding duty cycle signal according to the limited first electrical signal. When limiting the duty cycle, it can be limited by the interval (0-, 1). 0- represents below 0, which can block the circuit. 1 is the maximum duty cycle, which can also be smaller than 1.
[0066] Optionally, based on the given current of the second control unit, the current inductor on the second control unit is controlled to output a corresponding second electrical signal, an initial duty cycle signal of the second control unit is generated based on the second electrical signal, and the initial duty cycle signal is inverted to generate the duty cycle signal of the second control unit.
[0067] The given current of the second control unit is the given current of the inductor current loop on the second control unit. The current inductor loop on the second control unit outputs a second electrical signal according to the given current. This second electrical signal can represent an electrical signal with a duty cycle. By limiting the size of the duty cycle of the second electrical signal, the pulse width modulation outputs the initial duty cycle signal of the second closed loop circuit according to the limited second electrical signal, and inverts the initial duty cycle signal to generate the duty cycle signal of the second control unit.
[0068] In the second control unit, the PWM is reverse logic, which means that when the modulated wave is less than the carrier wave, the switching device in the control unit is turned on, so that the control unit participates in voltage equalization modulation.
[0069] Figure 6 This is a block diagram of a dual outer-loop competition and switching logic loop according to an embodiment of this application, such as... Figure 6 As shown, compared to Figure 2The independent control unit employs a dual-voltage-equalizing outer-loop competition strategy. Through a dual-circuit absolute value comparison unit of the dual-voltage outer loop, it outputs a logic switch switching signal to control and select the selection logic unit. It can select the current limit with the smaller absolute value as the priority control target current. The target current limit is... Figure 5 The IL_ref in the first control unit Q1 input is the PWM signal output by the PWM unit and a 0-to-1 selector signal, and the Q2 input of the second control unit Q2 input is the inverted PWM signal output by the PWM unit and a 0-to-1 selector signal.
[0070] Figure 7 This application provides a schematic diagram of a process for generating a duty cycle signal, as shown in the embodiment. Figure 7 As shown, it may also include: S301. Determine the target given current based on the given current of the first control unit and the second control unit.
[0071] Optionally, this method is based on the above. Figure 6 The dual outer loop competition and switching logic loop in the middle.
[0072] The given current of the first control unit and the given current of the second control unit are compared by an absolute value comparison unit to select the target given current. Specifically, the given current value with the smaller absolute value can be selected as the target given current value.
[0073] For example, if the given current of the first control unit is IL_ref1 and the given current of the first control unit is IL_ref2, then if the absolute value of IL_ref1 is greater than the absolute value of IL_ref2, then IL_ref2 is taken as the target given current.
[0074] S302. Based on the target given current, control the target inductor current loop to output the corresponding third electrical signal, and generate the target duty cycle signal based on the third electrical signal.
[0075] The target inductor current loop can be a shared inductor current loop of the first control unit and the second control unit. The target given current is the given current of the target inductor current loop. The target current inductor loop outputs a third electrical signal according to the given target given current. The third electrical signal can represent an electrical signal with a duty cycle. By limiting the size of the duty cycle of the third electrical signal, the PWM finally generates a target duty cycle signal according to the limited third electrical signal.
[0076] S303. Based on the target duty cycle signal, generate the duty cycle signal of the first control unit and the duty cycle signal of the second control unit respectively.
[0077] Specifically, the target duty cycle signal can be generated using a preset method to generate the duty cycle signal of the first control unit and the duty cycle signal of the second control unit, respectively.
[0078] Optionally, the above-mentioned generation of the duty cycle signal of the first control unit and the duty cycle signal of the second control unit based on the target duty cycle signal may include: Optionally, the target duty cycle signal can be used as the duty cycle signal of the first control unit. That is, for the switching device Q1 of the first control unit, the input is the target duty cycle signal. The target duty cycle signal can be selected from 0 and the PWM signal. 0 means the duty cycle is 0. For example, if the target duty cycle signal is a duty cycle signal with a duty cycle of 0.6, then the duty cycle signal of the first control unit is a duty cycle signal with a duty cycle of 0.6.
[0079] Optionally, the inverted target duty cycle signal can be used as the duty cycle signal of the second control unit. That is, for the switching device Q2 of the second control unit, the input is the inverted target duty cycle signal. For example, for a target duty cycle signal with a duty cycle of 0.6, the inverted signal becomes a duty cycle signal with a duty cycle of 0.4. Therefore, when the target duty cycle signal is a duty cycle signal with a duty cycle of 0.6, the duty cycle signal for the second control unit is a duty cycle signal with a duty cycle of 0.4.
[0080] In this embodiment, by sharing an inductor current loop and simultaneously determining the given current of one of the control units as the given current of the shared inductor current loop through competition and selection among the control units, one inductor current loop can be reduced, thereby reducing the loop resource occupation and debugging workload.
[0081] Figure 8 A pressure equalization control device provided in the embodiments of this application, such as Figure 8 As shown, the device includes: The acquisition module 401 is used to acquire the DC bus voltage difference in the half-bridge circuit; The generation module 402 is used to generate a duty cycle signal of a first switching device in the first control unit based on the DC bus voltage difference and a first control unit, and to generate a duty cycle signal of a second switching device in the second control unit based on the DC bus voltage difference and a second control unit. The control module 403 is used to perform voltage equalization control on the half-bridge circuit based on the duty cycle signal of the first switching device and the duty cycle signal of the second switching device.
[0082] Optionally, the generation module 402 is specifically used for: The given current of the first control unit is determined based on the DC bus voltage difference, the voltage difference reference value, and the reference current range; the given current of the second control unit is determined based on the DC bus voltage difference, the voltage difference reference value, and the reference current range. Based on the given current of the first control unit, generate the duty cycle signal of the first control unit; based on the given current of the second control unit, generate the duty cycle signal of the second control unit. The duty cycle signal of the first control unit is input to the first control unit to control the first switching device to block or transmit a wave, and the duty cycle signal of the second control unit is input to the second control unit to cause the second switching device to block or transmit a wave.
[0083] Optionally, the generation module 402 is specifically used for: If the DC bus voltage difference is less than the voltage difference reference value, then the given current of the first control unit is determined to be the negative maximum current of the reference current range, and the given current of the second control unit is determined to be the positive maximum current of the reference current range. If the DC bus voltage difference is greater than the voltage difference reference value, then the given current of the first control unit and the given current of the second control unit are determined based on the current time, the reference current range, and the target curve.
[0084] Optionally, the target curve is used to characterize the mapping relationship between the given current and the reference current range and time; If the current time is within a first preset time period, the given current is the maximum current value in the reference current range; If the current time is within the second preset time period, the given current is the current value between the maximum and minimum current values in the reference current range; If the current time is within the third preset time period, the given current is the minimum current value in the reference current range.
[0085] Optionally, the generation module 402 is specifically used for: Based on the given current of the first control unit, the inductor current loop on the first control unit is controlled to output a corresponding first electrical signal, and the duty cycle signal of the first control unit is generated based on the first electrical signal. Based on the limiting current of the second control unit, the inductor current loop on the second control unit is controlled to output a corresponding second electrical signal. Based on the second electrical signal, an initial duty cycle signal of the second control unit is generated, and the initial duty cycle signal is inverted to generate the duty cycle signal of the second control unit.
[0086] Optionally, the generation module 402 is specifically used for: Determine the target given current based on the given currents of the first control unit and the second control unit; Based on the target given current, control the target inductor current loop to output the corresponding third electrical signal, and generate the target duty cycle signal based on the third electrical signal; Based on the target duty cycle signal, the duty cycle signals of the first control unit and the second control unit are generated respectively.
[0087] Optionally, the generation module 402 is specifically used for: The target duty cycle signal is used as the first given duty cycle signal; The inverted target duty cycle signal is used as the second given duty cycle signal.
[0088] Figure 9 A structural block diagram of an electronic device 500 provided in this application embodiment is shown below. Figure 9 As shown, the electronic device may include: processor 501 and memory 502.
[0089] Optionally, a bus 503 may also be included, wherein the memory 502 is used to store machine-readable instructions executable by the processor 501. When the electronic device 500 is running, the processor 501 and the memory 502 communicate via the bus 503. When the machine-readable instructions are executed by the processor 501, the method steps in the above method embodiments are performed.
[0090] This application also provides a computer-readable storage medium storing a computer program, which, when executed by a processor, performs the method steps described in the above-described network topology information processing method embodiments.
[0091] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems and devices described above can be referred to the corresponding processes in the method embodiments, and will not be repeated here. In the several embodiments provided in this application, it should be understood that the disclosed systems, devices, and methods can be implemented in other ways. The device embodiments described above are merely illustrative. For example, the division of modules is only a logical functional division, and in actual implementation, there may be other division methods. Furthermore, multiple modules or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the displayed or discussed mutual coupling or direct coupling or communication connection can be through some communication interfaces; the indirect coupling or communication connection of devices or modules can be electrical, mechanical, or other forms.
[0092] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. If the functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes: USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, optical disks, and other media capable of storing program code.
[0093] The above are merely specific embodiments of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application.
Claims
1. A pressure equalization control method, characterized in that, The method includes: Obtain the DC bus voltage difference in the half-bridge circuit; Based on the DC bus voltage difference, a duty cycle signal for a first switching device in the first control unit is generated based on the first control unit; based on the DC bus voltage difference, a duty cycle signal for a second switching device in the second control unit is generated based on the second control unit. The half-bridge circuit is subjected to voltage equalization control based on the duty cycle signals of the first and second switching devices. The step of generating a duty cycle signal for a first switching device in a first control unit based on the DC bus voltage difference, and generating a duty cycle signal for a second switching device in a second control unit based on a second control unit, includes: The given current of the first control unit is determined based on the DC bus voltage difference, the voltage difference reference value, and the reference current range; the given current of the second control unit is determined based on the DC bus voltage difference, the voltage difference reference value, and the reference current range. Based on the given current of the first control unit, the inductor current loop on the first control unit is controlled to output a corresponding first electrical signal, and the duty cycle signal of the first control unit is generated based on the first electrical signal. Based on the limiting current of the second control unit, the inductor current loop on the second control unit is controlled to output a corresponding second electrical signal. Based on the second electrical signal, an initial duty cycle signal of the second control unit is generated, and the initial duty cycle signal is inverted to generate the duty cycle signal of the second control unit. The duty cycle signal of the first control unit is input to the first control unit to control the first switching device to block or transmit a wave, and the duty cycle signal of the second control unit is input to the second control unit to cause the second switching device to block or transmit a wave.
2. The pressure equalization control method according to claim 1, characterized in that, Also includes: Determine the target given current based on the given currents of the first control unit and the second control unit; Based on the target given current, control the target inductor current loop to output the corresponding third electrical signal, and generate the target duty cycle signal based on the third electrical signal; Based on the target duty cycle signal, the duty cycle signals of the first control unit and the second control unit are generated respectively.
3. The pressure equalization control method according to claim 2, characterized in that, Based on the target duty cycle signal, the duty cycle signal of the first control unit and the duty cycle signal of the second control unit are generated respectively, including: The target duty cycle signal is used as the duty cycle signal of the first control unit; The inverted target duty cycle signal is used as the duty cycle signal of the second control unit.
4. A pressure equalization control device, characterized in that, include: The acquisition module is used to acquire the DC bus voltage difference in the half-bridge circuit; The generation module is used to generate a duty cycle signal of a first switching device in the first control unit based on the DC bus voltage difference and a first control unit, and to generate a duty cycle signal of a second switching device in the second control unit based on the DC bus voltage difference and a second control unit. The control module is used to perform voltage equalization control on the half-bridge circuit based on the duty cycle signal of the first switching device and the duty cycle signal of the second switching device. The generation module is specifically used for: The given current of the first control unit is determined based on the DC bus voltage difference, the voltage difference reference value, and the reference current range; the given current of the second control unit is determined based on the DC bus voltage difference, the voltage difference reference value, and the reference current range. Based on the given current of the first control unit, the inductor current loop on the first control unit is controlled to output a corresponding first electrical signal, and the duty cycle signal of the first control unit is generated based on the first electrical signal. Based on the limiting current of the second control unit, the inductor current loop on the second control unit is controlled to output a corresponding second electrical signal. Based on the second electrical signal, an initial duty cycle signal of the second control unit is generated, and the initial duty cycle signal is inverted to generate the duty cycle signal of the second control unit. The duty cycle signal of the first control unit is input to the first control unit to control the first switching device to block or transmit a wave, and the duty cycle signal of the second control unit is input to the second control unit to cause the second switching device to block or transmit a wave.
5. An electronic device, characterized in that, It includes a memory and a processor, the memory storing a computer program executable by the processor, and the processor executing the computer program to implement the steps of the equalization control method according to any one of claims 1-3.
6. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, performs the steps of the voltage equalization control method as described in any one of claims 1-3.