Low noise amplifier circuit and chip
By placing the secondary coil at the rear end of the first amplifier circuit in the low-noise amplifier circuit, the noise of the secondary coil is suppressed by the first amplifier circuit. By using a secondary coil with a low Q value, the problem of balancing the area and noise performance of the transformer coil design is solved, achieving low noise performance and cost reduction.
Patent Information
- Application Number
- CN202411347838.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-25
- Publication Date
- 2026-03-27
AI Technical Summary
The design of transformer coils in existing low-noise amplifier circuits is limited. High-Q coils have large areas and high costs, while low-Q coils have increased noise figures, making it difficult to balance area and noise performance.
The secondary coil of the transformer is placed at the end of the first amplifier circuit. The first amplifier circuit is used to suppress the noise of the secondary coil. The secondary coil with a low Q value is used to improve impedance matching and reduce circuit area and cost.
This achieves low-noise performance while reducing circuit area and chip cost, and decreasing the contribution of secondary coils to amplifier noise.
Smart Images
Figure CN121749913A_ABST
Abstract
Description
Technical Field
[0001] This application belongs to the field of low-noise amplifier technology, and particularly relates to a low-noise amplifier circuit and chip. Background Technology
[0002] In the field of signal processing, low-noise amplifier circuits are typically located at the front end of the receiving link. Power matching at the input port is required to boost the power of the received signal, and its performance plays a crucial role in the entire link. In chip-based systems, due to the parasitic capacitance of on-chip devices, existing low-noise amplifier circuits usually utilize on-chip inductors or transformers for matching. On-chip transformers, with their higher-order networks, offer stronger impedance regulation capabilities than a single inductor, thus finding wider application in low-noise amplifier circuits.
[0003] However, the transformer coils in low-noise amplifier circuits also affect the overall noise, so coils with high Q values are generally required. But higher Q values mean increasing the coil radius and wire diameter, thus increasing the coil area. Since transformers have multiple coils and there are parasitic capacitances between them, the transformer area increases exponentially, thus increasing chip costs. Conversely, choosing coils with low Q values can easily lead to an increase in the noise figure of the low-noise amplifier circuit, degrading its performance. Therefore, the design of transformer coils in traditional low-noise amplifier circuits is subject to significant limitations. Summary of the Invention
[0004] This application aims to at least solve one of the technical problems existing in the prior art. To this end, this application proposes a low-noise amplifier circuit and chip, which uses a first amplification circuit to suppress noise in the secondary coil, thereby enabling the use of a low-Q secondary coil to improve the impedance matching of the low-noise amplifier, while ensuring low-noise performance and reducing circuit area.
[0005] In a first aspect, this application provides a low-noise amplifier circuit, comprising:
[0006] The first amplifier circuit has an input stage and an output stage;
[0007] A transformer has a primary coil and a secondary coil. The first end of the primary coil is electrically connected to the input stage of a first amplifier circuit, and the second end of the primary coil is electrically connected to the signal input node. The first end of the secondary coil is electrically connected to the output stage of the first amplifier circuit, and the second end of the secondary coil is electrically connected to the signal output node.
[0008] According to the low-noise amplifier circuit of this application, by placing the secondary coil of the transformer at the rear end of the first amplifier circuit, the noise of the secondary coil is suppressed by the first amplifier circuit, reducing the contribution of the secondary coil to the amplifier noise. Thus, a low-Q secondary coil can be further used to improve the impedance matching of the low-noise amplifier while ensuring low-noise performance.
[0009] According to one embodiment of this application, the quality factor of the primary coil is greater than the quality factor of the secondary coil.
[0010] According to one embodiment of this application, the inductance of the primary coil is greater than the inductance of the secondary coil.
[0011] According to one embodiment of this application, the first amplifier circuit includes:
[0012] The system comprises a first NMOS transistor, a first PMOS transistor, a first capacitor, a second capacitor, and a first current source. The first terminal of the first capacitor is electrically connected to the gate of the first NMOS transistor and the gate of the first PMOS transistor, respectively. The drain of the first NMOS transistor is electrically connected to the drain of the first PMOS transistor. The output terminal of the first current source is electrically connected to the source of the first PMOS transistor and the first terminal of the second capacitor, respectively. The second terminal of the second capacitor and the source of the first NMOS transistor are both electrically connected to a ground node.
[0013] According to one embodiment of this application, a bias resistor is connected between the gate and drain of the first PMOS transistor and the first NMOS transistor, and the resistance value of the bias resistor is greater than 10K ohms.
[0014] According to one embodiment of this application, the low-noise amplifier circuit further includes:
[0015] The second amplifier circuit has its input stage electrically connected to the second end of the secondary coil, and its output stage electrically connected to the signal output node.
[0016] According to one embodiment of this application, the first amplifier circuit includes a complementary common-source amplifier circuit, a common-source common-gate amplifier circuit, a common-gate amplifier circuit, or a resistive load common-source amplifier circuit, and the second amplifier circuit includes a complementary common-source amplifier circuit, a common-source common-gate amplifier circuit, a common-gate amplifier circuit, or a resistive load common-source amplifier circuit.
[0017] According to one embodiment of this application, the second amplifier circuit includes a second NMOS transistor, a second PMOS transistor, a second resistor, a third capacitor, a fourth capacitor, and a second current source. The first terminal of the third capacitor is electrically connected to the gate of the second NMOS transistor, the gate of the second PMOS transistor, and the first terminal of the second resistor. The second terminal of the second resistor is electrically connected to the drain of the second NMOS transistor, the drain of the second PMOS transistor, and a signal output node. The output terminal of the second current source is electrically connected to the source of the second PMOS transistor and the first terminal of the fourth capacitor. The second terminal of the fourth capacitor and the source of the second NMOS transistor are both electrically connected to a ground node.
[0018] The first end of the primary coil is electrically connected to the signal input node, the second end of the primary coil is electrically connected to the second end of the first capacitor, the first end of the secondary coil is electrically connected to the second end of the first resistor, and the second end of the secondary coil is electrically connected to the second end of the third capacitor.
[0019] Secondly, this application provides a chip having the aforementioned low-noise amplifier circuit.
[0020] According to the chip of this application, a low-noise amplifier circuit is integrated. The secondary coil of the transformer in the low-noise amplifier circuit is located at the rear end of the first amplifier circuit. The first amplifier circuit is used to suppress the noise of the secondary coil and reduce the contribution of the secondary coil to the noise of the low-noise amplifier. Thus, a low-Q secondary coil can be used to improve the impedance matching of the low-noise amplifier, while ensuring low-noise performance, reducing the circuit area, and saving costs.
[0021] Additional aspects and advantages of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this application. Attached Figure Description
[0022] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which:
[0023] Figure 1 This is one of the circuit structure diagrams of the low-noise amplifier circuit provided in the embodiments of this application;
[0024] Figure 2 This is a second schematic diagram of the circuit structure of the low-noise amplifier circuit provided in the embodiments of this application;
[0025] Figure 3 This is a schematic diagram of the S11 parameters of the low-noise amplifier circuit provided in the embodiments of this application under different coil connection conditions;
[0026] Figure 4This is a graph showing the relationship between the quality factor Q of the secondary coil Ls and the noise figure in the low-noise amplifier circuit provided in this application embodiment.
[0027] Figure 5 This is a graph showing the relationship between the quality factor Q of the secondary coil Ls and the S11 parameter in the low-noise amplifier circuit provided in this application embodiment;
[0028] Figure 6 This is a schematic diagram of the circuit structure of the common-source cascode amplifier circuit provided in the embodiments of this application;
[0029] Figure 7 This is a schematic diagram of the circuit structure of the resistive load common-source amplifier circuit provided in the embodiments of this application;
[0030] Figure 8 This is a schematic diagram of the circuit structure of the common-gate amplifier circuit provided in the embodiments of this application.
[0031] Figure label:
[0032] First amplifier circuit 100, second amplifier circuit 200, primary coil Lp, secondary coil Ls, signal input node IN, signal output node OUT, first to second NMOS transistors N1 to N2, first to second PMOS transistors P1 to P2, first to second resistors R1 to R2, first to fourth capacitors C1 to C4, and first current source I1 to I2. Detailed Implementation
[0033] The embodiments of this application are described in detail below, examples of which are illustrated in the accompanying drawings. In the drawings, for clarity, the dimensions of layers, regions, elements, and their relative dimensions may be exaggerated. The same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application.
[0034] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this disclosure.
[0035] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.
[0036] Reference Figure 1 , Figure 1 A circuit structure for a low-noise amplifier circuit is shown. One embodiment of this application provides a low-noise amplifier circuit. In this embodiment, the low-noise amplifier circuit includes a first amplifier circuit 100 and a transformer. The first amplifier circuit 100 has an input stage and an output stage. The transformer has a primary coil Lp and a secondary coil Ls. A first end of the primary coil Lp is electrically connected to the input stage of the first amplifier circuit 100, and a second end of the primary coil Lp is electrically connected to the signal input node IN. A first end of the secondary coil Ls is electrically connected to the output stage of the first amplifier circuit 100, and a second end of the secondary coil Ls is electrically connected to the signal output node OUT.
[0037] The signal input node IN is used to input the signal to be processed. The input stage of the first amplifier circuit 100 is used to input the signal that needs to be amplified once. The output stage of the first amplifier circuit 100 is used to output the amplified signal. The signal output node OUT is used to provide the signal processed by the low-noise amplifier circuit.
[0038] Refer to the following formula for calculating the cascaded noise factor:
[0039]
[0040] Among them, F n Let g be the noise factor of the nth stage amplifier circuit. n Let L be the gain of the nth stage amplifier circuit. As can be seen from the formula, for the entire low-noise amplifier, the noise contribution of each subsequent stage amplifier circuit gradually decreases, meaning the noise of the subsequent stage amplifier circuit is suppressed by the noise of the preceding stage amplifier circuit. In this embodiment, the secondary coil Ls is connected to the rear end of the first amplifier circuit 100. The noise of the secondary coil Ls is suppressed by the first amplifier circuit 100, thus the noise contribution of the secondary coil Ls to the low-noise amplifier is small. Even with a low-quality-factor coil design that is prone to noise, the secondary coil Ls in this application generates less noise compared to coils in related technologies.
[0041] According to the low-noise amplifier circuit of this application, by placing the secondary coil of the transformer at the rear end of the first amplifier circuit, the noise of the secondary coil is suppressed by the first amplifier circuit, thereby reducing the contribution of the secondary coil to the amplifier noise. The secondary coil does not need to have a high Q value to achieve low noise performance, thereby reducing the chip area and reducing the cost.
[0042] In some embodiments, the quality factor of the primary coil Lp is greater than the quality factor of the secondary coil Ls.
[0043] The quality factor Q is an important parameter reflecting coil quality and transformer performance. Q represents the ratio of the imaginary to the real part of the transformer coil. A higher Q value indicates better coil noise performance, but requires a larger coil radius and wire diameter, increasing the coil area. In this embodiment, the primary coil Lp is located in the preceding stage on the signal path, and it can use a higher Q value to reduce noise. The secondary coil Ls is located in the following stage on the signal path, and it can use a lower Q value to reduce the area of the secondary coil Ls and lower costs.
[0044] As an example, the quality factor of the primary coil Lp can be 8-11, such as 9 or 10. The quality factor of the secondary coil Ls can be 0.1-2, such as 0.2 or 1.
[0045] This embodiment uses a primary coil Lp with a large inductance for impedance matching and a secondary coil Ls with a small inductance to reduce noise.
[0046] Reference Figure 2 , Figure 2A circuit structure for a low-noise amplifier circuit is shown. One embodiment of this application provides a low-noise amplifier circuit. In this embodiment, the low-noise amplifier circuit further includes a second amplifier circuit 200, the input stage of which is electrically connected to the second terminal of the secondary coil Ls, and the output stage of which is electrically connected to the signal output node OUT.
[0047] The first amplifier circuit 100 amplifies the signal for the first time as the first stage, and the second amplifier circuit 200 amplifies the signal for the second time as the second stage. This embodiment uses cascaded amplifier circuits to achieve higher gain and stronger anti-interference capability. It should be noted that in this embodiment, the secondary coil Ls improves matching by adjusting the input impedance through a transformer structure, and its own noise is effectively suppressed by the first-stage amplifier circuit 100, effectively reducing its contribution to circuit noise.
[0048] As an example, the first amplifier circuit 100 includes a first NMOS transistor N1, a first PMOS transistor P1, a first capacitor C1, a second capacitor C2, and a first current source I1. The second amplifier circuit 200 includes a second NMOS transistor N2, a second PMOS transistor P2, a second resistor R2, a third capacitor C3, a fourth capacitor C4, and a second current source I2.
[0049] The first terminal of the first capacitor C1 is electrically connected to the gate of the first NMOS transistor N1 and the gate of the first PMOS transistor P1. The output terminal of the first current source I1 is electrically connected to the source of the first PMOS transistor P1 and the first terminal of the second capacitor C2. The second terminal of the second capacitor C2 and the source of the first NMOS transistor N1 are both electrically connected to the ground node. The first terminal of the third capacitor C3 is electrically connected to the gate of the second NMOS transistor N2, the gate of the second PMOS transistor P2, and the first terminal of the second resistor R2. The second terminal of the second resistor R2 is electrically connected to the drain of the second NMOS transistor N2, the drain of the second PMOS transistor P2, and the signal output node OUT. The output terminal of the second current source I2 is electrically connected to the source of the second PMOS transistor P2 and the first terminal of the fourth capacitor C4. The second terminal of the fourth capacitor C4 and the source of the second NMOS transistor N2 are both electrically connected to the ground node. The first terminal of the primary coil Lp is electrically connected to the signal input node IN. The second terminal of the primary coil Lp is electrically connected to the second terminal of the first capacitor C1. The first terminal of the secondary coil Ls is electrically connected to the drain of the first NMOS transistor N1 and the drain of the first PMOS transistor. The second terminal of the secondary coil Ls is electrically connected to the second terminal of the third capacitor C3.
[0050] In this example, both the first amplifier circuit 100 and the second amplifier circuit 200 are complementary common-source amplifier circuits with high equivalent transconductance, which is beneficial for achieving high gain and low noise figure.
[0051] In some embodiments, a bias resistor is provided between the gate and drain of the first PMOS transistor and the first NMOS transistor, and the resistance value of the bias resistor is greater than 10K ohms.
[0052] It should be noted that in related technologies, the first resistor R1 typically uses a low resistance value to achieve impedance matching, such as around 1kΩ. However, the lower the resistance value of the first resistor R1, the more noise it introduces, degrading the amplifier's noise performance. In this embodiment, the bias resistor is the first resistor R1. The transformer has a stronger impedance regulation capability, allowing the bias resistor to be chosen without being specifically designed for impedance matching. Its resistance value can be larger, such as 10kΩ, and the bias resistor is only used for DC bias, thereby further optimizing noise.
[0053] Reference Figure 3 , Figure 3 The S11 parameters of a low-noise amplifier circuit with different coil connection conditions are shown. The S11 parameter is an important indicator of a low-noise amplifier; the smaller the S11 value, the better the input matching performance and the stronger the received signal.
[0054] exist Figure 3 In the text, case 1 indicates no transformer is connected, that is, in Figure Two Based on the circuit, the primary coil Lp and the secondary coil Ls are removed, and the corresponding ports are shorted; case 2 indicates that only the primary coil Lp is connected, that is, in Figure Two Based on the circuit, the secondary coil Ls is deleted and its corresponding two ends are shorted; case 3 indicates the connection of a complete transformer, and the circuit topology is as follows. Figure 2 As shown, it can be seen that after connecting the secondary coil Ls between the first amplifier circuit 100 and the second amplifier circuit 200, S11 is significantly reduced and the matching is improved.
[0055] It should be noted that, Figure 3 The S11 parameter is smallest and the matching is best at a frequency of around 2.4 GHz. This frequency is determined by the parameters of the specific circuit and does not constitute a limitation on this embodiment. Its specific value can be set according to requirements, and this embodiment does not impose any restrictions on it. Among them, the primary coil Lp and the first capacitor C1 jointly adjust the matching frequency, and Ls is used to adjust the matching depth.
[0056] Continue with Figure 2 Taking the circuit structure shown as an example, refer to... Figure 4 and Figure 5 , Figure 4 The effect of the quality factor Q of the secondary coil Ls on the noise figure of a low-noise amplifier circuit is shown. Figure 5 The effect of the quality factor Q variation of the secondary coil Ls on the S11 parameters of a low-noise amplifier circuit is shown. Figure 4In this circuit, the quality factors of the secondary coil Ls are Q = 10, Q = 1, or Q = 0.1. However, the noise figure of the low-noise amplifier circuit does not change significantly under these three quality factors. This indicates that a low-Q secondary coil can achieve a good noise figure under this scheme. Figure 5 In the figure, the quality factors of the secondary coil Ls are Q=10, Q=1, or Q=0.1. As can be seen from the figure, good matching can still be achieved even when the Q value of the secondary coil is reduced.
[0057] In other examples, the first amplifier circuit 100 and the second amplifier circuit 200 may also employ other types of amplifier circuits, such as a common-source common-gate amplifier circuit or a resistive load common-source amplifier circuit. The first amplifier circuit 100 and the second amplifier circuit 200 may use the same circuit structure or different circuit structures.
[0058] Reference Figure 6 , Figure 6 The circuit structure of a common-source common-gate amplifier circuit is shown. The common-source common-gate amplifier circuit includes two N-type MOS transistors. The gate of one NMOS transistor is provided with a capacitor for signal input, and the source of the NMOS transistor is grounded. The drain of the NMOS transistor is connected to the source of the other NMOS transistor, and the drain of the other NMOS transistor is connected to a load. The amplifier outputs the amplified signal.
[0059] Reference Figure 7 , Figure 7 The circuit structure of a common-source amplifier circuit with a resistive load is shown. The common-source amplifier circuit includes an N-type MOS transistor with a capacitor at its gate for signal input. The source of the NMOS transistor is grounded, and its drain is connected to the load resistor. The amplifier outputs an amplified signal.
[0060] Reference Figure 8 , Figure 8 The circuit structure of a common-gate amplifier circuit is shown. The common-gate amplifier circuit includes an NMOS transistor. The source of the NMOS transistor is connected to the signal through a capacitor and is also connected to a current source. The drain of the NMOS transistor is connected to the load resistor and the power supply, and the drain of the NMOS transistor outputs the amplified signal.
[0061] One embodiment of this application also provides a chip having the aforementioned low-noise amplifier circuit. The chip can be formed with the aforementioned transformer, MOSFETs, capacitors, etc., from the amplifier circuit. The specific structure of the low-noise amplifier circuit can be referred to the foregoing; this embodiment will not repeat it here.
[0062] The chip according to this application integrates a low-noise amplifier circuit. The secondary coil of the transformer in the low-noise amplifier circuit is located after the output of the first amplifier circuit, and the noise of the secondary coil is suppressed by the first amplifier circuit. This reduces the contribution of the secondary coil to the noise of the low-noise amplifier, allowing for greater design flexibility for the secondary coil. Under these conditions, low-Q value secondary coils using metal layers with non-maximum conductivity can also achieve low-noise performance, thereby reducing chip area and saving costs.
[0063] In some embodiments, the primary coil Lp and the secondary coil Ls are located on different layers of the chip, with the primary coil Lp located on the layer with the highest conductivity in the chip and the secondary coil Ls located on the layer with the second highest conductivity in the chip.
[0064] In this embodiment, an on-chip transformer can be integrated into the chip, with the primary coil Lp and the secondary coil Ls located on different layers of the chip. This allows for better utilization of three-dimensional space and reduces the chip area occupied by the transformer.
[0065] Meanwhile, the lower the coil resistance, the lower the resistive noise, which is more beneficial for reducing the noise figure of the low-noise amplifier. The primary coil Lp is located before the input of the first-stage amplifier and contributes significantly to noise. Therefore, the primary coil is placed in the layer with the highest conductivity to reduce parasitic resistance and thus reduce noise. The noise of the secondary coil Ls is suppressed by the first-stage amplifier, so even if it is located in a layer with lower conductivity, it has little impact on the overall noise performance of the low-noise amplifier.
[0066] In some embodiments, the radius and / or wire diameter of the primary coil Lp is greater than the radius and / or wire diameter of the secondary coil Ls.
[0067] Using a large coil radius / wire diameter for the primary coil Lp is beneficial for achieving a high Q value and low noise inductance, while using a small coil radius / wire diameter for the secondary coil Ls is beneficial for reducing chip area and reducing coupling capacitance between coils, thus avoiding noise degradation.
[0068] Although embodiments of this application have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of this application, the scope of which is defined by the claims and their equivalents.
Claims
1. A low-noise amplifier circuit, characterized in that, include: The first amplifier circuit has an input stage and an output stage; A transformer has a primary coil and a secondary coil. A first end of the primary coil is electrically connected to the input stage of the first amplifier circuit, and a second end of the primary coil is electrically connected to a signal input node. A first end of the secondary coil is electrically connected to the output stage of the first amplifier circuit, and a second end of the secondary coil is electrically connected to a signal output node.
2. The low-noise amplifier circuit according to claim 1, characterized in that, The quality factor of the primary coil is greater than that of the secondary coil.
3. The low-noise amplifier circuit according to claim 1, characterized in that, The inductance of the primary coil is greater than the inductance of the secondary coil.
4. The low-noise amplifier circuit according to claim 1, characterized in that, The first amplifier circuit includes: The system comprises a first NMOS transistor, a first PMOS transistor, a first capacitor, a second capacitor, and a first current source. The first terminal of the first capacitor is electrically connected to the gate of the first NMOS transistor and the gate of the first PMOS transistor, respectively. The drain of the first NMOS transistor is electrically connected to the drain of the first PMOS transistor. The output terminal of the first current source is electrically connected to the source of the first PMOS transistor and the first terminal of the second capacitor, respectively. The second terminal of the second capacitor and the source of the first NMOS transistor are both electrically connected to a ground node.
5. The low-noise amplifier circuit according to claim 4, characterized in that, A bias resistor is connected between the gate and drain of the first PMOS transistor and the first NMOS transistor, and the resistance of the bias resistor is greater than 10K ohms.
6. The low-noise amplifier circuit according to any one of claims 1-5, characterized in that, The low-noise amplifier circuit also includes: The second amplifier circuit has its input stage electrically connected to the second terminal of the secondary coil, and its output stage electrically connected to the signal output node.
7. The low-noise amplifier circuit according to claim 6, characterized in that, The first amplifier circuit and the second amplifier circuit have the same circuit structure.
8. The low-noise amplifier circuit according to claim 7, characterized in that, The first amplifier circuit includes a complementary common-source amplifier circuit, a common-source cascode amplifier circuit, a common-gate amplifier circuit, or a resistive load common-source amplifier circuit, and the second amplifier circuit includes a complementary common-source amplifier circuit, a common-source cascode amplifier circuit, a common-gate amplifier circuit, or a resistive load common-source amplifier circuit.
9. The low-noise amplifier circuit according to claim 6, characterized in that, The second amplifier circuit includes a second NMOS transistor, a second PMOS transistor, a second resistor, a third capacitor, a fourth capacitor, and a second current source. The first terminal of the third capacitor is electrically connected to the gate of the second NMOS transistor, the gate of the second PMOS transistor, and the first terminal of the second resistor. The second terminal of the second resistor is electrically connected to the drain of the second NMOS transistor, the drain of the second PMOS transistor, and the signal output node. The output terminal of the second current source is electrically connected to the source of the second PMOS transistor and the first terminal of the fourth capacitor. The second terminal of the fourth capacitor and the source of the second NMOS transistor are both electrically connected to a ground node. The first end of the primary coil is electrically connected to the signal input node, the second end of the primary coil is electrically connected to the second end of the first capacitor, the first end of the secondary coil is electrically connected to the second end of the first resistor, and the second end of the secondary coil is electrically connected to the second end of the third capacitor.
10. A chip, characterized in that, The chip is configured with a low-noise amplifier circuit according to any one of claims 1-9.