Gate driving circuit and driving method thereof

Abstract

The invention provides a gate driving circuit and a driving method. A gate driving circuit includes: a gate injection transistor; a first resistor connected between a source electrode of the gate injection transistor and ground; the conduction branch circuit is connected between a first voltage and a grid electrode of the grid electrode injection transistor, and the conduction branch circuit is configured to respond to the fact that the voltage of the grid electrode of the grid electrode injection transistor is higher than a preset voltage in a conduction state so as to reduce or cut off current flowing into the grid electrode of the grid electrode injection transistor.

Description

Technical Field

[0001] This disclosure relates to the field of electronic technology, and more specifically, to gate drive circuits and driving methods thereof. Background Technology

[0002] In recent years, gallium nitride (GaN) power devices have attracted much attention due to their superior performance, especially in motor drive applications. Because only majority carriers participate in conduction in both forward and reverse conduction modes, GaN devices do not have a reverse recovery process, thus significantly reducing switching losses and the corresponding electromagnetic interference (EMI). GaN devices also lack turn-off tail current, further reducing switching losses. Furthermore, their lower specific on-resistance allows motor inverters to be packaged into smaller intelligent power modules (IPMs) without the need for heat sinks.

[0003] However, motor drive applications highly value short-circuit capability in power devices. This poses a significant challenge for GaN devices due to the thermal accumulation effect of their two-dimensional conductive thin layer and their small chip size. Therefore, much research has focused on developing ultrafast short-circuit detection and protection for GaN devices. Existing technologies offer a high-speed short-circuit protection method based on a PCB magnetically coupled current sensor, but this method requires a large PCB area and additional high-speed amplifiers, making it difficult to implement in low-cost applications. Another approach involves rapidly detecting changes in drain terminal voltage, active current limiting by the gate driver, and short-circuit protection based on desaturation-based fault detection. Researchers have also developed an overcurrent protection circuit for GaN gate-injected transistors (GITs) based on detecting gate voltage overcurrent affected by drain current. However, in practical applications, blanking time (typically several hundred nanoseconds) is required to filter out noise, which impacts these fast current detection and protection methods. It has been reported that commercially available 600V GaN devices, under certain conditions (e.g., drain voltage V...),... D (At 400V and a short-circuit duration of 100ns, GaN devices can only withstand a few short-circuit cycles before failing. Therefore, improving the short-circuit withstand time of GaN devices is crucial for enhancing their reliability and performance in motor drive applications.) Summary of the Invention

[0004] This invention focuses on enhancing the short-circuit capability of GaN GIT devices through a novel gate drive scheme. A shunt resistor is added between the device source and reference ground in the gate drive loop, utilizing source negative feedback to limit the short-circuit current. Employing current-mode drive allows the gate voltage of the GIT device to remain as constant as possible, ensuring that the on-resistance of the GaN GIT device does not degrade due to underdrive during normal operation.

[0005] The shunt resistor not only utilizes source negative feedback to limit the short-circuit peak current of GaN-GIT devices, but also serves as an indispensable current sensing element for low-cost motor control. Experimental results demonstrate that this driving scheme significantly improves the short-circuit capability of the device, increasing the number of consecutive short-circuit cycles it can withstand from single digits to over 10. 4 Meanwhile, the gate driving method of this application does not sacrifice other aspects of the performance of the GaN GIT device.

[0006] The gate drive circuit disclosed herein extends the short-circuit duration of GaN GIT devices, thereby improving the robustness and reliability of the system.

[0007] According to one aspect of this disclosure, a gate driving circuit is provided, comprising: a gate injection transistor; a first resistor connected between the source of the gate injection transistor and ground; and a conduction branch connected between a first voltage and the gate of the gate injection transistor, wherein the conduction branch is configured to reduce or turn off the current flowing into the gate of the gate injection transistor in a conduction state in response to the voltage of the gate of the gate injection transistor being higher than a predetermined voltage.

[0008] According to an embodiment of the present disclosure, the conducting branch includes a first current source and a first switch connected in series, and the first current source is configured to maintain a constant output current when the voltage difference across its terminals is higher than or equal to a first value, and to reduce its output current when the voltage difference across its terminals is lower than the first value.

[0009] According to embodiments of this disclosure, the gate driving circuit further includes an input logic block and a turn-off branch. The turn-off branch and the turn-on branch are connected in parallel between the input logic block and the gate of the gate injection transistor. The input logic block is configured to output a logic level to the turn-on branch and the turn-off branch. The turn-on branch is configured to be in a conducting state when the logic level is high. The turn-off branch is configured to be in a conducting state when the logic level is low, so as to discharge the gate of the gate injection transistor.

[0010] According to embodiments of this disclosure, the conducting branch includes a plurality of strings connected in parallel with each other, each of the plurality of strings including a first switch and a first current source connected in series with each other.

[0011] According to embodiments of this disclosure, the shut-off branch includes a second switch and a second current source connected in series.

[0012] According to embodiments of this disclosure, the shut-off branch includes a second switch and a second resistor connected in series.

[0013] According to embodiments of this disclosure, the shutdown branch includes a first shutdown branch and a second shutdown branch connected in parallel with each other. The first shutdown branch includes a second switch and a second resistor connected in series, and the second shutdown branch includes a Miller clamp switch.

[0014] According to embodiments of this disclosure, the turn-on branch includes a first switching transistor and a current source implemented by a current mirror. The current mirror includes a bipolar transistor, a second resistor, a third resistor, a fourth resistor, and a capacitor. The input logic block includes an inverter. The turn-off branch includes a fifth resistor and a second switching transistor. The output of the inverter is connected to the gates of the first and second switching transistors. The first terminal of the first switching transistor is connected to a first voltage. The capacitor and the second resistor are connected in parallel between the bipolar transistor and the second terminal of the first switching transistor. The third resistor is connected between the bipolar transistor and the first voltage. The fourth resistor is connected between the bipolar transistor and ground. One end of the fifth resistor is connected to the gate of the gate injection transistor and the bipolar transistor. The other end of the fifth resistor is connected to the first terminal of the second switching transistor. The second terminal of the second switching transistor is connected to ground.

[0015] According to embodiments of this disclosure, the turn-on branch includes a first switching transistor and a current source implemented by a current mirror. The current mirror includes a first MOS transistor, a second MOS transistor, and a bias current source. The input logic block includes an inverter. The turn-off branch includes a second resistor and a second switching transistor. The output terminal of the inverter is connected to the gate of the first switching transistor and the gate of the second switching transistor. The first terminal of the first switching transistor is connected to a first voltage. One end of the second resistor is connected to the gate of the gate injection transistor, and the other end of the second resistor is connected to the first terminal of the second switching transistor. The second terminal of the second switching transistor is connected to ground.

[0016] According to embodiments of this disclosure, a gate voltage of a gate-injected transistor being higher than a predetermined voltage indicates that a short circuit has occurred in the gate-injected transistor.

[0017] According to embodiments of this disclosure, the gate injection transistor is a gallium nitride-based gate injection transistor.

[0018] According to another aspect of this disclosure, a driving method for a gate driving circuit is provided, wherein the gate driving circuit includes: a gate injection transistor; a first resistor connected between the source of the gate injection transistor and ground; and a conduction branch connected between a first voltage and the gate of the gate injection transistor, wherein the driving method includes: detecting the gate potential of the gate injection transistor through the conduction branch; and if the gate potential is higher than a predetermined voltage, reducing or turning off the output current flowing to the gate of the gate injection transistor through the conduction branch.

[0019] According to embodiments of the present disclosure, the gate driving circuit further includes a turn-off branch, and the driving method further includes: discharging the gate of the gate injection transistor through the turn-off branch to turn off the gate injection transistor.

[0020] According to the present invention, when the GIT device (i.e., gate injection transistor) is short-circuited, the short-circuit current causes the voltage across the first resistor to increase, raising the source potential. Consequently, the gate potential of the GIT device also increases, reducing the voltage difference between the conducting branches. Therefore, the current flowing into the gate of the GIT device from the conducting branches decreases, and the gate voltage (V0) of the GIT device decreases. GS As the heat dissipation factor (FDM) decreases, the short-circuit current of the GIT device decreases, resulting in lower short-circuit power consumption. Consequently, the damage to the GIT device caused by heat dissipation is reduced, and the number of short-circuit cycles the GIT device can withstand increases. Attached Figure Description

[0021] The illustrative, non-limiting exemplary embodiments will be understood more clearly from the following detailed description taken in conjunction with the accompanying drawings.

[0022] Figures 1 to 6 A diagram of a gate drive circuit according to an embodiment of the present disclosure is shown.

[0023] Figure 7(a) shows a circuit diagram of a gate drive circuit according to an embodiment of the present disclosure.

[0024] Figure 7(b) shows a circuit diagram of a gate drive circuit according to another embodiment of the present disclosure.

[0025] Figure 8 Typical IV curves of current sources in the conduction branch of a gate drive circuit according to an embodiment of the present disclosure are shown.

[0026] Figure 9 The static turn-on IV curves of the gate drive circuit according to an embodiment of the present disclosure are shown with different bias resistors R4.

[0027] Figure 10 The gate drive circuit according to embodiments of the present disclosure is shown under different drive currents (V). D =0V) Gate potential V for the experiment G and gate current I G The waveform diagram.

[0028] Figure 11 The gate drive circuit according to embodiments of the present disclosure is shown under different drive schemes (V D =311V,T P The short-circuit waveform of the experiment (=1μs).

[0029] Figure 12 The number of short-circuit cycles experienced by a gate drive circuit according to an embodiment of the present disclosure before failure / failure is shown. Detailed Implementation

[0030] In the embodiments, see Figure 1The gate drive circuit includes a GIT device 001, a shunt resistor 002, an input logic block 030, a turn-on branch 010, and a turn-off branch 020. In an embodiment, the GIT device 001 may be a GaN gate-injected transistor. In an embodiment, the turn-on branch 010 and the turn-off branch 020 are connected in parallel between the input logic block and the gate of the GIT device 001. In an embodiment, the first terminal (e.g., the drain) of the GIT device 001 may be connected to a first voltage V. dri The second terminal (e.g., the source terminal) can be connected to one end of the shunt resistor (Rs) 002. The other end of the shunt resistor 002 can be grounded.

[0031] Input logic block 030 is configured to output logic levels for the conduction branch 010 and the shutdown branch 202.

[0032] The turn-on branch 010 is configured to be turned on when the logic level is high, and is configured to reduce or turn off the current flowing into the gate of the GIT device when the gate potential of the GIT device is higher than a predetermined voltage. The turn-off branch 020 is configured to be turned on when the logic level is low to discharge the gate of the GIT device.

[0033] In other words, the conduction branch 010 is used to detect the gate potential of the GIT device, and when the gate potential is higher than a predetermined voltage, the conduction branch 010 reduces or turns off the current flowing into the gate of the GIT device. According to an embodiment, a short circuit in the GIT device will cause the gate potential to be higher than the predetermined voltage.

[0034] In the embodiments, see Figure 2 The conducting branch 010 may include a current source 011 and a switch 012 connected in series. In an embodiment, one end of the current source 011 may be connected to an external power source to receive a first voltage V applied by the external power source. dri The other end of current source 011 can be connected to one end of switch 012. Current source 011 can be used to drive GIT device 001. Switch 012 can switchably connect current source 011 to the gate of GIT device. For example, when the output of input logic block 030 is high (e.g., logic 1), switch 012 can be in the ON state to connect current source 011 to the gate of GIT device. When the output of input logic block 030 is low (e.g., logic 0), switch 012 can be in the OFF state to disconnect current source 011 from GIT device. At this time, switch 022 (see...) Figure 4 It can be in the ON state, thereby discharging the gate of the GIT device.

[0035] Specifically, when a short circuit occurs in the GIT device, due to the first voltage V driSince the voltage across the shunt resistor Rs is constant, the voltage across the shunt resistor Rs increases, and the gate potential of the GIT device also increases synchronously, which reduces the voltage difference in the conducting branch 010, thereby automatically reducing or turning off the gate current of the GIT device.

[0036] According to embodiments of this disclosure, input logic block 030 and shutdown branch 020 can be omitted.

[0037] In the embodiments, see Figure 3 The conducting branch 010 can be implemented by multiple series-connected current sources and switches. In an embodiment, the conducting branch 010 may include a first string consisting of a series-connected current source 011 and switch 012, and a second string consisting of a series-connected current source 013 and switch 014. The connection methods of the current source 011 and switch 012 in the first string and the current source 013 and switch 014 in the second string are the same as described above. Figure 2 The connection method of the current source 011 and switch 012 is the same, and will not be repeated here. In the embodiment, in addition to the first and second strings, the conducting branch 010 may include more strings, each string of which may include a current source and a switch connected in series. In this way, the conducting branch 010 can sequentially output current pulses with different amplitudes. This can be achieved by controlling the magnitude of the current provided by the current sources 011 and 013 and the switching sequence of switches 012 and 014. According to the present invention, by implementing the conducting branch 010 as multiple strings of current sources and switches connected in series, the GIT device can be turned on in stages, reducing the turn-on delay time, reducing switching losses, and controlling the voltage change rate of the GIT device during turn-on, thereby achieving better EMC performance.

[0038] In the embodiments, see Figure 4 The shutdown branch 020 can be implemented by a current source 021 and a switch 022, wherein the current source 021 and the switch 022 can be connected in series. In an embodiment, one end of the current source 021 can be connected to one end of the conduction branch 010 and the gate of the GIT device, and the other end of the current source 021 can be connected to the switch 022. In an embodiment, the switch 022 can switchably connect the gate of the GIT device to ground via the current source 021. For example, when the output of the input logic block 030 is low (e.g., logic 0), the switch 022 can be in the on state, so that the gate of the GIT device is connected to ground via the current source 021, thereby discharging the gate of the GIT device and turning off the GIT device. When the output of input logic block 030 is high (e.g., logic 1), switch 022 can be in the off state so that the off branch 020 does not work. At this time, switch 012 is in the on state so that current flows through the on branch 010 to the gate of the GIT device, thereby turning on the GIT device.

[0039] In the embodiments, see Figure 5 The turn-off branch 022 can be implemented by a turn-off resistor 023 and a switch 022, wherein the turn-off resistor 023 and the switch 022 can be connected in series. In an embodiment, one end of the turn-off resistor 023 can be connected to the gate of the conduction branch 010 and the GIT device, and the other end of the turn-off resistor 023 can be connected to the switch 022. That is, the turn-off resistor 023 can replace... Figure 4 The current source 021 is used in the circuit. For example, when the output of input logic block 030 is low (e.g., logic 0), switch 022 can be in the ON state, so that the gate of the GIT device is electrically connected to ground via turn-off resistor 023, thereby discharging the gate of the GIT device and turning it off. When the output of input logic block 030 is high (e.g., logic 1), switch 022 can be in the OFF state, so that the turn-off branch 020 is inactive. At this time, switch 012 is in the ON state, so that current flows through the gate of the GIT device via the ON branch 010, thereby turning on the GIT device. According to an embodiment of the present invention, by replacing current source 021 with turn-off resistor 023, the gate discharge of the GIT device can be achieved while simplifying the circuit structure.

[0040] In the embodiments, see Figure 6 In addition to the turn-off resistor 023 and switch 022, the turn-off branch 020 may also include a third switch 024. The third switch 024 may be a Miller clamp switch. The third switch 024 can be used to switchably connect the gate of the GIT device to ground. According to the present invention, by including the Miller clamp switch 024, the turn-off branch 020 can have a lower impedance, thereby preventing the drain of the GIT device from being mis-connected through capacitor Cgd during external pull-up, thus reducing GIT switching losses and improving its operational reliability.

[0041] Figure 7(a) shows a circuit diagram of a gate drive circuit according to an embodiment of the present disclosure.

[0042] Referring to Figure 7(a) Figure 1 The conduction branch 010 may include a switching transistor M1 and a current source implemented by a current mirror. The current mirror includes bipolar transistors Q1 and Q2, matching resistors R1 and R3, and a bias resistor R4. Optionally, the conduction branch 010 may also include a capacitor C1 connected in parallel with the matching resistor R1. The function of capacitor C1 is to add instantaneous current during conduction. The turn-off branch consists of a switching transistor M2 and a turn-off resistor R2. The input logic module is implemented by an inverter.

[0043] Specifically, the output of the inverter is connected to the gate of the switching transistor M1. The switching transistor M1 can be a PMOS transistor. Capacitor C1 and matching resistor R1 are connected in parallel between one end of the bipolar transistor and the first terminal (e.g., drain) of the switching transistor M1. The second terminal (e.g., source) of the switching transistor M1 can be connected to the power supply voltage Vdri. Bias resistor R4 can be connected between one end of the bipolar transistor and ground. Matching resistor R3 can be connected between the power supply voltage Vdri and the other end of the bipolar transistor. The switching transistor M2 can be an NMOS transistor. The gate of the switching transistor M2 can be connected to the output of the input logic block. The first terminal (e.g., drain) of the switching transistor M2 can be connected to one end of the turn-off resistor R2. The other end of the turn-off resistor R2 can be connected to the gate of the GIT device and one end of the bipolar transistor. The second terminal (e.g., source) of the switching transistor M2 can be grounded.

[0044] When the GIT device is short-circuited, the short-circuit current causes the shunt resistor R to... S As the voltage on the gate increases, the source potential rises, and the gate potential of the GIT device also rises. The collector-emitter voltage difference of transistor Q1 decreases, thus reducing the current flowing into the gate of the GIT device from the conduction branch 010. This lowers the gate voltage (V0) of the GIT device. GS As the heat dissipation factor (FDM) decreases, the short-circuit current of the GIT device decreases, resulting in lower short-circuit power consumption. Consequently, the damage to the GIT device caused by heat dissipation is reduced, and the number of short-circuit cycles the GIT device can withstand increases.

[0045] When the gate potential V at the gate of the GIT device G When it is above the inflection point (e.g.) Figure 9 As shown in the diagram, the gate drive current drops sharply as transistor Q1 enters the transistor region. Since a larger voltage drop across the matching resistor R1 results in a higher drive current, the gate potential V... G The smaller the corresponding inflection point voltage, the better. Adding the voltage across matching resistor R1 to the saturation voltage of Q1 yields the net voltage (V). head Therefore, it is not difficult to derive the shunt resistor R. S The relationship between it and the short-circuit current is expressed as follows:

[0046] Among them, I SC For short-circuit current, V GS_ON This is the turn-on voltage of the GIT device (typically 3.5V). From the above formula, the shunt resistor R can be used to... S Predetermine the short-circuit current or saturation current of the GIT device.

[0047] It is understandable that the short-circuit current determines how long the GIT device can withstand a short circuit without damage. Therefore, the shunt resistor R can be determined based on the desired short-circuit current. S The appropriate value. For example, the value of the shunt resistor can be from several hundred milliohms to several ohms, such as 100mΩ to 10Ω. Covering the power range from tens of W to hundreds of W.

[0048] Figure 7(b) shows a circuit diagram of a gate drive circuit according to another embodiment of the present disclosure.

[0049] The gate drive circuit includes an input logic block, a turn-on branch, a turn-off branch, a GIT device, and a shunt resistor Rs. The turn-on branch includes a switching transistor M1 and a current source composed of a current mirror. The current mirror consists of MOS transistors M3 and M4 and a bias current source I. B Composition: The shutdown branch consists of switch M2 and shutdown resistor R2. The input logic block is implemented using inverters.

[0050] Specifically, the conduction branch in this embodiment differs from that in Figure 7(a). In Figure 7(b), MOS transistors M3 and M4 can be PMOS transistors, respectively. In Figure 7(b), the gate of switching transistor M1 is connected to the output of the input logic block, its source is connected to the drain of MOS transistor M3, and its drain is connected to the gate of the GIT device. Bias current source I B It is connected between ground and the drain of MOS transistor M4.

[0051] When the GIT device is short-circuited, the short-circuit current causes the shunt resistor R to... S As the voltage on the gate increases, the source potential rises, and the gate potential of the GIT device also rises. The voltage difference between the MOS transistors decreases, thus reducing the current flowing into the gate of the GIT device from the conduction branch, and consequently, the gate voltage (V) of the GIT device decreases. GS As the heat dissipation factor (FDM) decreases, the short-circuit current of the GIT device decreases, resulting in lower short-circuit power consumption. Consequently, the damage to the GIT device caused by heat dissipation is reduced, and the number of short-circuit cycles the GIT device can withstand increases.

[0052] Specifically, in the embodiment, when the input logic block receives an external signal indicating the enable logic, the conduction branch is enabled and the shutdown branch is disabled, thus enabling the GIT device to conduct; when the input logic block receives an external signal indicating the disable logic, the conduction branch is disabled and the shutdown branch is enabled, thus enabling the GIT device to disable. When the conduction branch is enabled, if a short-circuit event occurs in the GIT device, the current flowing from the conduction branch into the gate of the GIT device decreases, limiting the short-circuit current.

[0053] In other words, in the embodiments of this application, the shunt resistor R SThe gate drive circuit is configured to work in conjunction with a gate current source. Thus, when a short circuit occurs in the GaN GIT device, the source potential rises, and the gate voltage V... GS The channel short-circuit current decreases, which in turn suppresses the rise of the source potential (i.e., using source negative feedback to limit the short-circuit current). In this way, short-circuit power consumption is reduced. Therefore, the damage to the GIT device caused by heat dissipation is reduced, and thus the number of short-circuit cycles the GIT device can withstand increases.

[0054] Figure 8 A typical IV curve for a current source in a conducting branch is shown. Only when the voltage direction is opposite to the arrow (see, for example, [reference]). Figures 2 to 4 The current source exhibits constant current characteristics only when the current direction indicated by the arrow (in the middle section) is consistent with that of the current source. If the voltage across the current source approaches zero, the output current will drop to zero. That is, in the conducting branch according to the present invention, when the voltage difference across the current source is higher than or equal to a first value (i.e., the value that gives it constant current characteristics), its output current remains constant, and when the voltage difference across its terminals is lower than the first value, its output current decreases.

[0055] Combination Figure 8 When the gate potential of the GIT device is higher than the predetermined voltage (i.e., the GIT device is short-circuited), the source potential rises, causing the voltage across the current source to drop below the voltage that makes the current source have constant current characteristics. As a result, the current input from the current source to the GIT device decreases, thereby reducing the gate voltage limit of the GIT device for short-circuit current.

[0056] Figure 9 The static on-state IV curves of the gate drive circuit with different resistance values ​​for the bias resistor R4 in Figure 7(a) are shown. Figure 9 As can be seen, the larger the value of R4, the higher the gate potential at the inflection point. The bias resistor R4 can be used to adjust the gate conduction branch current (gate current I). G The size of the ) controls the conduction speed of the GIT device.

[0057] Figure 10 The gate drive circuit is shown under different drive currents (V). D =0V) Gate potential V for the experiment G and gate current I G The waveform diagram. The gate conduction branch current (gate current I) can be adjusted using the bias resistor R4. G The size of the ) controls the conduction speed of the GIT device.

[0058] Figure 11 The gate drive circuit according to embodiments of the present disclosure is shown under different drive schemes (V D=311V,T P The short-circuit waveform was obtained from an experiment with a current of 1 μs. Observations showed that the peak short-circuit current was reduced by approximately half after adopting a source-feedback-based gate drive scheme, indicating a significant reduction in thermal stress.

[0059] Figure 12 The number of short-circuit cycles experienced by a gate drive circuit according to an embodiment of the present disclosure before a fault is shown. Figure 12 The figures show (a) V respectively. D =311V and (b) V D At a voltage of 400V, the number of short-circuit cycles the gate drive circuit withstands for different durations is shown. It can be seen that the gate drive circuit experiences different short-circuit durations (T0) at 1 microsecond and 10 microseconds. P ) and V D Under the condition of 311V, it can continuously withstand 10 4 The gate drive circuit can withstand a short-circuit cycle without failure; while a gate drive circuit without source feedback drive (i.e., without a shunt resistor Rs) can only withstand a single-digit number of short-circuit cycles under the same conditions before failing. The gate drive circuit according to this disclosure... P =1 µs and V D It also showed a significant improvement in short-circuit performance under the condition of 400 V.

[0060] According to embodiments of this disclosure, a method for enhancing short-circuit capability is provided, comprising: detecting the gate potential of a GIT device through a conduction branch; if the gate potential is higher than a predetermined voltage, reducing or shutting off the output current flowing to the gate of the GIT device through the conduction branch. According to embodiments of this disclosure, the method further comprises: discharging the gate of the GIT device through a shutdown branch to shut off the GIT device.

[0061] The foregoing description is illustrative of exemplary embodiments and should not be construed as limiting them. Although some exemplary embodiments have been described, those skilled in the art will readily understand that many modifications can be made to the exemplary embodiments without substantially departing from the novel teachings and advantages of the exemplary embodiments. Therefore, all such modifications are intended to be included within the scope of the exemplary embodiments defined in the claims. It should be understood that the foregoing description is illustrative of various exemplary embodiments and should not be construed as limiting to the specific exemplary embodiments disclosed, and modifications to the disclosed exemplary embodiments and some of the exemplary embodiments are intended to be included within the scope of the appended claims.

Claims

1. A gate driving circuit, comprising: Gate injection transistor; A first resistor is connected between the source of the gate-injected transistor and ground; The conduction branch is connected between the first voltage and the gate of the gate-injected transistor. The conducting branch is configured to reduce or turn off the current flowing into the gate of the gate injection transistor in response to the gate potential of the gate injection transistor being higher than a predetermined voltage when the transistor is in the conducting state.

2. The gate driving circuit according to claim 1, wherein, The conducting branch includes a first current source and a first switch connected in series, and The first current source is configured to maintain a constant output current when the voltage difference across its terminals is higher than or equal to a first value, and to reduce its output current when the voltage difference across its terminals is lower than the first value.

3. The gate driving circuit according to claim 1, wherein, The gate drive circuit further includes an input logic block and a turn-off branch, wherein the turn-off branch and the turn-on branch are connected in parallel between the input logic block and the gate of the gate injection transistor. The input logic block is configured to output logic levels to the on branch and the off branch; The conducting branch is configured to be in the conducting state when the logic level is high. and The shutdown branch is configured to be turned on when the logic level is low to discharge the gate of the gate-injected transistor.

4. The gate driving circuit according to claim 3, wherein, The conducting branch includes multiple strings connected in parallel to each other, each of the multiple strings including a first switch and a first current source connected in series to each other.

5. The gate driving circuit according to claim 3, wherein, The shutdown branch includes a second switch and a second current source connected in series.

6. The gate driving circuit according to claim 3, wherein, The shutdown branch includes a second switch and a second resistor connected in series.

7. The gate driving circuit according to claim 3, wherein, The shutdown branch includes a first shutdown branch and a second shutdown branch connected in parallel. The first shutdown branch includes a second switch and a second resistor connected in series, and the second shutdown branch includes a Miller clamp switch.

8. The gate driving circuit according to claim 3, wherein, The conducting branch includes a first switching transistor and a current source implemented by a current mirror, wherein the current mirror includes a bipolar transistor, a second resistor, a third resistor, a fourth resistor, and a capacitor. The input logic block includes an inverter. The shutdown branch includes a fifth resistor and a second switching transistor. The output of the inverter is connected to the gates of the first and second switching transistors. The first terminal of the first switching transistor is connected to the first voltage. The capacitor and the second resistor are connected in parallel between the bipolar transistor and the second terminal of the first switching transistor. The third resistor is connected between the bipolar transistor and the first voltage. The fourth resistor is connected between the bipolar transistor and ground. One end of the fifth resistor is connected to the gate of the gate injection transistor and the bipolar transistor, and the other end of the fifth resistor is connected to the first terminal of the second switching transistor, and the second terminal of the second switching transistor is connected to ground.

9. The gate driving circuit according to claim 3, wherein, The conduction branch includes a first switching transistor and a current source implemented by a current mirror, wherein the current mirror includes a first MOS transistor, a second MOS transistor, and a bias current source. The input logic block includes an inverter. The shutdown branch includes a second resistor and a second switching transistor. The output of the inverter is connected to the gates of the first and second switching transistors, and the first terminal of the first switching transistor is connected to the first voltage. One end of the second resistor is connected to the gate of the gate injection transistor, the other end of the second resistor is connected to the first terminal of the second switching transistor, and the second terminal of the second switching transistor is connected to ground.

10. The gate driving circuit according to claim 3, wherein, A voltage at the gate of the gate-injected transistor that is higher than a predetermined voltage indicates that a short circuit has occurred in the gate-injected transistor.

11. The gate driving circuit according to claim 3, wherein, The gate injection transistor is a gallium nitride-based gate injection transistor.

12. A driving method for a gate driving circuit, wherein the gate driving circuit comprises: Gate injection transistor; A first resistor is connected between the source of the gate-injected transistor and ground; A conduction branch is connected between the first voltage and the gate of the gate-injected transistor, wherein the driving method includes: The gate potential of the gate injection transistor is detected through the conduction branch; as well as If the gate potential is higher than a predetermined voltage, the output current flowing to the gate of the gate-injected transistor is reduced or turned off through the conduction branch.

13. The driving method according to claim 12, wherein, The gate drive circuit further includes a turn-off branch, and the method further includes: The gate of the gate injection transistor is discharged through the shutdown branch to turn off the gate injection transistor.

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