High-speed acquisition device based on 4.5 GCPHY and DPHY

Abstract

A high-speed acquisition device based on 4.5 GCPHY and DPHY relates to the technical field of camera testing and comprises an acquisition module, a mode switching module, an FPGA processing module, a storage module, a transmission module and a power supply module. The acquisition module is connected with the mode switching module and is used for being connected with an external camera and receiving original image data; the working mode of the acquisition module comprises a CPHY mode and a DPHY mode; the FPGA processing module is respectively connected with other modules, synchronously sends instructions, processes original image data and stores the original image data in the storage module; the transmission module is used for uploading the image data to external equipment; the power module is used for providing an adjustable power supply. According to the invention, CPHY and DPHY dual-mode adaptation is realized, high-pixel cameras with different interface types are covered, high-speed acquisition, processing, storage and uploading of original image data are completed, and the test requirements of the high-pixel cameras are met.

Description

Technical Field

[0001] This application relates to the field of camera testing technology, specifically to a high-speed acquisition device based on 4.5G CPHY and DPHY. Background Technology

[0002] As an indispensable electronic product in modern life, mobile phones are becoming increasingly sophisticated and important. Sometimes, mobile phones can replace cameras as the main device for taking pictures and videos. People's requirements for image frame rate and image quality are constantly increasing, which places higher demands on the power stability, accuracy, noise fluctuation, signal-to-noise ratio, and bit error rate of camera modules. As a result, cameras with higher pixels and image quality are being used in mobile phones. However, the testing methods for camera modules are still at a low level and cannot meet the testing requirements of modern camera modules. Summary of the Invention

[0003] To address the aforementioned problems, this application provides a high-speed data acquisition device based on 4.5G CPHY and DPHY, the device comprising: The system includes an acquisition module, a mode switching module, an FPGA processing module, a storage module, a transmission module, and a power supply module. The acquisition module is connected to the mode switching module and is used to connect to an external camera to receive raw image data from the camera. After the mode switching module selects the working mode, the acquisition module transmits the raw image data to the FPGA processing module. The working modes include CPHY mode and DPHY mode. The FPGA processing module is connected to the other modules and synchronously sends acquisition commands to the acquisition module, power supply commands to the power supply module, and mode switching commands to the mode switching module. The FPGA processing module processes the raw image data and stores the processed image data in the storage module. The transmission module is used to connect to external devices and upload image data to them; The power module is connected to the other modules and the camera to provide adjustable power.

[0004] By adopting the above technical solution, dual-mode adaptation of CPHY and DPHY is achieved, covering high-pixel cameras with different interface types, and high-speed acquisition, processing, storage and uploading of raw image data are completed, solving the core problem that existing testing methods cannot meet the testing requirements of high-pixel cameras.

[0005] In one specific feasible implementation, the data acquisition module includes: CPHY acquisition unit and DPHY acquisition unit; The CPHY acquisition unit consists of a three-wire group, and the clock information and data signal of the CPHY acquisition unit are transmitted on the same line. The DPHY acquisition unit includes a differential line pair and is configured with an independent differential clock transmission line.

[0006] By adopting the above technical solutions, the transmission structure of the acquisition unit is optimized, the CPHY unit clock and data are transmitted in a common line to reduce wiring interference, the DPHY unit independent differential clock ensures synchronization accuracy, and the stability and rate of high-pixel camera data transmission are improved.

[0007] In a specific implementable scheme, the CPHY acquisition unit and the DPHY acquisition unit are both connected to the IO port of the FPGA processing module through independent links, one or more CPHY acquisition units, one or more DPHY acquisition units, or both CPHY acquisition units and DPHY acquisition units are selectively enabled through the mode switching module; the single-link transmission rate of the CPHY acquisition unit and the DPHY acquisition unit is both 4.5 Gbps.

[0008] By adopting the above technical solutions, independent link transmission and selective enablement of the acquisition unit are realized, signal cross-interference in different modes is avoided, the flexibility and reliability of mode switching are improved, and the accuracy of multi-type camera testing is ensured.

[0009] In a specific implementable scheme, the transmission module includes: a QSFP optical module and a network card module; The QSFP optical module is connected to the high-speed transceiver channel of the FPGA processing module, receives data output by the FPGA processing module, and performs optical signal conversion, and is connected to external equipment through an optical fiber line; The network card module is used for realizing wired data transmission and is connected to the wired port of external equipment.

[0010] By adopting the above technical solutions, a dual-path architecture of optical transmission and wired transmission is constructed, which is suitable for long-distance and short-distance data uploading scenarios, breaks through the bandwidth limitation of traditional transmission links, and ensures the continuity and efficiency of high-capacity image data transmission.

[0011] In a specific implementable scheme, the QSFP optical module includes a reference clock chip, which is used for ensuring transmission timing consistency.

[0012] By adopting the above technical solutions, the transmission timing consistency of the QSFP optical module is ensured, timing drift and errors in high-speed data transmission are reduced, and the transmission accuracy of high-pixel camera test data is improved.

[0013] In one specific implementation scheme, the mode switching module includes a switching chip that switches the operating mode via a level control signal. The switching chip receives the level control signal output by the FPGA processing module. A low-level control signal of a single switching chip corresponds to the activation of the CPHY acquisition unit link under its jurisdiction, and a high-level control signal corresponds to the activation of the DPHY acquisition unit link under its jurisdiction. The level signals of multiple switching chips can be configured independently.

[0014] By adopting the above technical solution, we can achieve rapid and stable switching of working modes, adapt to the rapid testing needs of cameras with different interfaces, reduce the testing delay caused by mode switching, and improve the overall testing efficiency.

[0015] In one specific implementation, the storage module includes a memory chip for storing image data.

[0016] By adopting the above technical solution, a large-capacity, high-speed data cache space is provided to meet the temporary storage needs of raw image data and processed data from high-pixel cameras, thus avoiding test interruptions caused by data overflow.

[0017] In one specific implementation, the power module is also used to collect power noise and voltage stability data and transmit them to the FPGA processing module.

[0018] By adopting the above technical solution, the power supply operating status can be monitored in real time, and power supply noise and voltage stability data can be fed back in a timely manner, providing a basis for power supply parameter adjustment and ensuring the power supply stability and accuracy required for high-pixel camera testing.

[0019] In one specific feasible implementation, the data acquisition module includes: An independent power supply circuit, including multi-stage filter capacitors, is used to suppress power ripple during high-speed signal transmission.

[0020] By adopting the above technical solutions, power ripple interference during high-speed signal transmission can be suppressed, ensuring that the acquisition module operates in a stable power supply environment, reducing the impact of ripple on signal quality, and improving the reliability of high-pixel camera test data.

[0021] In one specific implementation, the FPGA processing module is also used to record test process data, which includes: Link status of the acquisition module, read / write rate of the storage module, and voltage and current parameters of the power supply module; When data frame loss or power supply noise exceeds the standard, the FPGA processing module triggers an alarm and stores the relevant data at the time of the abnormality, which is stored in blocks named according to time rules.

[0022] By adopting the technical scheme, the test process data is traced and stored, and problems such as data frame loss and power noise exceeding the standard are quickly located, so that the troubleshooting efficiency and test reliability of the high-pixel camera test are improved. BRIEF DESCRIPTION OF DRAWINGS

[0023] Figure 1 is a module schematic diagram of a high-speed acquisition device based on 4.5G CPHY and DPHY provided by the embodiment of the application. DETAILED DESCRIPTION

[0024] In order for those skilled in the art to better understand the technical solutions in the specification, the technical solutions in the embodiments of the specification will be clearly and completely described below in conjunction with the drawings in the embodiments of the specification. Obviously, the described embodiments are only some of the embodiments of the application, not all the embodiments.

[0025] In the description of the embodiments of the application, the words such as "for example" or "for instance" are used to represent an example, illustration or description. Any embodiment or design scheme described as "for example" or "for instance" in the embodiments of the application should not be interpreted as more preferred or more advantageous than other embodiments or design schemes. Rather, the words such as "for example" or "for instance" are intended to present the relevant concept in a specific manner.

[0026] In the description of the embodiments of the application, the term "a plurality of" means two or more. In addition, the terms "first", "second" are used for description purposes only, and should not be interpreted as indicating or implying relative importance or implicitly indicating the indicated technical features. Therefore, the features defined with "first", "second" can explicitly or implicitly include one or more features. The terms "include", "contain", "have" and their variants mean "include but are not limited to", unless otherwise specifically emphasized.

[0027] The following will be described in detail in combination with the drawings in the embodiments of the application. Figure 1 The application will be further described in detail.

[0028] The embodiment of the application discloses a high-speed acquisition device based on 4.5G CPHY and DPHY, such as Figure 1As shown, the device comprises a collection module, a mode switching module, an FPGA processing module, a storage module, a transmission module and a power module; the collection module is connected with the mode switching module and is used to connect with an external camera and receive original image data of the camera; after the mode switching module selects a working mode, the collection module transmits the original image data to the FPGA processing module, and the working mode comprises a CPHY mode and a DPHY mode; the FPGA processing module is connected with the remaining modules respectively, synchronously sends a collection instruction to the collection module, a power supply instruction to the power module and a mode switching instruction to the mode switching module, the FPGA processing module processes the original image data, and stores processed image data in the storage module; the transmission module is used to connect with an external device and upload image data to the external device; the power module is connected with the remaining modules and the camera respectively and is used to provide adjustable power supply.

[0029] In some embodiments, the collection module is connected with an external camera through a hardware interface, the hardware interface is adapted to a CPHY or DPHY interface type of the camera and is compatible with camera modules of different pixel specifications; the collection module is directly connected with the mode switching module through a signal line, and original image data is transmitted to the mode switching module through the line.

[0030] Further, the mode switching module receives a mode switching instruction output by the FPGA processing module, switches the original image data transmitted by the collection module to a corresponding transmission path according to the instruction and then transmits the original image data to the FPGA processing module.

[0031] In some embodiments, the core chip of the FPGA processing module adopts XCVM2152-2MSENV M1369-ES9729, the chip integrates a high-speed transceiver channel, an IO interface, a data processing unit and the like; the FPGA processing module is connected with the collection module, the mode switching module, the storage module, the transmission module and the power module through independent control lines and synchronously sends different instructions: sends a collection instruction to the collection module to control the collection module to start or stop data collection; sends a power supply instruction to the power module to adjust power output parameters; and sends a mode switching instruction to the mode switching module to select a CPHY mode or a DPHY mode.

[0032] The processing of the FPGA processing module on the original image data comprises format conversion, converting RAW format data output by the camera into a general image format; noise reduction preprocessing, filtering noise signals in the image through a preset algorithm, and transmitting the processed image data to the storage module through a DDRMC interface for temporary storage.

[0033] The transmission module is connected with the FPGA processing module through a signal line, receives the processed image data output by the FPGA processing module, and then connects external devices through a corresponding transmission medium. The external devices can be computers, servers, and other devices for data storage and analysis.

[0034] The power module is connected with the acquisition module, the mode switching module, the FPGA processing module, the storage module, the transmission module, and the external camera through a power supply line respectively, adjusts the output voltage according to the power supply instruction of the FPGA processing module, and meets the power supply requirements of different modules.

[0035] In some embodiments, the synchronization instruction transmission of the FPGA processing module adopts a parallel signal transmission mechanism, that is, the acquisition instruction, the power supply instruction, and the mode switching instruction are sent through different control lines at the same time, so as to avoid the out-of-sync of the modules caused by the delay of the instruction transmission, improve the acquisition and processing efficiency of the device, and adapt to the high-speed data acquisition requirements of the high-pixel camera.

[0036] In some embodiments, the adjustable voltage range of the power module is 0.8V-3.3V, the voltage accuracy is not higher than 0.05V, and the maximum output current is not less than 1A; the high-speed transceiver channel of the FPGA processing module is a GTM / GTYP series channel, which supports multi-rate data transmission.

[0037] On the basis of the above-mentioned embodiments, as another optional embodiment, the acquisition module comprises: a CPHY acquisition unit and a DPHY acquisition unit; the CPHY acquisition unit comprises a tri, and the clock information of the CPHY acquisition unit is transmitted in a common line with the data signal; the DPHY acquisition unit comprises a differential line pair and is configured with an independent differential clock transmission line.

[0038] In some embodiments, the CPHY acquisition unit and the DPHY acquisition unit are adapted to the CPHY interface and the DPHY interface of the camera respectively, and are used to realize the high-speed acquisition of the raw image data of the camera with different interface types.

[0039] The clock information of the CPHY acquisition unit is transmitted in a common line with the data signal, specifically, the clock signal is modulated into the data signal and transmitted through the same tri, and the receiving end separates the clock information from the data signal through a demodulation algorithm to realize data synchronization. This transmission mode can reduce the number of signal lines, reduce the wiring complexity, and at the same time improve the transmission rate. The tri refers to a transmission unit composed of three signal lines, and the three signal lines jointly undertake the transmission task of data and clock signal without additional configuration of an independent clock transmission line.

[0040] The transmission carrier of the DPHY acquisition unit is a differential line pair, which refers to a transmission unit composed of two signal lines with matched characteristic impedance. The two signal lines transmit differential signals with equal amplitude and opposite polarity, which can effectively suppress common-mode interference. The DPHY acquisition unit is configured with an independent differential clock transmission line, which is composed of two differential signal lines and is used to transmit clock signals. The clock signal provides a synchronization reference for data transmission. The receiving end reads the data signal in the differential line pair according to the rising or falling edge of the clock signal to ensure the accuracy of data transmission. The design of the independent differential clock transmission line can avoid interference between the clock signal and the data signal, and improve the signal-to-noise ratio of signal transmission.

[0041] In some embodiments, the acquisition module includes four independent CPHY acquisition units and four independent DPHY acquisition units, which are suitable for multi-camera module parallel testing scenarios. It can simultaneously interface with four cameras supporting the CPHY interface and four cameras supporting the DPHY interface, meeting the needs of high-pixel mobile phone camera module batch testing.

[0042] The four CPHY acquisition units are a first CPHY acquisition unit, a second CPHY acquisition unit, a third CPHY acquisition unit, and a fourth CPHY acquisition unit. Each CPHY acquisition unit uses a three-wire group as a transmission carrier, and the clock information and data signals are transmitted in a common line. Each CPHY acquisition unit is connected to the dedicated IO port of the FPGA processing module through an independent signal link. The power supply of each CPHY acquisition unit is provided by an independent power supply circuit, and the supply voltage is 1.2V. It is equipped with multi-stage capacitors of 47uF, 10uF, and 0.1uF specifications for filtering to suppress the interference of power supply ripple on high-speed signals.

[0043] The four DPHY acquisition units are a first DPHY acquisition unit, a second DPHY acquisition unit, a third DPHY acquisition unit, and a fourth DPHY acquisition unit. Each DPHY acquisition unit uses a differential line pair as a transmission carrier, and is configured with two groups of differential line pairs and an independent differential clock transmission line. Each DPHY acquisition unit is also connected to the dedicated IO port of the FPGA processing module through an independent signal link. The independent differential clock transmission line of each DPHY acquisition unit is connected to the clock synchronization unit of the FPGA processing module to ensure the consistency of data transmission timing.

[0044] The mode switching module includes four TS3DV642 type high-speed signal switch chips, which correspond to the enable state of the four CPHY acquisition units and the four DPHY acquisition units. The FPGA processing module outputs mode switching instructions through four independent level control lines.

[0045] In work, the FPGA processing module synchronously sends the acquisition instruction to the eight-way acquisition unit, and sends the power supply instruction to the power module. The power module provides stable 1.2V independent power supply for each acquisition unit. When testing four CPHY interface cameras, the FPGA outputs a low-level control signal, and the four switch chips are turned on to the CPHY acquisition unit link. The raw image data of the four cameras is transmitted to the FPGA processing module through the corresponding CPHY acquisition unit three-wire group; when testing four DPHY interface cameras, the FPGA outputs a high-level control signal, and the switch chip is turned on to the DPHY acquisition unit link. The data is transmitted through the differential line pair and the independent clock line; or through the level combination of different switch chips, the mixed parallel test of CPHY and DPHY interface cameras can be realized.

[0046] In some embodiments, the transmission rate of CPHY is 4.5Gbps / tri, supporting 4tri parallel transmission, and the total transmission rate of a single CPHY acquisition unit can reach 40Gbps; the maximum transmission rate of a single differential line pair of each DPHY acquisition unit is 4.5Gbps, and the total transmission rate of four differential line pairs can reach 18Gbps, meeting the acquisition requirements of high-pixel camera simultaneous output of raw image data.

[0047] In other embodiments, the acquisition module can also include two CPHY acquisition units and two DPHY acquisition units, six CPHY acquisition units and six DPHY acquisition units, eight CPHY acquisition units and eight DPHY acquisition units, etc.

[0048] On the basis of the above-mentioned embodiments, as another optional embodiment, the CPHY acquisition unit and the DPHY acquisition unit are connected to the IO port of the FPGA processing module through independent links, and one or more CPHY acquisition units, one or more DPHY acquisition units, or CPHY acquisition units and DPHY acquisition units are selectively enabled through the mode switching module; the single-link transmission rate of the CPHY acquisition unit and the DPHY acquisition unit is 4.5Gbps.

[0049] The independent link refers to the signal transmission line corresponding to each acquisition unit, and the two lines are independent of each other without signal cross interference, ensuring the purity of signal transmission in different working modes. The IO port of the FPGA processing module is a dedicated high-speed IO port, which supports high-speed signal transmission and can match the transmission rate of the CPHY and DPHY acquisition units. The interface level is 1.8V, which meets the level standard of high-speed signal transmission.

[0050] The CPHY acquisition unit and the DPHY acquisition unit are enabled by the mode switching module, and the specific implementation process is as follows: the mode switching module receives the mode control signal output by the FPGA processing module, when the CPHY mode needs to be enabled, the mode switching module turns on the independent link between the CPHY acquisition unit and the FPGA processing module, and at the same time, the corresponding link of the DPHY acquisition unit is disconnected; when the DPHY mode needs to be enabled, the mode switching module turns on the independent link between the DPHY acquisition unit and the FPGA processing module, and at the same time, the corresponding link of the CPHY acquisition unit is disconnected. The turning on and turning off of the link is realized by the switching element in the mode switching module, and the switching response time of the switching element is not more than 1 microsecond, which ensures that there is no interruption in data transmission during mode switching, and can improve the adaptation efficiency of the device to different interface cameras.

[0051] In some embodiments, the independent link of the CPHY acquisition unit includes 12 signal lines, corresponding to 4 groups of three-wire groups; the independent link of the DPHY acquisition unit includes 14 signal lines, corresponding to 7 groups of differential line pairs and 2 clock lines.

[0052] On the basis of the above-mentioned embodiments, as another optional embodiment, the transmission module includes: a QSFP optical module and a network card module; the QSFP optical module is connected with the high-speed transceiver channel of the FPGA processing module, receives the data output by the FPGA processing module and performs optical signal conversion, and is connected with the external device through an optical fiber line; the network card module is used for realizing wired data transmission and is connected with the wired port of the external device.

[0053] In some embodiments, the QSFP optical module is connected with the external device through a 160G optical fiber line; the network card module adopts a 160G network card, which is used for realizing super-high-speed wired data transmission and is connected with the 160G wired port of the external device. Among them, the 160G optical fiber line refers to an optical fiber transmission link supporting a transmission rate of 160Gbps, and the 160G network card refers to a high-speed Ethernet network card with a rate of 160Gbps.

[0054] The QSFP optical module is a four-channel small form-factor pluggable optical module, which is connected with the FPGA processing module through a high-speed transceiver channel. The high-speed transceiver channel is a GTM / GTYP series high-speed serial channel of the FPGA processing module, which supports multi-rate transmission and can match the super-high-speed transmission demand of the QSFP optical module, and further adapt the bandwidth bearing capacity of the 160G optical fiber line.

[0055] The specific working process of the QSFP optical module is as follows: the FPGA processing module transmits the processed image data in the storage module to the QSFP optical module through a high-speed transceiving channel, an electro-optical conversion chip inside the QSFP optical module converts the electrical signal into an optical signal, the optical signal is transmitted to an external device through a 160G optical fiber line, and the optical module of the external device restores the optical signal into an electrical signal for subsequent processing. The high-bandwidth characteristic of the 160G optical fiber line can avoid bandwidth bottleneck during multi-channel data acquisition and transmission, and is suitable for batch uploading of long-distance and large-capacity raw image data, such as multi-device parallel data synchronization in camera mass production testing.

[0056] The 160G network card is a super-speed Ethernet card module, supports 160Gbps wired Ethernet transmission, is connected with the FPGA processing module through a PCIe3.0x16 and above version interface, receives the processed image data output by the FPGA processing module, converts the data into an Ethernet frame format with a corresponding rate, and is connected with a 160G wired port of an external device through a special network cable to realize near-distance super-speed data transmission. This configuration is particularly suitable for parallel working scenarios of four or more CPHY / DPHY acquisition units. When the total transmission bandwidth of the acquisition module reaches 72Gbps or above, the dual-path architecture of the 160G network card and the 160G optical fiber line can fully guarantee the data transmission rate, avoid data frame loss or delay caused by insufficient transmission link bandwidth, and automatically switch between the two paths to ensure the continuity and reliability of data transmission.

[0057] In some embodiments, the QSFP optical module supports a transmission rate of 10Gbps-40Gbps, and when combined with the 160G optical fiber line, a total transmission rate of 160Gbps can be achieved through multi-module binding; the 160G network card supports an Ethernet rate of 160Gbps, and is suitable for the multi-channel parallel data uploading requirement under the 4.5Gbps single-link transmission rate of the CPHY / DPHY acquisition unit; the transmission distance of the 160G optical fiber line can reach several kilometers, and the signal attenuation is low, meeting the long-distance deployment requirement of devices and servers in mass production testing scenarios.

[0058] On the basis of the above-mentioned embodiments, as another optional embodiment, the QSFP optical module includes a reference clock chip for guaranteeing transmission timing consistency.

[0059] The reference clock chip is a core element for providing a stable clock signal for the QSFP optical module, and is used to guarantee the data transmission timing consistency between the QSFP optical module, the FPGA processing module and the external device, and avoid data transmission errors caused by clock signal drift.

[0060] The reference clock chip is integrated in the QSFP optical module, is connected with a signal processing unit of the QSFP optical module through a clock signal line, clock signals output by the reference clock chip are stable in frequency and small in phase jitter, and the reference clock chip provides a time reference for processes such as electro-optical conversion and data frame packaging of the QSFP optical module. Meanwhile, the reference clock chip is connected with a clock synchronization unit of the FPGA processing module through a synchronization signal line, clock synchronization between the QSFP optical module and the FPGA processing module is realized, data output by the FPGA processing module is matched with a receiving timing sequence of the QSFP optical module, and the accuracy of data transmission is improved.

[0061] In some embodiments, the clock signal of the reference clock chip adopts a differential output mode, common-mode interference in a clock signal transmission process can be effectively suppressed, the stability of the clock signal is further improved, and the problem that the clock signal is susceptible to interference in a high-speed transmission scenario is solved.

[0062] In some embodiments, the output clock frequency of the reference clock chip is 103.125 MHz, and the phase jitter of the clock signal is not more than 0.5 ps.

[0063] On the basis of the above-mentioned embodiments, as another optional embodiment, the mode switching module includes a switch chip, and the working mode is switched through a level control signal. The switch chip receives a level control signal output by the FPGA processing module, a low-level control signal of a single switch chip corresponds to turning on a CPHY acquisition unit link under the jurisdiction of the single switch chip, a high-level control signal corresponds to turning on a DPHY acquisition unit link under the jurisdiction of the single switch chip, and the level signals of multiple switch chips can be independently configured.

[0064] In some embodiments, the switch chip is a high-speed analog switch chip, has the characteristics of low on-resistance and high switching speed, and can adapt to the high-speed signal transmission requirement of the CPHY and DPHY acquisition units. The switch chip switches the working mode through a level control signal, the level control signal is generated and output by the FPGA processing module, a control end of the switch chip is a level control pin, the pin receives a level signal output by the FPGA processing module, and the corresponding working mode is selected according to the high and low of the level signal.

[0065] When the level control signal is low, the switch chip switches to the CPHY mode, at this time, the switch channel corresponding to the CPHY acquisition unit in the switch chip is turned on, the original image data transmitted by the CPHY acquisition unit is transmitted to the FPGA processing module through the channel, at the same time, the switch channel corresponding to the DPHY acquisition unit is turned off, so as to avoid the interference signal of the DPHY channel entering the transmission link; when the level control signal is high, the switch chip switches to the DPHY mode, at this time, the switch channel corresponding to the DPHY acquisition unit in the switch chip is turned on, the original image data transmitted by the DPHY acquisition unit is transmitted to the FPGA processing module through the channel, at the same time, the switch channel corresponding to the CPHY acquisition unit is turned off.

[0066] The level control pin of the switch chip has a Schmitt trigger characteristic, which can effectively filter noise interference in the level signal, ensure the accuracy of mode switching, and improve the working stability of the mode switching module in a complex electromagnetic environment.

[0067] In some embodiments, the model of the switch chip is TS3DV642; the voltage range of the low level is 0V-0.8V, and the voltage range of the high level is 2.0V-3.3V; the switching response time of the switch chip is not more than 10ns.

[0068] On the basis of the above-mentioned embodiments, as another optional embodiment, the storage module includes a memory chip for storing image data.

[0069] In some embodiments, the memory chip is a high-speed synchronous dynamic random access memory, which has the characteristics of fast read-write speed and large storage capacity, and is used for storing the original image data of the camera and the image data processed by the FPGA processing module, thereby providing a cache space for data processing and uploading.

[0070] The memory chip is connected with the FPGA processing module through a DDRMC interface, the DDRMC interface supports multi-channel data transmission and can match the high-speed read-write speed of the memory chip. The storage process of the original image data is as follows: after the FPGA processing module receives the original image data transmitted by the mode switching module, the data is written into a specified storage area of the memory chip through the DDRMC interface; the storage process of the processed image data is as follows: after the FPGA processing module performs format conversion and noise reduction preprocessing on the original image data, the processing result is written into another storage area of the memory chip through the DDRMC interface, and the two storage areas are independent of each other, thereby avoiding data coverage.

[0071] The memory chip adopts a dual-memory-die dual-Rank design. The dual-die design refers to that two storage cores are integrated in the memory chip, and the dual-Rank design refers to that the memory chip has two independent storage arrays. This design can improve the parallel read-write capability of the memory chip, and expand the storage capacity to meet the storage demand of high-pixel camera raw image data, and solve the problem of insufficient read-write rate of single-die single-Rank memory.

[0072] In some embodiments, the model of the memory chip is a LPDDR5X memory chip; the capacity of the single memory chip is not less than 768MBx32bit, and the supported read-write rate is not less than 3200Mbps.

[0073] On the basis of the above-mentioned embodiments, as another optional embodiment, the power module is further used to collect power noise and voltage stability data and transmit them to the FPGA processing module.

[0074] In some embodiments, the collection function of the power module is realized through a feedback unit, which includes a current sampling resistor and an analog-to-digital conversion chip. The current sampling resistor is connected in series in the output circuit of the power module. When current passes through the sampling resistor, a voltage drop is generated across the resistor, which is proportional to the output current. The output current data can be indirectly obtained by detecting the voltage drop. The analog-to-digital conversion chip is connected with the current sampling resistor to convert the analog voltage signal across the sampling resistor into a digital signal. The analog-to-digital conversion chip also directly collects the output voltage signal of the power module and converts the voltage analog signal into a digital signal. The power noise data is obtained by detecting the fluctuation amplitude of the voltage signal, and the voltage stability data is obtained by calculating the variance of the continuously collected voltage digital signal.

[0075] The feedback unit is connected with the FPGA processing module through an SPI interface to transmit the collected digital data such as power noise and voltage stability to the FPGA processing module at a transmission rate of not less than 1Mbps to ensure the real-time nature of the data. After receiving the data, the FPGA processing module analyzes the data. When an abnormality is detected, the output parameters of the power module can be adjusted through a power supply instruction, thereby improving the power supply stability of the power module.

[0076] In some embodiments, the model of the analog-to-digital conversion chip is AD5520, the resistance value of the current sampling resistor is 0.05 ohms, and the data collection frequency is 1kHz.

[0077] On the basis of the above-mentioned embodiments, as another optional embodiment, the collection module includes an independent power supply circuit, which includes multiple-stage filtering capacitors for suppressing power supply ripple during high-speed signal transmission.

[0078] In some embodiments, the power supply voltage of the independent power supply circuit is a fixed value, which matches the working voltage requirement of the acquisition module and can provide stable working power supply for the CPHY acquisition unit and the DPHY acquisition unit. The independent power supply circuit includes multi-stage filter capacitors, which are different specifications of ceramic capacitors connected in parallel in the power supply circuit and arranged close to the power input end of the acquisition module to form a near filtering structure.

[0079] The working principle of the multi-stage filter capacitors is that the large-capacity capacitors mainly suppress low-frequency power supply ripple, the medium-capacity capacitors suppress medium-frequency ripple, and the small-capacity capacitors suppress high-frequency ripple. Through the synergistic effect of capacitors of different capacities, power supply ripple suppression in a wide frequency range is achieved, ensuring that the power supply voltage supplied to the acquisition module is smooth and stable and reducing the interference of ripple on high-speed signal transmission. The near filtering structure and multi-stage capacitors combination solve the problem of power supply ripple affecting signal quality in high-speed acquisition scenarios.

[0080] In some embodiments, the power supply voltage of the independent power supply circuit is 1.2V; the specifications of the multi-stage filter capacitors include 47 microfarads, 10 microfarads, and 0.1 microfarad; and the voltage resistance value of the capacitors is not less than 6.3V.

[0081] On the basis of the above-mentioned embodiments, as another optional embodiment, the FPGA processing module is further used to record test process data, the test process data including: link state of the acquisition module, read-write rate of the storage module, voltage and current parameters of the power supply module; when data frame loss or power supply noise exceeds the standard occurs, the FPGA processing module triggers an alarm and stores related data at the abnormal moment, and stores in blocks named by time rules.

[0082] In some embodiments, the link state data of the acquisition module includes link conduction state, signal transmission error rate, etc., which are obtained through the link detection unit of the FPGA processing module; the read-write rate data of the storage module are obtained through the rate detection unit of the DDRMC interface, and the rate of data writing and reading is recorded in real time; the voltage and current parameters of the power supply module are obtained through the digital data transmitted by the feedback unit, including real-time output voltage, output current, voltage fluctuation amplitude, etc. The FPGA processing module stores these data in the special storage area of the storage module, which is convenient for subsequent reading and analysis.

[0083] When data frame loss or power supply noise exceeds the standard occurs, the FPGA processing module triggers an alarm, the alarm mode is to output an alarm signal through the GPIO interface, the alarm signal can control external alarm devices such as indicator lights and buzzers to issue an alarm prompt, and at the same time, the FPGA processing module stores related data at the abnormal moment, and stores in blocks named by time rules.

[0084] In some embodiments, the FPGA processing module also has an automatic analysis function of abnormal data, which can determine the fault cause according to the stored abnormal data, for example, analyze whether the frame loss is caused by link interference or transmission rate mismatch, and whether the power supply noise exceeds the standard is caused by the failure of filter capacitor or load mutation.

[0085] In some embodiments, the judgment threshold of data frame loss is that the number of single-second frame loss exceeds 10 frames; the judgment threshold of power supply noise exceeding the standard is that the voltage fluctuation amplitude exceeds 0.05V; and the storage duration of abnormal data is 1 minute before and after the abnormal moment.

[0086] The collection module of the application includes a plurality of CPHY collection units and a plurality of DPHY collection units, supports parallel testing of multiple camera modules and mixed testing of CPHY / DPHY interface cameras, and the FPGA processing module can record test process data and realize abnormal alarm and data storage, thereby improving test efficiency and troubleshooting ability.

Claims

1. A high-speed data acquisition device based on 4.5G CPHY and DPHY, characterized in that, The device includes: The system includes an acquisition module, a mode switching module, an FPGA processing module, a storage module, a transmission module, and a power supply module. The acquisition module is connected to the mode switching module and is used to connect to an external camera to receive raw image data from the camera. After the mode switching module selects the working mode, the acquisition module transmits the raw image data to the FPGA processing module. The working modes include CPHY mode and DPHY mode. The FPGA processing module is connected to the other modules respectively, and synchronously sends acquisition commands to the acquisition module, power supply commands to the power supply module, and mode switching commands to the mode switching module. The FPGA processing module processes the original image data and stores the processed image data in the storage module. The transmission module is used to connect to an external device and upload the image data to the external device. The power module is connected to the other modules and the camera respectively, and is used to provide adjustable power.

2. The high-speed acquisition device based on 4.5G CPHY and DPHY according to claim 1, characterized in that, The acquisition module includes: CPHY acquisition unit and DPHY acquisition unit; The CPHY acquisition unit includes a three-wire group, and the clock information and data signal of the CPHY acquisition unit are transmitted on the same line. The DPHY acquisition unit includes differential line pairs and is configured with independent differential clock transmission lines.

3. The high-speed acquisition device based on 4.5G CPHY and DPHY according to claim 2, characterized in that, Both the CPHY acquisition unit and the DPHY acquisition unit are connected to the IO port of the FPGA processing module through independent links. The mode switching module can selectively enable one or more CPHY acquisition units, one or more DPHY acquisition units, or enable both CPHY acquisition units and DPHY acquisition units simultaneously. The single-link transmission rate of both the CPHY acquisition unit and the DPHY acquisition unit is 4.5Gbps.

4. The high-speed acquisition device based on 4.5G CPHY and DPHY according to claim 1, characterized in that, The transmission module includes: QSFP optical modules and network interface card modules; The QSFP optical module is connected to the high-speed transceiver channel of the FPGA processing module, receives the data output by the FPGA processing module and performs optical signal conversion, and connects to the external device through an optical fiber. The network interface card module is used to enable wired data transmission and connects to the wired port of the external device.

5. The high-speed acquisition device based on 4.5G CPHY and DPHY according to claim 4, characterized in that, The QSFP optical module includes a reference clock chip to ensure transmission timing consistency.

6. The high-speed acquisition device based on 4.5G CPHY and DPHY according to claim 2, characterized in that, The mode switching module includes a switch chip, which switches the working mode through a level control signal. The switch chip receives the level control signal output by the FPGA processing module. A low-level control signal of a single switch chip corresponds to the activation of the CPHY acquisition unit link under its jurisdiction, and a high-level control signal corresponds to the activation of the DPHY acquisition unit link under its jurisdiction. The level signals of multiple switch chips can be configured independently.

7. The high-speed acquisition device based on 4.5G CPHY and DPHY according to claim 1, characterized in that, The storage module includes a memory chip for storing the image data.

8. The high-speed acquisition device based on 4.5G CPHY and DPHY according to claim 1, characterized in that, The power module is also used to collect power noise and voltage stability data and transmit them to the FPGA processing module.

9. The high-speed acquisition device based on 4.5G CPHY and DPHY according to claim 2, characterized in that, The acquisition module includes: An independent power supply circuit, which includes multi-stage filter capacitors, is used to suppress power ripple during high-speed signal transmission.

10. The high-speed acquisition device based on 4.5G CPHY and DPHY according to claim 1, characterized in that, The FPGA processing module is also used to record test process data, which includes: The link status of the acquisition module, the read / write rate of the storage module, and the voltage and current parameters of the power supply module; When data frame loss or power noise exceeds the standard, the FPGA processing module triggers an alarm and stores the relevant data at the abnormal moment, which is stored in blocks named according to time rules.

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