Memory device, manufacturing method and memory system

Abstract

The embodiment of the invention discloses a memory device, a manufacturing method and a memory system, and the memory device comprises a semiconductor main body which extends along a first direction; the semiconductor main body comprises a first end and a second end which are oppositely arranged along a first direction; a bit line extending in a second direction; the bit line is positioned on one side, close to the first end, of the semiconductor main body in the first direction, and the bit line is coupled with the first end of the semiconductor main body; the first dielectric layer is located between at least two adjacent semiconductor main bodies, and the first dielectric layer at least partially covers the side wall, extending in the first direction, of the first end of each semiconductor main body; the second direction is intersected with the first direction; the second dielectric layer is positioned between at least two adjacent semiconductor main bodies; wherein the first dielectric layer is located between the second dielectric layer and the semiconductor main body.

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure relate to the technical field of semiconductor technology, and in particular, to a memory device, a manufacturing method thereof, and a memory system. BACKGROUND

[0002] Memory devices are storage devices used to save information in modern information technology. Some semiconductor memories, including some non-volatile memories and volatile memories, have gradually become mainstream products in the storage market due to their high storage density, controllable production cost, appropriate read-write speed, and retention characteristics. However, as people's requirements for storage devices continue to increase, there is much room for improvement in memory devices and manufacturing methods thereof. SUMMARY

[0003] According to some aspects of embodiments of the present disclosure, a memory device is provided, comprising: a semiconductor body extending along a first direction; the semiconductor body comprising a first end and a second end oppositely arranged along the first direction; a bit line extending along a second direction; the bit line being located on a side of the semiconductor body close to the first end in the first direction, and the bit line being coupled to the first end of the semiconductor body; a first dielectric layer located between at least two adjacent semiconductor bodies, the first dielectric layer at least partially covering a sidewall of the first end of the semiconductor body extending along the first direction; the second direction intersecting the first direction; a second dielectric layer located between at least two adjacent semiconductor bodies; wherein the first dielectric layer is located between the second dielectric layer and the semiconductor body.

[0004] In some embodiments, the memory device further comprises: a gate layer extending along a third direction; the gate layer being located between at least two adjacent semiconductor bodies, and the gate layer covering a sidewall between the first end and the second end of the semiconductor body extending along the first direction; the gate layer being located on a side of the first dielectric layer away from the bit line in the first direction; wherein the third direction intersects the second direction, and a plane formed by the second direction and the third direction intersects the first direction.

[0005] In some embodiments, a portion of the first dielectric layer extending along the second direction at least partially covers the gate layer.

[0006] In some embodiments, the memory device further comprises: a conductive structure extending along the third direction and located at an end of the first dielectric layer away from the bit line; wherein the gate layer is located between at least two adjacent conductive structures.

[0007] In some embodiments, the memory device further comprises: a semiconductor strip extending along the second direction; the semiconductor strip is located between the bit line and the semiconductor body, and the semiconductor strip connects the first end of the semiconductor body; the first dielectric layer comprises: a first portion at least partially covering the sidewall of the first end of the semiconductor body extending along the first direction; the first portion at least partially covers the semiconductor strip region between the adjacent two semiconductor bodies; a second portion protruding from the first portion toward the gate layer along the first direction; the part of the second portion extending along the second direction at least partially covers the gate layer.

[0008] In some embodiments, the part of the first dielectric layer extending along the second direction at least partially covers the region between the adjacent two semiconductor bodies.

[0009] In some embodiments, the first dielectric layer has a closed figure shape in a cross-section of a first plane, the first plane being a plane formed by the first direction and the second direction; the closed figure comprises: a straight line; and / or, an arc.

[0010] In some embodiments, the first dielectric layer comprises: a third portion located between at least two adjacent semiconductor bodies in a third direction; the third portion extends on a second plane; the second plane is a plane formed by the first direction and the second direction; the third portion at least partially covers the sidewall of the first end of the semiconductor body extending along the first direction; wherein the third direction intersects the second direction, and the plane formed by the second direction and the third direction intersects the first direction.

[0011] In some embodiments, the bit line is located at one end of the third portion of the first dielectric layer in the first direction, and the third portion has a spacing with the bit line in the first direction.

[0012] In some embodiments, the first dielectric layer further comprises: a fourth portion located between at least two adjacent semiconductor bodies in the second direction; the third portion of the first dielectric layer has a first distance with the bit line at one end close to the bit line in the first direction, and the fourth portion has a second distance with the bit line at one end close to the bit line in the first direction; the first distance is less than or equal to the second distance.

[0013] In some embodiments, the memory device further comprises: an isolation structure located between at least two adjacent semiconductor bodies; wherein the isolation structure comprises the first dielectric layer, a second dielectric layer, and an air gap surrounded by the first dielectric layer and the second dielectric layer, and the air gap is close to the bit line in the first direction.

[0014] In some embodiments, the first dielectric layer portion covering the sidewall extending along the first direction at the first end of the semiconductor body has a thickness ranging from 0.1 nm to 2 nm in the second direction.

[0015] In some embodiments, the first dielectric layer includes a negative charge.

[0016] In some embodiments, the dielectric constant of the first dielectric layer is greater than that of the second dielectric layer, and the constituent material of the first dielectric layer includes at least one of the following: aluminum oxide and hafnium oxide.

[0017] In some embodiments, the dielectric constant of the first dielectric layer ranges from 5 to 40.

[0018] According to some aspects of embodiments of this disclosure, a method for fabricating a memory device is provided, comprising: providing a semiconductor body extending along a first direction; the semiconductor body including a first end and a second end disposed opposite to each other along the first direction; filling at least two adjacent semiconductor bodies with a first dielectric material; a second direction intersecting the first direction, a third direction intersecting the second direction, and a plane formed by the second direction and the third direction intersecting the first direction; etching the first dielectric material between adjacent first ends in the third direction to form a first trench extending along the second direction; the sidewalls of the first trench exposing a cavity between adjacent first ends in the second direction; forming a first dielectric layer on the sidewalls of the first trench and the inner wall of the cavity, the first dielectric layer at least partially covering the sidewalls of the first ends of the semiconductor body extending along the first direction; filling the first trench with a second dielectric material, and forming a second dielectric layer in the trench and the cavity.

[0019] In some embodiments, the fabrication method further includes: a first dielectric layer penetrating the bottom of the first trench along the first direction.

[0020] In some embodiments, the cross-sectional shape of the first dielectric layer in the first plane is a closed shape, and the first plane is a plane formed by the first direction and the second direction; the closed shape includes: a straight line; and / or, an arc.

[0021] In some embodiments, the fabrication method includes: forming a first dielectric material layer on the sidewall of the first trench and the inner wall of the cavity; filling the first trench and the cavity to form a sacrificial structure; etching the first dielectric material layer in the first trench; reducing the top surface height of the first dielectric material layer in the first trench in the first direction to form the first dielectric layer; and removing the sacrificial structure to form the second dielectric layer.

[0022] In some embodiments, the fabrication method further includes: the second dielectric material filling a portion of the space in the first trench, the second dielectric material filling a portion of the space in the cavity; and the second dielectric layer forming an air gap.

[0023] In some embodiments, the fabrication method includes: etching the first dielectric material layer to form a second trench extending along the second direction, the bottom of the second trench being located above or flush with the top inner wall of the cavity.

[0024] In some embodiments, the cavity exposes a conductive material layer between adjacent semiconductor bodies, the conductive material layer at least partially covering the sidewalls of the semiconductor bodies extending along the first direction; the fabrication method further includes: etching the portion of the conductive material layer exposed from the cavity through the first trench, penetrating the portion of the conductive material layer extending along the second direction along the first direction to form a gate layer; forming a first dielectric layer on the gate layer, the portion of the first dielectric layer extending along the second direction at least partially covering the gate layer.

[0025] In some embodiments, the fabrication method further includes: etching the gate layer along the first direction to reduce the size of the gate layer in the first direction to form a third trench extending along the third direction on the gate layer, the third trench communicating with the cavity; and forming the first dielectric layer on the inner wall of the cavity and the inner wall of the third trench.

[0026] In some embodiments, the fabrication method further includes forming a bit line extending along a second direction on a side of the semiconductor body near the first end, the bit line being coupled to the first end of the semiconductor body.

[0027] In some embodiments, a first end of the semiconductor body is connected by a semiconductor strip, and the first trench is located between adjacent semiconductor strips; the method of forming the bit line includes: forming the bit line based on the semiconductor strip, at least a portion of the bit line being located in the semiconductor strip, and the bit line being located above the first dielectric layer.

[0028] According to some aspects of embodiments of the present disclosure, a memory system is provided, including the aforementioned memory device; and a memory controller coupled to and controlling the memory device.

[0029] This disclosure provides a memory device including a semiconductor body extending along a first direction, the semiconductor body having a first end and a second end disposed opposite to each other along the first direction, the first end of the semiconductor body being coupled to a bit line; a first dielectric layer located between two adjacent semiconductor bodies, at least partially covering the sidewall of the first end of the semiconductor body extending along the first direction, the first dielectric layer providing electrical isolation for the first end of the semiconductor body, repelling charge on the sidewall of the first end, and reducing leakage current at the first end; a second dielectric layer located between two adjacent semiconductor bodies and covering the first dielectric layer, used to enhance electrical isolation between adjacent semiconductor bodies to reduce leakage current; the second dielectric layer can provide a smaller dielectric constant, reducing parasitic capacitance between adjacent semiconductor bodies. Attached Figure Description

[0030] Figure 1 This is a schematic diagram illustrating a storage array according to an exemplary embodiment;

[0031] Figures 2 to 9 This is a schematic diagram of an exemplary storage device according to embodiments of the present disclosure;

[0032] Figure 10 This is a flowchart illustrating an exemplary method for manufacturing a storage device according to embodiments of the present disclosure;

[0033] Figures 11 to 20 This is a schematic diagram illustrating the fabrication of an exemplary storage device according to embodiments of the present disclosure;

[0034] Figure 21 and Figure 22 This is a schematic diagram of an exemplary system shown according to embodiments of the present disclosure. Detailed Implementation

[0035] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0036] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0037] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this disclosure.

[0038] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below,” “under,” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0039] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0040] It should be understood that the phrases "some embodiments" or "an embodiment" throughout the specification mean that a specific feature, structure, or characteristic related to an embodiment is included in at least one embodiment of this disclosure. Therefore, "some embodiments" or "an embodiment" appearing throughout the specification do not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this disclosure, the sequence numbers of the above processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this disclosure.

[0041] Some storage devices, such as Dynamic Random Access Memory (DRAM), may include a storage array and peripheral circuitry. The peripheral circuitry can control the storage array and operate it to perform read, write, or refresh operations. The storage devices provided in the embodiments of this disclosure may be storage devices or part of a storage device. The storage device may be DRAM, or at least a portion of a DRAM storage device, or the storage device may include DRAM. The DRAM includes the storage devices of this disclosure and is applicable to DDR4 memory specifications, DDR5 memory specifications, double data rate synchronous dynamic random access memory, and LPDDR5 memory specifications, low power double data rate synchronous dynamic random access memory.

[0042] In DRAM, memory arrays can be arranged in rows and columns, allowing memory cells to be addressed by specifying their rows and columns. A memory array includes multiple word lines corresponding to rows and multiple bit lines corresponding to columns. The word lines and bit lines intersect; selecting the memory cell at the intersection of the selected word line and bit line selects the cell for read, write, or refresh operations. For example... Figure 1 As exemplified, the memory array may include multiple word lines WLn, WLn+1, WLn-1, and WLn-2, ​​and multiple bit lines BLn, BLn+1, BLn-1, and BLn-2, ​​with the word lines and bit lines intersecting. Memory cells within the memory array may include capacitors and transistors; a memory cell may include one transistor and one capacitor. The word lines may also be conductive structures such as gate layers, serving as the gates of transistors. One controlled terminal (source) of the transistor is coupled to one electrode of the capacitor, and the other controlled terminal (drain) of the transistor is coupled to the bit line. The other electrode of the capacitor may be grounded or have an additional voltage (such as Vcc / 2) applied to it. Figure 1As shown, the memory cell array is arranged in an x-column, y-row configuration. The rows and columns can be perpendicular or not. The z-direction is either vertical or the thickness direction of the device, and can be the first direction in this embodiment. The xoy plane intersects with or is perpendicular to the z-direction, and the x-direction can be the second direction in this embodiment. The y-direction can be a third direction in this embodiment. The extension direction of word lines or rows can be parallel to the y-direction or at an angle to it. The extension direction of bit lines or columns can be parallel to the x-direction or at an angle to it. The orthographic projection of the word line onto the xoy plane is perpendicular to the orthographic projection of the bit line onto the xoy plane, or they may not be perpendicular but have an angle between them.

[0043] In some embodiments, during read or write operations, a word line selection signal can be used to select the corresponding word line, and a column selection signal can be used to select the corresponding bit line. Simultaneous selection of the word line and bit line allows location of the selected memory cell. At this time, the transistor of the selected memory cell is turned on due to the operating voltage applied to the word line, thereby enabling read, write, or refresh operations on the selected memory cell. In some embodiments, the capacitor can be replaced with other memory structures, including but not limited to: phase-change memory structures, resistive switching memory structures, or magnetic switching memory structures.

[0044] In some embodiments, a capacitor represents a logical 1 or 0 by the amount of charge stored within it, or by the voltage difference across its terminals. A voltage signal on the word line is applied to the gate to control the transistor's on or off state, thus selecting or deselecting the capacitor. This allows data stored in the capacitor to be read via the bit line, or data to be written to the capacitor for storage via the bit line.

[0045] In some embodiments, the DRAM memory device or DRAM memory apparatus further includes... Figure 1 Peripheral circuitry coupled to the memory array. Exemplary examples of peripheral circuitry may include, but are not limited to: a sensing amplifier circuit, a row decoding circuit, a column decoding circuit, and a voltage generation circuit. The sensing amplifier circuit is coupled to bit lines and can be configured to capture weak voltage fluctuations on the bit lines and locally reconstruct the capacitor voltage of the memory cell based on the voltage fluctuations. The sensing amplifier circuit may include a latch to latch the reconstructed capacitor voltage value, thereby transferring the information stored in the memory cell from the capacitor to the amplifier circuit. The sensing amplifier circuit may include a differential sensing amplifier circuit coupled to two bit lines, operating using a selected bit line and a complementary bit line used as a reference line to detect and amplify the voltage difference between a pair of bit lines. The row decoding circuit is configured to address the memory array and apply an operating voltage to the word lines. The column decoding circuit is configured to column address the memory array, apply a bit line voltage, or receive a bit line voltage. The voltage generation circuit generates the required high and low voltages for each device.

[0046] In some embodiments, the peripheral circuit may include a CMOS structure or CMOS circuit, including digital or analog circuits composed of transistors, for controlling the memory array or powering the memory array. Increasing the device integration of the peripheral circuit is beneficial to increasing the overall integration of the memory device, and improving the stability of the peripheral circuit devices is beneficial to improving the operational stability of the memory device.

[0047] According to some aspects of embodiments of this disclosure, Figure 2 A storage device 10 is provided, including a first semiconductor structure 11 and a second semiconductor structure 12 disposed in the z-direction. The first semiconductor structure 11 is interconnected by a hybrid bonding connection. The first semiconductor structure 11 and the second semiconductor structure 12 are coupled through a bonding contact 133 penetrating a bonding interface, which may include a dielectric layer; alternatively, the first semiconductor structure 11 is formed on the second semiconductor structure 12 without the bonding contact 133. The first semiconductor structure 11 may include a memory array, which may include DRAM, phase-change memory, resistive switching memory, or magnetic switching memory, such as... Figure 2 The memory device 10 can be used as or part of a DRAM memory device, and the first semiconductor structure 11 can include a DRAM memory array, including transistors 110 and capacitor structures 120 coupled to transistors 110. In some other embodiments, Figure 2 The capacitor structure 120 can be replaced with a phase-change memory structure, a resistive switching memory structure, or a magnetic switching memory structure to form other memory devices 10. The second semiconductor structure 12 may include peripheral circuitry 210, which is coupled to the memory array for controlling read, write, and other operations of the memory array.

[0048] Reference Figure 2 As shown, the first semiconductor structure 11 may include: a semiconductor body 111, which may include semiconductor pillars extending along the z-direction, and the semiconductor body 111 having a first end and a second end disposed opposite each other in the z-direction; a gate layer 113 extending along the y-direction, which covers the sidewalls of the semiconductor body 111 extending along the z-direction, such as covering the sidewalls between the first end and the second end of the semiconductor body 111, and serving as a control gate for the transistor 110 to control the conduction and cutoff of the transistor 110; and a gate dielectric layer 112 located between the semiconductor body 111 and the gate layer 113. The cross-sectional shape of the semiconductor body 111 in the xoy plane may include, but is not limited to: rectangle, quadrilateral, other polygons; circle, ellipse, or other irregular shapes, etc., and this disclosure does not impose any limitations on this.

[0049] A semiconductor substrate 111, a gate layer 113, and a gate dielectric layer 112 can constitute a transistor 110. A dielectric material 142 can be filled between adjacent transistors 110. The dielectric material 142 may include or form an air gap 141 to reduce inductive capacitance. A conductive structure 132 can be disposed between adjacent semiconductor substrates 111 to reduce crosstalk between adjacent gate layers 113. The conductive structure 132 and the gate layer 113 can be disposed on opposite sides of a semiconductor substrate 111 in the x-direction. When the gate layer 113 is subjected to the turn-on voltage of the transistor 110, the conductive structure 132 can be grounded or connected to a fixed voltage (e.g., a negative voltage) to reduce crosstalk between transistors 110. The fixed voltage may be a fixed voltage value calibrated during the factory testing phase of the memory device, or a calibrated voltage range. For example, taking two adjacent conductive structures 132 as an example, two semiconductor bodies 111 may be disposed between the two adjacent conductive structures 132, two gate layers 113 disposed face-to-face are disposed between the two semiconductor bodies 111, and an air gap 141 is disposed between the two gate layers 113 disposed face-to-face. Figure 2 One semiconductor body 111 may correspond to one gate layer 113, and two semiconductor bodies 111 may share one conductive structure 132. In other embodiments, to increase the gate control performance of the semiconductor body 111, one semiconductor body 111 may be provided with two gate layers 113, or a fully surrounding gate layer 113 may be provided around the sidewall of the semiconductor body 111. To adapt to the increased integration of the memory device 10 and the reduction of parasitic capacitance and parasitic resistance, the conductive structure 132 may also have other arrangements, such as one semiconductor body 111 corresponding to one conductive structure 132.

[0050] The semiconductor body 111 may have the same type of doping at its first and second ends in the z-direction to serve as the first and second active regions, respectively, and as the drain and source of the transistor 110. The drain and source can be interchanged. The intermediate region between the first and second ends may have doping of the opposite type to that at the first end to serve as the channel of the transistor 110. The first end of the semiconductor body 111 is... Figure 2 At the bottom in the negative z-direction, it is coupled to the bit line 131 extending along the x-direction, and the second end of the semiconductor body 111 is... Figure 2The top of the positive z-axis is coupled to the capacitor structure 120. The first end of the semiconductor body 111 near the bit line 131 can be heavily doped or a metal silicide can be formed to reduce the contact resistance between the semiconductor body 111 and the bit line 131. The bit line 131 can include a metallic conductive material or a metal-semiconductor compound. For example, the semiconductor body 111 can include silicon, and the bit line 131 can include a metal silicide, such as tungsten silicide or titanium silicide; or it can include a metal silicide layer and a metal layer deposited on the side of the metal silicide layer away from the semiconductor body 111 to form the bit line. The metal layer can include, but is not limited to, tungsten, copper, aluminum, etc.

[0051] Gate layer 113 can serve as a word line, and one gate layer 113 can correspond to multiple semiconductor bodies 111 arranged in the y-direction; bit line 131 extends along the x-direction, and one bit line 131 can correspond to multiple semiconductor bodies 111 arranged in the x-direction. Selecting gate layer 113 and bit line 131 allows selection of the semiconductor bodies 111 corresponding to both, enabling the semiconductor bodies 111 to conduct and select capacitor structure 120. Charging and discharging capacitor structure 120 or sensing the charge level allows for write, refresh, or read operations. The specific structure of capacitor structure 120 is not limited in this embodiment. Capacitor structure 120 may include a first electrode, a dielectric layer, and a second electrode. The dielectric layer electrically isolates the first and second electrodes. One electrode in capacitor structure 120 may extend along the z-direction and may be columnar in shape.

[0052] Reference Figure 3 The illustrated transistor 110 and capacitor structure 120 are partially enlarged schematic diagrams. The capacitor structure 120 may include a first electrode 121 extending in the z-direction, a dielectric layer 123 surrounding the first electrode 121, and a second electrode 122 surrounding the dielectric layer 123. The dielectric layer 123 is located between the first electrode 121 and the second electrode 122. The second electrode 122 is coupled to a second end of the semiconductor body 111 away from the bit line 131. The dimension in the x-direction of the end of the capacitor structure 120 away from the semiconductor body 111 in the z-direction may be greater than or equal to the dimension of the end of the capacitor structure 120 close to the semiconductor body 111 in the z-direction. The first electrodes 121 of multiple capacitor structures 120 may be coupled to an interconnect layer (e.g., Figure 2 The first interconnect layer 134) is used to ground or connect to other operating voltages; or, multiple capacitor structures 120 share a first electrode 121, the first electrode 121 having a film structure extending along the x and / or y directions at the end away from the semiconductor body 111, the first electrode 121 being grounded or connected to other operating voltages, and multiple capacitor structures 120 sharing the first electrode 121 and connected to a common voltage.

[0053] In some embodiments, a contact portion may be provided between the capacitor structure 120 and the semiconductor body 111, and the semiconductor body 111 is coupled to the capacitor structure 120 through the contact portion. The contact portion may include a metal silicide to reduce the contact resistance between the semiconductor body 111 and the capacitor structure 120 and improve the adhesion, such as titanium silicide. The contact portion may include a multilayer structure, and the portion near the semiconductor body 111 and the portion in contact with the semiconductor body 111 may include a metal silicide to reduce contact resistance and improve adhesion; the portion in contact with the capacitor structure 120 may include a metal to improve electrical connection performance.

[0054] For example, the semiconductor body 111 may include, but is not limited to: elemental semiconductor materials (e.g., silicon, germanium), III-V compound semiconductor materials, II-VI compound semiconductor materials, organic semiconductor materials, or other semiconductor materials known in the art. For example, silicon, germanium, or silicon carbide. It may also include materials such as indium gallium zinc oxide (IGZO), which may be composed of oxides of elements such as indium, gallium, and zinc, exhibiting superior semiconductor properties. The addition of indium and gallium can improve the electron mobility of the semiconductor material, achieving lower operating voltage and lower power consumption compared to traditional semiconductor materials such as silicon; the introduction of zinc helps improve the stability of the semiconductor material. The IGZO material allows the semiconductor body 111 to directly contact and couple with the metal material of bit line 131, capacitor structure 120, or other contact structures, reducing contact resistance.

[0055] The gate layer 113 and the first electrode 121 may include, but are not limited to, conductive materials such as tungsten, gold, silver, platinum, copper, aluminum, titanium, or nickel. In addition to the above-mentioned conductive materials, the bit line 131 may also include doped semiconductor materials, such as doped silicon, or may also include metal silicides.

[0056] The gate dielectric layer 112 may include, but is not limited to, insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, or aluminum oxide. The gate dielectric layer 112 may be the same as or similar to the dielectric material 142 filling the space between adjacent semiconductor bodies 111, and may not have a clear physical boundary.

[0057] In some embodiments, refer to Figure 2 The storage device 10 shown also includes a second semiconductor structure 12, which includes peripheral circuitry 210. The second semiconductor structure 12 is interconnected with the first semiconductor structure 11 via hybrid bonding electrical signals.

[0058] Before bonding, the bonding surfaces of the first semiconductor structure 11 and the second semiconductor structure 12 respectively have a first bonding contact and a second bonding contact, which respectively lead the electrical signals of the semiconductor structure to the bonding surface. The bonding surface of the first semiconductor structure 11 is the side of the bit line 131 away from the capacitor structure 120 and has a certain distance from the bit line 131. The bonding contact may include structures such as pads and conductive plugs. The bonding surfaces of the first semiconductor structure 11 and the second semiconductor structure 12 are bonded together, and the interface where the two bonding surfaces contact is the bonding interface. The first bonding contact and the second bonding contact contact and bond at the bonding interface to realize the electrical signal interconnection between the first semiconductor structure 11 and the second semiconductor structure 12. After bonding, the first bonding contact and the second bonding contact may not have a physical boundary and can be regarded as bonding contact 133. The bonding contact 133 penetrates the bonding interface, which is a dielectric layer. The portion of bonding contact 133 located in the first semiconductor is the first bonding contact before bonding, and the portion of bonding contact 133 located in the second semiconductor is the second bonding contact before bonding. Bonding contact 133 leads the electrical signals of the first semiconductor structure 11 to the bonding interface for electrical signal interconnection with the second semiconductor structure 12. The memory array in the first semiconductor structure 11 can be coupled to bonding contact 133 via wiring layers or connection structures, and is electrically interconnected with the second semiconductor structure 12.

[0059] In some embodiments, refer to Figure 2 As shown, the memory device 10 also includes a pad 135, which is located on the side of the first semiconductor structure 11 away from the second semiconductor structure 12. The pad 135 serves as an I / O interface for power supply and communication interaction with the memory device 10. The bit line 131, gate layer 113, capacitor structure 120, and pad 135 can lead electrical signals to the bonding interface through interconnect layers and connection structures, and are coupled to bonding contacts 133, which are then coupled to the peripheral circuit 210 in the second semiconductor structure 12. The interconnect layer may include a wiring layer, a line layer, or a wiring layer that is multi-layered and coupled through conductive vias or conductive plugs; the connection structure may include conductive plugs, conductive vias, or multiple stacked and coupled conductive plugs.

[0060] For example, bit line 131 can be coupled to bonding contact 133 via first connection structure 136; multiple capacitor structures 120 can be coupled via first interconnect layer 134, and first interconnect layer 134 is coupled to bonding contact 133 via second connection structure 137, as shown. Figure 3The first electrode 121 of the capacitor structure 120 is coupled to the first interconnect layer 134; the pad 135 can be coupled to the bonding contact 133 through the third connection structure 138; the gate layer 113 can be coupled to the bonding contact 133 through other connection structures, such as providing a fourth connection structure on at least one end of the gate layer 113 in the y direction to lead out the electrical signal of the gate layer 113 to the bonding contact 133 for coupling. The fourth connection structure is not shown because the cross-sectional direction is obscured.

[0061] In some other implementations, the second semiconductor structure 12 and the first semiconductor structure 11 may not be connected by bonding. The second semiconductor structure 12 is formed on the side of the bit line 131 of the first semiconductor structure 11 away from the semiconductor body 111. The bonding contact 133 serves as a conductive contact or connection structure, or the bonding contact 133 may not be provided.

[0062] In some embodiments, Figure 4 It shows Figure 2 A schematic diagram of the middle section structure. Figure 2 and Figure 4 As shown, the sidewalls extending along the z-direction from the first end of the semiconductor body 111 are covered or surrounded by a dielectric material 142 to reduce leakage current. The dielectric material 142 has an air gap 141 on the side near the first end in the z-direction. During the fabrication of the memory device 10, the semiconductor body 111 may be exposed, introducing impurity ions or interface trap states, leading to leakage current. For example, during the formation of the gate layer 113, a continuous U-shaped conductive material may be formed first. The conductive material may include, but is not limited to, metals such as tungsten. Etching breaks the conductive material to form mutually isolated gate layers 113. Etching breaks the conductive material, causing the semiconductor body 111 to introduce metal ions or interface trap states, resulting in leakage current in the semiconductor body 111. According to some aspects of embodiments of this disclosure, a memory device 10 is provided, in... Figure 2 and Figure 3 Multiple dielectric layers are disposed at the first end of the semiconductor body 111 shown to increase electrical isolation to the first end of the semiconductor body 111. Figure 2 and Figure 3 Another dielectric layer, such as a first dielectric layer 151, is disposed between the dielectric material 142 surrounding the first end of the semiconductor body 111 and the first end. The first dielectric layer 151 may include a high dielectric material to improve insulation. In other embodiments, the first dielectric layer 151 may also include a negatively charged layer and / or form a fixed negative charge layer to repel interface charges at the first end of the semiconductor body 111 and reduce leakage current in the semiconductor body 111.

[0063] In some embodiments, refer to Figure 5As shown, a memory device 10 is provided, comprising: a semiconductor body 111 extending along a first direction (z direction); the semiconductor body 111 includes a first end and a second end disposed opposite to each other along the z direction; a bit line 131 extending along a second direction (x direction); the bit line 131 is located on the side of the semiconductor body 111 near the first end in the z direction, and the bit line 131 is coupled to the first end of the semiconductor body 111; a first dielectric layer 151 located between at least two adjacent semiconductor bodies 111, the first dielectric layer 151 at least partially covering the sidewall of the first end of the semiconductor body 111 extending along the z direction; the x direction intersects the z direction; and a second dielectric layer 152 located between at least two adjacent semiconductor bodies; wherein the first dielectric layer 151 is located between the second dielectric layer 152 and the semiconductor body 111.

[0064] Figure 6 It can be Figure 5 A partial structural diagram of the first semiconductor structure 11 in the intermediate storage device 10. Figure 6 The first ends of multiple semiconductor bodies 111 are connected by semiconductor material or semiconductor strips 130. The semiconductor strips 130 are residual, unbroken portions formed during the etching of the semiconductor layer to create the multiple semiconductor bodies 111. The semiconductor strips 130 extend along the x-direction and may not have a clear physical boundary with the semiconductor bodies 111. The side of the semiconductor strip 130 away from the semiconductor bodies 111 in the z-direction is used to form bit lines 131 or to carry bit lines 131. For example... Figure 6 The position of the midpoint line 131 is defined by a dashed line. The portion of the semiconductor strip 130 above the dashed line serves as the midpoint line 131. The midpoint line 131 can be formed by heavy doping of this portion of the semiconductor strip 130 region, or by metallization of this portion of the semiconductor region to form a metal silicide, such as titanium silicide or tungsten silicide, to form the midpoint line 131. The midpoint line 131 may not have a clear physical boundary with the first end of the semiconductor body 111. In some other embodiments, the midpoint line 131 can be formed by depositing a conductive material, such as tungsten, on the side of the semiconductor strip 130 away from the semiconductor pillar.

[0065] Reference Figure 6The semiconductor body 111 shown may include semiconductor pillars extending along the z-direction. A portion of the first dielectric layer 151 may be located between any two adjacent semiconductor bodies 111 in the x-direction. The first dielectric layer 151 at least covers the sidewalls of the semiconductor body 111 extending along the z-direction, and may also cover the region between adjacent semiconductor bodies 111; alternatively, some adjacent semiconductor bodies 111 may not have the first dielectric layer 151 between them. The number of semiconductor bodies 111 is not limited in this embodiment. Some portions of the first dielectric layer 151 may be located between at least two adjacent semiconductor pillars in the y-direction. For example, a portion of the first dielectric layer 151 extending along the xoz plane may cover the sidewalls of the semiconductor body 111 extending along the z-direction. The first dielectric layer 151 may serve as a continuous three-dimensional film layer surrounding the sidewalls extending along the z-direction at the first end of the semiconductor body 111. For example, the cross-sectional shape of the semiconductor body 111 in the xoy plane is a rectangle or a quadrilateral, or a regular or irregular polygon; taking a rectangle as an example, the first dielectric layer 151 can surround the four sidewalls of the first end of the semiconductor body 111 in the transverse direction perpendicular to the z direction.

[0066] A portion of the second dielectric layer 152 is located between adjacent semiconductor bodies 111 in the x-direction, and another portion is located between adjacent semiconductor bodies 111 in the y-direction. It is permissible for some adjacent semiconductor bodies 111 to be without the second dielectric layer 152. The second dielectric layer 152 can fill the space after the first dielectric layer 151 is disposed on the first end sidewall of adjacent semiconductor bodies 111 in the x and y directions. The first dielectric layer 151 is located between the first end of the semiconductor body 111 and the second dielectric layer 152. The second dielectric layer 152 may have an air gap 141 to reduce parasitic capacitance. The first dielectric layer 151 can be composed of a high-dielectric material, and its dielectric constant k can be greater than that of silicon oxide.

[0067] Figure 7 It can be Figure 5 A partial structural diagram of the first semiconductor structure 11 in the intermediate storage device 10. Figure 7 The portion of the first dielectric layer 151 shown, located between adjacent semiconductor bodies 111 in the x-direction, can be coupled with... Figure 6 same, Figure 7 The film height of the first dielectric layer 151 portion located between adjacent semiconductor bodies 111 in the y-direction shown can be less than Figure 6 The second dielectric layer 152 is used to fill the gaps between adjacent semiconductor bodies 111 in the x / y direction to reduce leakage current and provide support. The portion of the second dielectric layer 152 located between adjacent semiconductor bodies 111 in the x / y direction may have an air gap 141 to reduce parasitic capacitance; the morphology of the air gap 141 is not limited. For example, Figure 7The portion of the first dielectric layer 151 shown between adjacent semiconductor bodies 111 in the y-direction can extend along the xoz plane. This portion can be spaced from the bit line 131, i.e., not in contact with the bit line 131, which can reduce the dielectric constant between adjacent bit lines 131 in the y-direction and thus reduce the parasitic capacitance between the bit lines 131. The dielectric material between the first dielectric layer 151, the second dielectric layer 152, the air gap 141, and the gate layer 113 can form an isolation structure 150, which can have a portion extending in the x-direction and a portion extending in the y-direction.

[0068] In some embodiments, the first dielectric layer 151 covering the sidewall extending along the z-direction at the first end of the semiconductor body 111 has a thickness ranging from 0.1 nm to 2 nm in the x-direction. In some embodiments, the first dielectric layer 151 includes a negative charge. In some embodiments, the dielectric constant k of the first dielectric layer 151 is greater than the dielectric constant of the second dielectric layer 152, and the constituent material of the first dielectric layer 151 includes at least one of the following: aluminum oxide, hafnium oxide. In some embodiments, the dielectric constant of the first dielectric layer 151 ranges from 5 to 40. The dielectric constant of the first dielectric layer 151 is greater than that of the second dielectric constant to maintain a small film thickness while maintaining good electrical insulation performance. The first dielectric layer 151 may also include a negative charge and / or form a fixed negative charge layer to repel interface charges at the first end of the semiconductor body 111 and reduce leakage current at the first end of the semiconductor body 111. The second dielectric layer 152 may include an air gap 141 to increase insulation performance while reducing parasitic capacitance.

[0069] In some embodiments, refer to Figures 5 to 7 As shown, the memory device 10 further includes: a gate layer 113 extending along a third direction (y direction); the gate layer 113 is located between at least two adjacent semiconductor bodies 111, and the gate layer 113 covers a sidewall extending along the z direction between a first end and a second end of the semiconductor body 111; the gate layer 113 is located on the side of the first dielectric layer 151 away from the bit line 131 in a first direction; wherein the y direction intersects the x direction, and the plane formed by the x and y directions intersects the z direction. The memory device 10 also includes a gate dielectric layer 112 located between the gate layer 113 and the semiconductor body 111, and an interconnect layer, such as titanium nitride, may be included between the gate dielectric layer 112 and the gate layer 113 to increase adhesion and increase the insulating properties of the gate dielectric layer 112. A transistor 110 may include a semiconductor body 111, a gate dielectric layer 112 located on a sidewall of the semiconductor body 111 in the x-direction, and a gate layer 113. The first and second ends of the semiconductor body 111 in the z-direction are the source and drain of the transistor 110, respectively, and the area covered by the gate layer 113 serves as a channel. The composition material of the gate dielectric layer 112 may be the same as that of the second dielectric layer 152, and the film layers of the same material may not have physical boundaries when in contact.

[0070] In some embodiments, a portion of the first dielectric layer 151 extending in the x-direction at least partially covers the gate layer 113.

[0071] In some embodiments, the memory device 10 further includes: a conductive structure 132 extending in the y direction and located at one end of the first dielectric layer 151 away from the bit line 131; wherein the gate layer 113 is located between at least two adjacent conductive structures 132.

[0072] Gate layer 113 covers the intermediate region between the first and second ends of semiconductor body 111, serving as the control gate of transistor 110 to control the conduction and cutoff of semiconductor body 111. First dielectric layer 151 is located on the side of gate layer 113 near bit line 131. Besides covering a portion of the sidewall extending along the z-direction of semiconductor body 111, first dielectric layer 151 also has a portion extending in the xoy plane to cover the portion between gate layer 113 and semiconductor body 111. First dielectric layer 151 is also located at one end of conductive structure 132 near bit line 131, and the portion of first dielectric layer 151 extending in the xoy plane can cover conductive structure 132. When a conduction voltage is applied to gate layer 113, conductive structure 132 can be grounded or connected to the turn-off voltage (e.g., negative voltage) of transistor 110 to reduce crosstalk between transistors 110. The conductive structure 132 may include a multilayer structure, such as a multilayer structure of titanium nitride, tungsten, or polycrystalline silicon, to increase conductivity, reduce leakage current, increase adhesion, and reduce stress concentration. This disclosure does not limit this aspect.

[0073] In some embodiments, a portion of the first dielectric layer 151 extending along the x-direction at least partially covers the region between two adjacent semiconductor bodies 111.

[0074] In some embodiments, refer to Figure 6 and Figure 7 As shown, the memory device 10 further includes: a semiconductor strip 130 extending along the x-direction; the semiconductor strip 130 is located between the bit line 131 and the semiconductor body 111, and the semiconductor strip 130 is connected to a first end of the semiconductor body 111; Refer to Figure 8 and Figure 9 As shown, the first dielectric layer 151 includes: a first portion 1511 that at least partially covers a sidewall extending in the z-direction at a first end of a semiconductor body 111; the first portion 1511 at least partially covers a semiconductor strip 130 region between two adjacent semiconductor bodies 111; a second portion 1512 that protrudes in the z-direction from the first portion 1511 toward the gate layer 113; and a portion of the second portion 1512 extending in the x-direction that at least partially covers the gate layer 113.

[0075] In some embodiments, the cross-sectional shape of the first dielectric layer 151 in the first plane is a closed shape, and the first plane is a plane formed by the z-direction and the y-direction, such as the xoz plane; the closed shape includes: a straight line; and / or, an arc.

[0076] Reference Figure 6 The semiconductor strip 130 shown is a residual, unbroken portion formed during the etching of the semiconductor layer to create multiple semiconductor bodies 111. The semiconductor strip 130 extends along the x-direction and may not have a clear physical boundary with the semiconductor bodies 111. The side of the semiconductor strip 130 away from the semiconductor bodies 111 in the z-direction is used to form bit lines 131 or to carry bit lines 131. The bit lines 131 can be formed based on the semiconductor strip 130 using metal silicide, or a metal layer can be deposited on the semiconductor layer to form the bit lines 131. The first dielectric layer 151 may have a portion extending along the xoy plane, covering the semiconductor strip 130 region between the semiconductor bodies 111 to reduce leakage current of the semiconductor strip 130. It may completely cover the semiconductor strip 130 region between the semiconductor bodies 111 or only partially cover it.

[0077] In other embodiments, when etching the semiconductor layer to form the semiconductor body 111, the semiconductor layer may be interrupted or penetrated. There is no semiconductor material between adjacent semiconductor bodies 111 in the x-direction, and a dielectric material spacer is provided between adjacent semiconductor bodies 111 in the x-direction. The dielectric material can be the same as the material of the second dielectric layer 152, and can be silicon oxide or a spin-coated insulating dielectric. In this embodiment, the portion of the first dielectric layer 151 extending along the plane xoy covers the dielectric material between the semiconductor bodies 111 in the z-direction. A conductive material is deposited on the side of the semiconductor body 111 near the first end to form a bit line 131.

[0078] In some embodiments, Figure 6 and Figure 7 Enlarged cross-sectional views of the first dielectric layer 151 and the second dielectric layer 152 in the xoz plane are shown in Figure 8 As shown in the image. Figure 8In the first dielectric layer 151, the upper portion is a first portion 1511 covering the sidewalls extending along the z-direction from the first end of the semiconductor body 111, and the lower portion is a second portion 1512 extending towards the gate layer 113 and protruding therefrom. The dimension of the second portion 1512 in the x-direction is smaller than that of the first portion 1511 in the x-direction. The two sidewalls extending along the z-direction of the first portion 1511 cover the first ends of the two semiconductor bodies 111; the upper wall extending along the x-direction of the first portion 1511 covers the area between the first ends of two adjacent semiconductor bodies 111, such as the semiconductor strip 130 area between the first ends of two adjacent semiconductor bodies 111; the lower wall extending along the x-direction of the first portion 1511, which is shorter than the upper wall, covers the gate dielectric layer 112. The sidewalls extending along the z-direction of the second portion 1512 are in contact with the gate dielectric layer 112, and the lower wall extending along the x-direction of the second portion 1512 is in contact with and covers the gate layer 113.

[0079] Figure 8 In the first embodiment, the first portion 1511 of the first dielectric layer 151 has an n-shaped or inverted U-shaped morphology. Figure 9 The first portion 1511 of the first dielectric layer 151 shown can be rectangular or other quadrilateral. Figure 8 and Figure 9 The cross-sectional shape of the first dielectric layer 151 in the xoz plane can be a closed shape. The edges of the closed shape can be straight or curved. For example, a curved shape can exist at the corner where two straight lines meet, which may be due to the material residue formed during the etching process, resulting in a curved film landing surface. The second dielectric layer 152 can be deposited on the first dielectric layer 151 based on its morphology. The shape of the second dielectric layer 152 can be the same as that of the first dielectric layer 151. The space enclosed by the second dielectric layer 152 is an air gap 141 or a cavity, and is not filled with dielectric material.

[0080] In some embodiments, Figure 8 as well as Figure 9 The first dielectric layer 151 may not have a portion extending along the x-direction covering the region between the semiconductor bodies 111, or may not have a second portion 1512 extending toward the gate layer 113, and may only have a sidewall portion extending along the z-direction covering the first end of the semiconductor body 111 to form a non-closed pattern; or any side of the closed pattern may have a gap, resulting in the morphology of the non-closed pattern.

[0081] In some embodiments, refer to Figure 7As shown, the first dielectric layer 151 includes: a third portion 1513 located between at least two adjacent semiconductor bodies 111 in the y-direction; the third portion 1513 extends on a second plane; the second plane is a plane formed by the z-direction and the x-direction, such as the xoz plane; the third portion 1513 at least partially covers the sidewall of the first end of the semiconductor body 111 extending in the z-direction; wherein the y-direction intersects the x-direction, and the plane formed by the x-direction and the y-direction intersects the z-direction. The third portion 1513 of the first dielectric layer 151 may be a non-closed pattern with an opening on the side near the bit line 131; the third portion 1513 of the first dielectric layer 151 may include a portion extending in the z-direction to cover the sidewall of the semiconductor body 111; the third portion 1513 of the first dielectric layer 151 may also include a portion extending in the y-direction, connecting the portion covering the sidewall of the semiconductor body 111; the cross-sectional shape of the third portion 1513 of the first dielectric layer 151 in the yoz plane is U-shaped.

[0082] In some embodiments, refer to Figure 7 As shown, bit line 131 is located at one end of the third portion 1513 of the first dielectric layer 151 in the first direction, and the third portion 1513 is spaced from bit line 131 in the first direction. The third portion 1513 of the first dielectric layer 151 located between adjacent semiconductor bodies 111 in the y-direction can be spaced from bit line 131 or from the pre-formed position of bit line 131, that is, it does not contact bit line 131 or overlap in the y-direction, which can reduce the dielectric constant between adjacent bit lines 131 in the y-direction and thus reduce the parasitic capacitance between bit lines 131.

[0083] In some embodiments, refer to Figure 7 As shown, the first dielectric layer 151 further includes: a fourth portion 1514 located between at least two adjacent semiconductor bodies 111 in the x-direction; the third portion 1513 of the first dielectric layer 151 has a first distance D1 between itself and the bit line 131 in the z-direction, and the fourth portion 1514 has a second distance D2 between itself and the bit line 131 in the first direction; the first distance D1 is less than or equal to the second distance D2. The cross-sectional structure of the fourth portion 1514 of the first dielectric layer 151 in the xoz plane can be as follows. Figure 8 or Figure 9 As shown, or the fourth portion 1514 of the first dielectric layer 151 may include at least Figure 8 or Figure 9The fourth portion 1514, extending along the z-direction, at least covers the sidewalls of the semiconductor body 111 extending along the z-direction. Taking the portion of the first dielectric layer 151 covering the first end sidewall of the semiconductor body 111 as an example, the fourth portion 1514 has a second distance D2 with the bit line 131 or a pre-formed position of the bit line 131. The second distance D2 is greater than the first distance D1. The third portion 1513 of the first dielectric layer 151 is closer to the bit line 131 than the fourth portion 1514. Figure 7 The film height of the third part 1513 is greater than that of the fourth part 1514, which can reduce the loss of the fourth part 1514 during the manufacturing process. This is beneficial to maintaining a large coverage area of ​​the first dielectric layer 151 over the semiconductor body 111 and reducing leakage current at the first end of the semiconductor body 111.

[0084] In some embodiments, refer to Figure 8 and Figure 9 As shown, the memory device 10 further includes an isolation structure 150 located between at least two adjacent semiconductor bodies 111; wherein the isolation structure 150 includes a first dielectric layer 151, a second dielectric layer 152, and an air gap 141 formed by the second dielectric layer 152, the air gap 141 being close to the bit line 131 in the z-direction. The first dielectric layer 151, the second dielectric layer 152, and the air gap 141 may constitute at least a portion of the isolation structure 150, and the isolation structure 150 may also include dielectric material between gate layers 113, and may also include other dielectric materials located between adjacent semiconductor bodies 111; the isolation structure 150 may have a portion extending in the x-direction and a portion extending in the y-direction.

[0085] In some embodiments, it is possible to Figure 6 and Figure 7 A capacitor structure 120 is provided on the side of the structure away from bit line 131. The capacitor structure 120 is coupled to the second end of the semiconductor body 111 away from bit line 131.

[0086] According to some aspects of embodiments of this disclosure, Figure 10A method for fabricating a memory device 10 includes: providing a semiconductor body extending along a first direction (z-direction); the semiconductor body including a first end and a second end disposed opposite to each other along the first direction; filling the space between at least two adjacent semiconductor bodies with a first dielectric material; a second direction (x-direction) intersecting the first direction, a third direction (y-direction) intersecting the second direction, and a plane formed by the second direction and the third direction intersecting the first direction; etching the first dielectric material between adjacent first ends in the third direction to form a first trench extending along the second direction; exposing a cavity between adjacent first ends in the second direction on the sidewalls of the first trench; forming a first dielectric layer on the sidewalls of the first trench and the inner wall of the cavity, the first dielectric layer at least partially covering the sidewalls of the first ends of the semiconductor bodies extending along the first direction; filling the first trench with a second dielectric material, and forming a second dielectric layer in the trench and the cavity.

[0087] Reference Figure 11 As shown, a plurality of semiconductor bodies 111 arranged along the x-direction and a plurality of semiconductor bodies 111 arranged along the y-direction are provided to form an array of semiconductor bodies 111. Each semiconductor body 111 has a first end and a second end disposed opposite to each other along the z-direction. The first end of each semiconductor body 111 is connected to a semiconductor strip 130, which is used to form or carry bit lines 131. Figure 11 The first end of the semiconductor body 111 is the top. The semiconductor strip 130 and the semiconductor body 111 may be made of the same material and may not have a physical boundary. A gate layer 113 extending in the y-direction is disposed between adjacent semiconductor bodies 111. The gate layer 113 covers the sidewall of the region between the first end and the second end of the semiconductor body 111. A gate dielectric layer 112 is disposed between the gate layer 113 and the semiconductor sidewall. A conductive structure 132 may be disposed between adjacent semiconductor bodies 111 to reduce crosstalk between adjacent gate layers 113. A first dielectric material 1521 is filled between adjacent semiconductor bodies 111. The first dielectric material 1521 has a cavity 1411 near the first end of the semiconductor body 111, or in... Figure 11 The top of the first dielectric material 1521 has a cavity 1411. The cavity 1411 is located on the side of the gate layer 113 near the first end of the semiconductor body 111, and also on the side of the conductive structure 132 near the first end of the semiconductor body 111.

[0088] Reference Figure 11 As shown, the first dielectric material 1521 between the first ends of adjacent semiconductor bodies 111 in the y direction is etched to form a first trench 1522 extending in the x direction. The sidewalls of the first trench 1522 can expose at least a portion of the cavity 1411. The first trench 1522 is connected to the cavity 1411. Figure 11A partially enlarged schematic diagram of the cavity 1411 structure is also shown.

[0089] A schematic diagram of the cross-section of the first trench 1522 in the yoz plane can be seen as follows: Figure 12 As shown. During the etching of the first trench 1522, the etchant can enter the cavity 1411 to etch the inner wall of the cavity 1411 to expand the cavity 1411, or the cavity 1411 can be expanded after etching the first trench 1522, or the cavity 1411 can be expanded without expansion. The sidewalls of the first trench 1522 can be provided by the semiconductor body 111, or the sidewalls of the first trench 1522 can be provided by the first dielectric material 1521; when forming the first trench 1522, a portion of the first dielectric material 1521 is retained to cover the sidewalls of the semiconductor body 111 to reduce oxidation and over-etching damage to the semiconductor body 111. The etching process may include, but is not limited to, dry etching, wet etching, or a combination thereof.

[0090] The formation process of the first dielectric layer 151 may include deposition processes, including but not limited to: chemical vapor deposition (CVD), physical vapor deposition (PVD), and atomic layer deposition (ALD). The process of filling the remaining space of the first trench 1522 may include deposition processes or spin-coating dielectric processes.

[0091] Reference Figure 13 As shown, a first dielectric layer 151 can be formed on the sidewalls and bottom of the first trench 1522, and on the inner wall of the cavity 1411. The first dielectric layer 151 can be formed in the same deposition process, including atomic layer deposition. It should be noted that... Figure 13 The first trench 1522 is not filled by the first dielectric layer 151. The first dielectric layer 151 on the inner wall of the first trench 1522 is shown due to the angle of the schematic diagram. A portion of the first dielectric layer 151 may be formed on the inner wall of the cavity 1411 at the top of the conductive structure 132.

[0092] Reference Figure 14 As shown, etching removes a portion of the first dielectric layer 151 on the sidewall of the second trench 1531, reducing the film height of the first dielectric layer 151. Alternatively, the first dielectric layer 151 at the bottom of the second trench 1531 may be etched away or left unremoved.

[0093] In some embodiments, refer to Figure 14 As shown, the manufacturing method further includes: a first dielectric layer 151 penetrating the bottom of the first trench 1522 along the z-direction.

[0094] In some embodiments, refer to Figure 13 As shown, the cross-sectional shape of the first dielectric layer 151 in the first plane is a closed figure, and the first plane is the xoz plane formed by the z direction and the x direction; the closed figure includes: a straight line; and / or, an arc. Figure 13 The first dielectric layer 151 covering the inner wall of the cavity 1411 shown is a closed shape on the xoz plane. This closed shape can be formed by straight lines or arcs. At some corners of the cavity 1411, some residual material may form arcs, and the dielectric material, after covering, forms the arc-shaped morphology of the first dielectric layer 151. In other embodiments, Figure 14 When etching away part of the first dielectric layer 151, some etchant will enter the cavity 1411 and etch part of the first dielectric layer 151 on the top inner wall of the cavity 1411, thereby forming a non-closed pattern of the first dielectric layer 151.

[0095] In some embodiments, the fabrication method further includes forming a bit line 131 extending in the x-direction on the side of the semiconductor body 111 near the first end, the bit line 131 being coupled to the first end of the semiconductor body 111.

[0096] In some embodiments, a first end of a semiconductor body 111 is connected to a semiconductor strip 130, and a first trench 1522 is located between adjacent semiconductor strips 130; the method of forming a bit line 131 includes: forming a bit line 131 based on a semiconductor strip 130, at least a portion of the bit line 131 being located in the semiconductor strip 130, and the bit line 131 being located above the first dielectric layer 151.

[0097] In some embodiments, Figure 11 , Figure 13 or Figure 14 A bit line 131 is formed on the side of the semiconductor strip 130 away from the gate layer 113, and the bit line 131 is coupled to the first end of the semiconductor body 111. For example, a metal material is deposited on the side of the semiconductor strip 130 away from the gate layer 113, or a gas containing a metal element is introduced, and the semiconductor strip 130 is heat-treated. A portion of the semiconductor strip 130 reacts with the metal element to form a metal-semiconductor compound as the bit line 131, such as tungsten silicide or titanium silicide. This reduces the increase in z-direction dimension caused by additional bit line 131 deposition. The position of the bit line 131 formed in the semiconductor strip 130 can be as follows: Figure 6As exemplified. In some other embodiments, conductive material may be deposited on the side of semiconductor strip 130 away from gate layer 113 to form bit line 131. The conductive material may include, but is not limited to, tungsten, gold, silver, platinum, copper, aluminum, titanium, or nickel. In some other embodiments, the semiconductor strip 130 may extend along the z-direction, with no semiconductor material connecting the semiconductor bodies 111, and conductive material may be deposited at the first end of the semiconductor body 111 to form bit line 131. This disclosure does not limit the formation order or node of bit line 131. Bit line 131 can be formed at the process nodes exposed by semiconductor strip 130 to reduce manufacturing costs.

[0098] In some embodiments, refer to Figure 6 As shown, filled with a second dielectric material Figure 14 The second dielectric material fills a portion of the space of the first trench 1522 shown in the figure, and forms a second dielectric layer 152 with an air gap 141.

[0099] In some embodiments, the manufacturing method includes: referring to Figure 15 As shown, Figure 11 The first trench 1522 sidewall and the cavity 1411 inner wall form a first dielectric material layer 1511; the first trench 1522 and the cavity 1411 are filled to form a sacrificial structure 153;

[0100] Reference Figure 16 and Figure 17 As shown, the first dielectric material layer 1511 in the first trench 1522 is etched, and the height of the top surface of the first dielectric material layer 1511 in the first trench 1522 is reduced in the z direction to form the first dielectric layer 151.

[0101] Reference Figure 18 As shown, the sacrificial structure 153 is removed to form the second dielectric layer 152.

[0102] exist Figure 15 In this process, the sacrificial structure 153 fills the remaining space of the first trench 1522 having the first dielectric material layer 1511, and the sacrificial structure 153 also fills the remaining space of the cavity 1411 having the first dielectric material layer 1511. At this time, the first trench 1522 and the cavity 1411 are not connected. Figure 16 During the etching process, when the first dielectric material layer 1511 on the sidewall of the first trench 1522 is removed, the etching is controlled to stop above the top inner wall of the cavity 1411 to prevent the etchant from etching the first dielectric layer 151 inside the cavity 1411.

[0103] In some embodiments, refer to Figure 16As shown, the fabrication method includes: etching a first dielectric material layer 1511 to form a second trench 1531 extending along the x-direction. The bottom of the second trench 1531 is located above or flush with the top inner wall of the cavity 1411. The second trench 1531 extends along the x-direction, in... Figure 17 In the example, the bottom of the second trench 1531 is above the top inner wall of the cavity 1411 and is isolated by the sacrificial structure 153, so that the second trench 1531 does not expose the first dielectric material layer 1511 inside the cavity 1411, thus preventing the first dielectric material layer 1511 inside the cavity 1411 from being etched.

[0104] In some embodiments, the manufacturing method further includes: [the method can be implemented in a specific manner]. Figure 15 or Figure 16 A bit line 131 is formed on the side of the semiconductor strip 130 away from the gate layer 113, and the bit line 131 is coupled to the first end of the semiconductor body 111; Refer to Figure 18 As shown, removing the sacrificial structure 153 within the first trench 1522 releases the space within the first trench 1522; refer to Figure 7 As shown, a second dielectric layer 152 is formed by filling a portion of the space in the first trench 1522 with a second dielectric material, and a portion of the space in the cavity 1411 with the second dielectric material; the second dielectric layer 152 surrounds the air gap 141. Figure 16 neutralization Figure 17 As shown, the fabrication order of bit line 131 and second trench 1531 is not limited. The bottom of second trench 1531 may be located between bit line 131 or the pre-formed position of bit line 131 and the first dielectric layer 151 on top of cavity 1411, so that the first dielectric layer 151 does not cover bit line 131 to reduce parasitic capacitance between bit lines 131, and also to reduce the etching agent from etching the first dielectric layer 151 in cavity 1411 through second trench 1531.

[0105] In some embodiments, refer to Figure 19 As shown, cavity 1411 exposes a conductive material layer 1131 between adjacent semiconductor bodies 111, the conductive material layer 1131 at least partially covering the sidewalls of the semiconductor bodies 111 extending along the z-direction; the fabrication method further includes: referring to Figure 20 As shown, the portion of the conductive material layer 1131 exposed from the cavity 1411 is etched through the first trench 1522, penetrating the portion of the conductive material layer 1131 extending in the x direction along the z direction to form a gate layer 113; the gate layer 113 can be further etched to reduce its size, so that the gate layer 113 is located in the middle portion of the sidewall of the semiconductor body 111 corresponding to the channel; subsequently, a first dielectric layer 151 is formed on the gate layer 113, and the portion of the first dielectric layer 151 extending in the x direction at least partially covers the gate layer 113.

[0106] In some embodiments, refer to Figure 20 As shown, the gate layer 113 is etched along the z-direction to reduce the size of the gate layer 113 in the z-direction, forming a shape as shown. Figure 11 The gate layer 113 shown has a morphology such that a third trench 1132 extending along the y-direction is formed on the gate layer 113, and the third trench 1132 communicates with the cavity 1411; subsequently, a first dielectric layer 151 is formed on the inner wall of the cavity 1411 and the inner wall of the third trench 1132. The first dielectric layer 151 can be as follows: Figure 8 As shown, it has a first portion 1511 and a second portion 1512. The first portion 1511 is formed on the inner wall of the cavity 1411, and the second portion 1512 is formed on the inner wall of the third trench 1132. The portion of the second portion 1512 extending in the x-direction covers the gate layer 113.

[0107] In some embodiments, etching the conductive material layer 1131 to form mutually isolated gate layers 113 can introduce metal ions or interface trap states into the semiconductor body 111, causing leakage current in the semiconductor body 111. A first dielectric layer 151 is formed to at least partially cover the sidewalls extending along the z-direction at the first end of the semiconductor body 111. The first dielectric layer 151 may include a high-dielectric material to improve insulation performance and reduce leakage current. The first dielectric layer 151 may also include a negatively charged layer and / or form a fixed negative charge layer to repel interface charges at the first end of the semiconductor body 111, thereby reducing leakage current in the semiconductor body 111.

[0108] In some embodiments, remove Figure 6 and Figure 7 A second dielectric layer 152, located away from the gate layer 113, exposes the bit line 131. A second semiconductor structure 12 is bonded to the side of the bit line 131 away from the gate layer 113. The peripheral circuitry 210 of the second semiconductor structure 12 is coupled to the bit line 131 via bonding contacts 133. The carrier wafer or substrate on the side of the semiconductor body 111 away from the bit line 131 is removed to expose the second end of the semiconductor body 111. A capacitor structure 120 is formed on the second end and coupled to the semiconductor body 111. A pad 135 and other structures are formed on the side of the capacitor structure 120 away from the semiconductor body 111 to form a memory device 10. Figure 5 The example provided.

[0109] According to some aspects of embodiments of the present disclosure, a memory system 202 is provided, including, as described above... Figures 2 to 7 The example storage device 10; and the memory controller 206, which is coupled to and controls the storage device 10. Figure 21 A memory system 202 is provided, comprising a memory device 204 and a memory controller 206 coupled thereto. The memory controller 206 controls the memory device 204, which includes...Figures 2 to 7 The storage device 10 described herein is a storage device 204 or at least a portion thereof.

[0110] Reference Figure 21 As shown, this disclosure provides a system 200 including a host 208. The system 200 may be a mobile phone, graphics processing device, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having memory therein. Figure 21 As shown, system 200 may include host 208 and memory system 202, the memory system 202 having one or more memory devices 204 and memory controller 206. Host 208 may be a processor (e.g., central processing unit (CPU)) or system-on-a-chip (SoC) (e.g., application processor (AP)). Host 208 may be configured to send data to or receive data from memory device 204, memory device 204 may include... Figures 2 to 7 The aforementioned storage device 10.

[0111] According to some embodiments, a memory controller 206 is coupled to the memory device 204 and the host 208, and is configured to control the memory device 204 to perform read, write, or refresh operations. The memory controller 206 can manage data stored in the memory device 204 and communicate with the host 208. The memory device 204 includes DRAM, or a package structure formed by stacking multiple DRAMs, which can be applied to HBM or HMC package structures.

[0112] In some specific examples, the HBM packaging structure may include multiple DRAM chips vertically stacked on a logic chip, with the logic chip and the multiple DRAM chips interconnected via TSVs. The multiple DRAM chips and the logic chip can form a memory system. The logic chip may include, but is not limited to, components such as control logic, interface control modules, and SRAM caches. The logic chip can be configured as a memory controller 206. Figures 2 to 7The storage device 10 shown can be configured as a memory device 204; the HBM package structure may also include processor chips such as GPUs, CPUs, or SOC chips, and the processor may integrate a memory controller to control data transfer of DRAM chips. For example, a processor such as a GPU is coupled to a logic chip, and data interaction occurs between the logic chip and the DRAM. In other specific examples, the HMC (Hybrid Memory Cube) package structure may include multiple DRAM chips vertically stacked on a logic chip, with the logic chip and the multiple DRAM chips interconnected via TSVs. The multiple DRAM chips and the logic chip can form a memory system, and the logic chip may include, but is not limited to, components such as control logic, interface control modules, and SRAM caches, and the logic chip may integrate a memory controller.

[0113] In some specific examples, the memory system 202 can be used in conjunction with a solid-state drive (SSD) to improve read and write speeds. Currently, high-end SSDs often embed DRAM to enhance performance and improve random read / write speeds. For example, during file writing, especially small file writing, small files are processed by DRAM before being stored in flash memory, resulting in higher SSD storage efficiency and faster speeds. Flash memory includes non-volatile memory, including but not limited to 2D NAND flash memory or 3D NAND flash memory. In some specific examples, the memory system 202 can be used as a cache device in a graphics processing device (GPU), which may include, but is not limited to, a graphics graphics card.

[0114] In other embodiments, reference is made to Figure 22 As shown, system 200 may consist only of host 208 and a memory device 204 coupled thereto. The controller for the memory device 204 may be located inside host 208, such as a memory controller integrated within a central processing unit (CPU), or a southbridge or northbridge chip integrated into the motherboard of system 200. Memory device 204 may include, but is not limited to: DDR4 memory, DDR5 memory (Double Data Rate Synchronous Dynamic Random Access Memory), and LPDDR5 memory (Low Power Double Data Rate Synchronous Dynamic Random Access Memory). Memory device 204 may include... Figures 2 to 7 The storage device 10 shown.

[0115] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A storage device, characterized in that, include: A semiconductor body extends along a first direction; the semiconductor body includes a first end and a second end disposed opposite to each other along the first direction; Bit lines extend along the second direction; The bit line is located on the side of the semiconductor body closer to the first end in the first direction, and the bit line is coupled to the first end of the semiconductor body; A first dielectric layer is located between at least two adjacent semiconductor bodies, the first dielectric layer at least partially covering a sidewall extending along the first direction at a first end of the semiconductor body; the second direction intersects the first direction; A second dielectric layer is located between at least two adjacent semiconductor bodies; wherein the first dielectric layer is located between the second dielectric layer and the semiconductor body.

2. The storage device according to claim 1, characterized in that, The storage device further includes: A gate layer extends along a third direction; the gate layer is located between at least two adjacent semiconductor bodies, the gate layer covers a sidewall extending along the first direction between a first end and a second end of the semiconductor body; the gate layer is located on the side of the first dielectric layer away from the bit line in the first direction; wherein the third direction intersects the second direction, and the plane formed by the second direction and the third direction intersects the first direction.

3. The storage device according to claim 2, characterized in that, The portion of the first dielectric layer extending along the second direction at least partially covers the gate layer.

4. The storage device according to claim 2, characterized in that, The storage device further includes: A conductive structure extends along the third direction and is located at the end of the first dielectric layer away from the bit line; wherein the gate layer is located between at least two adjacent conductive structures.

5. The storage device according to claim 2, characterized in that, The storage device further includes: A semiconductor strip extends along the second direction; the semiconductor strip is located between the bit line and the semiconductor body, and the semiconductor strip is connected to a first end of the semiconductor body; The first dielectric layer includes: The first portion at least partially covers the sidewall extending along the first direction at the first end of the semiconductor body; the first portion at least partially covers the semiconductor strip region between two adjacent semiconductor bodies; The second portion protrudes from the first portion toward the gate layer along the first direction; the portion of the second portion extending along the second direction at least partially covers the gate layer.

6. The storage device according to claim 1, characterized in that, The portion of the first dielectric layer extending along the second direction at least partially covers the region between two adjacent semiconductor bodies.

7. The storage device according to claim 1, characterized in that, The first dielectric layer has a closed cross-sectional shape in the first plane, which is a plane formed by the first direction and the second direction; the closed shape includes: Straight line; and / or, arc.

8. The storage device according to claim 1, characterized in that, The first dielectric layer includes: The third portion is located between at least two adjacent semiconductor bodies in a third direction; the third portion extends on a second plane; the second plane is a plane formed by the first direction and the second direction; the third portion at least partially covers the sidewall of the first end of the semiconductor body extending along the first direction; wherein the third direction intersects the second direction, and the plane formed by the second direction and the third direction intersects the first direction.

9. The storage device according to claim 8, characterized in that, The bit line is located at one end of the third portion of the first dielectric layer in the first direction, and the third portion is spaced from the bit line in the first direction.

10. The storage device according to claim 9, characterized in that, The first dielectric layer further includes: The fourth part is located between at least two adjacent semiconductor bodies in the second direction; The third portion of the first dielectric layer has a first distance from the bit line at one end near the bit line in the first direction, and the fourth portion has a second distance from the bit line at one end near the bit line in the first direction; the first distance is less than or equal to the second distance.

11. The storage device according to claim 1, characterized in that, The storage device further includes: An isolation structure is located between at least two adjacent semiconductor bodies; wherein the isolation structure includes a first dielectric layer, a second dielectric layer, and an air gap formed by the second dielectric layer, the air gap being close to the bit line in the first direction.

12. The storage device according to claim 1, characterized in that, The first dielectric layer portion covering the sidewall extending along the first direction at the first end of the semiconductor body has a thickness ranging from 0.1 nm to 2 nm in the second direction.

13. The storage device according to claim 1, characterized in that, The first dielectric layer contains negative charges.

14. The storage device according to claim 13, characterized in that, The dielectric constant of the first dielectric layer is greater than that of the second dielectric layer, and the constituent materials of the first dielectric layer include at least one of the following: Aluminum oxide, hafnium oxide.

15. The storage device according to claim 14, characterized in that, The dielectric constant of the first dielectric layer ranges from 5 to 40.

16. A method for manufacturing a storage device, characterized in that, include: A semiconductor body is provided, extending along a first direction; the semiconductor body includes a first end and a second end disposed opposite to each other along the first direction; a first dielectric material is filled between at least two adjacent semiconductor bodies; a second direction intersects the first direction, a third direction intersects the second direction, and a plane formed by the second direction and the third direction intersects the first direction; The first dielectric material between the first ends adjacent to each other in the second direction is etched to form a first trench extending in the second direction; the sidewalls of the first trench expose the cavity between the first ends adjacent to each other in the second direction. A first dielectric layer is formed on the sidewall of the first trench and the inner wall of the cavity, the first dielectric layer at least partially covering the sidewall of the first end of the semiconductor body extending along the first direction; The first trench is filled with a second dielectric material, and a second dielectric layer is formed in the trench and the cavity.

17. The manufacturing method according to claim 16, characterized in that, The manufacturing method further includes: The first dielectric layer penetrates the bottom of the first trench along the first direction.

18. The manufacturing method according to claim 16, characterized in that, The first dielectric layer has a closed cross-sectional shape in the first plane, which is a plane formed by the first direction and the second direction; the closed shape includes: Straight line; and / or, arc.

19. The manufacturing method according to claim 16, characterized in that, The manufacturing method includes: A first dielectric material layer is formed on the sidewall of the first trench and the inner wall of the cavity; The first trench and the cavity are filled to form a sacrificial structure; Etch the first dielectric material layer in the first trench and reduce the top surface height of the first dielectric material layer in the first trench in the first direction to form the first dielectric layer; The sacrificial structure is removed to form the second dielectric layer.

20. The manufacturing method according to claim 19, characterized in that, The manufacturing method further includes: The second dielectric material fills a portion of the space in the first trench, and the second dielectric material fills a portion of the space in the cavity; The second dielectric layer forms an air gap.

21. The manufacturing method according to claim 19, characterized in that, The manufacturing method includes: The first dielectric material layer is etched to form a second trench extending along the second direction, the bottom of the second trench being located above or flush with the top inner wall of the cavity.

22. The manufacturing method according to claim 16, characterized in that, The cavity exposes a conductive material layer between adjacent semiconductor bodies, the conductive material layer at least partially covering the sidewalls of the semiconductor bodies extending along the first direction; The manufacturing method further includes: The portion of the conductive material layer exposed from the cavity is etched through the first trench, and the portion extending along the second direction through the conductive material layer in the first direction is etched to form a gate layer. A first dielectric layer is formed on the gate layer, and a portion of the first dielectric layer extending along the second direction at least partially covers the gate layer.

23. The manufacturing method according to claim 22, characterized in that, The manufacturing method further includes: The gate layer is etched along the first direction to reduce the size of the gate layer in the first direction, so as to form a third trench extending along the third direction on the gate layer, the third trench communicating with the cavity; the first dielectric layer is formed on the inner wall of the cavity and the inner wall of the third trench.

24. The manufacturing method according to claim 16, characterized in that, The manufacturing method further includes: A bit line extending in the second direction is formed on the side of the semiconductor body near the first end, and the bit line is coupled to the first end of the semiconductor body.

25. The manufacturing method according to claim 24, characterized in that, The first end of the semiconductor body is connected by semiconductor strips, and the first trench is located between adjacent semiconductor strips; The method for forming the bit line includes: The bit line is formed based on the semiconductor strip, at least a portion of the bit line is located in the semiconductor strip, and the bit line is located above the first dielectric layer.

26. A memory system, characterized in that, include: The storage device as described in any one of claims 1 to 15; as well as A memory controller, which is coupled to and controls the memory device.

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