Semiconductor structure and preparation method thereof

Abstract

The invention discloses a semiconductor structure and a preparation method thereof, and the semiconductor structure comprises a storage unit which comprises a first transistor and a second transistor, the first transistor comprises a first channel layer and a charge storage structure which are arranged along a first direction, and the second transistor comprises a second channel layer which is located at one side of the charge storage structure along the first direction, the second channel layer is electrically connected with the charge storage structure; the read word line extends along the second direction and is adjacent to the side surface of the first channel layer; the writing word line extends along the second direction and is adjacent to the side surface of the second channel layer; and the bit line extends along the first direction and is electrically connected with the first channel layer and the second channel layer. According to the semiconductor structure, the integration level of the semiconductor structure can be improved.

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure relate to the technical field of semiconductor technology, and particularly relate to a semiconductor structure and a preparation method thereof. BACKGROUND

[0002] Dynamic Random Access Memory (DRAM) is a kind of semiconductor memory. Compared with static memory, DRAM memory has the advantages of simple structure, low manufacturing cost and high capacity density. With the development of technology, the application of DRAM memory is becoming more and more widespread.

[0003] Due to the large area occupied by the capacitor, the storage cell structure of one transistor and one capacitor (1T1C) faces the challenges of physical limitations and manufacturing constraints, and it is difficult to meet the increasing demand for storage density. The storage cell structure of two transistors without capacitor (2T0C) occupies a small area, which can adapt to the requirements of continuous miniaturization of semiconductor structure size and continuous increase of storage density of DRAM and other semiconductor structures, and gradually becomes the mainstream storage cell structure.

[0004] Therefore, how to improve the performance of the semiconductor structure with 2T0C structure and increase the storage density of the semiconductor structure is a technical problem to be solved at present. SUMMARY

[0005] According to a first aspect of embodiments of the present disclosure, a semiconductor structure is provided, comprising: a storage cell comprising a first transistor and a second transistor, the first transistor comprising a first channel layer and a charge storage structure arranged along a first direction, the second transistor comprising a second channel layer located on a side of the charge storage structure away from the first channel layer along the first direction, the second channel layer being electrically connected with the charge storage structure; a read word line extending along a second direction and adjacent to a side surface of the first channel layer; a write word line extending along the second direction and adjacent to a side surface of the second channel layer; and a bit line extending along the first direction and electrically connected with the first channel layer and the second channel layer.

[0006] In some embodiments, the first channel layer comprises a vertical channel portion and a bent channel portion connected with each other, the vertical channel portion extends along a vertical direction, and the read word line and the charge storage structure are respectively located on two sides of the vertical channel portion along the first direction; the first transistor further comprises a first dielectric layer sandwiched between the read word line and the vertical channel portion, and a second dielectric layer sandwiched between the charge storage structure and the vertical channel portion.

[0007] In some embodiments, the bit line is electrically connected with an end of the vertical channel portion away from the bent channel portion; and the semiconductor structure further comprises: an active line electrically connected with the bent channel portion of the first channel layer.

[0008] In some embodiments, the active line includes a horizontal active portion and a vertical active portion, the vertical active portion protruding from a bottom surface of the horizontal active portion along a vertical direction and connecting the bent channel portion.

[0009] In some embodiments, the charge storage structure includes a vertical storage portion and a horizontal storage portion connected to each other, the vertical storage portion extending along a vertical direction, the horizontal storage portion protruding from a sidewall of the vertical storage portion along a first direction and connecting the second channel layer; the memory cell further includes a spacer layer, the spacer layer being sandwiched between the vertical storage portion and the second channel layer and between the first channel layer and the second channel layer at an end portion close to the bit line.

[0010] In some embodiments, the horizontal storage portion is located at an end portion of the vertical storage portion away from the bit line, and the horizontal storage portion is electrically connected to an end portion of the second channel layer away from the bit line.

[0011] In some embodiments, a plurality of memory cells are arranged in the first direction and the second direction to form a memory array; the read word line is located at a side of a plurality of first channel layers arranged along the second direction; the write word line is located at a side of a plurality of second channel layers arranged along the second direction; and the bit line is electrically connected to a plurality of memory cells arranged along the first direction.

[0012] In some embodiments, among a plurality of memory cells arranged along the first direction, two adjacent memory cells are mirror symmetrical along a plane formed by the second direction and the vertical direction; wherein the spacing between the first channel layers is smaller than the spacing between the second channel layers, and the first channel layers of the two adjacent memory cells are interconnected to each other through a first channel connection portion; and the spacing between the second channel layers is smaller than the spacing between the first channel layers, and the second channel layers of the two adjacent memory cells are interconnected to each other through a second channel connection portion.

[0013] In some embodiments, the first channel connection portion and the second channel connection portion both extend along the first direction, the first channel connection portion connects end portions of two adjacent first channel layers close to the bit line, and the second channel connection portion connects end portions of two adjacent second channel layers close to the bit line, and the first channel connection portion and the second channel connection portion are both electrically connected to the bit line.

[0014] In some embodiments, at least two memory arrays are stacked in the vertical direction to form a three-dimensional semiconductor structure; the semiconductor structure further includes an insulating layer between two adjacent memory arrays in the vertical direction.

[0015] According to a second aspect of the embodiments of the present disclosure, a method for manufacturing a semiconductor structure is provided. The method comprises: forming a memory cell, the memory cell comprising a first transistor and a second transistor, the first transistor comprising a first channel layer and a charge storage structure arranged along a first direction, the second transistor comprising a second channel layer located at a side of the charge storage structure away from the first channel layer along the first direction, the second channel layer being electrically connected with the charge storage structure; forming a write word line, the write word line extending along a second direction and being adjacent to a side surface of the first channel layer; forming a read word line, the read word line extending along the second direction and being adjacent to a side surface of the second channel layer; and forming a bit line, the bit line extending along the first direction and being electrically connected with the first channel layer and the second channel layer.

[0016] In some embodiments, the forming of the memory cell comprises: forming a first isolation structure, the first isolation structure extending along the second direction; sequentially forming the second channel layer and a third dielectric layer on a side wall of the first isolation structure; forming the charge storage structure located at a side wall of the second channel layer; and sequentially forming a second dielectric layer, the first channel layer and a first dielectric layer on a side wall of the charge storage structure.

[0017] In some embodiments, the sequentially forming the second channel layer and the third dielectric layer on the side wall of the first isolation structure comprises: sequentially forming a second channel material layer and a third dielectric material layer on the side wall of the first isolation structure; forming a first mask pattern extending along the first direction and arranged along the second direction on the third dielectric material layer; and etching the second channel material layer and the third dielectric material layer sequentially to form the second channel layer and the third dielectric layer by taking the first mask pattern as a mask.

[0018] In some embodiments, the sequentially forming the second dielectric layer, the first channel layer and the first dielectric layer on the side wall of the charge storage structure comprises: sequentially forming a second dielectric material layer, a first channel material layer and a first dielectric material layer on a side wall of the charge storage structure; forming a second mask pattern extending along the first direction on the first channel material layer; and etching the second dielectric material layer, the first channel material layer and the first dielectric material layer to form the second dielectric layer, the first channel layer and the first dielectric layer by taking the second mask pattern as a mask, the first channel layer comprising a vertical channel portion and a bent channel portion connected with each other; and the method further comprises: forming an active line, the active line being electrically connected with the bent channel portion of the first channel layer.

[0019] In some embodiments, the forming of the charge storage structure located at the side wall of the second channel layer comprises: removing part of the first isolation structure to expose a top side wall of the second channel layer; forming a horizontal storage portion located at the top side wall of the second channel layer, the horizontal storage portion being located on the first isolation structure and extending along the second direction; etching the first isolation structure by taking the horizontal storage portion as a mask to form a spacing groove; and forming a vertical storage portion located at a side wall of the horizontal storage portion and a side wall of the spacing groove, the horizontal storage portion and the vertical storage portion constituting the charge storage structure.

[0020] In the embodiments of the present disclosure, since two transistors are used as the storage unit, the size limitation caused by the capacitor is avoided, and the size of the storage unit is greatly reduced. The read word line and the charge storage structure are respectively located on the two sides of the first channel layer along the first direction, and the first transistor is used as the read transistor and the storage element. Secondly, the structure layers of the first transistor and the second transistor are sequentially arranged along the first direction, which compresses the size of the storage unit in the vertical direction. In addition, the first transistor and the second transistor share one bit line and are respectively controlled by the read word line and the write word line, which effectively improves the utilization rate of the bit line and further improves the integration of the semiconductor structure. BRIEF DESCRIPTION OF DRAWINGS

[0021] Figure 1 is a circuit schematic diagram of a storage unit according to an exemplary embodiment;

[0022] Figure 2 is a circuit schematic diagram of a storage array according to an exemplary embodiment;

[0023] Figure 3 is a schematic diagram of a semiconductor structure according to an exemplary embodiment;

[0024] Figure 4 is a schematic diagram of a semiconductor structure according to another exemplary embodiment;

[0025] Figure 5 is a schematic diagram of a three-dimensional semiconductor structure according to an exemplary embodiment;

[0026] Figure 6 is a schematic diagram of a three-dimensional semiconductor structure according to another exemplary embodiment;

[0027] Figure 7 is a flowchart of a preparation method of a semiconductor structure according to an exemplary embodiment;

[0028] Figures 8-23 is a three-dimensional schematic diagram of a semiconductor structure at each step of a preparation method of a semiconductor structure according to an exemplary embodiment.

[0029] BRIEF DESCRIPTION OF DRAWINGS

[0030] 10 / 20 - semiconductor structure; 10S / 20S - three-dimensional semiconductor structure; MC - memory cell; MA - memory array; 100 - substrate; 101 - substrate; 102 - isolation layer; 115 - read word line; 123 - write word line; 110 - first transistor; 120 - second transistor; 111 - first channel layer; 111a - bent channel portion; 111b - vertical channel portion; 111c - first channel connection portion; 112 - charge storage structure; 112a - horizontal storage portion; 112b - vertical storage portion; 121 - second channel layer; 121c - second channel connection portion; first dielectric layer 113; second dielectric layer 114; third dielectric layer 122; 210 - bit line; bit line isolation structure 211; active line 310; 311a - horizontal active portion; 311b - vertical active portion; 401 - first isolation structure; 402 - first mask pattern; 403 - second isolation structure; 404 - third isolation structure; 405 - second mask pattern; 406 - fourth isolation structure; 407 - fifth isolation structure; 410 - spacer layer; 510 - insulating layer; X - first direction; Y - second direction; Z - vertical direction. DETAILED DESCRIPTION

[0031] The technical solutions of the present disclosure will be further described in detail below in combination with the drawings and examples. Although the exemplary implementation methods of the present disclosure are shown in the drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the implementation described herein. On the contrary, these implementations are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0032] The present disclosure will be described in more detail in the following paragraphs with reference to the drawings. The advantages and features of the present disclosure will be more apparent from the following description and claims. It should be noted that the drawings are very simplified and use non-precise proportions only for the purpose of facilitating, clarifying and assisting in the description of the embodiments of the present disclosure.

[0033] It can be understood that the meanings of "on", "over" and "above" of the present disclosure should be interpreted in the broadest way, so that "on" not only means "on" with no intervening features or layers therebetween (i.e. directly on), but also includes the meaning of "on" with intervening features or layers therebetween.

[0034] In the embodiments of the present disclosure, the terms "first", "second", "third" and the like are used to distinguish similar objects, and do not necessarily have to describe a specific order or sequence.

[0035] In embodiments of this disclosure, the term "layer" refers to a portion of material comprising a region having thickness. A layer may extend over the entirety of a lower or upper structure, or may have a range smaller than that of the lower or upper structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure with a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or a layer may be located between any horizontal faces at the top and bottom surfaces of the continuous structure. A layer may extend horizontally, vertically, and / or along an inclined surface. A layer may include multiple sublayers.

[0036] It should be noted that the technical solutions described in the embodiments of this disclosure can be combined arbitrarily without conflict.

[0037] Figure 1 This is a circuit diagram of a storage unit; Figure 2 This is a circuit diagram of a storage array; Figure 3 and Figure 4 This is a schematic diagram of a semiconductor structure; Figure 5 and Figure 6 This is a schematic diagram of a three-dimensional semiconductor structure; Figure 7 This is a flowchart of a method for fabricating a semiconductor structure; Figures 8-23 This is a three-dimensional schematic diagram of the semiconductor structure at each step of the semiconductor structure fabrication process. The following will combine... Figures 1-23 The semiconductor structure and its fabrication method are described.

[0038] Reference Figure 1 As shown, Figure 1 This is a schematic diagram of the circuit structure of a single memory cell. The memory cell MC includes a first transistor RT and a second transistor WT. The memory cell MC can be called a 2TOC memory cell. The first transistor RT can be a read transistor, and the second transistor WT can be a write transistor. One of the first transistor RT and the second transistor WT can be an N-type transistor or a P-type transistor. In one example, both the first transistor RT and the second transistor WT are N-type transistors.

[0039] In this design, the first source (or first drain) of the first transistor RT and the second source (or second drain) of the second transistor WT are both connected to the bit line BL. The first drain (or first source) of the first transistor RT is connected to the active line SL, which can be used to apply a low voltage or ground voltage. The first gate of the first transistor RT is connected to the read word line RWL. The second gate of the first transistor RT is connected to the second drain (or second source) of the second transistor WT through the memory node contact SN. The third gate of the second transistor WT is connected to the write word line WWL. The first transistor RT has two gates, allowing for flexible control of the read operation through the gates. The first transistor RT and the second transistor WT share the bit line BL, thereby improving the integration density of the memory cells in the semiconductor structure.

[0040] The storage unit MC can be configured to store information of one bit (e.g., having binary 0 ("0") or binary 1 ("1"), or more than one bit (e.g., multiple bits having a combination of at least two binary bits).

[0041] For the process of writing a "1" to the memory cell MC, a positive voltage is applied to the third gate (i.e., the write word line WWL) of the second transistor WT. The positive voltage must be greater than the threshold voltage of the second transistor WT, thereby turning on the second transistor WT. A positive voltage is applied to the first drain (i.e., the bit line BL) of the second transistor WT to inject charge into the second gate capacitor of the first transistor RT. After the charge injection, the gate voltage and drain voltage of the second transistor WT are removed, and the "1" state is retained.

[0042] For the process of reading "1" in the memory cell MC, a read voltage is applied to the first gate (i.e., read word line RWL) of the first transistor RT. Since there is a certain charge in the second gate capacitor, the first transistor RT is in a low resistance state and obtains a large current. After being amplified and identified by the peripheral circuit, the process of reading "1" is completed.

[0043] For the process of writing "0" to the memory cell MC, a positive voltage is applied to the third gate (i.e., the write word line WWL) of the second transistor WT. The positive voltage must be greater than the threshold voltage of the second transistor WT, thereby turning on the second transistor WT. A negative voltage is applied to the first drain (i.e., the bit line BL) of the second transistor WT to draw charge from the second gate capacitance of the first transistor RT. After the charge is drawn, the first gate voltage and drain voltage of the second transistor WT are removed, and the "0" state is maintained.

[0044] For the process of reading "0" in the memory cell MC, a read voltage is applied to the first gate (i.e., the read word line RWL) of the first transistor RT. Since there is no charge in the second gate capacitor, the first transistor RT is in a high resistance state and obtains a small current. The reading of "0" is then completed by the amplification and recognition by the external circuit.

[0045] Reference Figure 2 As shown, Figure 2 This is a schematic diagram of the circuit structure of a memory array consisting of multiple memory cells. The memory array MA is composed of multiple memory cells (MC1 / MC2 / MC3 / MC4 / MC5 / MC6…) arranged in an array. Each memory cell contains two transistors, and the memory cell can be referred to as a 2T0C memory cell. Specifically, memory cells MC1 / MC2 / MC3 are arranged in the same row and share bit line BL1 and active line SL1; memory cells MC4 / MC5 / MC6 are arranged in the same row and share bit line BL2 and active line SL2; memory cells MC1 / MC4 are arranged in the same column and share read word line RWL1 and write word line WWL1; memory cells MC2 / MC5 are arranged in the same column and share read word line RWL2 and write word line WWL2; and memory cells MC3 / MC6 are arranged in the same column and share read word line RWL3 and write word line WWL2. It is understood that although only 6 memory cells are shown in the diagram, the memory array MA can include more memory cells MC. Multiple memory cells arranged in an array constitute a memory cell array. By sharing bit lines and active lines, the integration density of the semiconductor structure can be further improved.

[0046] The memory array MA can perform write operations to store information in memory cells (MC1 / MC2 / MC3 / MC4 / MC5 / MC6) and read operations to retrieve information from memory cells (MC1 / MC2 / MC3 / MC4 / MC5 / MC6). The memory array MA can be configured to operate as a DRAM memory array. Compared to DRAM memory that stores information in capacitors, the memory array MA stores information as charge in the memory cell MC. The first transistor RT is electrically connected to the second gate (which can be understood as the memory node contact SN) of the second transistor WT, avoiding the size limitations imposed by capacitors.

[0047] Reference Figure 3 As shown, the semiconductor structure 10 includes: a memory cell MC, a read word line 115, a write word line 123, and a bit line 210. The memory cell MC includes a first transistor 110 and a second transistor 120. The first transistor 110 includes a first channel layer 111 disposed along a first direction X and a charge storage structure 112. The second transistor 120 includes a second channel layer 121 located on the side of the charge storage structure 112 away from the first channel layer 111 along the first direction X, and the second channel layer 121 is electrically connected to the charge storage structure 112. The read word line 115 extends along a second direction Y and is adjacent to the side of the first channel layer 111. The write word line 123 extends along the second direction Y and is adjacent to the side of the second channel layer 121. The bit line 210 extends along the first direction X and is electrically connected to the first channel layer 111 and the second channel layer 121.

[0048] By using two transistors as the memory cell MC, the size limitations imposed by capacitors are avoided, significantly reducing the size of the memory cell MC. The read word line 115 and the charge storage structure 112 are located on opposite sides of the first channel layer 111 along the first direction X, and the first transistor 110 serves as both a read transistor and a storage element. Furthermore, the structural layers of the first transistor 110 and the second transistor 120 are sequentially arranged along the first direction X, compressing the size of the memory cell MC in the vertical direction Z and reducing the manufacturing difficulty of the memory cell. In addition, the first transistor 110 and the second transistor 120 share a bit line 210 and are controlled by the read word line 115 and the write word line 123 respectively, effectively improving the utilization rate of the bit line 210 and further enhancing the integration density of the semiconductor structure.

[0049] Understandable, Figure 3 and Figure 4 The semiconductor structure 10 / 20 shown and Figure 5 and Figure 6 The three-dimensional semiconductor structure shown, 10S / 20S, is suitable for... Figure 1 The sum of the storage cell circuits shown Figure 2 The working principle of the storage array circuit shown.

[0050] In some embodiments, the side of the read line 115 adjacent to the first channel layer 111 means that the read line 115 is not in direct contact with the first channel layer 111, and the distance between the read line 115 and the first channel layer 111 is less than the distance between the read line 115 and the second channel layer 121; the side of the write line 123 adjacent to the second channel layer 121 means that the write line 123 is not in direct contact with the second channel layer 121, and the distance between the write line 123 and the second channel layer 121 is less than the distance between the write line 123 and the first channel layer 121.

[0051] In some embodiments, the first transistor 110 can be used as a read transistor, and the second transistor 120 can be used as a write transistor. One of the first transistor 110 and the second transistor 120 can be an N-type transistor or a P-type transistor. In one example, both the first transistor 110 and the second transistor 120 are N-type transistors.

[0052] In some embodiments, refer to Figure 3As shown, both the first transistor 110 and the second transistor 120 are vertical channel transistors (VCTs). The first gate of the first transistor 110 is a portion of the read word line 115, the second gate of the first transistor 110 is a charge storage structure 112, and the third gate of the second transistor 120 is a portion of the write word line 123. The first transistor 110 also includes a first dielectric layer 113 located at least between the read word line 115 and the first channel layer 111, and a second dielectric layer 114 located at least between the charge storage structure 112 and the first channel layer 111. The second transistor 120 also includes a third dielectric layer 122 located at least between the write word line 123 and the second channel layer 121. The materials of the first dielectric layer 113, the second dielectric layer 114, and the third dielectric layer 122 may include, for example, high-k dielectric materials, silicon oxide materials, silicon nitride materials, silicon oxynitride materials, or combinations thereof.

[0053] In some embodiments, refer to Figure 3 As shown, the first transistor 110 is controlled by the adjacent read word line 115, and the second transistor 120 is controlled by the adjacent write word line 123. The first transistor 110 and the second transistor 120 are arranged along a first direction X, and their arrangement direction is the same as the extension direction of the bit line 210. Furthermore, the first transistor 110 and the second transistor 120 are located on the same horizontal layer. That is, the spans of the first transistor 110 and the second transistor 120 in the vertical direction Z are substantially the same, and their projections in the first direction X substantially overlap. For example, the ratio of the overlapping portion of the projections of the first transistor 110 and the second transistor 120 in the first direction X to the projection of the first transistor 110 in the first direction X is greater than 80%.

[0054] In some embodiments, the length of the first channel layer 111 in the vertical direction Z is greater than the length of the second channel layer 121 in the vertical direction Z. The bottom end of the first channel layer 111 and the bottom end of the second channel layer 121 may be flush, and the top end of the first channel layer 111 may be higher than the top end of the second channel layer 121, which facilitates connecting the first channel layer 111 of the first transistor 110 to the active line and avoids short circuits in the second transistor 120.

[0055] In some embodiments, the threshold voltages of the first transistor 110 and the second transistor 120 are different. In one example, the threshold voltage of the first transistor 110 is greater than the threshold voltage of the second transistor 120, and the length of the read word line 115 in the vertical direction Z is greater than the length of the write word line 123 in the vertical direction Z. During the write operation of the memory cell MC, the second transistor 120 is turned on. The larger threshold voltage can avoid the possibility of leakage of the first transistor 110 during the write operation, ensuring the charge storage capacity of the charge storage structure 112.

[0056] In some embodiments, the source, channel region, and drain of the first transistor 110 and the second transistor 120 may be formed of the same material and have the same conductivity type, such as N-type or P-type.

[0057] In some embodiments, the materials of the first channel layer 111 of the first transistor 110 and the second channel layer 121 of the second transistor 120 can be monocrystalline silicon, polycrystalline silicon, germanium, silicon-germanium, and oxide semiconductor materials (e.g., zinc tin oxide (ZnO)). x Sn y O, commonly known as "ZTO"), indium zinc oxide (In x Zn y O, commonly known as "IZO"), zinc oxide (Zn) x O), Indium gallium zinc oxide (In x Ga y Zn z O, commonly known as "IGZO"), indium gallium silicon oxide (In) x Ga y Si z O, commonly known as "IGSO"), indium tin oxide (In) x Sn y ITO (Indium Tin O, commonly known as "ITO") and one or more other similar materials. In some examples, the material of the first channel layer 111 and the second channel layer 121 is IGZO. Because IGZO has good electron mobility and low leakage current, it can improve the switching speed of the first transistor 110 and the second transistor 120 and reduce their power consumption, thereby improving the overall performance and reliability of the memory cell.

[0058] In some embodiments, the materials of bit line 210, read word line 115, write word line 123, and charge storage structure 112 of the first transistor 110 can be conductive materials. Conductive materials can include one or more of the following: metals (e.g., tungsten (W), titanium (Ti), molybdenum (Mo), niobium (Nb), vanadium (V), hafnium (Hf), tantalum (Ta), chromium (Cr), zirconium (Zr), iron (Fe), ruthenium (Ru), cobalt (Co), nickel (Ni)); alloys (e.g., Co-based alloys, Ti-based alloys, Co and Ni-based alloys, Fe and Co-based alloys); materials containing conductive metals (e.g., conductive metal nitrides, conductive metal silicides, conductive metal carbides, conductive metal oxides); and conductive doped semiconductor materials (e.g., conductive doped polysilicon, conductive doped silicon-germanium). In one example, the material of charge storage structure 112 can be titanium nitride, which has a high charge storage density and good chemical and electrical stability, enabling it to retain stored charge for a long time and reducing the risk of data loss.

[0059] In some embodiments, refer to Figure 3 As shown, the first channel layer 111 includes a vertical channel portion 111b and a bent channel portion 111a connected to each other. The vertical channel portion 111b extends along the vertical direction Z, and the bent channel portion 111a extends along the first direction X. The read line 115 and the charge storage structure 112 are located on both sides of the vertical channel portion 111b along the first direction X, respectively. The first transistor 110 also includes a first dielectric layer 113 sandwiched between the read line 115 and the vertical channel portion 111b, and a second dielectric layer 114 sandwiched between the charge storage structure 112 and the vertical channel portion 111b. The first channel layer 111 and the first dielectric layer 113 are stacked in an "L" shape in cross-section along the first direction X and the vertical direction Z. The length of the vertical channel portion 111b along the vertical direction Z is greater than the length of the bent channel portion 111a along the first direction X. The end of the first channel layer 111 away from the bit line 210 can serve as the first drain (or first source) of the first transistor 110, that is, the bent channel portion 111a can serve as the first drain (or first source) of the first transistor 110; the end of the first channel layer 111 near the bit line 210 can serve as the first source (or first drain) of the first transistor 110.

[0060] In some embodiments, refer to Figure 4 As shown, in the semiconductor structure 20, the first channel layer 111 includes a vertical channel portion 111b and a bent channel portion 111a connected to each other. The vertical channel portion 111b extends along the vertical direction Z, and the bent channel portion 111a bends along the end of the vertical channel portion 111b toward the first direction X and the vertical direction Z away from the bit line 210. The bent channel portion 111a is arc-shaped.

[0061] In some embodiments, refer to Figure 3 As shown, bit line 210 is electrically connected to the end of vertical channel portion 111b away from bent channel portion 111a; the semiconductor structure 10 also includes an active line 310 electrically connected to the bent channel portion 111a of the first channel layer 111. Active line 310 can be a linear structure extending along a first direction X or a second direction Y. Active line 310 can also be a planar structure extending along the first direction X and the second direction Y. The material of active line 310 includes conductive material, and the material of active line 310 can be the same as that of bit line 210. Active line 310 can be used to apply a low voltage or ground voltage, and during a read operation on a selected memory cell MC, a current path can be formed between active line 310 and the corresponding bit line 210 through the first transistor 110 of the selected memory cell MC.

[0062] In some embodiments, refer to Figure 4 As shown, in the semiconductor structure 20, the active line 310 includes a horizontal active portion 311a and a vertical active portion 311b. The vertical active portion 311b protrudes vertically Z from the bottom surface of the horizontal active portion 311a and connects to the bent channel portion 111a. The horizontal active portion 311a may not directly contact the first channel layer 111, but contacts the bent channel portion 111a through the vertical active portion 311b. The vertical active portion 311b may also contact the first dielectric layer 113. Since the bent channel portion 111a is arc-shaped, contacting the bent channel portion 111a through the vertical active portion 311b increases the contact area, avoids poor contact, and reduces contact resistance.

[0063] In some embodiments, refer to Figure 3 As shown, the charge storage structure 112 includes a vertical storage section 112b and a horizontal storage section 112a connected to each other. The vertical storage section 112b extends along the vertical direction Z, and the horizontal storage section 112a protrudes from the sidewall of the vertical storage section 112b along the first direction X and connects to the second channel layer 121. The storage cell MC also includes a spacer layer 410, which is sandwiched between the vertical storage section 112b and the second channel layer 121, and between the ends of the first channel layer 111 and the second channel layer 121 near the bit line. The spacer layer 410 has an "L" shaped pattern in cross-section along the first direction X and the vertical direction Z. The material of the spacer layer 410 includes low-k dielectric materials such as silicon oxide, silicon nitride, silicon carbide, silicon carbide nitride, or silicon oxynitride. Because the spacer layer 410 is a low-k dielectric material, it can reduce the mutual interference between the first transistor 110 and the second transistor 120.

[0064] In some embodiments, refer to Figure 3As shown, the top surface of the horizontal storage unit 112a is flush with the top surface of the second channel layer 121, and the second dielectric layer 114 covers the top surface of the horizontal storage unit 112a and the top surface of the second channel layer 121.

[0065] In some embodiments, refer to Figure 4 As shown, the top of the horizontal storage section 112a is higher than the top surface of the second channel layer 121, and the second dielectric layer 114 covers the top of the horizontal storage section 112a and does not contact the top surface of the second channel layer 121.

[0066] In some embodiments, the thickness of the vertical storage section 112b along the first direction X is greater than the thickness of the reading line 115 along the first direction. For example, the ratio of the thickness of the vertical storage section 112b along the first direction X to the thickness of the reading line 115 along the first direction is in the range of 2-4. By providing a thicker charge storage structure 112, the charge storage capacity can be increased, and the charge storage time can be guaranteed.

[0067] In some embodiments, the horizontal storage portion 112a is located at the end of the vertical storage portion 112b away from the bit line 210, and the horizontal storage portion 112a is electrically connected to the end of the second channel layer 121 away from the bit line 210. The end of the second channel layer 121 away from the bit line 210 can serve as the second drain (or second source) of the second transistor 120, and the end of the second channel layer 121 near the bit line 210 can serve as the second source (or second drain) of the second transistor 120.

[0068] In some embodiments, refer to Figure 3 and Figure 4 As shown, multiple memory cells MC are arranged in an array along a first direction X and a second direction Y to form a memory array MA; read word lines 115 are located on the sides of multiple first channel layers 111 arranged along the second direction Y; write word lines 123 are located on the sides of multiple second channel layers 121 arranged along the second direction Y; bit lines 210 are electrically connected to the multiple memory cells MC arranged along the first direction X. Active lines 310 can be electrically connected to each memory cell MC. Multiple memory cells MC constitute a 4F array. 2 Arrangement or 6F 2 Layout. On the 4th floor. 2 In this arrangement, the first direction X is perpendicular to the second direction Y, and the storage cells MC are closely arranged, thus the storage array MA has a high degree of integration.

[0069] In some embodiments, refer to Figure 4As shown, among the multiple memory cells MC arranged along the first direction X, adjacent memory cells MC are mirror-symmetrical in a plane formed by the second direction Y and the vertical direction Z; wherein, between adjacent memory cells MC where the spacing between the first channel layers 111 is smaller than the spacing between the second channel layers 121, the first channel layers 111 of the adjacent memory cells MC are interconnected with each other through the first channel connection portion 111c; between adjacent memory cells MC where the spacing between the second channel layers 121 is smaller than the spacing between the first channel layers 111, the second channel layers 121 of the adjacent memory cells MC are interconnected with each other through the second channel connection portion 121c.

[0070] In some embodiments, among a plurality of memory cells MC arranged along the first direction X, any two adjacent memory cells MC are mirror-symmetrical along the plane formed by the second direction Y and the vertical direction Z. (Refer to...) Figure 4 As shown, taking three sequentially adjacent memory cells MC as an example, the memory cell MC on the left and the memory cell MC in the middle are mirror-symmetrical in the plane formed by the second direction Y and the vertical direction Z, and the memory cell MC in the middle and the memory cell MC on the right are also mirror-symmetrical in the plane formed by the second direction Y and the vertical direction Z. In the two memory cells MC on the left and the middle, the spacing between the second channel layers 121 is smaller than the spacing between the first channel layers 111. Therefore, the second channel layers 121 of the two memory cells MC on the left and the middle are interconnected through the second channel connection portion 121c. In the two memory cells MC on the middle and the right, the spacing between the first channel layers 111 is smaller than the spacing between the second channel layers 121. Therefore, the first channel layers 111 of the two memory cells MC on the middle and the right are interconnected through the first channel connection portion 111c.

[0071] In some embodiments, the first channel connector 111c and two first channel layers 111 interconnected by the first channel connector 111c are integrally formed, with a "U"-shaped cross-section in the first direction X and the vertical direction Z, and the first channel connector 111c and the first channel layers 111 have the same thickness. The second channel connector 121c and two second channel layers 121 interconnected by the second channel connector 121c are integrally formed, with a "U"-shaped cross-section in the first direction X and the vertical direction Z, and the second channel connector 121c and the second channel layers 121 have the same thickness.

[0072] In some embodiments, the first channel connection portion 111c, the first channel layer 111, the second channel connection portion 121c, and the second channel layer 121 all have the same thickness.

[0073] In some embodiments, the spacing between any two adjacent memory cells MC is the same. For example, the spacing between two memory cells MC located on the left and the middle is equal to the spacing between two memory cells MC located in the middle and the right. As a result, the memory array MA has better structural uniformity, which is beneficial for increasing the process manufacturing window.

[0074] In some embodiments, refer to Figure 4 As shown, both the first channel connection portion 111c and the second channel connection portion 121c extend along the first direction X. The first channel connection portion 111c connects the ends of two adjacent first channel layers 111 near the bit line 210, and the second channel connection portion 121c connects the ends of two adjacent second channel layers 121 near the bit line 210. Both the first channel connection portion 111c and the second channel connection portion 121c are electrically connected to the bit line 210. By increasing the contact area between the first channel layers 111 and 121 and the bit line 210, poor contact is avoided and the contact resistance is reduced.

[0075] In some embodiments, refer to Figure 5 and Figure 6 As shown, Figure 5 for Figure 3 The semiconductor structure 10S, consisting of the memory array MA, is shown. Figure 6 for Figure 4 The semiconductor structure 20S shown is composed of memory arrays MA. At least two memory arrays MA are stacked in the vertical direction Z to form a three-dimensional semiconductor structure. The semiconductor structure 10S / 20S also includes an insulating layer 510 located between two adjacent memory arrays MA in the vertical direction Z. The semiconductor structure 10S / 20S contains multiple layers of vertically stacked memory cells MC, forming a three-dimensional semiconductor structure, increasing the storage capacity of the semiconductor structure 10S / 20S, allowing more memory cells MC to be formed on a wafer of the same area. The insulating layer 510 is made of low-k dielectric materials such as silicon oxide, silicon nitride, silicon carbide, silicon carbide nitride, or silicon oxynitride. The insulating layer 510 separates adjacent memory arrays MA in the vertical direction Z, reducing the parasitic capacitance between the bit lines 210 of the upper memory array MA and the active lines 310 of the lower memory array MA, thus reducing mutual interference between memory cells MC.

[0076] Reference Figures 7-23 This disclosure also provides a method for fabricating a semiconductor structure. It is understood that... Figures 8-23In the figure, the first direction X and the second direction Y are horizontal directions parallel to the plane where the substrate 101 is located, and the first direction X intersects the second direction Y. For example, the first direction X can be perpendicular to the second direction Y. The vertical direction Z is the direction that intersects the plane where the substrate 101 is located. For example, the vertical direction Z is perpendicular to the plane where the substrate 101 is located.

[0077] Reference Figure 7 As shown, the method for fabricating a semiconductor structure includes at least the following steps:

[0078] S101: Form a memory cell, the memory cell including a first transistor and a second transistor, the first transistor including a first channel layer and a charge storage structure disposed along a first direction, the second transistor including a second channel layer located on one side of the charge storage structure along the first direction, the second channel layer being electrically connected to the charge storage structure;

[0079] S102: Forming a writing line, the writing line extending along the second direction and adjacent to the side of the first channel layer;

[0080] S103: Forming a reading line, which extends along the second direction and is adjacent to the side of the second channel layer;

[0081] S104: Form a bit line that extends along a first direction and is electrically connected to the first channel layer and the second channel layer.

[0082] It should be understood that Figure 7 The steps shown are not exclusive; other steps may be performed before, after, or between any of the steps shown. Figure 7 The steps shown can be adjusted in order according to actual needs. For example, bit lines can be formed first, followed by memory cells.

[0083] Reference Figure 8 As shown, a substrate 100 is provided, which may include a substrate 101 and an isolation layer 102. Bit lines 210 extending along a first direction X are formed on the substrate 100. This can be achieved by first forming the bit lines 210 and then filling the bit line isolation structures 211 between the bit lines 210, or by first forming the bit line isolation structures 211 and then filling the bit lines 210 between the bit line isolation structures 211. For example, a bit line material layer can be formed on the substrate 100, the bit line material layer can be patterned into bit lines 210, a bit line isolation material layer can be deposited to fill the gaps between the bit lines 210, and the bit line isolation material layer can be planarized to form a bit line isolation structure 211 with its top surface flush with the top surface of the bit lines 210.

[0084] The substrate 101 is made of semiconductor materials, such as elemental semiconductor materials (e.g., silicon (Si) or germanium (Ge), III-V compound semiconductor materials (e.g., gallium nitride (GaN), gallium arsenide (GaAs), or indium phosphide (InP), etc.), II-VI compound semiconductor materials (e.g., zinc sulfide (ZnS), cadmium sulfide (CdS), or cadmium telluride (CdTe), etc.), organic semiconductor materials, or other semiconductor materials known in the art. The isolation layer 102 and the bit line isolation structure 211 include silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, or silicon oxynitride, etc.

[0085] In some embodiments, the substrate 100 may not include the isolation layer 102, but only includes a substrate 101, which may be made of single-crystal silicon. A mask layer is formed on the substrate 100, exposing the region in the substrate 100 where the bit lines 210 need to be formed. The bit lines 210 are formed in the substrate 101 by doping. For example, a high concentration of dopant, such as boron or phosphorus, is used to ensure that the bit lines 210 have good conductivity. Doping can be performed by methods such as ion implantation or diffusion.

[0086] In some embodiments, forming a storage unit includes: a reference Figure 9 As shown, a first isolation structure 401 is formed, and the first isolation structure 401 extends along the second direction Y; refer to Figure 10 As shown, a second channel layer 121 and a third dielectric layer 122 are sequentially formed on the sidewall of the first isolation structure 401; a charge storage structure 112 is formed on the sidewall of the second channel layer 121; refer to Figures 19-23 As shown, a second dielectric layer 114, a first channel layer 111, and a first dielectric layer 113 are sequentially formed on the sidewall of the charge storage structure 112.

[0087] In some embodiments, a second channel layer 121 and a third dielectric layer 122 are sequentially formed on the sidewall of the first isolation structure 401, including: (reference) Figure 10 As shown, a second channel material layer 121' and a third dielectric material layer 122' are sequentially formed on the sidewall of the first isolation structure 401; refer to Figure 11 As shown, a first mask pattern 402 extending along the first direction X and arranged along the second direction Y is formed on the third dielectric material layer 122'; Refer to Figure 11 As shown, the second channel material layer 121' and the third dielectric material layer 122' are sequentially etched using the first mask pattern 402 as a mask to form the second channel layer 121 and the third dielectric layer 122.

[0088] In some embodiments, refer to Figure 10As shown, a first mask material layer 402' is formed on the surfaces of the second channel material layer 121' and the third dielectric material layer 122'. The first mask material layer 402' fills the gap between the first isolation structures 401, and the top surface of the first mask material layer 402' is higher than the top surface of the third dielectric material layer 122'. (Refer to...) Figure 11 As shown, the first mask material layer 402' is patterned to form a first mask pattern 402, each first mask pattern 402 covers the third dielectric material layer 122' and extends along the first direction X, and the plurality of first mask patterns 402 are arranged along the second direction Y.

[0089] In some embodiments, after sequentially etching the second channel material layer 121' and the third dielectric material layer 122' using the first mask pattern 402 as a mask, a third dielectric supplementary material layer is deposited on the surface of the first isolation structure 401 and the patterned third dielectric material layer 122', with the third dielectric material layer 122' and the third dielectric supplementary layer serving as the third dielectric layer 122. The third dielectric supplementary material layer is used to cover the exposed sidewalls of the second channel layer 121, preventing short circuits or leakage between adjacent second channel layers 121 along the second direction Y.

[0090] In some embodiments, refer to Figure 11 , 12 As shown in Figure 13, after removing the first mask pattern 402, a second isolation structure 403 is formed between the trenches formed between the second channel layer 121, the third dielectric layer 122, and the first isolation structure 401. The second isolation structure 403 includes a second isolation first portion 403a located at the bottom of the trench and a second isolation second portion 403b located above the second isolation first portion 403a. The height of the second isolation first portion 403a in the vertical direction Z is less than one-fifth of the height of the second isolation second portion 403b in the vertical direction Z.

[0091] In some embodiments, refer to Figure 12As shown, after forming the second isolation first portion 403a, write lines 123 are formed on the exposed sidewalls of the third dielectric layer 122 and the first isolation structure 401. For example, a write line material layer can be formed on the surface of the third dielectric layer 122 and the second isolation first portion 403a. The write line material layer located on the top surface of the third dielectric layer 122 and the second isolation first portion 403a is removed by anisotropic etching, leaving the write line material layer located on the sidewall of the third dielectric layer 122 as the write line 123. The top surface of the write line 123 is lower than the top surface of the third dielectric layer 122. After forming the write lines 123, the gaps between the write lines 123 are filled with the second isolation second portion 403b. The second isolation first portion 403a is used to separate the write lines 123 from the second source (or second drain) of the second transistor and the bit line 210, reducing the coupling between the write lines 123 and the bit line 210.

[0092] In some embodiments, refer to Figure 13 As shown, after the writing line 123 is formed, the second isolation second portion 403b is filled, and the top surface of the second isolation second portion 403b can be flush with the top surface of the third dielectric layer 122.

[0093] In some embodiments, refer to Figure 13 and 14 As shown, before removing part of the first isolation structure 401, the method further includes: removing the second channel layer 121 and the third dielectric layer 122 located on the top surface of the first isolation structure 401, so that... Figure 13 The continuous second channel layer 121 along the first direction X is broken into multiple second channel layers 121 arranged at intervals along the first direction X. The cross-section of the broken second channel layer 121 in the first direction X and the vertical direction Z is "U" shaped.

[0094] In some embodiments, a charge storage structure 112 is formed on the sidewall of the second channel layer 121, including: referencing Figure 14 As shown, a portion of the first isolation structure 401 is removed to expose the top sidewall of the second channel layer 121; refer to Figure 15 As shown, a horizontal storage section 112a is formed on the top sidewall of the second channel layer 121. The horizontal storage section 112a is located on the first isolation structure 401 and extends along the second direction Y; Refer to Figure 16 As shown, the first isolation structure 401 is etched using the horizontal storage section 112a as a mask to form the first spacer trench 401T; Refer to Figure 17 As shown, a vertical storage section 112b is formed on the side wall of the horizontal storage section 112a and the side wall of the first spacer 401T. The horizontal storage section 112a and the vertical storage section 112b constitute a charge storage structure 112.

[0095] It is understood that the top 121a of the second channel layer 121, exposed by removing part of the first isolation structure 401, is used as the second drain (or second source) of the second transistor. A horizontal storage portion 112a contacting the sidewall of the top 121a of the second channel layer 121, and a vertical storage portion 112b contacting the sidewall of the horizontal storage portion 112a, can be formed by self-alignment to ensure structural uniformity. In the actual etching process, the tops of the horizontal storage portion 112a and the vertical storage portion 112b are arc-shaped.

[0096] In some embodiments, refer to Figure 18 As shown, after forming the charge storage structure 112, the remaining first isolation structure 401 is further etched along the charge storage structure 112 to form a spacer layer 410. The spacer layer 410 has an "L" shape in cross-section along the first direction X and the vertical direction Z. The width of the spacer layer 410 at one end near the bit line 210 along the first direction X is greater than the width at the other end.

[0097] In some embodiments, a second dielectric layer 114, a first channel layer 111, and a first dielectric layer 113 are sequentially formed on the sidewall of the charge storage structure 112, including: [reference] Figure 20 As shown, a second dielectric material layer 114', a first channel material layer 111', and a first dielectric material layer 113' are sequentially formed on the sidewall of the charge storage structure 112; a second mask pattern 405 extending along the first direction X is formed on the first channel material layer 111' (the second mask pattern is shown with an unfilled frame to avoid obscuring other structures); see reference Figure 21 As shown, the second dielectric material layer 114', the first channel material layer 111', and the first dielectric material layer 113' are etched using the second mask pattern 405 as a mask to form the second dielectric layer 114, the first channel layer 111, and the first dielectric layer 113, and the second mask pattern 405 is removed. (Refer to...) Figure 4 As shown, the first channel layer 111 includes vertical channel portions 111b and bent channel portions 111a connected to each other, with the top surface of the bent channel portion 111a flush with the top surface of the second isolation structure 403; the method further includes: referring to Figure 23 As shown, an active line 310 is formed, and the active line 310 is electrically connected to the bent channel portion 111a of the first channel layer 111.

[0098] In some embodiments, refer to Figure 20As shown, after the sidewalls of the charge storage structure 112 conformally cover the second dielectric material layer 114', the first channel material layer 111', and the first dielectric material layer 113', a third isolation structure 404 is filled into the trench formed by the first dielectric material layer 113'. The top surface of the third isolation structure 404 is flush with the top surfaces of the second isolation structure 403 and the first channel material layer 111'. (Refer to...) Figure 21 As shown, when etching the second dielectric material layer 114', the first channel material layer 111', and the first dielectric material layer 113' using the second mask pattern 405 as a mask, the etching process also includes removing a portion of the third isolation structure 404 using the second mask pattern 405 as a mask to form a second spacer groove 404T. The second spacer groove 404T exposes a portion of the sidewall of the second isolation structure 403, and the width of the second spacer groove 404T along the first direction X is equal to the spacing between adjacent second isolation structures 403. (Refer to...) Figure 22 As shown, a fourth isolation structure 406 is filled into the second spacer slot 404T.

[0099] In some embodiments, refer to Figure 22 As shown, the third isolation structure 404 and part of the fourth isolation structure 406 can also be removed, while the fourth isolation structure 406 located in the gap between the memory cells MC along the second direction Y is retained to expose the first dielectric layer 113. Read word lines 115 extending along the second direction Y are formed on the sidewalls of the first dielectric layer 113 and the fourth isolation structure 406. Then, the gap between adjacent read word lines 115 is filled with a fifth isolation structure 407, and the top surface of the fifth isolation structure 407 is flush with the top surface of the first channel layer 111.

[0100] In some embodiments, refer to Figure 23 and Figure 4 As shown, the active line 310 includes a plate-shaped horizontal active section 311a and a vertical active section 311b. The vertical active section 311b protrudes along the vertical direction Z from the bottom surface of the horizontal active section 311a and connects to the bent channel section 111a. The vertical active section 311b can be connected to the memory cell MC one-to-one.

[0101] The various semiconductor structures illustrated in this specific embodiment can be used in electronic devices with storage functions. These electronic devices can be terminal devices, such as mobile phones, tablets, and smart bracelets, or personal computers (PCs), servers, workstations, etc. The storage function in these electronic devices can be implemented using the following types of memory: Dynamic Random Access Memory (DRAM), Ferroelectric Random Access Memory (FRAM), Phase Change Memory (PCM), Magnetic Random Access Memory (MRAM), or Resistive Random Access Memory (RRAM).

[0102] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A semiconductor structure, characterized in that, include: A memory cell includes a first transistor and a second transistor. The first transistor includes a first channel layer and a charge storage structure disposed along a first direction. The second transistor includes a second channel layer located on the side of the charge storage structure away from the first channel layer along the first direction. The second channel layer is electrically connected to the charge storage structure. A reading line, which extends along a second direction and is adjacent to the side of the first channel layer; A writing line, the writing line extending along a second direction and adjacent to the side of the second channel layer; Bit lines extend along the first direction and are electrically connected to the first channel layer and the second channel layer.

2. The semiconductor structure according to claim 1, characterized in that, The first channel layer includes vertical channel portions and bent channel portions connected to each other. The vertical channel portions extend in a vertical direction, and the reading lines and the charge storage structure are located on both sides of the vertical channel portions along a first direction, respectively. The first transistor further includes a first dielectric layer sandwiched between the read line and the vertical channel portion, and a second dielectric layer sandwiched between the charge storage structure and the vertical channel portion.

3. The semiconductor structure according to claim 2, characterized in that, The bit line is electrically connected to the end of the vertical channel portion away from the bent channel portion; The semiconductor structure also includes: An active wire is electrically connected to the bent channel portion of the first channel layer.

4. The semiconductor structure according to claim 3, characterized in that, The active line includes a horizontal active section and a vertical active section. The vertical active section protrudes vertically from the bottom surface of the horizontal active section and connects to the bent channel section.

5. The semiconductor structure according to claim 1, characterized in that, The charge storage structure includes a vertical storage section and a horizontal storage section connected to each other. The vertical storage section extends in a vertical direction, and the horizontal storage section protrudes from the sidewall of the vertical storage section in a first direction and is connected to the second channel layer. The storage cell further includes a spacer layer sandwiched between the vertical storage section and the second channel layer, and between the ends of the first channel layer and the second channel layer near the bit line.

6. The semiconductor structure according to claim 5, characterized in that, The horizontal storage section is located at the end of the vertical storage section away from the bit line, and the horizontal storage section is electrically connected to the end of the second channel layer away from the bit line.

7. The semiconductor structure according to claim 1, characterized in that, The plurality of said storage cells are arranged in an array along the first direction and the second direction to form a storage array; The reading lines are located on the sides of a plurality of first channel layers arranged along the second direction; The writing lines are located on the sides of a plurality of second channel layers arranged along the second direction; The bit lines are electrically connected to a plurality of memory cells arranged along the first direction.

8. The semiconductor structure according to claim 7, characterized in that, In a plurality of storage cells arranged along the first direction, adjacent storage cells are mirror-symmetrical in a plane formed by the second direction and the vertical direction; wherein, Between two adjacent memory cells where the spacing between the first channel layers is smaller than the spacing between the second channel layers, the first channel layers of the two adjacent memory cells are interconnected with each other through a first channel connection portion. Between two adjacent memory cells, the spacing between the second channel layers is smaller than the spacing between the first channel layers, and the second channel layers of the two adjacent memory cells are interconnected with each other through the second channel connection portion.

9. The semiconductor structure according to claim 8, characterized in that, Both the first channel connection portion and the second channel connection portion extend along the first direction. The first channel connection portion connects the ends of two adjacent first channel layers near the bit line, and the second channel connection portion connects the ends of two adjacent second channel layers near the bit line. Both the first channel connection portion and the second channel connection portion are electrically connected to the bit line.

10. The semiconductor structure according to claim 7, characterized in that, At least two of the memory arrays are stacked vertically to form a three-dimensional semiconductor structure; The semiconductor structure further includes an insulating layer located between two adjacent memory arrays in the vertical direction.

11. A method for fabricating a semiconductor structure, characterized in that, include: A memory cell is formed, the memory cell including a first transistor and a second transistor, the first transistor including a first channel layer and a charge storage structure disposed along a first direction, the second transistor including a second channel layer located on the side of the charge storage structure away from the first channel layer along the first direction, the second channel layer being electrically connected to the charge storage structure; A writing line is formed, the writing line extending along a second direction and adjacent to the side of the first channel layer; A reading line is formed, the reading line extending along a second direction and adjacent to the side of the second channel layer; A bit line is formed, which extends along the first direction and is electrically connected to the first channel layer and the second channel layer.

12. The preparation method according to claim 11, characterized in that, The formation of the storage unit includes: A first isolation structure is formed, and the first isolation structure extends along a second direction; A second channel layer and a third dielectric layer are sequentially formed on the sidewall of the first isolation structure; A charge storage structure is formed on the sidewall of the second channel layer; A second dielectric layer, a first channel layer, and a first dielectric layer are sequentially formed on the sidewall of the charge storage structure.

13. The preparation method according to claim 12, characterized in that, The second channel layer and the third dielectric layer are sequentially formed on the sidewall of the first isolation structure, including: A second channel material layer and a third dielectric material layer are sequentially formed on the sidewall of the first isolation structure; A first mask pattern extending along the first direction and arranged along the second direction is formed on the third dielectric material layer; Using the first mask pattern as a mask, the second channel material layer and the third dielectric material layer are etched sequentially to form the second channel layer and the third dielectric layer.

14. The preparation method according to claim 12, characterized in that, A second dielectric layer, a first channel layer, and a first dielectric layer are sequentially formed on the sidewall of the charge storage structure, including: A second dielectric material layer, a first channel material layer, and a first dielectric material layer are sequentially formed on the sidewall of the charge storage structure; A second mask pattern extending along the first direction is formed on the first channel material layer; Using the second mask pattern as a mask, the second dielectric material layer, the first channel material layer, and the first dielectric material layer are etched to form the second dielectric layer, the first channel layer, and the first dielectric layer. The first channel layer includes vertical channel portions and bent channel portions that are connected to each other. The method further includes: forming an active line, the active line being electrically connected to the bent channel portion of the first channel layer.

15. The preparation method according to claim 12, characterized in that, The formation of the charge storage structure located on the sidewall of the second channel layer includes: Remove part of the first isolation structure to expose the top sidewall of the second channel layer; A horizontal storage section is formed on the top sidewall of the second channel layer, the horizontal storage section being located on the first isolation structure and extending along the second direction; The first isolation structure is etched using the horizontal storage section as a mask to form a spacer groove; A vertical storage section is formed on the sidewall of the horizontal storage section and the sidewall of the spacer slot, and the horizontal storage section and the vertical storage section constitute the charge storage structure.

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