Memory device structure including capacitor

Abstract

The invention relates to a memory device structure including a capacitor. A structure for a memory device and a method of forming a structure for a memory device. The structure includes a first transistor including a first gate structure and a first source / drain region; a second transistor including a second gate structure and a second source / drain region; and a capacitor including a first capacitor plate directly coupled to the first source / drain region, a second capacitor plate, and a capacitor dielectric layer between the first capacitor plate and the second capacitor plate.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to semiconductor device fabrication and integrated circuits, and more particularly to structures for memory devices and methods of forming structures for memory devices. BACKGROUND

[0002] Non-volatile memory devices are used in various electronic products for applications such as general storage and transfer of data. The stored data is retained by non-volatile memory devices when the memory cells are not powered. The persistence of data storage by non-volatile memory devices contrasts with the formation of volatile memory technologies such as static random access memory (SRAM) devices, where the stored data is eventually lost when the memory cells are powered off, and dynamic random access memory (DRAM) devices, where the stored data is lost when the memory cells are not periodically refreshed. Conventional non-volatile memory devices have a footprint that occupies a large chip area, which limits their use in electronic products.

[0003] There is a need for improved structures for memory devices and methods of forming structures for memory devices. SUMMARY

[0004] In an embodiment of the invention, a structure for a memory device is provided. The structure includes a first transistor including a first gate structure and a first source / drain region, a second transistor including a second gate structure and a second source / drain region, and a capacitor including a first capacitor plate directly coupled to the first source / drain region, a second capacitor plate, and a capacitor dielectric layer between the first capacitor plate and the second capacitor plate.

[0005] In an embodiment of the invention, a structure for a memory device is provided. The structure includes a silicon-on-insulator substrate including a semiconductor substrate, a dielectric layer on the semiconductor substrate, and a semiconductor layer on the dielectric layer. The dielectric layer adjoins the semiconductor substrate along an interface. The structure further includes a transistor including a gate structure and a source / drain region in the semiconductor layer, and a capacitor including a first capacitor plate adjacent the interface, a second capacitor plate, and a capacitor dielectric layer between the first capacitor plate and the second capacitor plate. The structure further includes a conductor layer extending from the source / drain region through the dielectric layer to the first capacitor plate.

[0006] In an embodiment of the present invention, a method for forming a structure for a memory device is provided. The method includes: forming a first transistor, the first transistor including a first gate structure and a first source / drain region; forming a second transistor, the second transistor including a second gate structure and a second source / drain region; and forming a capacitor, the capacitor including a first capacitor plate directly coupled to the first source / drain region, a second capacitor plate, and a capacitor dielectric layer located between the first capacitor plate and the second capacitor plate. Attached Figure Description

[0007] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate various embodiments of the invention and, together with the general description of the invention given above and the detailed description of the embodiments given below, serve to explain the embodiments of the invention. In the drawings, the same reference numerals denote the same features in the various views.

[0008] Figure 1 This is a cross-sectional view of the structure of the initial manufacturing stage of the processing method according to an embodiment of the present invention.

[0009] Figure 1A It is roughly along Figure 1 The cross-sectional view taken from line 1A-1A in the diagram.

[0010] Figure 2 Is Figure 1 , 1A A top view of the structure during the manufacturing stage of the subsequent processing methods.

[0011] Figure 2A It is roughly along Figure 2 The cross-sectional view taken from line 2A-2A in the diagram.

[0012] Figure 3 Is Figure 2 , 2A A top view of the structure during the manufacturing stage of the subsequent processing methods.

[0013] Figure 3A It is roughly along Figure 3 The cross-sectional view taken from line 3A-3A in the diagram.

[0014] Figure 4 Is Figure 3 , 3A A top view of the structure during the manufacturing stage of the subsequent processing methods.

[0015] Figure 4A It is roughly along Figure 4 The cross-sectional view taken from line 4A-4A in the diagram.

[0016] Figure 4B It is roughly along Figure 4The cross-sectional view taken from line 4B-4B in the diagram.

[0017] Figure 5 Is Figure 4 , 4A A top view of the structure of the manufacturing stage of the processing method after 4B.

[0018] Figure 5A It is roughly along Figure 5 The cross-sectional view taken from line 5A-5A in the diagram.

[0019] Figure 5B It is roughly along Figure 5 The cross-sectional view taken from line 5B-5B in the diagram.

[0020] Figure 6 Is Figure 5 , 5A A cross-sectional view of the structure in the manufacturing stage of the processing method after 5B.

[0021] Figure 7 This is a cross-sectional view of the structure according to an alternative embodiment of the present invention.

[0022] Figure 8 This is a cross-sectional view of the structure according to an alternative embodiment of the present invention.

[0023] Figure 9 This is a cross-sectional view of the structure according to an alternative embodiment of the present invention.

[0024] Figure 10 This is a cross-sectional view of the structure according to an alternative embodiment of the present invention. Detailed Implementation

[0025] refer to Figure 1 , 1A Furthermore, according to embodiments of the present invention, a structure 10 for a memory device can be fabricated using a silicon-on-insulator (SiI) substrate, the SiI substrate comprising a semiconductor layer 12, a semiconductor substrate 16, and a dielectric layer 14 disposed between the semiconductor layer 12 and the semiconductor substrate 16. The semiconductor layer 12 may be made of a semiconductor material such as monocrystalline silicon. The dielectric layer 14 may be made of a dielectric material such as silicon dioxide, which is an electrical insulator. The semiconductor substrate 16 may be made of a semiconductor material such as monocrystalline silicon, which is lightly doped to have, for example, p-type conductivity. The semiconductor layer 12, which is physically separated from and electrically isolated from the semiconductor substrate 16 by the intermediate dielectric layer 14, can be significantly thinner than the semiconductor substrate 16. The dielectric layer 14 has a lower interface with the semiconductor substrate 16 and an upper interface with the semiconductor layer 12.

[0026] In an embodiment, the dielectric layer 14 may be a buried oxide layer on a silicon-on-insulator (SiI) substrate, and the semiconductor layer 12 may be a device layer on the SiI substrate. The buried oxide layer provided by the dielectric layer 14 can separate the device layer provided by the semiconductor layer 12 from the semiconductor substrate 16. In an embodiment, the semiconductor layer 12 on the SiI substrate may have a thickness suitable for fabricating a fully depleted SiI device structure. In an embodiment, the semiconductor layer 12 may have a thickness in the range of about 4 nanometers to about 20 nanometers.

[0027] Gate structures 18, 20, 22, and 24 may be formed on the top surface of semiconductor layer 12 at a given pitch P. Each of gate structures 18, 20, 22, and 24 includes a gate electrode 26 and a gate dielectric layer 28. A dielectric spacer 30 surrounds the gate electrode 26 and the gate dielectric layer 28 of each of gate structures 18, 20, 22, and 24. The gate electrode 26 may be made of a conductor such as doped polysilicon, the gate dielectric layer 28 may be made of a dielectric material such as silicon dioxide as an electrical insulator, and the dielectric spacer 30 may be made of a dielectric material such as silicon nitride as an electrical insulator. A silicide barrier layer (not shown) may be formed on the top surface of each gate electrode 26. Each of gate structures 18, 20, 22, and 24 has a length L measured along its longest dimension, and the dielectric spacer 30 may have a thickness T0.

[0028] Semiconductor layers 31 and 32 can be formed on the top surface of semiconductor layer 12 in the space between gate structures 18, 20, 22, and 24. Dielectric spacers 27 electrically isolate semiconductor layers 31 and 32 from gate structures 18, 20, 22, and 24. Semiconductor layers 31 and 32 can provide raised source / drain regions for structure 10. A portion of semiconductor layer 12 below semiconductor layers 31 and 32 can receive diffused dopant from semiconductor layers 31 and 32 and provide source / drain regions in semiconductor layer 12. As used herein, the term "source / drain region" refers to a region of semiconductor material that can be used as the source or drain of a field-effect transistor. Semiconductor layers 31 and 32 can be composed of single-crystal semiconductor materials such as silicon or silicon-germanium formed by epitaxial growth processes. As used herein, single-crystal semiconductor materials are characterized by a continuous lattice and the absence of grain boundaries. The single-crystal semiconductor material of semiconductor layer 12 has a crystal structure that serves as a crystal template during the epitaxial growth of the crystal structure of the single-crystal semiconductor materials of semiconductor layers 31 and 32. In an embodiment, semiconductor layers 31 and 32 may be doped with a concentration of n-type dopant, such as arsenic or phosphorus, that provides p-type conductivity during epitaxial growth. In an alternative embodiment, semiconductor layers 31 and 32 may be doped with a concentration of p-type dopant, such as boron, that provides p-type conductivity during epitaxial growth.

[0029] refer to Figure 2 , 2A The same reference numerals indicate Figure 1 , 1A The same features as those in the previous process allow for the formation of a dielectric layer 34 over gate structures 18, 20, 22, 24 and semiconductor layers 31, 32 during subsequent fabrication stages. For example, dielectric layer 34 may be composed of a deposited and planarized dielectric material such as silicon dioxide. Dielectric layer 34 can be patterned using photolithography and etching processes to form openings exposing gate structures 20 and 24. Trench 33 can be formed by removing gate structure 20 and portions of semiconductor layer 12 and dielectric layer 14 beneath the removed gate structure 20. Trench 33 extends through dielectric layer 34, semiconductor layer 12, and dielectric layer 14, and into semiconductor substrate 16. Trench 35 can be formed by removing gate structure 24 and portions of semiconductor layer 12 and dielectric layer 14 beneath the removed gate structure 24 and dielectric spacer 30. Trench 35 extends through dielectric layer 34, semiconductor layer 12, and dielectric layer 14, and into semiconductor substrate 16.

[0030] Trench 33 is laterally positioned between semiconductor layer 31 and a doped portion of semiconductor layer 12 beneath semiconductor layer 31. A portion of trench 33 is surrounded by dielectric spacers 30 associated with the removed gate structure 20. A portion of trench 35 is also surrounded by dielectric spacers 30 associated with gate structure 24.

[0031] refer to Figure 3 , 3A The same reference numerals indicate Figure 2 , 2A With the same characteristics as in the previous stage, in subsequent manufacturing stages, trench 35 can be filled with a dielectric layer 36 made of a dielectric material such as silicon dioxide to provide a single diffusion break. Trench 33 can be temporarily filled with a removable filler such as an organic dielectric layer, which is removed after the dielectric layer 36 is formed to reopen trench 33.

[0032] The trench 33 may be filled by the dielectric layer 38 and the conductor layer 40 of the trench capacitor. The conductor layer 40 is disposed inside the dielectric layer 38 as a core layer. The conductor layer 40 has sidewalls 41, and the dielectric layer 38 surrounds the sidewalls 41 of the conductor layer 40 as a liner. A portion of the dielectric layer 38 is disposed between a portion of the conductor layer 40 and the semiconductor layer 31, and between a portion of the conductor layer 40 and a portion of the semiconductor layer 12 located below the semiconductor layer 31. The dielectric layer 38 may have a thickness T1. A portion of the dielectric layer 34 and a portion of the conductor layer 40 are surrounded by dielectric spacers 30 associated with the removed gate structure 20.

[0033] In one embodiment, the dielectric layer 38 may be made of an electrically insulating dielectric material. In another embodiment, the dielectric layer 38 may be made of a high-k dielectric material characterized by a dielectric constant greater than about 20, such as hafnium oxide, titanium oxide, zirconium oxide, tantalum oxide, or strontium titanate. In an alternative embodiment, the dielectric layer 38 may be made of silicon dioxide. Forming the dielectric layer 38 from a high-k dielectric material can promote increased capacitance and retention time. The conductor layer 40 may be made of a material such as doped amorphous silicon or tungsten, which is an electrical conductor. The conductor layer 40 may have a length L of gate structures 18, 20, 22, 24.

[0034] In one embodiment, a portion of the dielectric layer 38 covering the bottom of the trench 33 may be removed before the conductor layer 40 is formed, such that the conductor layer 40 includes a bottom portion that is physically and electrically in contact with the semiconductor substrate 16. The same etching process can remove a portion of the dielectric material of the dielectric layer 38 from the top surface of the dielectric layer 34.

[0035] refer to Figure 4 , 4A 4B, where the same reference numerals indicate Figure 3 , 3AThe same features are present in the trenches 33, which include the dielectric layer 38 and the conductor layer 40, and trenches 42 and 44 can be formed in pairs along the length of the trench 33. The formation of trenches 42, 44 removes corresponding sections of the dielectric spacer 30 surrounding the dielectric layer 38 and the conductor layer 40, as well as portions of the semiconductor layer 12 beneath the removed sections of the dielectric spacer 30. In embodiments, the material of the dielectric spacer 30 can be selectively removed relative to the materials of the dielectric layer 38 and the conductor layer 40. As used herein, the term “selective” with respect to a material removal process (e.g., etching) means that, with appropriate etchant selection, the material removal rate (i.e., the etching rate) for the target material is greater than the removal rate for at least one other material exposed to the material removal process. The removed sections of the dielectric spacer 30 are associated with the location of the source / drain regions provided by the semiconductor layers 31, 32 and portions of the semiconductor layer 12 beneath the semiconductor layers 31, 32. In this embodiment, trenches 42 and 44 may partially penetrate the thickness of semiconductor layer 12.

[0036] refer to Figure 5 , 5A 5B, where the same reference numerals indicate Figure 4 , 4A The same features as in 4B can be used in subsequent manufacturing stages, where trench 42 can be filled by corresponding portions of conductor layer 43, and trench 44 can be filled by corresponding portions of conductor layer 45. Conductor layers 43 and 45 can be made of materials such as doped silicon or titanium, which are electrical conductors. In embodiments, conductor layers 43 and 45 can be deposited and planarized by chemical mechanical polishing. In embodiments, conductor layers 43 and 45 can be formed by an epitaxial growth process. Portions of dielectric spacers 30 are positioned as dielectric layers of electrically insulating dielectric material between portions of conductor layers 43, and portions of dielectric spacers 30 are also positioned as dielectric layers of electrically insulating dielectric material between portions of conductor layers 45. Conductor layers 43 and 45 are spaced apart along the length of conductor layer 40.

[0037] Structure 10 includes a plurality of transistors 48 associated with gate structure 18 and semiconductor layers 31, 32 located on the sides of gate structure 18, and a plurality of transistors 50 associated with gate structure 22 and semiconductor layers 31, 32 located on the sides of gate structure 22. Structure 10 also includes a plurality of capacitors 52 associated with each of the transistors 48 and a plurality of capacitors 54 associated with each of the transistors 50. Capacitors 52 and 54 share a conductor layer 40 serving as a capacitor plate or electrode, and share a dielectric layer 38 serving as a capacitor dielectric layer. Each capacitor 52 includes a conductor layer 43 serving as a capacitor plate or electrode in conductor layer 43, which is separated from a portion of conductor layer 40 by a portion of dielectric layer 38. Each capacitor 54 includes a conductor layer 45 serving as a capacitor plate or electrode in conductor layer 45, which is separated from a portion of conductor layer 40 by a portion of dielectric layer 38. Patterned portions of the dielectric spacer 30 provide dielectric layers that provide electrical isolation between adjacent portions of the conductor layer 43 of the capacitor 52 and adjacent portions of the conductor layer 45 of the capacitor 54. Each conductor layer 43 and each conductor layer 45 may have a thickness T2 that is substantially equal to the thickness T0 of the dielectric spacer 30.

[0038] Each pair of capacitor 52 and transistor 48 can define a memory cell of the memory device, and each pair of capacitor 54 and transistor 50 can define a memory cell of the memory device. Memory cells including capacitors 52, 54 and transistors 48, 50 can be deployed in a memory device comprising a large array of memory cells.

[0039] The capacitance of capacitors 52 and 54 can be increased or decreased proportionally to the height of conductor layers 43 and 45. The height of conductor layers 43 and 45 can be adjusted by recessing conductor layers 43 and 45 within trenches 42 and 44. The capacitance of capacitors 52 and 54 can be increased or decreased inversely proportional to the thickness T1 of dielectric layer 38.

[0040] refer to Figure 6 The same reference numerals indicate Figure 5 , 5AWith the same features as in 5B, in subsequent manufacturing stages, structure 10 may further include a contact layer having a dielectric layer 55 formed on dielectric layer 34, contacts 56 physically and electrically coupled in dielectric layers 34 and 55 to gate electrodes 26 in gate structure 18 of transistor 48 and gate electrode 26 in gate structure 22 of transistor 50, contacts 58 physically and electrically coupled in dielectric layers 34 and 55 to semiconductor layer 32 of transistors 48 and 50, and contacts 60 physically and electrically coupled in dielectric layers 34 and 55 to conductor layer 40 shared by capacitors 52 and 54. The contact layer can be formed by intermediate process steps, and semiconductor layers 31, 32, gate electrode 26, and conductor layer 40 can be silicided.

[0041] In this embodiment, portions of the semiconductor layer 12 located beneath semiconductor layer 31, which are laterally disposed between capacitor 52 and transistor 48 and also between capacitor 54 and transistor 50, are not contacted by contacts within a contact layer. Instead, semiconductor layer 31 and / or the underlying portion of semiconductor layer 12 beneath semiconductor layer 31 are physically and electrically directly coupled to conductor layers 43 and 45 of capacitors 52 and 54.

[0042] Contacts 56, 58, and 60 are coupled to wiring in the back-end stack formed above the contact level. Specifically, contact 56 couples the gate electrode 26 to a word line in the back-end stack, and contact 58 couples the semiconductor layer 32 to a bit line in the back-end stack. A conductor layer 40 shared by capacitors 52 and 54 can be coupled to ground. In one embodiment, the conductor layer 40 shared by capacitors 52 and 54 can be coupled to ground via contact 60. In an alternative embodiment, contact 60 can be omitted, and the conductor layer 40 can be coupled to ground via the semiconductor substrate 16. In another alternative embodiment, contact 60 couples the conductor layer 40 to ground, and the conductor layer 40 can also be coupled to ground via the semiconductor substrate 16.

[0043] The memory device implemented in structure 10 includes transistors 48 and 50, which may be fully depleted silicon-on-insulator (SiI) transistors, and at-pitch capacitors 52 and 54. Each at-pitch capacitor 52 and 54 has a capacitor plate formed by directly abutting or contacting a source / drain region, which includes a portion of semiconductor layer 12 located beneath one of the semiconductor layers 31. Each of the capacitors 52 and 54 includes a shared capacitor plate represented by conductor layer 40 and a shared capacitor dielectric layer represented by dielectric layer 38, and the shared capacitor plate and capacitor dielectric layer are self-aligned to a pulled at-pitch gate structure 20. Transistors 48 and 50, electrically isolated from semiconductor substrate 16 by dielectric layer 14, can be characterized by lower leakage than transistors formed using a bulk substrate.

[0044] refer to Figure 7 Furthermore, according to an alternative embodiment, the dielectric layer 38 may not need to be removed from the bottom of the trench 33 before the conductor layer 40 is formed. As a result, the bottom portion of the conductor layer 40 is coated with a portion of the dielectric layer 38. The trench 33 may also be shallower and not penetrate into the semiconductor substrate 16, since the conductor layer 40 can be grounded via contact 60 instead of through the semiconductor substrate 16.

[0045] refer to Figure 8 According to an alternative embodiment, structure 10 can be deployed in a ferroelectric random access memory device, wherein conductor layer 40 is coupled to plate line (PL) via contact 60. Dielectric layer 38 may include a ferroelectric material characterized by a pair of stable remanent polarization states, which are persistent and reversibly change in response to an electric field applied between the respective capacitor plates of each capacitor 52, 54. This pair of stable remanent polarization states represents binary logic states. In one remanent polarization state, the net polarizations of the ferroelectric material in its grains can be aligned parallel to each other, which provides a low-capacitance state. In the other remanent polarization state, the net polarizations of the ferroelectric material in its grains can be aligned antiparallel to each other, which provides a high-capacitance state. The low-capacitance and high-capacitance states of the remanent polarization states enable different binary logic states. Voltage pulses can be applied from the plate line to conductor layer 43 of each capacitor 52 to switch polarizations between different states. Voltage pulses can be applied from the plate line to conductor layer 45 of each capacitor 54 to switch between different polarization states.

[0046] refer to Figure 9Furthermore, according to an alternative embodiment, structure 10 can be deployed as a ferroelectric memory field-effect transistor, wherein the semiconductor layers 31 adjacent to capacitors 52 and 54 are coupled via contacts 62 to read transistors in a sensing circuit that can be used to sense different capacitance states of capacitors 52 and 54. Contact 58 can couple semiconductor layer 32 to the source line. The ferroelectric memory field-effect transistor can be deployed in circuits used for artificial intelligence or machine learning technologies.

[0047] refer to Figure 10 In an alternative embodiment, conductor layer 40 and dielectric layer 38, as well as another conductor layer 39 similar to conductor layer 40, may be formed beneath dielectric layer 14. Capacitors 52 and 54 share conductor layer 40 as a capacitor plate or electrode, conductor layer 39 as a capacitor plate or electrode, and dielectric layer 38 as a capacitor dielectric layer located between conductor layer 39 and conductor layer 40. Conductor layers 39, 40, and dielectric layer 38 define a horizontal capacitor. Conductor layer 39 may be grounded via semiconductor substrate 16. In an embodiment, conductor layer 40 may be adjacent to dielectric layer 14.

[0048] Each capacitor 52 includes one of the conductor layers 43 that physically and electrically couples the source / drain regions of transistor 48 directly to conductor layer 40, and more specifically, physically and electrically couples the associated semiconductor layer 31 and the underside portion of semiconductor layer 12 of transistor 48 directly to conductor layer 40. Each capacitor 54 includes one of the conductor layers 45 that physically and electrically couples the source / drain regions of transistor 50 directly to conductor layer 40, and more specifically, physically and electrically couples the associated semiconductor layer 31 and the underside portion of semiconductor layer 12 of transistor 50 directly to conductor layer 40. The space within trench 33 may be filled with a dielectric material to electrically isolate conductor layers 43 and 45.

[0049] The methods described above are used to manufacture integrated circuit chips. The resulting integrated circuit chips can be distributed by manufacturers in the form of raw wafers (e.g., as a single wafer with multiple unpackaged chips), as bare dies, or in packages. The chips can be integrated with other chips, discrete circuit elements, and / or other signal processing devices as part of intermediate or final products. The final product can be any product that includes integrated circuit chips, such as a computer product with a central processing unit or a smartphone.

[0050] References to terms modified by approximate language such as “approximately,” “about,” or “substantially” are not limited to the specified exact values ​​or conditions. In embodiments, approximate language may indicate a range of + / -10% of the value or condition.

[0051] The use of terms such as “vertical” and “horizontal” in this document is by way of example rather than limitation, in order to establish a frame of reference. The term “horizontal” as used herein is defined as a plane parallel to the conventional plane of the semiconductor substrate, regardless of its actual three-dimensional spatial orientation. The terms “vertical” and “normal” refer to directions in the frame of reference perpendicular to the horizontal plane just defined. The term “lateral” refers to a direction within the horizontal plane in the frame of reference.

[0052] A feature that is “connected” or “coupled” to or with another feature can be directly connected or coupled to that other feature, or alternatively, one or more intermediate features may exist. If no intermediate feature exists, a feature can be “directly connected” or “directly coupled” to or with another feature. If at least one intermediate feature exists, a feature can be “indirectly connected” or “indirectly coupled” to or with another feature. A feature that is “on” or “in contact” with another feature can be directly on or in direct contact with that other feature, or alternatively, one or more intermediate features may exist. If no intermediate feature exists, a feature can be “directly” on or in direct contact with another feature. If at least one intermediate feature exists, a feature can be “indirectly” on or indirectly in contact with another feature. If a feature extends over and covers a portion of another feature, the different features can “overlap.”

[0053] The description of various embodiments of the present invention is given for illustrative purposes and is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles of the embodiments, their practical application, or technical improvements relative to technologies found in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A structure for a memory device, the structure comprising: The first transistor includes a first gate structure and a first source / drain region; The second transistor includes a second gate structure and a second source / drain region; as well as The first capacitor includes a first capacitor plate directly coupled to the first source / drain region, a second capacitor plate, and a capacitor dielectric layer located between the first capacitor plate and the second capacitor plate.

2. The structure according to claim 1, wherein, The capacitor dielectric layer comprises a ferroelectric material.

3. The structure according to claim 1, wherein, The first capacitor is positioned laterally between the first transistor and the second transistor.

4. The structure according to claim 3 further includes: The second capacitor includes a first capacitor plate directly coupled to the second source / drain region, a second capacitor plate, and a capacitor dielectric layer located between the first capacitor plate and the second capacitor plate.

5. The structure according to claim 4, wherein, The first capacitor and the second capacitor share the second capacitor plate and the capacitor dielectric layer.

6. The structure according to claim 5, wherein, The second capacitor plate includes a portion laterally located between the first capacitor plate of the first capacitor and the first capacitor plate of the second capacitor, the capacitor dielectric layer includes a first portion laterally located between the portions of the first capacitor plate of the first capacitor and the second capacitor plate of the second capacitor, and the capacitor dielectric layer includes a second portion laterally located between the portions of the first capacitor plate of the second capacitor and the second capacitor plate of the second capacitor.

7. The structure according to claim 6, wherein, The portion of the second capacitor plate, the first portion of the capacitor dielectric layer, the second portion of the capacitor dielectric layer, the first capacitor plate of the first capacitor, and the first capacitor plate of the second capacitor are laterally positioned between the first source / drain region and the second source / drain region.

8. The structure according to claim 1, further comprising: A silicon-on-insulator substrate includes a semiconductor substrate, a first dielectric layer on the semiconductor substrate, and a semiconductor layer on the first dielectric layer. The first source / drain region includes a portion of the semiconductor layer.

9. The structure according to claim 8, wherein, The second capacitor plate of the first capacitor and the capacitor dielectric layer of the first capacitor are located in a trench, and the trench includes a first portion located in the semiconductor layer.

10. The structure according to claim 9, wherein, The trench includes a second portion located in the first dielectric layer and a third portion located in the semiconductor substrate, and the second capacitor plate of the first capacitor is in contact with the semiconductor substrate.

11. The structure according to claim 10, further comprising: A second dielectric layer located on the semiconductor layer; as well as A first contact located in the second dielectric layer, the contact being coupled to the second capacitor plate.

12. The structure according to claim 11, wherein, The first source / drain region includes a raised semiconductor layer located on said portion of the semiconductor layer, and the structure further includes: A second contact located in the second dielectric layer, the second contact being coupled to the first source / drain region through the raised semiconductor layer.

13. The structure according to claim 1, further comprising: The second capacitor includes a first capacitor plate directly coupled to the second source / drain region, a second capacitor plate, and a capacitor dielectric layer located between the first capacitor plate and the second capacitor plate.

14. The structure according to claim 13, wherein, The first capacitor and the second capacitor share the second capacitor plate and the capacitor dielectric layer.

15. The structure according to claim 14, wherein, The second capacitor plate has a length, and the first capacitor plate of the second capacitor is spaced apart from the first capacitor plate of the first capacitor along the length of the second capacitor plate.

16. The structure according to claim 15, further comprising: A dielectric spacer surrounding the first gate structure of the first transistor, the dielectric spacer having a first thickness; as well as A dielectric layer is located between the first capacitor plate of the first capacitor and the second capacitor plate of the second capacitor, the dielectric layer having a second thickness substantially equal to the first thickness.

17. A structure for a memory device, the structure comprising: A silicon-on-insulator substrate includes a semiconductor substrate, a dielectric layer on the semiconductor substrate, and a semiconductor layer on the dielectric layer, the dielectric layer being adjacent to the semiconductor substrate along an interface; A transistor, comprising a gate structure and a source / drain region located in the semiconductor layer; A capacitor includes a first capacitor plate, a second capacitor plate, and a capacitor dielectric layer located between the first capacitor plate and the second capacitor plate, which are adjacent to the interface. as well as A conductor layer that extends from the source / drain region through the dielectric layer to the first capacitor plate.

18. The structure according to claim 17, wherein, The capacitor dielectric layer comprises a ferroelectric material.

19. A method of forming a structure for a memory device, the method comprising: A first transistor is formed, comprising a first gate structure and a first source / drain region; A second transistor is formed, comprising a second gate structure and a second source / drain region; as well as A capacitor is formed comprising a first capacitor plate directly coupled to the first source / drain region, a second capacitor plate, and a capacitor dielectric layer located between the first capacitor plate and the second capacitor plate.

20. The method according to claim 19, wherein, The capacitor comprising a first capacitor plate directly coupled to the first source / drain region, a second capacitor plate, and a capacitor dielectric layer located between the first capacitor plate and the second capacitor plate includes: Remove the third gate structure; and The second capacitor plate is formed, and the second capacitor plate includes a portion of the space formed during the removal of the third gate structure. A portion of the capacitor dielectric layer and the first capacitor plate are positioned between the portion of the second capacitor plate and the first source / drain region.

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