Semiconductor memory device

Abstract

A semiconductor memory device includes: a first data storage pattern on a substrate; a second data storage pattern spaced apart from the first data storage pattern in a first direction perpendicular to an upper surface of the substrate; a first bit line between the first and second data storage patterns and extending in a second direction perpendicular to the first direction; a second bit line between the first and second data storage patterns and extending in a second direction; a word line between the first and second bit lines and extending in a third direction perpendicular to the first and second directions; a first active pattern between the first and second bit lines and electrically connected to the first data storage pattern; and a second active pattern between the first and second bit lines and electrically connected to the second data storage pattern.

Description

Technical Field

[0001] This disclosure relates in its entirety to a semiconductor memory device, and more specifically, to a semiconductor memory device including a vertical channel transistor (VCT). Background Technology

[0002] To meet consumer demand for superior performance and low cost, increasing the integration density of semiconductor memory devices is essential. Since the integration density of semiconductor memory devices is a key factor determining product price, exceptionally high integration densities are required.

[0003] The integration density of two-dimensional (2D) or planar semiconductor memory devices is primarily determined by the area occupied by a single memory cell, and is therefore greatly influenced by the level of fine patterning technology. However, while the integration density of 2D semiconductor memory devices is increasing, it remains limited due to the need for extremely expensive equipment to miniaturize the patterns. Therefore, semiconductor memory devices incorporating vertical channel transistors (VCTs) in which the channels extend vertically have been proposed. Summary of the Invention

[0004] This disclosure provides a semiconductor memory device with improved integration density and electrical characteristics.

[0005] However, the aspects of this disclosure are not limited to those set forth herein. These and other aspects of the disclosure will become more apparent to those skilled in the art upon reference to the detailed description of the disclosure given below.

[0006] According to one aspect of this disclosure, a semiconductor memory device is provided, comprising: a first data storage pattern on a substrate; a second data storage pattern spaced apart from the first data storage pattern in a first direction; a first bit line between the first and second data storage patterns and extending in a second direction perpendicular to the first direction; a second bit line between the first and second data storage patterns, extending in the second direction and spaced apart from the first bit line in the first direction; a word line between the first and second bit lines and extending upward in a third direction perpendicular to the first and second directions; a first active pattern between the first and second bit lines and connected to the first data storage pattern; and a second active pattern between the first and second bit lines and connected to the second data storage pattern.

[0007] According to one aspect of this disclosure, a semiconductor memory device is provided, comprising: a first active pattern and a second active pattern on a substrate and including a first surface and a second surface opposite to each other in a first direction, the first surface of the first active pattern and the second active pattern facing the substrate; a first bit line extending in a second direction perpendicular to the first direction and electrically connected to the first surface of the first active pattern; a second bit line extending in the second direction and electrically connected to the second surface of the second active pattern; a first word line extending upward between the first and second bit lines and in a third direction perpendicular to both the first and second directions; a first data storage pattern electrically connected to the second surface of the first active pattern; and a second data storage pattern electrically connected to the first surface of the second active pattern.

[0008] According to one aspect of this disclosure, a semiconductor memory device is provided, comprising: a first data storage pattern on a substrate; a second data storage pattern spaced apart from the first data storage pattern in a first direction; a first active pattern and a second active pattern alternately disposed between the first data storage pattern and the second data storage pattern in a second direction perpendicular to the first direction; a third active pattern and a fourth active pattern alternately disposed in the second direction, wherein the third active pattern is spaced apart from the first active pattern in a third direction perpendicular to both the first and second directions, and the fourth active pattern is spaced apart from the second active pattern in a third direction; a first bit line between the first active pattern and the second data storage pattern and the third active pattern. Between the second active pattern and the third active pattern, an upward line extends in a third direction and is electrically connected to the first active pattern and the third active pattern; a second bit line extends in a third direction between the second active pattern and the first active pattern and between the fourth active pattern and the first active pattern, and is electrically connected to the second active pattern and the fourth active pattern; a first word line extends in a third direction adjacent to the first active pattern and the second active pattern and extends in a second direction; a second word line extends in a third direction adjacent to the third active pattern and the fourth active pattern and extends in a second direction, wherein the first active pattern and the third active pattern are electrically connected to the first active pattern, and the second and fourth active patterns are electrically connected to the second active pattern.

[0009] It should be noted that the effects of this disclosure are not limited to those described above, and other effects of this disclosure will be apparent from the following description.

[0010] However, the aspects, features, and benefits of this disclosure are not limited to those set forth herein. The foregoing and other aspects, features, and benefits of this disclosure will become more apparent to those skilled in the art upon reference to the detailed description of this disclosure given below. Attached Figure Description

[0011] The above and other aspects and features of this disclosure will become more apparent from the detailed description of exemplary embodiments thereof with reference to the accompanying drawings, wherein like reference numerals (when used) indicate corresponding elements in several views, and wherein:

[0012] Figure 1 It is a schematic layout diagram used to illustrate a semiconductor memory device according to some embodiments;

[0013] Figure 2 It is used for explanation Figure 1 A schematic diagram of the positional relationship between the first data storage pattern, the first contact pattern, and the second bit line;

[0014] Figure 3 It is used for explanation Figure 1 A schematic diagram showing the positional relationship between the second data storage pattern, the second contact pattern, and the first line;

[0015] Figure 4 It is along Figure 1 A schematic cross-sectional view of lines AA and BB;

[0016] Figure 5 It is along Figure 1 A schematic cross-sectional view of line CC;

[0017] Figure 6 It is along Figure 1 A schematic cross-sectional view of lines DD and EE;

[0018] Figure 7 yes Figure 4 A magnified schematic cross-sectional view of region P;

[0019] Figure 8 yes Figure 4 A magnified schematic cross-sectional view of region Q;

[0020] Figure 9 This is a schematic diagram illustrating a semiconductor memory device according to some embodiments;

[0021] Figure 10 This is a schematic diagram illustrating a semiconductor memory device according to some embodiments;

[0022] Figures 11 to 13 This is a schematic diagram illustrating a semiconductor memory device according to some embodiments;

[0023] Figure 14 and Figure 15 This is a schematic diagram illustrating a semiconductor memory device according to some embodiments;

[0024] Figure 16These are schematic diagrams illustrating a semiconductor memory device according to some embodiments; and

[0025] Figures 17 to 55 This is a schematic diagram illustrating intermediate steps in a method for manufacturing a semiconductor memory device according to some embodiments. Detailed Implementation

[0026] Figure 1 It is a schematic layout diagram used to illustrate a semiconductor memory device according to some embodiments. Figure 2 It is used for explanation Figure 1 A schematic diagram of the positional relationship between the first data storage pattern, the first contact pattern, and the second bit line. Figure 3 It is used for explanation Figure 1 A schematic diagram showing the positional relationship between the second data storage pattern, the second contact pattern, and the first line. Figure 4 It is along Figure 1 A schematic cross-sectional view of lines AA and BB. Figure 5 It is along Figure 1 A schematic cross-sectional view of the line CC. Figure 6 It is along Figure 1 A schematic cross-sectional view of lines DD and EE. Figure 7 yes Figure 4 A magnified schematic cross-sectional view of region P. Figure 8 yes Figure 4 A magnified schematic cross-sectional view of region Q.

[0027] A semiconductor memory device according to some embodiments may include a memory cell, the memory cell including a vertical channel transistor (VCT).

[0028] Let's refer to each other. Figures 1 to 8 According to some embodiments, a semiconductor memory device may include a first bit line BL1, a second bit line BL2, a first word line WL1, a second word line WL2, a back gate electrode BG, a first active pattern AP1 to a fourth active pattern AP4, a first data storage pattern DSP1, a second data storage pattern DSP2, and a first peripheral gate structure PG1.

[0029] The semiconductor memory device includes a substrate 100, which may be a silicon (Si) substrate or may include other materials such as silicon germanium (SiGe), indium antimonide, lead telluride compound, indium arsenide, indium phosphide, gallium arsenide or gallium antimonide, but this disclosure is not limited thereto.

[0030] Although not explicitly shown, substrate 100 may include a cell array region where data storage patterns DSP1 and DSP2 are disposed, and a peripheral circuit region defined to extend around the cell array region.

[0031] A first device isolation film 101 may be disposed within a substrate 100. The first device isolation film 101 may define an active region within the substrate 100. The first device isolation film 101 includes an insulating material.

[0032] The first peripheral gate structure PG1 may be disposed on the substrate 100. For example, the first peripheral gate structure PG1 may be disposed on the upper surface of the substrate 100. The first peripheral gate structure PG1 may be disposed across the cell array region and the peripheral circuit region. In other words, some of the first peripheral gate structures PG1 may be disposed in the cell array region of the substrate 100, and some of the first peripheral gate structures PG1 may be disposed in the peripheral circuit region of the substrate 100.

[0033] The first peripheral gate structure PG1 may be included in a sensing transistor, a transmission transistor, a driving transistor, etc. For example, the first peripheral gate structure PG1 included in the sensing transistor may be disposed in the cell array region of the substrate 100, but this disclosure is not limited thereto. The type of transistors included in the peripheral circuitry disposed on the cell array region of the substrate 100 may vary depending on the design layout of the semiconductor memory device according to some embodiments.

[0034] The first peripheral gate structure PG1 may include a first peripheral gate insulating film 221, a first peripheral lower conductive pattern 223, and a first peripheral upper conductive pattern 225. The first peripheral gate insulating film 221 may include silicon oxide, silicon oxide nitride, a high-k dielectric material having a dielectric constant higher than that of silicon oxide, or a combination thereof. The high-k dielectric material may include, for example, at least one of metal oxide, metal oxide nitride, metal silicon oxide, or metal silicon oxide nitride, but this disclosure is not limited thereto.

[0035] The lower conductive pattern 223 and the upper conductive pattern 225 of the first periphery include conductive materials. For example, the lower conductive pattern 223 and the upper conductive pattern 225 of the first periphery may include at least one of a doped semiconductor material, a conductive metal nitride, a conductive metal silicon nitride, a metal carbonitride, a conductive metal silicide, a conductive metal oxide, a two-dimensional (2D) material, or a metal. The first peripheral gate structure PG1 is illustrated to include multiple conductive patterns, but this disclosure is not limited thereto. The 2D material may be a metallic material and / or a semiconductor material. The 2D material may include a 2D allotrope or a 2D compound. For example, the 2D material may include at least one of graphene, molybdenum disulfide (MoS2), molybdenum diselenide (MoSe2), tungsten diselenide (WSe2), or tungsten disulfide (WS2), but this disclosure is not limited thereto. In other words, the aforementioned 2D materials are merely examples, and this disclosure is not limited thereto.

[0036] Although not shown, the first peripheral gate structure PG1 may further include a first peripheral gate mask pattern disposed on the first peripheral upper conductive pattern 225. The first peripheral gate mask pattern is formed of an insulating material.

[0037] First and second peripheral lower insulating films 227 and 228 are disposed on the upper surface of substrate 100. First and second peripheral lower insulating films 227 and 228 comprise insulating material.

[0038] The first peripheral contact plug 241a and the first peripheral wiring line 241b may be disposed within the first and second peripheral lower insulating films 227 and 228. The first peripheral contact plug 241a and the first peripheral wiring line 241b may be connected to a first source / drain region disposed on at least one side of the first peripheral gate structure PG1. The term “connection” (or “connecting…” or similar terms such as “contact” or “contacting…”) as may be used herein is intended to refer to a physical and / or electrical connection between two or more elements and may include other intermediate elements. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. Although not shown, the first peripheral contact plug 241a and the first peripheral wiring line 241b may be connected to the conductive patterns (223 and 225) of the first peripheral gate structure PG1. For example, the first peripheral wiring line 241b may be the wiring line closest to the first peripheral gate structure PG1 on a third-direction DR3 perpendicular to the upper surface of the substrate 100.

[0039] The first peripheral contact plug 241a and the first peripheral wiring line 241b are illustrated as different films, but this disclosure is not limited thereto. The boundary between the first peripheral contact plug 241a and the first peripheral wiring line 241b may be indistinguishable. The first peripheral contact plug 241a and the first peripheral wiring line 241b comprise a conductive material.

[0040] The first peripheral upper insulating film 261, the second peripheral upper insulating film 262, the third peripheral upper insulating film 263, and the fourth peripheral upper insulating film 264 can be disposed on the first peripheral contact plug 241a and the first peripheral wiring line 241b. Each of the first peripheral upper insulating film 261, the second peripheral upper insulating film 262, the third peripheral upper insulating film 263, and the fourth peripheral upper insulating film 264 includes insulating material. As shown, a single insulating film can be disposed on the first peripheral contact plug 241a and the first peripheral wiring line 241b, but this disclosure is not limited thereto.

[0041] The first peripheral connection structures (242a and 242b) can be connected to the first peripheral wiring line 241b. The first peripheral connection structures (242a and 242b) may include a first peripheral connection path 242a and a first peripheral connection wire 242b. The first peripheral connection path 242a and the first peripheral connection wire 242b include conductive material.

[0042] The first peripheral connection path 242a and the first peripheral connection wire 242b are illustrated as different films, but this disclosure is not limited thereto. The first peripheral connection structures (242a and 242b) are illustrated as including a plurality of first peripheral connection wires 242b disposed on two different metal layers, but this disclosure is not limited thereto. Alternatively, unlike those illustrated, the first peripheral connection structures (242a and 242b) may include first peripheral connection wires 242b disposed on a single metal layer.

[0043] The fifth outer perimeter upper insulating film 265 may be disposed on the first outer perimeter connecting structure (242a and 242b). The fifth outer perimeter upper insulating film 265 includes insulating material.

[0044] The lower bonding pad BP1 can be disposed on the first peripheral gate structure PG1. The lower bonding pad BP1 can be electrically connected to the first peripheral connection structure (242a and 242b).

[0045] For example, at least one of the lower bonding pads BP1 can be connected to the first peripheral gate structure PG1. At least another of the lower bonding pads BP1 can be connected to a first source / drain region disposed on at least one side of the first peripheral gate structure PG1.

[0046] The lower pad plug BPPG1 can connect the lower bonding pad BP1 and the first peripheral connecting wire 242b. The lower bonding pad BP1 and the lower pad plug BPPG1 can be disposed within the upper insulating film 265 of the fifth peripheral.

[0047] The lower insulating film 271 of the first unit, the lower insulating film 272 of the second unit, and the lower insulating film 273 of the third unit can be disposed on the upper insulating film 265 of the fifth periphery. The lower insulating film 271 of the first unit, the lower insulating film 272 of the second unit, and the lower insulating film 273 of the third unit can be disposed on the lower bonding pad BP1.

[0048] The lower insulating film 272 of the second unit can be disposed between the lower insulating film 271 of the first unit and the lower insulating film 273 of the third unit. The lower insulating film 271 of the first unit can be disposed between the lower insulating film 272 of the second unit and the upper insulating film 265 of the fifth periphery. The lower insulating film 271 of the first unit, the lower insulating film 272 of the second unit, and the lower insulating film 273 of the third unit can include insulating materials.

[0049] The upper bonding pad BP2 can be set on the lower bonding pad BP1. The upper bonding pad BP2 can be set on the fifth peripheral upper insulating film 265.

[0050] The upper bonding pad BP2 can be connected to the lower bonding pad BP1. The upper bonding pad BP2 can contact the lower bonding pad BP1.

[0051] The first unit connection wire 281 may be disposed on the first upper bonding pad BP2. The first unit connection wire 281 may be disposed between the upper bonding pad BP2 and the second data storage pattern DSP2. Although not shown, the first unit connection wire 281 may be electrically connected to at least one of the first bit line BL1, the second bit line BL2, the first word line WL1, or the second word line WL2, which will be described later.

[0052] The first unit connection wire 281, disposed on a single metal layer, is illustrated as being positioned between the upper bonding pad BP2 and the second data storage pattern DSP2, but this disclosure is not limited thereto. Alternatively, the first unit connection wire 281, disposed on different metal layers, may be positioned between the upper bonding pad BP2 and the second data storage pattern DSP2.

[0053] The upper pad plug BPPG2 can electrically connect the upper bonding pad BP2 and the first unit connection wire 281. The upper bonding pad BP2 can be connected to the first unit connection wire 281 through the upper pad plug BPPG2.

[0054] The upper bonding pad BP2 and the upper pad plug BPPG2 can be disposed within the lower insulating film 271 of the first unit. The connecting wire 281 of the first unit can be disposed within the lower insulating film 272 of the second unit.

[0055] The upper pad plug BPPG2 and the lower pad plug BPPG1 may include a conductive material containing metal. The lower bonding pad BP1 and the upper bonding pad BP2 may include a conductive material containing metal. The first unit connecting wire 281 may include a conductive material containing metal.

[0056] The lower bonding pad BP1 and the upper bonding pad BP2 are illustrated as a single membrane, but this disclosure is not limited thereto. The upper pad plug BPPG2 and the lower pad plug BPPG1 are illustrated as a single membrane, but this disclosure is not limited thereto. The first unit connecting wire 281 is illustrated as a single membrane, but this disclosure is not limited thereto.

[0057] A bonding insulating film 267 can be disposed between the lower insulating film 271 of the first unit and the upper insulating film 265 of the fifth periphery. The bonding insulating film 267 can be disposed along the extension line of the interface between the lower bonding pad BP1 and the upper bonding pad BP2. The interface between the lower bonding pad BP1 and the upper bonding pad BP2 can correspond to the boundary between the lower bonding pad BP1 and the upper bonding pad BP2.

[0058] For example, the bonding insulating film 267 may comprise silicon carbonitride. In another example, the bonding insulating film 267 may comprise silicon oxide.

[0059] At the interface between the lower bonding pad BP1 and the upper bonding pad BP2, the width of the lower bonding pad BP1 in the second direction DR2, parallel to the upper surface of the substrate, can be the same as the width of the upper bonding pad BP2 in the second direction DR2. Alternatively, unlike the illustration, at the interface between the lower bonding pad BP1 and the upper bonding pad BP2, the width of the lower bonding pad BP1 in the second direction DR2 can be different from the width of the upper bonding pad BP2 in the second direction DR2.

[0060] At the interface between the lower bonding pad BP1 and the upper bonding pad BP2, the lower bonding pad BP1 may be aligned with the upper bonding pad BP2 on the third direction DR3. Alternatively, unlike the illustration, at the interface between the lower bonding pad BP1 and the upper bonding pad BP2, the lower bonding pad BP1 may be misaligned (i.e., offset) from the upper bonding pad BP2 on the third direction DR3.

[0061] A first data storage pattern DSP1 and a second data storage pattern DSP2 can be disposed on a substrate 100. The first data storage pattern DSP1 can be spaced apart from the second data storage pattern DSP2 on a third-direction DR3. For example, the third-direction DR3 can be a vertical direction perpendicular to the substrate 100.

[0062] For example, a first data storage pattern DSP1 and a second data storage pattern DSP2 can be disposed on the upper bonding pad BP2. A first peripheral gate structure PG1 can be disposed between the second data storage pattern DSP2 and the substrate 100. The second data storage pattern DSP2 can be disposed between the first data storage pattern DSP1 and the first peripheral gate structure PG1.

[0063] like Figure 1 and Figure 2 As shown, the first data storage pattern DSP1 can be arranged in a matrix along the first direction DR1 and the second direction DR2. Figure 1 and Figure 3As shown, the second data storage pattern DSP2 can be arranged in a matrix along the first direction DR1 and the second direction DR2.

[0064] The first direction DR1 and the second direction DR2 can each be perpendicular to the third direction DR3. The first direction DR1 and the second direction DR2 can be horizontal directions parallel to the substrate 100. For example, the first direction DR1 can be perpendicular to the second direction DR2.

[0065] In one example, the first data storage pattern DSP1 and the second data storage pattern DSP2 can be capacitors. The first data storage pattern DSP1 may include a first storage electrode 251 and a first capacitor dielectric film 253 interposed between the first storage electrode 251 and the first plate electrode 255. The second data storage pattern DSP2 may include a second storage electrode 351 and a second capacitor dielectric film 353 interposed between the second storage electrode 351 and the second plate electrode 355. From a planar view (i.e., a planar diagram), the first storage electrode 251 and the second storage electrode 351 can have various shapes, such as circular, elliptical, rectangular, square, rhomboid, or hexagonal.

[0066] The first storage electrode 251, the second storage electrode 351, the first plate electrode 255, and the second plate electrode 355 may include at least one of, for example, a conductive semiconductor material, a conductive metal nitride, a conductive metal silicon nitride, a metal carbonitride, a conductive metal silicide, a conductive metal oxide, or a metal. The first capacitor dielectric film 253 and the second capacitor dielectric film 353 may include at least one of a ferroelectric material, an antiferroelectric material, or a paraelectric material. For example, the first capacitor dielectric film 253 and the second capacitor dielectric film 353 may include one of a ferroelectric material, an antiferroelectric material, a paraelectric material, a combination of a ferroelectric material and an antiferroelectric material, a combination of a ferroelectric material and a paraelectric material, a combination of a paraelectric material and an antiferroelectric material, or a combination of a ferroelectric material, an antiferroelectric material, and a paraelectric material.

[0067] Alternatively, the first data storage pattern DSP1 and the second data storage pattern DSP2 can be variable resistance patterns that can switch between two resistance states based on electrical pulses applied to the respective memory elements. For example, the first data storage pattern DSP1 and the second data storage pattern DSP2 can include phase change materials, perovskite compounds, transition metal oxides, magnetic materials, ferromagnetic materials, or antiferromagnetic materials whose crystallization state changes according to the amount of current.

[0068] Alternatively, for example, the first data storage pattern DSP1 or the second data storage pattern DSP2 may be a capacitor, and another data storage pattern may include a variable resistance pattern that can switch between two resistance states based on an electrical pulse applied to the respective memory element. Alternatively still, for example, the first data storage pattern DSP1 and the second data storage pattern DSP2 may include different types of variable resistance patterns.

[0069] The upper insulating film 274 of the first unit may be disposed on the first data storage pattern DSP1. The upper insulating film 274 of the first unit may cover the first plate electrode 255. The upper insulating film 274 of the first unit comprises an insulating material. As may be used herein, the term "cover" (or similar term) is intended to broadly refer to an element, structure, or layer that is directly on or over another element, structure, or layer, or in the presence of one or more other intermediate elements, structures, or layers therebetween.

[0070] The first active pattern AP1 and the second active pattern AP2 can be disposed between the first data storage pattern DSP1 and the second data storage pattern DSP2. The third active pattern AP3 and the fourth active pattern AP4 can be disposed between the first data storage pattern DSP1 and the second data storage pattern DSP2.

[0071] The first active pattern AP1 and the second active pattern AP2 can be arranged alternately along the second direction DR2. The first active pattern AP1 and the second active pattern AP2 can be spaced apart in the second direction DR2. For example, the first active pattern AP1 and the second active pattern AP2 can be aligned along the second direction DR2.

[0072] The third active pattern AP3 and the fourth active pattern AP4 can be arranged alternately along the second direction DR2. The third active pattern AP3 and the fourth active pattern AP4 can be spaced apart along the second direction DR2. For example, the third active pattern AP3 and the fourth active pattern AP4 can be aligned along the second direction DR2.

[0073] The first active pattern AP1 and the third active pattern AP3 can be arranged alternately along the first direction DR1. The first active pattern AP1 and the third active pattern AP3 can be spaced apart in the first direction DR1. For example, the first active pattern AP1 and the third active pattern AP3 can be aligned along the first direction DR1.

[0074] The second active pattern AP2 and the fourth active pattern AP4 can be arranged alternately along the first direction DR1. The second active pattern AP2 and the fourth active pattern AP4 can be spaced apart in the first direction DR1. For example, the second active pattern AP2 and the fourth active pattern AP4 can be aligned along the first direction DR1.

[0075] The first active pattern AP1, the second active pattern AP2, the third active pattern AP3, and the fourth active pattern AP4 can be arranged in two dimensions along the intersecting first direction DR1 and second direction DR2.

[0076] The first active pattern AP1, the second active pattern AP2, the third active pattern AP3, and the fourth active pattern AP4 can be channel regions. For example, the first active pattern AP1, the second active pattern AP2, the third active pattern AP3, and the fourth active pattern AP4 can be formed from a single-crystal semiconductor material. In one example, the first active pattern AP1, the second active pattern AP2, the third active pattern AP3, and the fourth active pattern AP4 can be formed from single-crystal silicon (Si). The first active pattern AP1, the second active pattern AP2, the third active pattern AP3, and the fourth active pattern AP4 can be Si active patterns.

[0077] The first active pattern AP1, the second active pattern AP2, the third active pattern AP3, and the fourth active pattern AP4 may each have a length in the first direction DR1, a width in the second direction DR2, and a height in the third direction DR3. The first active pattern AP1, the second active pattern AP2, the third active pattern AP3, and the fourth active pattern AP4 may each have a substantially uniform width.

[0078] The widths of the first active pattern AP1, the second active pattern AP2, the third active pattern AP3, and the fourth active pattern AP4 can range from a few nanometers (nm) to tens of nanometers (nm). For example, the widths of the first active pattern AP1, the second active pattern AP2, the third active pattern AP3, and the fourth active pattern AP4 can range from about 1 nm to 30 nm, more preferably from about 1 nm to 10 nm, but this disclosure is not limited thereto. The lengths of the first active pattern AP1 and the second active pattern AP2 can be greater than the linewidth of the first bit line BL1. That is, the lengths of the first active pattern AP1 and the second active pattern AP2 can be greater than the width of the first bit line BL1 in the first direction DR1. The lengths of the third active pattern AP3 and the fourth active pattern AP4 can be greater than the width of the second bit line BL2 in the first direction DR1.

[0079] exist Figure 7 and Figure 8In the first active pattern AP1, there are first surfaces S11 and second surfaces S12 that are opposite to each other on the third-direction DR3. The second active pattern AP2 includes first surfaces S21 and second surfaces S22 that are opposite to each other on the third-direction DR3. The third active pattern AP3 includes first surfaces S31 and second surfaces S32 that are opposite to each other on the third-direction DR3. The fourth active pattern AP4 includes first surfaces S41 and second surfaces S42 that are opposite to each other on the third-direction DR3. The first surface S11 of the first active pattern AP1, the first surface S21 of the second active pattern AP2, the first surface S31 of the third active pattern AP3, and the first surface S41 of the fourth active pattern AP4 may face the substrate 100.

[0080] The first active pattern AP1 includes a first sidewall SS11 and a second sidewall SS12 that are opposite to each other in the second direction DR2. The second active pattern AP2 includes a first sidewall SS21 and a second sidewall SS22 that are opposite to each other in the second direction DR2. The third active pattern AP3 includes a first sidewall SS31 and a second sidewall SS32 that are opposite to each other in the second direction DR2. The fourth active pattern AP4 includes a first sidewall SS41 and a second sidewall SS42 that are opposite to each other in the second direction DR2. The second sidewall SS12 of the first active pattern AP1 may face the second sidewall SS22 of the second active pattern AP2. The second sidewall SS32 of the third active pattern AP3 may face the second sidewall SS42 of the fourth active pattern AP4.

[0081] Although not shown, for example, the first active pattern AP1 and the second active pattern AP2 may include a first doped region adjacent to the first bit line BL1 and a second doped region adjacent to the first contact pattern BC1. The first active pattern AP1 and the second active pattern AP2 may include a first channel region between the first doped region and the second doped region. The first doped region and the second doped region are doped regions within the first active pattern AP1 and the second active pattern AP2. Alternatively, the first active pattern AP1 and the second active pattern AP2 may not include the first doped region or the second doped region. The third active pattern AP3 and the fourth active pattern AP4 may include a third doped region adjacent to the second bit line BL2 and a fourth doped region adjacent to the second contact pattern BC2. The third active pattern AP3 and the fourth active pattern AP4 may include a second channel region between the third doped region and the fourth doped region. Alternatively, the third active pattern AP3 and the fourth active pattern AP4 may not include the third doped region or the fourth doped region.

[0082] During operation of a semiconductor memory device according to some embodiments, the channel regions of the first active pattern AP1 to the fourth active pattern AP4 can be controlled by the first word line WL1, the second word line WL2, and the back gate electrode BG. Since the first active pattern AP1 to the fourth active pattern AP4 are formed of a single-crystal semiconductor material, the leakage current characteristics of the semiconductor memory device according to some embodiments can be improved.

[0083] The first bit line BL1 and the second bit line BL2 can be located between the first data storage pattern DSP1 and the second data storage pattern DSP2. The first bit line BL1 can be located between the second data storage pattern DSP2 and the first active pattern AP1, as well as between the second data storage pattern DSP2 and the second active pattern AP2. The second bit line BL2 can be located between the first data storage pattern DSP1 and the third active pattern AP3, as well as between the first data storage pattern DSP1 and the fourth active pattern AP4.

[0084] The first bit line BL1 can extend in the second direction DR2. Adjacent first bit lines BL1 can be spaced apart in the first direction DR1. The second bit line BL2 can extend in the second direction DR2. Adjacent second bit lines BL2 can be spaced apart in the first direction DR1.

[0085] The first active pattern AP1 to the fourth active pattern AP4 can be disposed between the first bit line BL1 and the second bit line BL2. The first bit line BL1 and the second bit line BL2 can be spaced apart on the third direction DR3, wherein the first active pattern AP1 to the fourth active pattern AP4 are disposed between the first bit line BL1 and the second bit line BL2. From a planar viewpoint, the first bit line BL1 can be disposed on the first direction DR1 between adjacent second bit lines BL2. The first bit line BL1 and the second bit line BL2 can be arranged alternately along the first direction DR1.

[0086] Although not shown, the first bit line BL1 and the second bit line BL2 can extend from the cell array region to the peripheral circuit region. A portion of the first bit line BL1 and a portion of the second bit line BL2 can be located in the peripheral circuit region.

[0087] The first bit line BL1 may include a first semiconductor pattern 161, a first metal pattern 163, and a first bit line mask pattern 165 sequentially stacked on the third-direction DR3. The second bit line BL2 may include a second semiconductor pattern 361, a second metal pattern 363, and a second bit line mask pattern 365 sequentially stacked on the third-direction DR3. Alternatively, unlike what is illustrated, for example, the first bit line BL1 may include the first semiconductor pattern 161 or the first metal pattern 163, and the second bit line BL2 may include the second semiconductor pattern 361 or the second metal pattern 363. Furthermore, alternatively, for example, the first bit line BL1 may not include the first bit line mask pattern 165, and the second bit line BL2 may not include the second bit line mask pattern 365.

[0088] The first bit line BL1 and the second bit line BL2 may include conductive bit lines. The conductive bit lines may include a film formed from a conductive material in the first bit line BL1 or the second bit line BL2. The conductive bit lines of the first bit line BL1 may include a first semiconductor pattern 161 and a first metal pattern 163, and the conductive bit lines of the second bit line BL2 may include a second semiconductor pattern 361 and a second metal pattern 363.

[0089] The first semiconductor pattern 161 and the second semiconductor pattern 361 may include a conductive semiconductor material. The conductive semiconductor material may be, for example, a semiconductor material doped with impurities. The first semiconductor pattern 161 and the second semiconductor pattern 361 may include at least one of polycrystalline silicon, polycrystalline silicon germanium, polycrystalline germanium, amorphous silicon, amorphous silicon germanium, or amorphous germanium.

[0090] The first metal pattern 163 and the second metal pattern 363 may include a conductive material containing a metal. For example, the first metal pattern 163 and the second metal pattern 363 may include at least one of a conductive metal nitride, a conductive metal silicon nitride, a metal carbonitride, a conductive metal silicide, a conductive metal oxide, a 2D material, or a metal.

[0091] The first line mask pattern 165 and the second line mask pattern 365 may include an insulating material. The first line mask pattern 165 and the second line mask pattern 365 may include, for example, silicon nitride or silicon oxide, but this disclosure is not limited thereto.

[0092] The first line spacer 167 can be disposed on the side wall BL1_SW of the first line BL1. The first line spacer 167 can extend along the side wall BL1_SW of the first line BL1 in the second direction DR2. The second line spacer 367 can be disposed on the side wall BL2_SW of the second line BL2. The second line spacer 367 can extend along the side wall BL2_SW of the second line BL2 in the second direction DR2.

[0093] The first line spacer 167 and the second line spacer 367 may include an insulating material. The first line mask pattern 165 and the second line mask pattern 365 may include, for example, silicon nitride or silicon oxide, but this disclosure is not limited thereto.

[0094] The first bit line BL1 can be connected to the first active pattern AP1 and the second active pattern AP2. For example, the first bit line BL1 can be electrically connected to the first active pattern AP1 and the second active pattern AP2. A single first bit line BL1 can be connected to the first active pattern AP1 and the second active pattern AP2, which are alternately arranged along the second direction DR2. The first active pattern AP1 and the second active pattern AP2 are not connected to the second bit line BL2.

[0095] The first surface S11 of the first active pattern AP1 and the first surface S21 of the second active pattern AP2 can face the first bit line BL1. The first surface S11 of the first active pattern AP1 and the first surface S21 of the second active pattern AP2 can be connected to the first bit line BL1. For example, the first surface S11 of the first active pattern AP1 and the first surface S21 of the second active pattern AP2 can be connected to the first semiconductor pattern 161 of the first bit line BL1. Alternatively, unlike the illustration, if the first semiconductor pattern 161 is omitted, the first surface S11 of the first active pattern AP1 and the first surface S21 of the second active pattern AP2 can be connected to the first metal pattern 163.

[0096] The second bit line BL2 can be connected to the third active pattern AP3 and the fourth active pattern AP4. For example, the second bit line BL2 can be electrically connected to the third active pattern AP3 and the fourth active pattern AP4. A single second bit line BL2 can be connected to the third active pattern AP3 and the fourth active pattern AP4, which are arranged alternately along the second direction DR2. The third active pattern AP3 and the fourth active pattern AP4 are not connected to the first bit line BL1.

[0097] The second surface S32 of the third active pattern AP3 and the second surface S42 of the fourth active pattern AP4 can face the second bit line BL2. The second surface S32 of the third active pattern AP3 and the second surface S42 of the fourth active pattern AP4 can be connected to the second bit line BL2. For example, the second surface S32 of the third active pattern AP3 and the second surface S42 of the fourth active pattern AP4 can be connected to the second semiconductor pattern 361 of the second bit line BL2. Alternatively, unlike the illustration, if the second semiconductor pattern 361 is omitted, the second surface S32 of the third active pattern AP3 and the second surface S42 of the fourth active pattern AP4 can be connected to the second metal pattern 363.

[0098] The first contact pattern BC1 can be set between the first data storage pattern DSP1 and the first active pattern AP1. The first contact pattern BC1 can be set between the first data storage pattern DSP1 and the second active pattern AP2. The first active pattern AP1 and the second active pattern AP2 can be set between the first contact pattern BC1 and the first bit line BL1.

[0099] The first contact pattern BC1 can be connected to the first active pattern AP1. The first contact pattern BC1 can be connected to the second active pattern AP2. The first contact pattern BC1 can be connected to the first active pattern AP1 and the first data storage pattern DSP1. The first contact pattern BC1 can be connected to the second active pattern AP2 and the first data storage pattern DSP1.

[0100] The second contact pattern BC2 can be positioned between the second data storage pattern DSP2 and the third active pattern AP3. The second contact pattern BC2 can also be positioned between the second data storage pattern DSP2 and the fourth active pattern AP4. The third active pattern AP3 and the fourth active pattern AP4 can be positioned between the second contact pattern BC2 and the second bit line BL2.

[0101] The second contact pattern BC2 can be connected to the third active pattern AP3. The second contact pattern BC2 can be connected to the fourth active pattern AP4. The second contact pattern BC2 can be connected to the third active pattern AP3 and the second data storage pattern DSP2. The second contact pattern BC2 can be connected to the fourth active pattern AP4 and the second data storage pattern DSP2.

[0102] The first active pattern AP1 and the second active pattern AP2 can be connected to the first data storage pattern DSP1. For example, the first active pattern AP1 and the second active pattern AP2 can be electrically connected to the first data storage pattern DSP1. The first active pattern AP1 and the second active pattern AP2 are not connected to the second data storage pattern DSP2.

[0103] The third active pattern AP3 and the fourth active pattern AP4 can be connected to the second data storage pattern DSP2. For example, the third active pattern AP3 and the fourth active pattern AP4 can be electrically connected to the second data storage pattern DSP2. The third active pattern AP3 and the fourth active pattern AP4 are not connected to the first data storage pattern DSP1.

[0104] The first contact pattern BC1 may be disposed on the first direction DR1 between adjacent second bit lines BL2. The first contact pattern BC1 may be spaced apart on the second direction DR2 between adjacent second bit lines BL2. The first contact pattern BC1 may be arranged on the second direction DR2 between adjacent second bit lines BL2. The first contact pattern BC1 arranged on the second direction DR2 may overlap with the first bit line BL1 on the third direction DR3. The first contact pattern BC1 may overlap with the second bit line BL2 on the first direction DR1. As used herein, "element A overlaps with element B in direction X" (or similar language) means that there is at least one line extending in direction X and intersecting both elements A and B.

[0105] The second contact pattern BC2 can be disposed on the first direction DR1 between adjacent first lines BL1. Between adjacent first lines BL1, the second contact pattern BC2 can be spaced apart on the second direction DR2. Between adjacent first lines BL1, the second contact pattern BC2 can be arranged on the second direction DR2. The second contact pattern BC2 arranged on the second direction DR2 can overlap with the second line BL2 on the third direction DR3. The second contact pattern BC2 can overlap with the first line BL1 on the first direction DR1.

[0106] The first fence pattern 259 can be disposed on the first direction DR1 between adjacent second bit lines BL2. The first fence pattern 259 can be disposed on the second direction DR2 between adjacent first contact patterns BC1. The first fence pattern 259 can separate adjacent first contact patterns BC1.

[0107] The first fence pattern 259 may protrude (i.e., extend) from the second bit spacer 367 in the first direction DR1. The first contact pattern BC1 may be surrounded by the first fence pattern 259 and the second bit spacer 367; that is, the first fence pattern 259 and the second bit spacer 367 may extend around the first contact pattern BC1. As may be used herein, the term “surrounding” (or “around” or similar terms) is intended to broadly refer to an element, structure, or layer that extends, encloses, surrounds, or encloses another element, structure, or layer on all sides, but breaks or gaps may also be present. Thus, for example, a layer of material having voids or gaps may still “surround” another layer it surrounds.

[0108] The second fence pattern 359 can be disposed on the first direction DR1 between adjacent first line BL1. The second fence pattern 359 can be disposed on the second direction DR2 between adjacent second contact patterns BC2. The second fence pattern 359 can separate adjacent second contact patterns BC2.

[0109] The second fence pattern 359 may protrude from the first line spacer 167 in the first direction DR1. The second contact pattern BC2 may be surrounded by the second fence pattern 359 and the first line spacer 167.

[0110] From a planar perspective, the first contact pattern BC1 can be rectangular. From a planar perspective, the second contact pattern BC2 can also be rectangular.

[0111] The first contact pattern BC1 and the second contact pattern BC2 may comprise a conductive material. The first contact pattern BC1 and the second contact pattern BC2 may comprise, for example, at least one of doped polycrystalline silicon, conductive metal nitride, conductive metal silicon nitride, metal carbonitride, conductive metal silicide, conductive metal oxide, 2D material, or metal. The first contact pattern BC1 and the second contact pattern BC2 are illustrated as a single film, but this disclosure is not limited thereto. Alternatively, unlike what is illustrated, the first contact pattern BC1 and the second contact pattern BC2 may have a multi-conductive film structure composed of multiple conductive films.

[0112] The first fence pattern 259 and the second fence pattern 359 may include insulating material.

[0113] The first contact pattern BC1 may include a first surface BC1_S1 and a second surface BC1_S2 opposite to each other on the third-direction DR3. The first surface BC1_S1 of the first contact pattern BC1 may be connected to a first active pattern AP1 or a second active pattern AP2. The second surface BC1_S2 of the first contact pattern BC1 may be connected to a first data storage pattern DSP1. For example, the second surface BC1_S2 of the first contact pattern BC1 may be connected to a first storage electrode 251.

[0114] The second surface S12 of the first active pattern AP1 and the second surface S22 of the second active pattern AP2 can face the first contact pattern BC1. The second surface S12 of the first active pattern AP1 and the second surface S22 of the second active pattern AP2 can be connected to the first contact pattern BC1. Since the first contact pattern BC1 is connected to the first data storage pattern DSP1, the first data storage pattern DSP1 can be connected to the second surface S12 of the first active pattern AP1 or the second surface S22 of the second active pattern AP2.

[0115] The second contact pattern BC2 may include a first surface BC2_S1 and a second surface BC2_S2 opposite to each other on the third-direction DR3. The first surface BC2_S1 of the second contact pattern BC2 may be connected to the third active pattern AP3 or the fourth active pattern AP4. The second surface BC2_S2 of the second contact pattern BC2 may be connected to the second data storage pattern DSP2. For example, the second surface BC2_S2 of the second contact pattern BC2 may be connected to the second storage electrode 351.

[0116] The first surface S31 of the third active pattern AP3 and the first surface S41 of the fourth active pattern AP4 can face the second contact pattern BC2. The first surface S31 of the third active pattern AP3 and the first surface S41 of the fourth active pattern AP4 can be connected to the second contact pattern BC2. Since the second contact pattern BC2 is connected to the second data storage pattern DSP2, the second data storage pattern DSP2 can be connected to the first surface S31 of the third active pattern AP3 or the first surface S41 of the fourth active pattern AP4.

[0117] The first fence pattern 259 may include an upper surface 259_US facing the first data storage pattern DSP1. The second fence pattern 359 may include a lower surface 359_BS facing the second data storage pattern DSP2. The upper surface 259_US of the first fence pattern 259 may be coplanar with the second surface BC1_S2 of the first contact pattern BC1. The lower surface 359_BS of the second fence pattern 359 may be coplanar with the second surface BC2_S2 of the second contact pattern BC2.

[0118] A first etch stop film 257 may be disposed between the first contact pattern BC1 and the first data storage pattern DSP1, and between the second bit line BL2 and the first data storage pattern DSP1. A second etch stop film 357 may be disposed between the second contact pattern BC2 and the second data storage pattern DSP2, and between the first bit line BL1 and the second data storage pattern DSP2.

[0119] The first storage electrode 251 can penetrate the first etch stop film 257 (i.e., extend therein). The second storage electrode 351 can penetrate the second etch stop film 357. The first etch stop film 257 and the second etch stop film 357 can be formed of an insulating material.

[0120] Since the contact patterns (BC1 and BC2) are disposed between adjacent bit lines (BL1 and BL2) on the first direction DR1, the interconnections between adjacent bit lines (BL1 and BL2) on the first direction DR1 can be reduced. Therefore, the performance and reliability of the semiconductor memory device according to some embodiments can be improved.

[0121] The back gate electrode BG can be disposed between the first bit line BL1 and the second bit line BL2. The back gate electrodes BG can be spaced apart from each other in the second direction DR2. The back gate electrodes BG can be spaced apart at regular intervals. The back gate electrodes BG can extend across the first bit line BL1 and the second bit line BL2 in the first direction DR1.

[0122] The back gate electrode BG can be disposed on the second direction DR2 between a pair of adjacent first active patterns AP1 and second active patterns AP2. The back gate electrode BG can also be disposed on the second direction DR2 between a pair of adjacent third active patterns AP3 and fourth active patterns AP4. In other words, the first active pattern AP1 and the third active pattern AP3 can be disposed on the first side of the respective back gate electrode BG, and the second active pattern AP2 and the fourth active pattern AP4 can be disposed on the second side of the respective back gate electrode BG. The height of the back gate electrode BG on the third direction DR3 can be less than the height of each of the first active patterns AP1 to the fourth active patterns AP4 on the third direction DR3.

[0123] The back gate electrode BG can be disposed between the second sidewall SS12 of the first active pattern AP1 and the second sidewall SS22 of the second active pattern AP2. The back gate electrode BG can be disposed between the second sidewall SS32 of the third active pattern AP3 and the second sidewall SS42 of the fourth active pattern AP4. The back gate electrode BG can also be disposed on the second sidewall SS12 of the first active pattern AP1, the second sidewall SS22 of the second active pattern AP2, the second sidewall SS32 of the third active pattern AP3, and the second sidewall SS42 of the fourth active pattern AP4.

[0124] The first active pattern AP1 and the third active pattern AP3 can be disposed between the first word line WL1 and the adjacent back gate electrode BG in the second direction DR2. The second active pattern AP2 and the fourth active pattern AP4 can be disposed between the second word line WL2 and the adjacent back gate electrode BG in the second direction DR2. A pair of first word lines WL1 and second word lines WL2 can be disposed between a pair of adjacent back gate electrodes BG in the second direction DR2.

[0125] The back gate electrode BG may include a first surface BG_S1 and a second surface BG_S2 opposite to each other on a third-direction DR3. The first surface BG_S1 of the back gate electrode BG may face the first bit line BL1. The second surface BG_S2 of the back gate electrode BG may face the second bit line BL2.

[0126] The back gate electrode (BG) may include a conductive material, such as at least one of conductive semiconductor materials, conductive metal nitrides, conductive metal silicon nitrides, metal carbonitrides, conductive metal silicides, conductive metal oxides, 2D materials, or metals.

[0127] During operation of a semiconductor memory device according to some embodiments, a voltage can be applied to the back gate electrode BG, thereby allowing adjustment of the threshold voltage of the VCT. By adjusting the threshold voltage of the VCT, degradation of leakage current characteristics can be prevented or at least reduced.

[0128] The back gate isolation pattern 111 and the back gate cover pattern 115 can be disposed on the second direction DR2 between a pair of adjacent first active patterns AP1 and second active patterns AP2. The back gate isolation pattern 111 and the back gate cover pattern 115 can also be disposed on the second direction DR2 between a pair of adjacent third active patterns AP3 and fourth active patterns AP4. The back gate isolation pattern 111 and the back gate cover pattern 115 can extend parallel to the back gate electrode BG on the first direction DR1.

[0129] The back gate isolation pattern 111 can be disposed on the corresponding second surface BG_S2 of the back gate electrode BG. The back gate cover pattern 115 can be disposed on the corresponding first surface BG_S1 of the back gate electrode BG.

[0130] The back gate isolation pattern 111 and the back gate cover pattern 115 may be formed of an insulating material. For example, the back gate isolation pattern 111 and the back gate cover pattern 115 may include silicon oxide, silicon oxide nitride, or silicon nitride, but this disclosure is not limited thereto.

[0131] The back gate insulating pattern 113 can be disposed on the second direction DR2 between the back gate electrode BG and the first active pattern AP1, and between the back gate electrode BG and the second active pattern AP2. The back gate insulating pattern 113 can also be disposed on the second direction DR2 between the back gate electrode BG and the third active pattern AP3, and between the back gate electrode BG and the fourth active pattern AP4.

[0132] A back gate insulating pattern 113 may be disposed on the second direction DR2 between the back gate isolation pattern 111 and the first active pattern AP1, and between the back gate isolation pattern 111 and the second active pattern AP2. The back gate insulating pattern 113 may also be disposed on the second direction DR2 between the back gate isolation pattern 111 and the third active pattern AP3, and between the back gate isolation pattern 111 and the fourth active pattern AP4. The back gate insulating pattern 113 may extend on the third direction DR3 on the second sidewall SS12 of the first active pattern AP1, the second sidewall SS22 of the second active pattern AP2, the second sidewall SS32 of the third active pattern AP3, and the second sidewall SS42 of the fourth active pattern AP4.

[0133] The back gate insulating pattern 113 can be formed of an insulating material. The back gate insulating pattern 113 may include, for example, a silicon oxide film, a silicon oxide nitride film, a high-k dielectric film having a higher dielectric constant than silicon oxide, or a combination thereof.

[0134] The first character line WL1 and the second character line WL2 can be positioned between the first position line BL1 and the second position line BL2. The first character line WL1 and the second character line WL2 can extend along the first direction DR1. The first character line WL1 and the second character line WL2 can be arranged alternately along the second direction DR2.

[0135] The first character line WL1 can be adjacent to the first active pattern AP1 and the third active pattern AP3. The first character line WL1 can be located on the first sidewall SS11 of the first active pattern AP1 and the first sidewall SS31 of the third active pattern AP3. The second character line WL2 can be adjacent to the second active pattern AP2 and the fourth active pattern AP4. The second character line WL2 can be located on the first sidewall SS21 of the second active pattern AP2 and the first sidewall SS41 of the fourth active pattern AP4.

[0136] The first character line WL1 may not be set on the second sidewall SS12 of the first active pattern AP1 or the second sidewall SS32 of the third active pattern AP3. The second character line WL2 may not be set on the second sidewall SS22 of the second active pattern AP2 or the second sidewall SS42 of the fourth active pattern AP4.

[0137] The first active pattern AP1 and the second active pattern AP2 can be disposed on the second direction DR2 between a pair of adjacent first word lines WL1 and second word lines WL2. The third active pattern AP3 and the fourth active pattern AP4 can be disposed on the second direction DR2 between a pair of adjacent first word lines WL1 and second word lines WL2.

[0138] The first character line WL1 and the second character line WL2 may be spaced apart from the first character line BL1 and the second character line BL2 on the third direction DR3. The first character line WL1 and the second character line WL2 may be spaced apart from the first contact pattern BC1 and the second contact pattern BC2 on the third direction DR3. The first character line WL1 and the second character line WL2 may be located between the first character line BL1 and the first contact pattern BC1, and between the second character line BL2 and the second contact pattern BC2.

[0139] The first character line WL1 and the second character line WL2 can each have a width in the second direction DR2. For example, the first character line WL1 and the second character line WL2 can include a first part WLa and a second part WLb, such as... Figure 1 As shown. The width of the first portion WLa in the second direction DR2 can be smaller than the width of the second portion WLb in the second direction DR2. In one example, the first portion WLa of the word lines (WL1 and WL2) can be set on the bit lines (BL1 and BL2). The second portion WLb of the word lines (WL1 and WL2) can be set in the first direction DR1 between a pair of adjacent first active patterns AP1 and third active patterns AP3, or in the first direction DR1 between a pair of adjacent second active patterns AP2 and fourth active patterns AP4.

[0140] The first word line WL1 and the second word line WL2 may include a first portion WLa and a second portion WLb arranged alternately along a first direction DR1. In the first word line WL1, a first active pattern AP1 and a third active pattern AP3 may be disposed on the first direction DR1 between the second portions WLb of adjacent word lines (WL1 and WL2). In the second word line WL2, a second active pattern AP2 and a fourth active pattern AP4 may be disposed on the first direction DR1 between the second portions WLb of adjacent word lines (WL1 and WL2).

[0141] Each of the first word line WL1 and the second word line WL2 may include a first surface WL_S1 and a second surface WL_S2 opposite to each other on a third-party direction DR3. The respective first surface WL_S1 of the first word line WL1 and the respective first surface WL_S1 of the second word line WL2 may face the first bit line BL1. The respective second surface WL_S2 of the first word line WL1 and the respective second surface WL_S2 of the second word line WL2 may face the second bit line BL2.

[0142] For example, the height of the first word line WL1 on the third-direction DR3 can be equal to the height of the back gate electrode BG on the third-direction DR3. In another example, the height of the first word line WL1 on the third-direction DR3 can be greater than the height of the back gate electrode BG on the third-direction DR3. In yet another example, the height of the first word line WL1 on the third-direction DR3 can be less than the height of the back gate electrode BG on the third-direction DR3.

[0143] For example, the upper surface of the first word line BL1 can be a surface connected to the first surface S11 of the first active pattern AP1 and the first surface S21 of the second active pattern AP2. For example, relative to the upper surface of the first word line BL1 as a reference, the height of the first surface WL_S1 of the first word line WL1 can be equal to the height of the first surface BG_S1 of the back gate electrode BG on the third direction DR3. In another example, relative to the upper surface of the first word line BL1, the first surface WL_S1 of the first word line WL1 can be higher than the first surface BG_S1 of the back gate electrode BG on the third direction DR3. In yet another example, relative to the upper surface of the first word line BL1, the first surface WL_S1 of the first word line WL1 can be lower than the first surface BG_S1 of the back gate electrode BG on the third direction DR3.

[0144] Additionally, for example, relative to the upper surface of the first word line BL1 used as a reference, the height of the second surface WL_S2 of the first word line WL1 on the third direction DR3 can be equal to the height of the second surface BG_S2 of the back gate electrode BG. In another example, relative to the upper surface of the first word line BL1, the second surface WL_S2 of the first word line WL1 can be higher than the second surface BG_S2 of the back gate electrode BG on the third direction DR3. In yet another example, relative to the upper surface of the first word line BL1, the second surface WL_S2 of the first word line WL1 can be lower than the second surface BG_S2 of the back gate electrode BG on the third direction DR3.

[0145] Each of the first surfaces WL_S1 of the first word line WL1 and WL_S1 of the second word line WL2 may be planar, but this disclosure is not limited thereto. Each of the second surfaces WL_S2 of the first word line WL1 and WL_S2 of the second word line WL2 may be planar, but this disclosure is not limited thereto. Each of the first surfaces BG_S1 and BG_S2 of the back gate electrode BG is illustrated as planar, but this disclosure is not limited thereto.

[0146] The first word line WL1 and the second word line WL2 may include conductive materials. For example, the first word line WL1 and the second word line WL2 may include at least one of conductive semiconductor materials, conductive metal nitrides, conductive metal silicon nitrides, metal carbonitrides, conductive metal silicides, 2D materials, or metals.

[0147] A first gate insulating pattern GOX1 may be disposed between the first word line WL1 and the first active pattern AP1, and between the first word line WL1 and the third active pattern AP3. The first gate insulating pattern GOX1 may extend along the first sidewall SS11 of the first active pattern AP1 and the first sidewall SS31 of the third active pattern AP3. The first gate insulating pattern GOX1 may extend parallel to the first word line WL1 in a first direction DR1.

[0148] The second gate insulating pattern GOX2 can be disposed between the second word line WL2 and the second active pattern AP2, and between the second word line WL2 and the fourth active pattern AP4. The second gate insulating pattern GOX2 can extend along the first sidewall SS21 of the second active pattern AP2 and the first sidewall SS41 of the fourth active pattern AP4. The second gate insulating pattern GOX2 can extend parallel to the second word line WL2 in the first direction DR1.

[0149] The first gate insulating pattern GOX1 and the second gate insulating pattern GOX2 may comprise silicon oxide, silicon oxide nitride, a high-k dielectric material having a higher dielectric constant than silicon oxide, or a combination thereof. The high-k dielectric material may comprise, for example, at least one of metal oxide, metal oxide nitride, metal silicon oxide, or metal silicon oxide nitride, but this disclosure is not limited thereto.

[0150] A gate separation pattern GSS can be disposed between the first bit line BL1 and the second bit line BL2. The gate separation pattern GSS can also be disposed on the second direction DR2 between a pair of adjacent first word lines WL1 and WL2. The first word lines WL1 and WL2 can be separated by the gate separation pattern GSS. The gate separation pattern GSS can extend on the first direction DR1 between the first word lines WL1 and WL2.

[0151] The first word line WL1 can be disposed between the gate-separated pattern GSS and the first active pattern AP1, and between the gate-separated pattern GSS and the third active pattern AP3. The second word line WL2 can be disposed between the gate-separated pattern GSS and the second active pattern AP2, and between the gate-separated pattern GSS and the fourth active pattern AP4.

[0152] The gate separation pattern (GSS) can be formed from an insulating material. The gate separation pattern (GSS) is illustrated as a single film, but this disclosure is not limited thereto. Alternatively, unlike the illustration, the gate separation pattern (GSS) may comprise multiple insulating films.

[0153] Figure 9 This is a schematic diagram illustrating a semiconductor memory device according to some embodiments. Figure 10This is a schematic diagram illustrating a semiconductor memory device according to some embodiments. For convenience, it will be described below. Figure 9 and Figure 10 The implementation methods mainly focus on the reference Figures 1 to 8 The differences in the content already described.

[0154] For reference only. Figure 9 It is along Figure 1 A schematic cross-sectional view of lines AA and BB, and Figure 10 It is along Figure 1 A schematic cross-sectional view of line DD.

[0155] refer to Figure 9 Relative to the first surface BC1_S1 of the first contact pattern BC1, the upper surface 259_US of the first fence pattern 259 may be higher than the second surface BC1_S2 of the first contact pattern BC1 on the third direction DR3.

[0156] The upper surface 259_US of the first fence pattern 259 may protrude toward the first data storage pattern DSP1 on the third direction DR3 relative to the second surface BC1_S2 of the first contact pattern BC1.

[0157] Relative to the first surface BC2_S1 of the second contact pattern BC2, the lower surface 359_BS of the second fence pattern 359 may be higher or lower than the second surface BC2_S2 of the second contact pattern BC2 on the third-direction DR3. The lower surface 359_BS of the second fence pattern 359 may protrude toward the second data storage pattern DSP2 on the third-direction DR3 relative to the second surface BC2_S2 of the second contact pattern BC2.

[0158] refer to Figure 1 and Figure 10 The width of the first part WLa of the word lines (WL1 and WL2) in the second direction DR2 can be equal to the width of the second part WLb of the word lines (WL1 and WL2) in the second direction DR2.

[0159] The second gate insulating pattern GOX2 can fill the space between a pair of adjacent second active patterns AP2 and fourth active patterns AP4 on the first direction DR1. The term "fill" (or a similar term) is intended to mean either completely filling the defined space (e.g., the space between adjacent second active patterns AP2 and fourth active patterns AP4) or partially filling the defined space; that is, the defined space does not need to be completely filled, but may, for example, be partially filled or always have gaps or other spaces. Although not explicitly shown, however... Figure 4 and Figure 5The first gate insulating pattern GOX1 can similarly fill the space between the pair of adjacent first active patterns AP1 and third active patterns AP3 on the first direction DR1.

[0160] Figures 11 to 13 This is a schematic diagram illustrating a semiconductor memory device according to some embodiments. For convenience, it will be described below. Figures 11 to 13 The implementation methods mainly focus on the reference Figures 1 to 8 The differences in the content already described.

[0161] For reference only. Figure 11 It is along Figure 1 A schematic cross-sectional view of lines AA and BB. Figure 12 It is along Figure 1 A schematic cross-sectional view of the line CC, and Figure 13 It is along Figure 1 A schematic cross-sectional view of lines DD and EE.

[0162] refer to Figures 11 to 13 According to some embodiments, the semiconductor memory device may further include a peripheral active substrate 200, a second peripheral gate structure PG2, and a peripheral interconnect through plug 343.

[0163] The first peripheral gate structure PG1, the lower bonding pad BP1, and the upper bonding pad BP2 (see...) Figure 4-6 It is not necessary to set it between the second data storage pattern DSP2 and the substrate 100.

[0164] The upper insulating film 275 of the second unit can be disposed on the upper insulating film 274 of the first unit. The upper insulating film 275 of the second unit may include insulating material.

[0165] The second unit connection path 282a and the second unit connection wire 282b can be disposed on the upper insulating film 274 of the first unit. The second unit connection path 282a and the second unit connection wire 282b can be disposed in the upper insulating film 275 of the second unit. Multiple second unit connection wires 282b disposed at different metal layers are illustrated as being disposed within the upper insulating film 275 of the second unit, but this disclosure is not limited thereto.

[0166] Although not shown, the second unit connecting wire 282b can be electrically connected to at least one of the first bit line BL1, the second bit line BL2, the first word line WL1, or the second word line WL2.

[0167] The second unit connection path 282a and the second unit connection wire 282b may include conductive materials. The second unit connection path 282a and the second unit connection wire 282b are illustrated as different films, but this disclosure is not limited thereto.

[0168] The peripheral active substrate 200 can be disposed on the second unit connection wire 282b. The peripheral active substrate 200 can be spaced apart from the substrate 100 on the third-direction DR3. The second unit connection path 282a and the second unit connection wire 282b can be located between the substrate 100 and the peripheral active substrate 200.

[0169] The peripheral active substrate 200 may include a peripheral semiconductor film 200SL and a peripheral semiconductor isolation film 200SI. For example, the peripheral active substrate 200 may include a plurality of peripheral semiconductor isolation films 200SI.

[0170] The peripheral semiconductor film 200SL may include a semiconductor material. For example, the peripheral semiconductor film 200SL may include at least one of silicon, silicon germanium, indium antimonide, lead telluride compound, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide, but this disclosure is not limited thereto. The peripheral semiconductor film 200SL will be described below as a silicon film comprising silicon.

[0171] The peripheral semiconductor isolation film 200SI may include an insulating material. The peripheral semiconductor isolation film 200SI is illustrated as a single film, but this disclosure is not limited thereto.

[0172] The peripheral active substrate 200 may include a first surface 200_S1 and a second surface 200_S2 that are opposite to each other on the third-direction DR3. The first surface 200_S1 of the peripheral active substrate 200 may face the substrate 100 and the second cell connection wire 282b.

[0173] The first surface 200_S1 and the second surface 200_S2 of the peripheral active substrate 200 may respectively include a peripheral semiconductor film 200SL and a peripheral semiconductor isolation film 200SI. In other words, the first surface 200_S1 and the second surface 200_S2 of the peripheral active substrate 200 may be defined by the peripheral semiconductor film 200SL and the peripheral semiconductor isolation film 200SI, respectively.

[0174] The second device isolation film 201 can be disposed within the peripheral semiconductor film 200SL. The second device isolation film 201 can be formed on the second surface 200_S2 of the peripheral active substrate 200. The second device isolation film 201 may not extend onto the first surface 200_S1 of the peripheral active substrate 200 on the third-direction DR3. The thickness of the second device isolation film 201 on the third-direction DR3 can be less than the thickness of the peripheral semiconductor isolation film 200SI on the third-direction DR3. The second device isolation film 201 may include an insulating material.

[0175] The second peripheral gate structure PG2 can be disposed on the peripheral semiconductor film 200SL. The second peripheral gate structure PG2 can be disposed on the second surface 200_S2 of the peripheral active substrate 200.

[0176] The second peripheral gate structure PG2 may include a second peripheral gate insulating film 321, a second peripheral lower conductive pattern 323, and a second peripheral upper conductive pattern 325. The second peripheral gate insulating film 321 may include silicon oxide, silicon nitride, a high-k dielectric material having a dielectric constant higher than that of silicon oxide, or a combination thereof. The second peripheral lower conductive pattern 323 and the second peripheral upper conductive pattern 325 may include at least one of a doped semiconductor material, a conductive metal nitride, a conductive metal silicon nitride, a metal carbonitride, a conductive metal silicide, a conductive metal oxide, a 2D material, or a metal. The second peripheral gate structure PG2 is illustrated to include multiple conductive patterns, but this disclosure is not limited thereto.

[0177] The third lower peripheral insulating film 327 and the fourth lower peripheral insulating film 328 can be disposed on the second surface 200_S2 of the peripheral active substrate 200. The third lower peripheral insulating film 327 and the fourth lower peripheral insulating film 328 may include insulating materials.

[0178] The second peripheral contact plug 341a and the second peripheral wire 341b can be disposed within the third peripheral lower insulating film 327 and the fourth peripheral lower insulating film 328. The second peripheral contact plug 341a and the second peripheral wire 341b can be disposed on the second surface 200_S2 of the peripheral active substrate 200.

[0179] The second peripheral contact plug 341a and the second peripheral conductor 341b can be connected to a first source / drain region disposed on at least one side of the second peripheral gate structure PG2. Although not explicitly shown, the second peripheral contact plug 341a and the second peripheral conductor 341b can be connected to the conductive patterns (323 and 325) of the second peripheral gate structure PG2. For example, the second peripheral conductor 341b can be the conductor on the third-direction DR3 closest to the second peripheral gate structure PG2.

[0180] The second peripheral contact plug 341a and the second peripheral conductor 341b are illustrated as different films, but this disclosure is not limited thereto. The second peripheral contact plug 341a and the second peripheral conductor 341b may include conductive materials.

[0181] The peripheral connection through plug 343 can be disposed between the second peripheral conductor 341b and the second unit connecting conductor 282b. The peripheral connection through plug 343 can connect the second peripheral conductor 341b and the second unit connecting conductor 282b.

[0182] The peripheral connection through-hole plug 343 may penetrate the peripheral active substrate 200 on the third-direction DR3 (i.e., extend in the peripheral active substrate 200). For example, the peripheral connection through-hole plug 343 may penetrate the peripheral semiconductor isolation film 200SI.

[0183] The peripheral connecting plug 343 may include a conductive material.

[0184] The sixth, seventh, and eighth peripheral upper insulating films 276, 277, and 278 may be disposed on the second peripheral contact plug 341a and the second peripheral conductor 341b. These films may comprise insulating material. Alternatively, unlike the illustration, a single insulating film may be disposed on the second peripheral contact plug 341a and the second peripheral conductor 341b.

[0185] The second peripheral connection structures (342a and 342b) can be connected to the second peripheral wire 341b. The second peripheral connection structures (342a and 342b) may include a second peripheral connection path 342a and a second peripheral connection wire 342b. The second peripheral connection path 342a and the second peripheral connection wire 342b may include conductive materials.

[0186] The second peripheral connection path 342a and the second peripheral connection wire 342b are illustrated as different membranes, but this disclosure is not limited thereto. The second peripheral connection structures (342a and 342b) are illustrated as including a second peripheral connection wire 342b disposed at a single metal layer, but this disclosure is not limited thereto. Alternatively, unlike those illustrated, the second peripheral connection structures (342a and 342b) may include multiple second peripheral connection wires 342b disposed at two different metal layers.

[0187] Figure 14 and Figure 15 This is a schematic top plan view used to illustrate a semiconductor memory device according to some embodiments. Figure 16 This is a schematic top plan view used to illustrate a semiconductor memory device according to some embodiments. For convenience, it will be described below. Figures 14 to 16 The implementation methods mainly focus on the reference Figures 1 to 8 The differences in the content already described.

[0188] For reference only. Figure 14 and Figure 16 It shows Figure 1 An example positional relationship between the first data storage pattern, the first contact pattern, and the second bit line, and Figure 15 It shows Figure 1The positional relationship between the second data storage pattern, the second contact pattern, and the first line.

[0189] refer to Figure 14 and Figure 15 The first contact pattern BC1 can be circular from a planar perspective.

[0190] From a planar perspective, the second contact pattern BC2 can be circular.

[0191] Alternatively, unlike the illustrations, in one example embodiment, the first contact pattern BC1 and the second contact pattern BC2 may have an elliptical shape when viewed from a planar perspective. In another example embodiment, such as Figure 2 and Figure 3 As shown, the first contact pattern BC1 or the second contact pattern BC2 can be rectangular from a planar perspective.

[0192] refer to Figure 16 If the first data storage pattern DSP1 represented by the first storage electrode 251 is misaligned (i.e. offset) with the first contact pattern BC1 when viewed from a planar perspective (i.e., in the first direction DR1 and / or the second direction DR2).

[0193] Although not explicitly shown, the second data storage pattern DSP2 may be misaligned with the second contact pattern BC2 from a planar view.

[0194] Figures 17 to 55 This is a schematic diagram illustrating an intermediate step in an example method for manufacturing a semiconductor memory device according to some embodiments. This method enables the manufacture of the device referenced above. Figures 1 to 8 The semiconductor memory device described.

[0195] refer to Figures 17 to 19 It can provide a sub-substrate structure including a first sub-substrate 300, a buried insulating layer 301 and an active layer 302.

[0196] A buried insulating layer 301 and an active layer 302 may be provided on the first sub-substrate 300. The first sub-substrate 300, the buried insulating layer 301, and the active layer 302 may form a silicon-on-insulator (SOI) substrate. The first sub-substrate 300 may be a semiconductor substrate. For example, the first sub-substrate 300 may be a silicon substrate, a germanium substrate, and / or a silicon-germanium substrate. The first sub-substrate 300 will be described below as a silicon substrate.

[0197] The buried insulating layer 301 may be a buried oxide (BOX) formed by an implanted oxygen separation (SIMOX) method or a bonding and layer transfer method. Alternatively, the buried insulating layer 301 may be an insulating film formed by chemical vapor deposition (CVD). The buried insulating layer 301 may include, for example, a silicon oxide film, a silicon nitride film, a silicon oxide nitride film, and / or a low dielectric constant (low k) insulating film.

[0198] The active layer 302 may be a single-crystal semiconductor film. The active layer 302 may be, for example, a single-crystal silicon substrate, a germanium substrate, and / or a silicon-germanium substrate. The active layer 302 may have a first surface and a second surface opposite to each other on a third-direction DR3, and the second surface of the active layer 302 may be in contact with the buried insulating layer 301.

[0199] refer to Figures 20 to 22 The mask pattern MP1 can be formed on the active layer 302.

[0200] The mask pattern MP1 may have a linear opening extending in the first direction DR1. The mask pattern MP1 may include a first lower mask film 11 and a first upper mask film 12 sequentially stacked on the third direction DR3. The first upper mask film 12 may be formed of a material having etch selectivity relative to the first lower mask film 11. For example, the first lower mask film 11 may include, but is not limited to, silicon oxide, and the first upper mask film 12 may include, but is not limited to, silicon nitride.

[0201] Subsequently, using mask pattern MP1 as an etching mask, the active layer 302 can be etched anisotropically. As a result, a back gate trench BG_T extending in a first direction DR1 can be formed in the active layer 302. The back gate trench BG_T can expose the buried insulating layer 301 (through the bottom of the back gate trench BG_T) and can be spaced at regular intervals in a second direction DR2. The term "exposed" (or "exposed" or similar terms) may be used herein to describe relationships between elements and / or to refer to intermediate processes in the fabrication of semiconductor devices, but it is not required that a specific element in the completed device be exposed. Similarly, the term "not exposed" may be used to describe relationships between elements and / or to refer to intermediate processes in the fabrication of semiconductor devices, but it is not required that a specific element be not exposed in the completed device.

[0202] Alternatively, unlike the illustration, at least a portion of the buried insulating layer 301 may be removed during the formation of the back gate trench BG_T.

[0203] refer to Figures 23 to 25 The back gate insulating pattern 113 and the back gate electrode BG can be formed within the back gate trench BG_T.

[0204] Specifically, the back gate insulating pattern 113 can be conformally formed along the sidewalls and lower surface of the back gate trench BG_T and along the upper surface of the mask pattern MP1. The term "conformally" (or "conformal" or similar terms) as used herein in the context of a material layer or coating is intended to broadly refer to a material layer or coating having a substantially uniform cross-sectional thickness relative to the contour of the surface to which the material layer is applied. A back gate conductive film can be formed on the back gate insulating pattern 113. The back gate conductive film can fill the back gate trench BG_T. Subsequently, by isotropically etching the back gate conductive film, a back gate electrode BG extending in the first direction DR1 can be formed. The back gate electrode BG can fill a portion of the back gate trench BG_T.

[0205] Additionally, in some embodiments, a gas phase doping (GPD) process or a plasma doping (PLAD) process may be performed before forming the back gate insulating pattern 113. This allows impurities to be doped into the portion of the active layer 302 exposed by the back gate trench BG_T.

[0206] refer to Figures 26 to 28 The back gate isolation pattern 111 can be formed on the back gate electrode BG.

[0207] The back gate isolation pattern 111 can fill other portions of the back gate trench BG_T. If the back gate isolation pattern 111 and the back gate insulating pattern 113 are formed of the same material (e.g., silicon oxide), the back gate insulating pattern 113 can be removed from above the upper surface of the mask pattern MP1 during the formation of the back gate isolation pattern 111.

[0208] Simultaneously, a GPD process or a PLAD process can be performed before the formation of the back gate isolation pattern 111. Thus, impurities can be doped into the active layer 302 by forming the back gate trench BG_T of the back gate electrode BG at that location.

[0209] refer to Figures 29 to 31 After forming the back gate isolation pattern 111, the first upper mask 12 can be removed (see...). Figure 21 and Figure 22 ).

[0210] The back gate isolation pattern 111 may have a shape that extends above the upper surface of the first lower mask 11 on the third-direction DR3.

[0211] Subsequently, a spacer film 120 can be formed along the upper surface of the first lower mask film 11, the sidewalls of the back gate insulating pattern 113, and the upper surface of the back gate isolation pattern 111. The spacer film 120 can be formed with a uniform thickness. The width of the active pattern of the vertical channel transistor can be determined depending on the deposition thickness of the spacer film 120.

[0212] The spacer membrane 120 may be formed of an insulating material. For example, the spacer membrane 120 may include silicon oxide, silicon oxide nitride, silicon nitride, silicon carbide, silicon carbonitride, or a combination thereof.

[0213] refer to Figures 32 to 34 An anisotropic etching process can be performed on the spacer film 120 to form a pair of spacer patterns 121 on the sidewall of each of the back gate insulating patterns 113.

[0214] Using spacer pattern 121 as an etching mask, the active layer 302 (see [reference]) can be etched. Figure 30 An anisotropic etching process is performed. This allows a pair of preliminary active patterns (PAPs) separated from each other to be formed on both sides of each of the back gate insulating patterns 113. As the preliminary active patterns (PAPs) are formed, the buried insulating layer 301 can be exposed.

[0215] The initial active pattern PAP can extend parallel to the back gate electrode BG in the first direction DR1. During the formation of the initial active pattern PAP, word line trenches WL_T can be formed between adjacent initial active patterns PAP in the second direction DR2.

[0216] refer to Figures 35 to 37 A sacrificial film can be formed to fill the word line trench WL_T. A pattern mask can be formed on the sacrificial film. The pattern mask can have a line shape extending in the second direction DR2. Alternatively, the pattern mask can have a line shape extending diagonally relative to both the first direction DR1 and the second direction DR2. Using the pattern mask as an etching mask, the sacrificial film can be etched to form sacrificial openings in the sacrificial film.

[0217] By etching the initial active pattern PAP exposed through the sacrificial opening, a first active pattern AP1, a second active pattern AP2, a third active pattern AP3, and a fourth active pattern AP4 can be formed on both sides of the back gate electrode BG. On the first sidewall of the back gate electrode BG, the first active pattern AP1 and the third active pattern AP3 can be formed alternately along the first direction DR1. On the second sidewall of the back gate electrode BG, the second active pattern AP2 and the fourth active pattern AP4 can be formed alternately along the first direction DR1. When forming the first active patterns AP1 to the fourth active patterns AP4, the sacrificial opening can expose a portion of the back gate insulating pattern 113.

[0218] Subsequently, the sacrificial film, pattern mask, and spacer pattern 121 can be removed. The first lower mask film 11 can remain on the first active patterns AP1 to the fourth active patterns AP4. The buried insulating layer 301 can be exposed.

[0219] Alternatively, unlike the illustration, the first lower mask 11 can be removed to expose the upper surfaces of the first active pattern AP1 to the fourth active pattern AP4.

[0220] refer to Figures 38 to 40 A preliminary gate insulation pattern PGOX can be formed along the sidewalls and lower surface of the word line trench WL_T.

[0221] The initial gate insulating pattern PGOX can be formed along the sidewalls of the first active pattern AP1 to the fourth active pattern AP4 and along the upper surface of the buried insulating layer 301.

[0222] The initial gate insulating pattern PGOX can be formed using at least one of physical vapor deposition (PVD), thermal CVD, low-pressure CVD (LP-CVD), plasma-enhanced CVD (PE-CVD), or atomic layer deposition (ALD) techniques, but this disclosure is not limited thereto.

[0223] Subsequently, a first word line WL1 and a second word line WL2 can be formed on the initial gate insulating pattern PGOX. The first word line WL1 can be formed on the sidewalls of the first active pattern AP1 and the third active pattern AP3. The second word line WL2 can be formed on the sidewalls of the second active pattern AP2 and the fourth active pattern AP4. Alternatively, unlike the illustration, the initial gate insulating pattern PGOX can be etched simultaneously with the formation of the first word line WL1 and the second word line WL2, exposing the buried insulating layer 301.

[0224] Subsequently, a preliminary gate separation pattern GSS_1 can be formed on the first word line WL1 and the second word line WL2. The preliminary gate separation pattern GSS_1 can fill the word line trench WL_T. The upper surface of the preliminary gate separation pattern GSS_1 can be located on the same plane as the upper surface of the back gate isolation pattern 111; that is, the upper surface of the preliminary gate separation pattern GSS_1 can be coplanar with the upper surface of the back gate isolation pattern 111 relative to the surface of the first sub-substrate 300, which serves as the reference layer. During the formation of the preliminary gate separation pattern GSS_1, the first lower mask film 11 can be removed to expose the first active patterns AP1 to the fourth active patterns AP4.

[0225] Alternatively, unlike the above description, the first lower mask 11 can be removed during the formation of the first word line WL1 and the second word line WL2 to expose the first to fourth active patterns AP1, AP2, AP3 and AP4.

[0226] refer to Figures 41 to 43 The second bit line BL2 can be formed on the initial gate separation pattern GSS_1.

[0227] The second bit line BL2 can be formed on the third active pattern AP3 and the fourth active pattern AP4. The second bit line BL2 can also be formed on the first active pattern AP1 and the second active pattern AP2.

[0228] Subsequently, a second position line spacer 367 can be formed along the sidewall of the second position line BL2.

[0229] The first active pattern AP1 and the second active pattern AP2 can be exposed between adjacent second bit lines BL2 on the first direction DR1.

[0230] refer to Figure 44 The initial gate separation pattern GSS_1 (see...) can be used. Figure 42 The first contact film BC1_P is formed on the surface.

[0231] The first contact film BC1_P can be formed between adjacent second bit lines BL2 in the first direction DR1. The first contact film BC1_P can be formed on the first active pattern AP1 and the second active pattern AP2.

[0232] refer to Figures 44 to 47 The first contact film BC1_P can be patterned to form the first contact pattern BC1.

[0233] The first contact pattern BC1 can be formed on the first active pattern AP1 and the second active pattern AP2. The first contact pattern BC1 can be connected to the first active pattern AP1 and the second active pattern AP2.

[0234] The first fence pattern 259 can be formed between adjacent second bit spacers 367 in the first direction DR1. The first fence pattern 259 can be used to pattern the first contact film BC1_P.

[0235] and Figures 44 to 47 Unlike the diagram, a mask film can be formed between adjacent second bit lines BL2 on the first direction DR1. Contact holes can be formed in the mask film. The contact holes can expose the first active pattern AP1 and the second active pattern AP2. Subsequently, a first contact pattern BC1 can be formed in the contact holes. The first contact pattern BC1 can fill the contact holes.

[0236] refer to Figure 48 and Figure 49 A first data storage pattern DSP1 can be formed on the first contact pattern BC1.

[0237] The first data storage pattern DSP1 can be electrically connected to the corresponding first contact pattern BC1.

[0238] An upper insulating film 274 of the first unit can be formed on the first data storage pattern DSP1.

[0239] refer to Figures 48 to 51 The first sub-substrate 300, which forms the back gate electrode BG, word lines (WL1 and WL2), active patterns (AP1 to AP4), second bit line BL2, and first data storage pattern DSP1, can be bonded to the second sub-substrate 400. In one or more embodiments, the second sub-substrate 400 can contact the upper insulating film 274 of the first cell.

[0240] The back gate electrode BG, word lines (WL1 and WL2), active patterns (AP1 to AP4), second bit line BL2, and first data storage pattern DSP1 can be disposed between the first sub-substrate 300 and the second sub-substrate 400.

[0241] In one example, the second sub-substrate 400 may be a semiconductor substrate. In another example, the second sub-substrate 400 may be an insulating substrate comprising an insulating material.

[0242] Subsequently, after bonding the first sub-substrate 300 and the second sub-substrate 400, a back-side polishing process can be performed to remove the first sub-substrate 300.

[0243] Removing the first sub-substrate 300 may involve sequentially performing a polishing process and a wet etching process to expose the buried insulating layer 301.

[0244] Subsequently, the buried insulating layer 301 can be removed to expose the first active patterns AP1 to the fourth active patterns AP4. As the buried insulating layer 301 is removed, portions of the back gate insulating pattern 113 and the preliminary gate insulating pattern PGOX can be exposed.

[0245] refer to Figures 50 to 53 This can remove the exposed portion of the back gate insulating pattern 113.

[0246] As a result, the back gate electrode BG can be exposed. A portion of the exposed back gate electrode BG can be removed by performing an etch-back process. A back gate cap pattern 115 can then be formed on the recessed back gate electrode BG.

[0247] Additionally, the exposed portion of the initial gate insulating pattern PGOX can be removed to form a first gate insulating pattern GOX1 and a second gate insulating pattern GOX2. A portion of the initial gate insulating pattern PGOX can be removed, exposing the first word line WL1 and the second word line WL2. An etch-back process can be performed to remove the exposed portions of the first word line WL1 and the second word line WL2. Insulating material can fill the recessed first word line WL1 and the recessed second word line WL2. As a result, a gate separation pattern GSS can be formed.

[0248] refer to Figure 54 and Figure 55 The first line BL1 can be formed on the first active pattern AP1 and the second active pattern AP2.

[0249] The first line spacer 167 can be formed along the sidewall of the first line BL1.

[0250] Subsequently, a second contact pattern BC2 can be formed on the third active pattern AP3 and the fourth active pattern AP4. A second data storage pattern DSP2 can be formed on the second contact pattern BC2.

[0251] Subsequently, refer to Figure 4 and Figure 6 The upper pad plug BPPG2 and the upper bonding pad BP2 can be formed on the second data storage pattern DSP2.

[0252] Subsequently, the substrate 100, which forms the first peripheral gate structure PG1, the first peripheral connection structure (242a and 242b), the lower bonding pad BP1, and the lower pad plug BPPG1, can be bonded to the second sub-substrate 400.

[0253] The second sub-substrate 400 and the substrate 100 can be bonded using the bonding insulating film 267. Alternatively, unlike the illustration, the second sub-substrate 400 and the substrate 100 can be bonded without the bonding insulating film 267.

[0254] After that, the second sub-substrate 400 can be removed.

[0255] Alternatively, the first sub-substrate 300, which forms the back gate electrode BG, word lines (WL1 and WL2), active patterns (AP1 to AP4), second bit line BL2, and first data storage pattern DSP1 at this location, can be bonded to... Figure 11 and Figure 13 The substrate 100. After removing the first sub-substrate 300, a first line BL1 and a second data storage pattern DSP2 can be formed. After forming the first line BL1 and the second data storage pattern DSP2, a peripheral active substrate 200 and a second peripheral gate structure PG2 can be formed on the second data storage pattern DSP2. Here, the first line BL1 corresponds to Figure 11 and Figure 13 The second bit line BL2, and the second data storage pattern DSP2 corresponds to Figure 11 and Figure 13 The first data storage pattern DSP1. In this case... Figures 17 to 49 The bit lines and data storage patterns formed on the first sub-substrate 300 can correspond to Figure 11 and Figure 13 The first line BL1 and the second data storage pattern DSP2.

[0256] In summarizing the detailed description, those skilled in the art will understand that many variations and modifications can be made to the preferred embodiments without substantially departing from the principles of the inventive concept. Therefore, the preferred embodiments disclosed herein are used only in a general and descriptive sense and not for limiting purposes.

[0257] This application claims priority to Korean Patent Application No. 10-2024-0128960, filed on September 24, 2024, with the Korean Intellectual Property Office.

Claims

1. A semiconductor memory device, comprising: First data storage pattern on the substrate; The second data storage pattern is spaced apart from the first data storage pattern in a first direction perpendicular to the upper surface of the substrate; The first line is located between the first data storage pattern and the second data storage pattern, and extends in a second direction that is parallel to the upper surface of the substrate and perpendicular to the first direction; The second bit line extends in the second direction between the first data storage pattern and the second data storage pattern, and is spaced apart from the first bit line in the first direction; The character line extends upward between the first character line and the second character line, and in a third direction that is parallel to the upper surface of the substrate and perpendicular to the first direction and the second direction. A first active pattern is located between the first bit line and the second bit line, and is electrically connected to the first data storage pattern; as well as A second active pattern is located between the first bit line and the second bit line, and is electrically connected to the second data storage pattern.

2. The semiconductor memory device of claim 1, wherein the first active pattern and the second active pattern are aligned with each other in the third direction.

3. The semiconductor memory device according to claim 2, wherein Each of the first active pattern and the second active pattern includes a first sidewall and a second sidewall that are opposite to each other in the second direction. The character lines are on the first sidewall of the first active pattern and the first sidewall of the second active pattern, and The character line is not on the second sidewall of the first active pattern or the second sidewall of the second active pattern.

4. The semiconductor memory device according to claim 2, further comprising: The back gate electrode is located between the first bit line and the second bit line, and extends upward from the third bit line. The first active pattern and the second active pattern are located between the word line and the back gate electrode.

5. The semiconductor memory device according to claim 1, wherein... The first active pattern is not electrically connected to the second data storage pattern, and The second active pattern is not electrically connected to the first data storage pattern.

6. The semiconductor memory device according to claim 1, wherein The first bit line is electrically connected to the first active pattern and not electrically connected to the second active pattern, and The second bit line is electrically connected to the second active pattern and is not electrically connected to the first active pattern.

7. The semiconductor memory device according to claim 1, further comprising: The contact pattern is located between the first data storage pattern and the first active pattern. The contact pattern overlaps with the second bit line in the third direction and with the first bit line in the first direction.

8. The semiconductor memory device of claim 7, wherein the contact pattern is rectangular when viewed in a plan view.

9. The semiconductor memory device of claim 7, wherein the contact pattern is circular when viewed in a plan view.

10. A semiconductor memory device, comprising: A first active pattern and a second active pattern on a substrate, each of the first active pattern and the second active pattern including a first surface and a second surface opposite to each other in a first direction perpendicular to the upper surface of the substrate, the respective first surface of the first active pattern and the second active pattern facing the substrate; The first bit line extends in a second direction parallel to the upper surface of the substrate and perpendicular to the first direction, and the first bit line is electrically connected to the first surface of the first active pattern. The second bit line extends in the second direction and is electrically connected to the second surface of the second active pattern; The first character line extends upward between the first character line and the second character line and in a third direction that is parallel to the upper surface of the substrate and perpendicular to both the first direction and the second direction. A first data storage pattern is electrically connected to the second surface of the first active pattern; as well as The second data storage pattern is electrically connected to the first surface of the second active pattern.

11. The semiconductor memory device of claim 10, wherein the first active pattern and the second active pattern are aligned with each other in the third direction.

12. The semiconductor memory device of claim 10, further comprising: A third active pattern is spaced apart from the first active pattern in the second direction and electrically connected to the first bit line.

13. The semiconductor memory device of claim 12, wherein the third active pattern is electrically connected to the first data storage pattern and not electrically connected to the second data storage pattern.

14. The semiconductor memory device of claim 12, further comprising: The second line is located between the first active pattern and the third active pattern and extends upward from the third.

15. The semiconductor memory device of claim 10, further comprising: The back gate electrode extends upward between the first bit line and the second bit line and upward from the third bit line. The first active pattern is located between the first word line and the back gate electrode.

16. The semiconductor memory device of claim 10, further comprising: The contact pattern is located between the first data storage pattern and the first active pattern. The contact pattern overlaps with the first bit line in the first direction and with the second bit line in the third direction.

17. The semiconductor memory device of claim 16, further comprising: Bit line spacers extend along the sidewall of the second bit line; as well as The fence pattern extends upward from the bit line spacers on the third side. The bit line spacers and the fence pattern extend around the contact pattern.

18. A semiconductor memory device, comprising: First data storage pattern on the substrate; The second data storage pattern is spaced apart from the first data storage pattern in a first direction perpendicular to the upper surface of the substrate; A first active pattern and a second active pattern are alternately disposed between the first data storage pattern and the second data storage pattern in a second direction that is parallel to the upper surface of the substrate and perpendicular to the first direction; A third active pattern and a fourth active pattern are alternately arranged in the second direction, wherein the third active pattern is spaced apart from the first active pattern in a third direction that is parallel to the upper surface of the substrate and perpendicular to both the first and second directions, and the fourth active pattern is spaced apart from the second active pattern in the third direction. The first line extends upward on the third party between the first active pattern and the second data storage pattern and between the third active pattern and the second data storage pattern, and is electrically connected to the first active pattern and the third active pattern; The second bit line extends upward on the third party between the second active pattern and the first data storage pattern and between the fourth active pattern and the first data storage pattern, and is electrically connected to the second active pattern and the fourth active pattern. The first character line is adjacent to the first active pattern and the second active pattern in the third direction and extends in the second direction; as well as The second character line is adjacent to the third active pattern and the fourth active pattern in the third direction and extends in the second direction. in The first active pattern and the third active pattern are electrically connected to the first data storage pattern, and The second active pattern and the fourth active pattern are electrically connected to the second data storage pattern.

19. The semiconductor memory device of claim 18, wherein, when viewed in a plan view, each of the first bit lines is between two second bit lines that are adjacent to each other in the second direction.

20. The semiconductor memory device of claim 18, further comprising: A peripheral gate structure is located between the substrate and the first data storage pattern.

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