Three-dimensional dynamic random access memory array structure and operation method thereof

Abstract

The invention provides a three-dimensional DRAM (Dynamic Random Access Memory) array structure which comprises L layers, M rows and N columns of DRAM unit structures, and each DRAM unit structure comprises a first transistor, a second transistor and a storage capacitor of a tubular structure, the M * N bit lines respectively extend in a tubular structure jointly formed by the first transistor, the second transistor and the storage capacitor in the M-row N-column DRAM unit structure along the vertical direction, and are respectively connected to second source / drain electrodes of the first transistor and the second transistor; the L * M first word lines and the L * M second word lines extend along the first horizontal direction and are respectively connected to grid electrodes of the first transistors and the second transistors in the L layers of DRAM unit structures; and one or more common bit line groups extending in a second horizontal direction perpendicular to the first horizontal direction, each common bit line group including N common bit lines, a selection transistor for connecting the bit line and the common bit line being disposed above and / or below each of the M * N bit lines.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and more specifically, to a three-dimensional dynamic random access memory (DRAM) array structure and its operation method. Background Technology

[0002] Since Intel Corporation invented Dynamic Random Access Memory (DRAM) in the 1970s, DRAM has been widely used in various computing or control electronic circuit systems.

[0003] A DRAM cell circuit typically consists of a selection transistor for selection and a storage capacitor for storing charge (1T1C structure). In DRAM cell structures using conventional planar horizontal transistors, such as Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs), the source, gate, and drain of the transistor are arranged horizontally parallel to the substrate surface. Because the source, gate, and drain each occupy an independent area in the horizontal direction, the miniaturization of DRAM cell circuit structures is limited by gate length and contact size, failing to meet the demands of continuous miniaturization of DRAM devices, thus restricting further increases in the integration density and bandwidth of DRAM devices.

[0004] Therefore, vertical DRAM cell structures have been proposed in recent years, in which the source, gate, and drain of transistors are arranged vertically perpendicular to the substrate surface, requiring no additional area and facilitating the miniaturization of DRAM array structures. Furthermore, by vertically stacking multiple layers of DRAM cells to form a three-dimensional DRAM array, memory integration density can be further improved.

[0005] DRAM manufacturing is a highly competitive industry. The industry continuously needs to reduce the size of individual cells and increase memory cell density, thereby allowing a single memory chip to hold more memory.

[0006] The information disclosed in this background section is only for understanding the background of the inventive concept and may therefore contain information that does not constitute prior art. Summary of the Invention

[0007] To address the aforementioned problems in the prior art, this disclosure proposes a novel three-dimensional dynamic random access memory (DRAM) array structure and its operation method.

[0008] According to one aspect of this disclosure, a three-dimensional dynamic random access memory (DRAM) array structure is provided, comprising a plurality of DRAM cell structures arranged in L layers, M rows, and N columns, wherein L, M, and N are natural numbers greater than 0. Each of the plurality of DRAM cell structures includes: a first transistor and a second transistor, each having a tubular channel and a gate surrounding the channel, sequentially disposed in a vertical direction and electrically connected in parallel; and a storage capacitor having a tubular structure, disposed in a vertical direction between the first transistor and the second transistor, its inner electrode connected to a first source / drain of the first transistor and the second transistor, and its outer electrode connected to a source line. The DRAM array structure further includes: M×N bit lines extending vertically within a tubular structure formed by the first and second transistors and storage capacitors in the M×N DRAM cell structure, and respectively connected to the second source / drain of the first and second transistors in the M×N DRAM cell structure; L×M first word lines extending along a first horizontal direction and respectively connected to the gates of the first transistors in the L×M DRAM cell structure; L×M second word lines extending along the first horizontal direction and respectively connected to the gates of the second transistors in the L×M DRAM cell structure; and one or more common bit line groups extending along a second horizontal direction perpendicular to the first horizontal direction, each common bit line group including N common bit lines. A selection transistor for connecting the bit lines and common bit lines is disposed above and / or below each of the M×N bit lines.

[0009] According to another aspect of this disclosure, a method is provided for operating a three-dimensional DRAM array structure according to the above aspects of this disclosure, wherein the three-dimensional DRAM array structure includes a common bit line group, wherein each of the N common bit lines included in the common bit line group is connected via a select transistor to a bit line having the same column number in each row of DRAM cell structures, and wherein the gate of the select transistor of each row of DRAM cell structures is connected to a common select line, the method comprising: simultaneously operating N DRAM cell structures in each layer of each row via the N common bit lines.

[0010] According to another aspect of this disclosure, a method is provided for operating a three-dimensional DRAM array structure according to the above aspects of this disclosure, wherein an M-row DRAM cell structure is divided into M / S row groups, where S is a natural number greater than 1 that is divisible by M, each row group has an S-row DRAM cell structure, wherein the first word lines of each layer in each row group are connected by a common first word line, and the second word lines of each row group are connected by a common second word line, wherein the three-dimensional DRAM array structure includes S common bit line groups, each of the N common bit lines included in each of the S common bit line groups is connected by a selection transistor to a bit line having the same row number and the same column number in each row group, and wherein the gate of the selection transistor of the DRAM cell structure of each row group is connected to a common selection line, the method comprising: simultaneously operating S×N DRAM cell structures of each layer in each row group through the S common bit line groups.

[0011] According to another aspect of this disclosure, a method is provided for operating a three-dimensional DRAM array structure according to the above aspects of this disclosure, wherein an M-row DRAM cell structure is divided into M / S row groups, where S is a natural number greater than 1 that divides M, each row group has an S-row DRAM cell structure, wherein each row group is divided into S / T sub-row groups, where T is a natural number greater than 1 that divides S, each sub-row group has a T-row DRAM cell structure, wherein the first word lines of each layer in each row group are connected through a common first word line, and the second word lines of each layer in each row group are connected through a common second word line, wherein the three-dimensional DRAM array structure includes T common bit line groups, each of the N common bit lines included in each of the T common bit line groups is connected through a selection transistor to a bit line having the same row number and the same column number in each sub-row group, and wherein the gate of the selection transistor of the DRAM cell structure of each sub-row group is connected to a common selection line, the method comprising: operating the S×N DRAM cell structures of each layer in each row group stepwise by sub-row groups through the T common bit line groups.

[0012] The DRAM cell structure constituting the DRAM array structure according to this disclosure includes two transistors and a storage capacitor arranged in a vertical direction, wherein the inner electrode of the storage capacitor and the source / drain and channel regions of the two transistors are formed by the same semiconductor material layer, thus having the advantages of simple structure and good switching performance.

[0013] Furthermore, the DRAM array structure according to this disclosure can achieve three-dimensional vertical integration by stacking multiple layers of DRAM cells, thereby increasing integration density. Additionally, the DRAM array structure according to this disclosure can be stacked on a circuit board including multiple circuits, thus enabling system-level three-dimensional vertical integration and significantly reducing the area overhead of the circuit system.

[0014] Furthermore, the DRAM array structure according to this disclosure simplifies word line and bit line configuration by dividing multiple rows of DRAM into row groups. Further, the DRAM array structure according to this disclosure reduces bit line resistance by using selection transistors corresponding to each bit line and grouping the selection transistors according to row groups, thereby improving the overall performance of the DRAM array structure, such as power consumption and speed.

[0015] However, the effects of this disclosure are not limited to those described above, and various extensions can be made without departing from the spirit and scope of this disclosure. It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory, and are intended to provide further illustration of the claimed disclosure. Attached Figure Description

[0016] The accompanying drawings, which are included to provide a further understanding of the present disclosure and are incorporated in and constitute a part of this specification, illustrate exemplary embodiments of the present disclosure and, together with the specification, serve to explain the inventive concept.

[0017] Figure 1 This is an equivalent circuit diagram illustrating a dynamic random access memory (DRAM) cell structure according to an embodiment of the present disclosure.

[0018] Figure 2 This is a perspective view showing a DRAM cell structure according to an embodiment of the present disclosure.

[0019] Figure 3 This is a top view showing a DRAM cell structure according to an embodiment of the present disclosure.

[0020] Figure 4 It shows along Figure 3 The image shows a cross-sectional view of a DRAM cell structure according to an embodiment of the present disclosure, taken by line AA'.

[0021] Figure 5 It shows along Figure 3 The image shows a cross-sectional view of a DRAM cell structure according to an embodiment of the present disclosure, taken from line BB'.

[0022] Figure 6 It shows along Figure 4 The image shows a cross-sectional view of a DRAM cell structure according to an embodiment of the present disclosure, taken by line CC'.

[0023] Figure 7 It shows along Figure 4 The image shows a cross-sectional view of a DRAM cell structure according to an embodiment of the present disclosure, taken by line DD'.

[0024] Figure 8 This illustrates an embodiment according to the present disclosure. Figure 1 The equivalent circuit diagram of the DRAM array structure formed by the DRAM cell structure shown is shown.

[0025] Figure 9 It is shown Figure 8 The diagram shows an equivalent circuit diagram of the DRAM cell structure in the first row of a DRAM array structure according to an embodiment of the present disclosure.

[0026] Figure 10 It is shown Figure 8 The diagram shows a schematic perspective view of the first row of DRAM cells in the first layer of a DRAM array structure according to an embodiment of the present disclosure.

[0027] Figure 11 It is shown Figure 8 The diagram shows a top view of a partial DRAM array structure according to an embodiment of the present disclosure.

[0028] Figure 12 It shows along Figure 11 The image shows a cross-sectional view of a DRAM array structure according to an embodiment of the present disclosure, taken by line AA'.

[0029] Figure 13 It shows along Figure 11 The image shows a cross-sectional view of a DRAM array structure according to an embodiment of the present disclosure, taken from line BB'.

[0030] Figure 14 It shows along Figure 12 The image shows a cross-sectional view of a DRAM array structure according to an embodiment of the present disclosure, taken by line CC'.

[0031] Figure 15 It shows along Figure 12 The image shows a cross-sectional view of a DRAM array structure according to an embodiment of the present disclosure, taken by line DD'.

[0032] Figure 16 This is an equivalent circuit diagram illustrating a DRAM array structure with alternative word line configurations according to an embodiment of the present disclosure.

[0033] Figure 17 This is an equivalent circuit diagram illustrating a DRAM array structure with an alternative configuration of bit lines according to an embodiment of the present disclosure.

[0034] Figure 18 This is an equivalent circuit diagram illustrating a DRAM array structure with alternative configurations of word lines and bit lines according to an embodiment of the present disclosure.

[0035] Figure 19 It is shown in Figure 1 The diagram shows the equivalent circuit diagram of adding a selection transistor to the DRAM cell structure shown.

[0036] Figure 20 It is shown in Figure 4 A cross-sectional view of the selected transistor is added above the DRAM cell structure shown.

[0037] Figure 21 It is shown in Figure 5 A cross-sectional view of the selected transistor is added above the DRAM cell structure shown.

[0038] Figure 22 This is an equivalent circuit diagram illustrating a DRAM array structure with a selectable transistor layer according to an embodiment of the present disclosure.

[0039] Figure 23 This is an equivalent circuit diagram illustrating a DRAM array structure with a selectable transistor layer according to another embodiment of the present disclosure.

[0040] Figure 24A and Figure 24B This is an equivalent circuit diagram showing the first row group in a DRAM array structure having a selectable transistor layer according to an embodiment of the present disclosure.

[0041] Figure 25 It is shown Figure 24A and Figure 24B The timing diagram for the read operation of the DRAM cell structure in the first row shown.

[0042] Figure 26 It is shown Figure 24A and Figure 24B The timing diagram for write operations of the DRAM cell structure in the first row shown.

[0043] Figure 27A and Figure 27B An equivalent circuit diagram of the first row group in a DRAM array structure having a selectable transistor layer according to another embodiment of the present disclosure is shown.

[0044] Figure 28 It is shown Figure 27A and Figure 27B The timing diagram for the read operation of the DRAM cell structure in the first row shown.

[0045] Figure 29 It is shown Figure 27Aand Figure 27B The timing diagram for write operations of the DRAM cell structure in the first row shown. Detailed Implementation

[0046] In the following description, numerous specific details are set forth for illustrative purposes in order to provide a thorough understanding of the various exemplary embodiments of this disclosure. As used herein, “implementation” is a non-limiting example of an apparatus or method employing one or more inventive concepts disclosed herein. However, it will be apparent that the exemplary embodiments may be implemented without these specific details or with one or more equivalent configurations. Furthermore, the exemplary embodiments may be different, but not necessarily exclusive. For example, specific features of other exemplary embodiments may be used or implemented in some exemplary embodiments without departing from the inventive concept.

[0047] Unless otherwise stated, the exemplary embodiments described are to be understood as exemplary features providing details of variations in some ways in which the inventive concept can be implemented in practice. Therefore, unless otherwise stated, the features, components, modules, regions and / or aspects of the various embodiments (hereinafter individually or collectively referred to as “elements”) may be combined, separated, interchanged and / or reconfigured without departing from the inventive concept.

[0048] For the purposes of this disclosure, “at least one of X, Y, and Z” and “at least one selected from the group consisting of X, Y, and Z” can be interpreted as X only, Y only, Z only, or any combination of two or more of X, Y, and Z, such as XYZ, XYY, YZ, and ZZ. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0049] Although terms such as “first” and “second” may be used herein to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. Therefore, without departing from the teachings of this disclosure, the first element discussed below may be referred to as the second element.

[0050] "Logic high" and "logic low" are used to describe the logic voltage of a signal. A signal with a "logic high" is distinguished from a signal with a "logic low". For example, when a signal with a first voltage corresponds to a signal with a "logic high", a signal with a second voltage can correspond to a signal with a "logic low". According to one embodiment, a "logic high" can be set to a voltage higher than a "logic low". According to one embodiment, the logic voltage of a signal can be set to different logic voltages or opposite logic voltages. For example, in some embodiments, a signal with a logic high can be set to a logic low, while in other embodiments, a signal with a logic low can be set to a logic high.

[0051] The terminology used herein is for the purpose of describing particular embodiments and is not intended to be limiting. As used herein, the singular forms “a” and “the” are intended to also include the plural forms unless the context clearly indicates otherwise. Furthermore, when used in this specification, the terms “comprising” and / or “including” mean the presence of the stated features, steps, operations, elements, components, and / or groups thereof, but do not exclude the presence or addition of one or more other features, steps, operations, elements, components, and / or groups thereof. It should also be noted that, as used herein, the terms “substantially,” “about,” and other similar terms are used as approximations rather than terms of degree, and are therefore used to account for inherent deviations in measurements, calculations, and / or values ​​provided that are recognized by those skilled in the art.

[0052] Unless otherwise specified, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. Terms such as those defined in common dictionaries shall be interpreted as having meanings consistent with their meanings in the context of the relevant field and shall not be interpreted in an idealized or overly formal sense, unless expressly defined herein.

[0053] Various embodiments of the present disclosure will now be described more fully below with reference to the accompanying drawings. However, the present disclosure may be implemented in many different ways and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that the disclosure will be exhaustive and complete, and will fully convey the scope of the disclosure to those skilled in the art. The same reference numerals denote the same parts throughout the drawings. Furthermore, in the drawings, parts are not necessarily drawn to scale for clarity, and the scale and dimensions of parts may be enlarged.

[0054] The dynamic random access memory (DRAM) cell structure according to embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings.

[0055] Figure 1 An equivalent circuit diagram of a DRAM cell structure 100 according to an embodiment of the present disclosure is shown.

[0056] like Figure 1 As shown, the DRAM cell structure 100 according to the embodiments of this disclosure can adopt a 2T1C (i.e., two gate transistors and one storage capacitor) cell structure. Specifically, the DRAM cell structure 100 may include two transistors, namely a first transistor T1 and a second transistor T2, which are sequentially disposed in the vertical direction (z direction) and electrically connected in parallel. Both the first and second transistors T1 and T2 may have (see below) Figures 2 to 17 The described channel is a tubular structure and is used as a gate transistor in the DRAM cell structure 100.

[0057] According to an embodiment of this disclosure, the first source / drain S / D11 of the first transistor T1 and the first source / drain S / D21 of the second transistor T2 are commonly connected to one plate (internal electrode) of the memory capacitor C, and the second source / drain S / D12 of the first transistor T1 and the second source / drain S / D22 of the second transistor T2 are commonly connected to the bit line BL. According to an embodiment of this disclosure, the bit line BL can extend in the vertical direction (z-direction). Furthermore, according to an embodiment of this disclosure, the gate G1 of the first transistor T1 can be connected to the first word line WLA, and the gate G2 of the second transistor T2 can be connected to the second word line WLB. According to an embodiment of this disclosure, the first word line WLA and the second word line WLB can extend along a first horizontal direction (y-direction) and overlap in the vertical direction (z-direction). According to an embodiment of this disclosure, the first word line WLA and the second word line WLB can be shorted together. Alternatively, according to an embodiment of this disclosure, the first word line WLA and the second word line WLB can also not be shorted together to control the first transistor T1 and the second transistor T2 separately.

[0058] Furthermore, according to embodiments of this disclosure, the other plate (external electrode) of the storage capacitor C can be connected to the source line SL. Those skilled in the art will recognize that in a DRAM array structure composed of the DRAM cell structure 100 according to this disclosure, the source lines SL of all DRAM cell structures can be connected together commonly or in groups; therefore, the source line SL can also be referred to herein as a "common electrode".

[0059] Figure 2 A perspective view of a DRAM cell structure 100 according to an embodiment of the present disclosure is shown. Figure 3 A top view of a DRAM cell structure 100 according to an embodiment of the present disclosure is shown. Figure 4 It shows along Figure 3The image shows a cross-sectional view of the DRAM cell structure 100 according to an embodiment of the present disclosure, taken by line AA'. Figure 5 It shows along Figure 3 The image shows a cross-sectional view of the DRAM cell structure 100 according to an embodiment of the present disclosure, taken by line BB'. Figure 6 It shows along Figure 4 The image shows a cross-sectional view of the DRAM cell structure 100 according to an embodiment of the present disclosure, taken by line CC'. Figure 7 It shows along Figure 4 The image shows a cross-sectional view of the DRAM cell structure 100 according to an embodiment of the present disclosure, taken by line DD'.

[0060] like Figures 2 to 7 As shown, according to embodiments of this disclosure, the DRAM cell structure 100 may include bit line holes (such as...) extending in the vertical direction (z-direction). Figure 3 , Figure 6 and Figure 7 The hole shown is located at the center and has, for example, a circular cross-section, and a common electrode trench (e.g., extending in the first horizontal direction (y direction) and penetrating the DRAM cell structure 100 in the vertical direction (z direction) is also present. Figure 2 , Figure 3 , Figure 4 , Figure 6 and Figure 7 The slots located on both sides of the central bit line hole are shown.

[0061] like Figures 2 to 7 As shown, according to embodiments of this disclosure, the DRAM cell structure 100 may include conductor lines 109 disposed in bit line holes. The conductor lines 109 extend in the vertical direction (z-direction) and can be used as... Figure 1 The bit line BL of the DRAM cell structure 100 shown. According to embodiments of the present disclosure, the material used to form the conductor line 109 may include tungsten silicide (WSi), tungsten nitride (WN), tungsten (W), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), or combinations thereof. In particular, according to embodiments of the present disclosure, the conductor line 109 may have a cylindrical shape extending in the vertical direction (z-direction). For example, as Figure 3 , Figure 6 and Figure 7 As shown, conductor line 109 can be a cylinder with a first diameter d1.

[0062] like Figures 2 to 7 As shown, according to embodiments of this disclosure, the DRAM cell structure 100 may include a semiconductor material layer 107 with a tubular structure and a first isolation material layer 111 disposed in a bit line hole surrounding a conductor line 109. Specifically, as Figure 4 and Figure 5 As shown more clearly, the upper and lower ends of the semiconductor material layer 107 are in direct contact with the conductor line 109, and the middle portion of the semiconductor material layer 107 is separated from the conductor line 109 by the first insulating material layer 111. In other words, according to embodiments of this disclosure, both the semiconductor material layer 107 and the first insulating material layer 111 have a tubular structure surrounding the conductor line 109. Although in Figure 3 , Figure 6 and Figure 7 In this invention, the tubular structure has a circular cross-section, but this disclosure is not limited to this. Those skilled in the art should recognize that the tubular structure may also have other arbitrary cross-sections, such as elliptical, square or rectangular cross-sections, in which case the cross-sectional shape of the conductor line 109 can be adjusted accordingly.

[0063] According to embodiments of this disclosure, the material used to form the first isolation material layer 111 can be a dielectric material commonly used in integrated circuit processes, such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, glass phosphate, or combinations thereof. According to embodiments of this disclosure, the material used to form the first isolation material layer 111 can also be a low-k material. Low-k materials can have a lower dielectric constant than silicon oxide. Silicon oxide can have a dielectric constant of about 3.9, and the first isolation material layer 111 can include a low-k material having a dielectric constant of about 3.9 or lower. According to embodiments of this disclosure, low-k materials can include porous silicon oxide (SiO2), organosilicon, fluorinated silicon glass (FSG), silsesquioxane (HSQ), silicon carbide (SiCOH), or polymer materials such as parylene and polyimide (PI). According to embodiments of this disclosure, the material used to form the first isolation material layer 111 can also be a combination of the above-mentioned dielectric materials and the above-mentioned low-k materials.

[0064] According to embodiments of this disclosure, the material used to form the semiconductor material layer 107 can be a semiconductor thin film material, such as single-crystal silicon, polycrystalline silicon, amorphous silicon, silicon-germanium compound, compound semiconductor, oxide semiconductor, sulfide semiconductor, graphene, or a combination thereof. According to embodiments of this disclosure, the material used to form the semiconductor material layer 107 can be an oxide semiconductor material, such as indium gallium zinc oxide (IGZO), indium oxide (InO), zinc oxide (ZnO), indium tungsten oxide (InWO), or indium aluminum oxide (InAlO) in different proportions. In particular, according to embodiments of this disclosure, the semiconductor material layer 107 may include a single layer of IGZO or a stack of multiple layers of IGZO in different proportions.

[0065] Furthermore, according to embodiments of this disclosure, as described in more detail below, the semiconductor material layer 107 can be formed as follows: Figure 1The source / drain regions and channel regions of the first transistor T1 and the second transistor T2 are shown, wherein the source / drain regions of the first transistor T1 and the second transistor T2 correspond to the first source / drain S / D11 and the second source / drain S / D12 of the first transistor T1 and the first source / drain S / D21 and the second source / drain S / D22 of the second transistor T2. It should be noted that the source / drain regions described from a structural perspective are equivalent to the source / drain regions described from a circuit perspective. Furthermore, according to embodiments of this disclosure, the semiconductor material layer 107 may also be formed as shown... Figure 1 The internal electrode of the storage capacitor C is shown. Therefore, according to embodiments of this disclosure, the storage capacitor C may also have a tubular structure.

[0066] like Figures 2 to 7 As shown, according to embodiments of the present disclosure, the DRAM cell structure 100 may include two first dielectric layers 106 disposed in bit line vias, respectively surrounding the upper and lower ends of the semiconductor material layer 107. According to embodiments of the present disclosure, the two first dielectric layers 106 may be respectively formed as shown in the diagram. Figure 1 The gate dielectrics of the first transistor T1 and the second transistor T2 are shown. Figure 4 and Figure 5 As shown, according to embodiments of this disclosure, the first dielectric layer 106 may also have a tubular structure with a bent cross-section. In other words, as... Figures 2 to 5 As shown, in a cross-section along the vertical direction (z-direction), the first dielectric layer 106 may have a thinner first portion near the end of the conductor line 109 and a thicker second portion relative to the first portion and away from the end of the conductor line 109. The first and second portions may be connected by a horizontal connecting portion. According to embodiments of this disclosure, the material used to form the first dielectric layer 106 may include, for example, silicon oxide (SiO2), silicon oxynitride (SiON), aluminum oxide (Al2O3), hafnium oxide (HfO2), zirconium oxide (ZrO2), lanthanum oxide (La2O3), or combinations thereof.

[0067] Therefore, according to the embodiments of this disclosure, both the first transistor T1 and the second transistor T2 are formed to have a tubular structure and both have a tubular channel.

[0068] like Figures 2 to 7 As shown, according to embodiments of the present disclosure, the DRAM cell structure 100 may include a lower first gate layer 104 and an upper second gate layer 105 configured to surround a thicker second portion of a lower and upper first dielectric layer 106, respectively. Figure 2 and Figure 6As shown, according to embodiments of the present disclosure, the first gate layer 104 and the second gate layer 105 may have a strip shape with a hole in the middle. According to embodiments of the present disclosure, the first gate layer 104 may correspond to... Figure 1 The first transistor T1 shown has a gate G1, and the second gate layer 105 can correspond to, as shown in the figure. Figure 1 The gate G2 of the second transistor T2 is shown. Furthermore, as... Figure 2 , Figure 3 and Figure 5 As shown, according to an embodiment of this disclosure, the first gate layer 104 may extend in a first horizontal direction (y-direction) to further correspond to, as Figure 1 The first word line WLA is shown, connected to the first gate G1 of the first transistor T1. Accordingly, according to embodiments of this disclosure, the second gate layer 105 may extend in the first horizontal direction (y direction) to further correspond to... Figure 1 The second word line WLB is shown, connected to the gate G2 of the second transistor T2. According to embodiments of this disclosure, the first word line WLA and the second word line WLB can be led out from the distal end in a first horizontal direction (y-direction). For example... Figures 2 to 7 As shown, according to an embodiment of the present disclosure, a first gate layer 104 forms a gate G1 surrounding a channel of a first transistor T1, and a second gate layer 105 forms a gate G2 surrounding a channel of a second transistor T2.

[0069] Therefore, according to embodiments of the present disclosure, the DRAM cell structure 100 may have a bit line BL extending in the vertical direction (z-direction), and a first word line WLA and a second word line WLB extending in the first horizontal direction (y-direction). According to embodiments of the present disclosure, the bit line BL of the DRAM cell structure 100 may extend vertically within a tubular structure formed by the first transistor T1, the second transistor T2, and the storage capacitor C. Furthermore, according to embodiments of the present disclosure, the first gate layer 104 and the second gate layer 105 corresponding to the first word line WLA and the second word line WLB of the DRAM cell structure 100 may overlap in the vertical direction (z-direction).

[0070] Furthermore, according to embodiments of this disclosure, the materials used to form the first gate layer 104 and the second gate layer 105 may include titanium nitride (TiN), tantalum nitride (TaN), aluminum titanium carbide (TiAlC), aluminum (Al), copper (Au), titanium (Ti), palladium (Pd), molybdenum (Mo), platinum (Pt), tungsten (W), doped polycrystalline / amorphous silicon, indium tin oxide (ITO), indium zinc oxide (IZO), or combinations thereof.

[0071] like Figures 2 to 7As shown, according to embodiments of this disclosure, the DRAM cell structure 100 may include two second insulating material layers 103 configured to surround, respectively, a thinner first portion of a first dielectric layer 106 above and below. Figure 2 and Figure 3 As shown, according to embodiments of the present disclosure, the second insulating material layer 103 may have a strip shape with a hole in the middle. According to embodiments of the present disclosure, the material used to form the second insulating material layer 103 may include silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbide (SiCOH), or aluminum oxide (Al2O3). According to embodiments of the present disclosure, the first insulating material layer 111 and the second insulating material layer 103 may be formed of the same or different insulating materials.

[0072] like Figure 4 and Figure 5 As shown, according to embodiments of this disclosure, as described above, the semiconductor material layer 107 along the vertical direction (z-direction) may include the formation indicated by the shaded area. Figure 1 The first portion 1071 of the channel region of the first and second transistors T1 and T2 shown, and the formation between the first portions 1071. Figure 1 The first source / drain region of the first transistor T1 (corresponding to the first source / drain S / D11 of the first transistor T1), the first source / drain region of the second transistor T2 (corresponding to the first source / drain S / D21 of the second transistor T2), and the second portion 1072 of the internal electrode of the memory capacitor C are shown. Therefore, according to an embodiment of this disclosure, the first source / drain S / D11 of the first transistor T1 and the first source / drain S / D21 of the second transistor T2 are connected together with the internal electrode of the memory capacitor C. According to an embodiment of this disclosure, the first portion 1071 and the second portion 1072 of the semiconductor material layer 107 are separated from the conductor line 109 (bit line BL) by a first insulating material layer 111 surrounding the conductor line 109 (bit line BL).

[0073] According to embodiments of this disclosure, the doping type, doping concentration, and / or atomic composition ratio of the second portion 1072 of the semiconductor material layer 107 can be changed through material modification processes such as doping and etching, thereby improving its conductivity as the internal electrode of the memory capacitor C. In other words, according to embodiments of this disclosure, the first portion 1071 and the second portion 1072 of the semiconductor material layer 107 can have different doping types, doping concentrations, and / or atomic composition ratios. According to embodiments of this disclosure, when the semiconductor material layer 107 is an IGZO oxide semiconductor, all or part of the gallium (Ga) atoms in the second portion 1072 can be removed by, for example, etching to improve its conductivity, or part of the oxygen (O) atoms in the second portion 1072 can be removed by, for example, etching to form metal atom interstitials or oxygen atom vacancies to improve its conductivity.

[0074] In addition, such as Figure 4 and Figure 5 As shown, according to embodiments of this disclosure, as described above, the semiconductor material layer 107 may further include, along the vertical direction (z-direction), contact conductor lines 109 at both ends serving as... Figure 1 The diagram shows the third portion 1073 of the second source / drain region of the first transistor T1 (corresponding to the second source / drain S / D12 of the first transistor T1) and the second source / drain region of the second transistor T2 (corresponding to the second source / drain S / D22 of the second transistor T2), and a first horizontal connection portion 1074 connecting the first portion 1071 and the third portion 1073. Therefore, according to an embodiment of this disclosure, the third portion 1073 of the semiconductor material layer 107 contacts the conductor line 109, such that the second source / drain S / D12 of the first transistor T1 and the second source / drain S / D22 of the second transistor T2 corresponding to the third portion 1073 of the semiconductor material layer 107 are connected to the bit line BL corresponding to the conductor line 109.

[0075] like Figure 3 As shown, according to an embodiment of this disclosure, the third portion 1073 of the tubular semiconductor material layer 107 may have a second diameter d2, which is larger than the first diameter d1 of the conductor line 109. Furthermore, as... Figures 3 to 7 As shown, according to an embodiment of the present disclosure, the first portion 1071 and the second portion 1072 of the tubular semiconductor material layer 107 may have a third diameter d3, which is larger than the second diameter d2 of the third portion 1073 of the semiconductor material layer 107.

[0076] like Figures 2 to 7As shown, according to an embodiment of the present disclosure, the DRAM cell structure 100 may include a second dielectric layer 108 disposed in a common electrode trench as a capacitor dielectric for a storage capacitor C. According to an embodiment of the present disclosure, the second dielectric layer 108 may be formed conformally along the trench wall of the common electrode trench. Figure 2 and Figure 4 As shown, according to an embodiment of this disclosure, the second dielectric layer 108 can contact the two second insulating material layers 103, the first gate layer 104, the second gate layer 105, and the second portion of the semiconductor material layer 107 in the second horizontal direction (x direction). Furthermore, as... Figure 2 and Figure 5 As shown, according to an embodiment of this disclosure, the second dielectric layer 108 can contact a second portion of the semiconductor material layer 107 in a first horizontal direction (y-direction). The first horizontal direction, i.e., the y-direction, can be perpendicular to the second horizontal direction, i.e., the x-direction.

[0077] Furthermore, according to embodiments of this disclosure, the material used to form the second dielectric layer 108 can be a high-k material. The high-k material can have a higher dielectric constant than silicon oxide. Silicon oxide can have a dielectric constant of about 3.9, and the second dielectric layer 108 can include a high-k material having a dielectric constant of about 4 or greater. According to embodiments of this disclosure, the high-k material can include hafnium oxide (HfO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), lanthanum oxide (La2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), niobium oxide (Nb2O5), strontium titanium oxide (SrTiO3), or combinations thereof.

[0078] like Figures 2 to 7 As shown, according to an embodiment of the present disclosure, the DRAM cell structure 100 may include an electrode layer 110 extending along the surface of the second dielectric layer 108 and filling a common electrode trench. According to an embodiment of the present disclosure, the electrode layer 110 may correspond to... Figure 1 The external electrode of the storage capacitor C, i.e., the common electrode of the storage capacitor C, and the source line SL are shown. Figures 2 to 7As shown, according to an embodiment of this disclosure, the electrode layer 110 corresponding to the external electrode of the storage capacitor C and the source line SL can extend in a first horizontal direction (y-direction) and penetrate the DRAM cell structure 100 in a vertical direction (z-direction). According to an embodiment of this disclosure, the material used to form the electrode layer 110 may include titanium nitride (TiN), tantalum nitride (TaN), aluminum titanium carbide (TiAlC), aluminum (Al), copper (Au), titanium (Ti), palladium (Pd), molybdenum (Mo), platinum (Pt), tungsten (W), doped polycrystalline / amorphous silicon, indium tin oxide (ITO), indium zinc oxide (IZO), or combinations thereof. Therefore, according to an embodiment of this disclosure, the storage capacitor C of the DRAM cell structure 100 can be formed as a cylindrical capacitor.

[0079] Furthermore, although not shown in the figures, according to embodiments of this disclosure, a third isolation material layer may be provided between the first gate layer 104 and the second gate layer 105 and the second dielectric layer 108 to reduce the parasitic capacitance and leakage current between the external electrode (source line SL) of the storage capacitor and the gates G1 and G2 (i.e., the first and second word lines WLA and WLB) of the first and second transistors T1 and T2.

[0080] The DRAM cell structure constituting the DRAM array structure according to this disclosure includes two transistors and a storage capacitor arranged in a vertical direction, wherein the inner electrode of the storage capacitor and the source / drain and channel regions of the two transistors are formed by the same semiconductor material layer, thus having the advantages of simple structure and good switching performance.

[0081] In particular, this cell structure solves the connection problem between the source and drain of the transistor and the internal electrode of the storage capacitor by using a vertical structure. It is suitable for three-dimensional vertical integration of multi-layer cells. Moreover, the vertical structure is suitable for the one-time processing of multi-layer cells, without the need for multiple epitaxial processes and processing techniques, resulting in low manufacturing costs.

[0082] Figure 8 This illustrates an embodiment according to the present disclosure. Figure 1 The equivalent circuit diagram of the DRAM array structure 200 formed by the DRAM cell structure shown is as follows. Figure 8 As shown, according to an embodiment of this disclosure, by Figure 1 The DRAM array structure 200 formed by the DRAM cell structure shown can be a three-dimensional DRAM array structure stacked in the vertical direction (z direction).

[0083] like Figure 8 As shown, according to embodiments of this disclosure, the DRAM array structure 200 may include, for example: Figure 1Multiple DRAM cell structures 100 are shown. For clarity, certain reference numerals within each DRAM cell structure are omitted. According to embodiments of this disclosure, the multiple DRAM cell structures are arranged in L layers, M rows, N columns, and L layers, where L, M, and N are all natural numbers greater than 0. In this document, each of the multiple DRAM cell structures included in the DRAM array structure 200 can be represented as Clmn, that is, the DRAM cell structure located in the m-th row, n-th column, and l-th layer of the DRAM array structure 200, where m, n, and l are natural numbers, and 1 ≤ m ≤ M, 1 ≤ n ≤ N, and 1 ≤ l ≤ L. Furthermore, in this document, M represents the number of rows of DRAM cell structures in the DRAM array structure 200 along the first horizontal direction (y-direction), N represents the number of columns of DRAM cell structures in the DRAM array structure 200 along the second horizontal direction (x-direction), and L represents the number of layers of DRAM cell structures in the DRAM array structure 200 along the vertical direction (z-direction).

[0084] According to embodiments of this disclosure, the cell selection operation of the plurality of DRAM cell structures included in the DRAM array structure 200 can be performed by L×M first word lines WLA11 to WLALM, L×M second word lines WLB11 to WLBLM, and M×N bit lines BL11 to BLMN.

[0085] Therefore, as Figure 8 As shown, according to the embodiments of this disclosure, in the DRAM array structure 200, each layer of the L-layer DRAM cell structure includes M rows and N columns, totaling M×N DRAM cell structures; each row of the M-row DRAM cell structure includes L layers and N columns, totaling L×N DRAM cell structures; and each column of the N-column DRAM cell structure includes L layers and M rows, totaling L×M DRAM cell structures.

[0086] As mentioned above Figures 1 to 7 As described, each of the plurality of DRAM cell structures included in the DRAM array structure 200 may include: a first transistor and a second transistor, each having a tubular channel and a gate surrounding the channel, arranged sequentially in a vertical direction and electrically connected in parallel; and a storage capacitor having a tubular structure, arranged in a vertical direction between the first transistor and the second transistor, the internal electrode of which is connected to a first source / drain of the first transistor and the second transistor.

[0087] In addition, such as Figure 8As shown, according to an embodiment of the present disclosure, the DRAM array structure 200 may further include M×N bit lines BL11 to BLMN, which extend vertically inside a tubular structure formed by L first transistors, L second transistors, and L storage capacitors in the M-row N-column DRAM cell structure, and are respectively connected to the second source / drain of the L first transistors and L second transistors in the M-row N-column DRAM cell structure.

[0088] Furthermore, although not shown, according to embodiments of this disclosure, in each row of an M-row DRAM array structure, L first word lines WLA1m to WLALm can be respectively connected to L second word lines WLB1m to WLBLm. For example, as Figure 8 As shown, in the first row of the DRAM array structure, the first word line WLA11 can be connected to the second word line WLB11, the first word line WLA21 can be connected to the second word line WLB21, and so on, until the first word line WLAL1 can be connected to the second word line WLBL1. According to an embodiment of this disclosure, in each row of the M-row DRAM array structure, the corresponding connections of L first word lines and L second word lines can be implemented from the remote end outside the array. In this document, since the paired first word lines WLAlm and second word lines WLBlm extending along the first horizontal direction (y direction) can be connected together, they can be collectively referred to as word lines WL and assigned the same number as the corresponding first word line WLAlm and second word line WLBlm, i.e., WLlm. At this time, according to an embodiment of this disclosure, the cell selection operation of the plurality of DRAM cell structures included in the DRAM array structure 200 can be performed by L×M word lines WL11 to WLLM and M×N bit lines BL11 to BLMN.

[0089] Furthermore, according to embodiments of this disclosure, the DRAM array structure 200 may further include L source lines SL corresponding to the L-layer DRAM cell structure, which extend along a first horizontal direction (y-direction) and are respectively connected to the external electrodes of the storage capacitors in the L-layer DRAM cell structure. Additionally, as... Figure 8 As shown, according to an embodiment of this disclosure, L source lines SL can be connected together by a common electrode trench disposed between the bit lines that runs vertically (z-direction) through the entire DRAM array structure 200, while the source lines SL also extend vertically (z-direction). Although not shown, according to an alternative embodiment of this disclosure, the L source lines SL can also be connected together simply outside the DRAM array structure 200, either commonly or in groups, thus omitting the common electrode trench.

[0090] Figure 9 It is shown Figure 8The diagram shown is an equivalent circuit diagram of the DRAM cell structures C111 to CL1N in the first row of the DRAM array structure 200 according to an embodiment of the present disclosure. Figure 9 As shown, a first-row, first-column DRAM cell structure C111 is provided at the intersection of the first row, first column bit line BL11 extending vertically (z-direction) and the first layer word line (first word line WLA11 and second word line WLB11) extending horizontally (y-direction). And so on. Figure 9 The first row of the DRAM array structure 200 shown includes N×L DRAM cell structures C111 to CL1N.

[0091] As mentioned above Figure 1 As described, according to embodiments of the present disclosure, each of the plurality of DRAM cell structures constituting the DRAM array structure 200, for example Figure 9 The DRAM cell structure C111 shown includes a first transistor T1, a second transistor T2, and a storage capacitor C.

[0092] Figure 10 It is shown Figure 8 The diagram shows a schematic perspective view of the first row of DRAM cells in the first layer of a DRAM array structure 200 according to an embodiment of the present disclosure. Figure 10 As shown, in the first row of the first layer of the DRAM array structure, the first word line WL11 (first word line WLA11 and second word line WLB11) can extend along a first horizontal direction (y-direction), and the first row bit lines (only BL11 to BL13 are shown) can extend along a vertical direction (z-direction). According to an embodiment of this disclosure, the source line SL of the first layer of the DRAM cell structure can extend along the first horizontal direction (y-direction). Furthermore, as... Figure 10 As shown, the source line SL can also be connected to the source lines SL in other layers in a common electrode trench that extends along the vertical direction (z direction).

[0093] In addition, such as Figures 8 to 10 As shown, according to an embodiment of this disclosure, the bit line BLmn in the m-th row and n-th column can be connected to the second source / drain of the L first transistors and L second transistors in the m-th row and n-th column DRAM cell structure of the DRAM array structure 200, for performing a cell selection operation on the m-th row and n-th column DRAM cell structure.

[0094] Figure 11 It is shown Figure 8 The diagram shows a top view of a partial DRAM array structure 201 of a DRAM array structure 200 according to an embodiment of the present disclosure. Figure 12 It shows along Figure 11The image shows a cross-sectional view of the DRAM array structure 201 according to an embodiment of the present disclosure, taken by line AA'. Figure 13 It shows along Figure 11 The image shows a cross-sectional view of the DRAM array structure 201 according to an embodiment of the present disclosure, taken by line BB'. Figure 14 It shows along Figure 12 The image shows a cross-sectional view of the DRAM array structure 201 according to an embodiment of the present disclosure, taken by line CC'. Figure 15 It shows along Figure 12 The image shows a cross-sectional view of the DRAM array structure 201 according to an embodiment of the present disclosure, taken by line DD'.

[0095] It should be noted that Figures 11 to 15 The example shown is as follows Figure 8 The partial DRAM array structure 201 of the DRAM array structure 200 shown includes DRAM cell structures C111, C112, C121, C122, C211, C212, C221 and C222 in the first row and first column of the first layer to the second row and second column of the second layer. These eight DRAM cell structures are arranged in two rows, two columns and two layers.

[0096] According to embodiments of this disclosure, the M rows and N columns of the DRAM array structure 200, from bit lines BL11 to BLMN, can extend vertically (z-direction) and be arranged in an M×N matrix in the first horizontal direction (y-direction) and the second horizontal direction (x-direction). Furthermore, according to embodiments of this disclosure, the L layers of DRAM cell structures of the DRAM array structure 200 are stacked sequentially in the vertical direction, and each layer of DRAM cell structure includes M×N DRAM cell structures.

[0097] Specifically, such as Figures 11 to 15 As shown, the four bit lines BL11, BL12, BL21, and BL22, arranged in two rows and two columns, can extend vertically (z-direction) and be arranged in a 2×2 matrix in the first horizontal direction (y-direction) and the second horizontal direction (x-direction). Furthermore, as... Figure 12 and Figure 13 As shown, the first-layer DRAM cell structures C111, C112, C121 and C122 are stacked on top of the second-layer DRAM cell structures C211, C212, C121 and C222.

[0098] like Figure 11 and Figure 12As shown, the first word line WLA11 of the first row of the first layer is connected to the gate of the first transistor in the first row of the first layer DRAM cell structures C111 and C112, and the second word line WLB11 of the first layer is connected to the gate of the second transistor in the first row of the first layer DRAM cell structures C111 and C112. Similarly, the first word line WLA12 of the second row of the first layer is connected to the gate of the first transistor in the second row of the first layer DRAM cell structures C121 and C122, and the second word line WLB12 of the second row of the first layer is connected to the gate of the second transistor in the second row of the first layer DRAM cell structures C121 and C122. Similarly, the first word line WLA21 of the first row of the second layer is connected to the gate of the first transistor in the first row of the second layer DRAM cell structures C211 and C212, and the second word line WLB21 of the first row of the second layer is connected to the gate of the second transistor in the first row of the second layer DRAM cell structures C211 and C212. Similarly, the first word line WLA22 of the second row of the second layer is connected to the gate of the first transistor in the second row of the second layer DRAM cell structure C221 and C222, and the second word line WLB22 of the second row of the second layer is connected to the gate of the second transistor in the second row of the second layer DRAM cell structure C221 and C222.

[0099] like Figures 11 to 15As shown, four bit lines BL11, BL12, BL21, and BL22 are formed in four bit line holes extending vertically (z-direction) through the DRAM array structure. Specifically, bit line BL11 in the first row and first column extends vertically inside the tubular structure formed by the first and second transistors and the storage capacitor in the first row and first column DRAM cell structures C111 and C211, and connects to the second source / drain of the first and second transistors in the first row and first column DRAM cell structures C111 and C211. Similarly, bit line BL12 in the first row and second column extends vertically inside the tubular structure formed by the first and second transistors and the storage capacitor in the first row and second column DRAM cell structures C112 and C212, and connects to the second source / drain of the first and second transistors in the first row and second column DRAM cell structures C112 and C212. Similarly, bit line BL21 in the second row and first column extends vertically inside the tubular structure formed by the first and second transistors and the storage capacitor in the second row and first column DRAM cell structures C121 and C221, and connects to the second source / drain of the first and second transistors in the second row and first column DRAM cell structures C121 and C221. Similarly, bit line BL22 in the second row and second column extends vertically inside the tubular structure formed by the first and second transistors and the storage capacitor in the second row and second column DRAM cell structures C122 and C222, and connects to the second source / drain of the first and second transistors in the second row and second column DRAM cell structures C122 and C222.

[0100] According to embodiments of this disclosure, in each of the M rows × N columns of the DRAM cell structure, the first source / drain and second source / drain of the first transistor and the second transistor, the channel region, and the internal electrode of the storage capacitor are formed from the same semiconductor material layer. That is, according to embodiments of this disclosure, in each of the M × N bit line vias penetrating the L-layer DRAM cell structure in the vertical direction (z-direction), the first source / drain and second source / drain of the first transistor and the second transistor, the channel region, and the internal electrode of the storage capacitor in the L-layer DRAM cell structure are formed from the same semiconductor material layer having a tubular structure. In other words, this tubular semiconductor material layer extends vertically (z-direction) throughout the entire DRAM array structure 200.

[0101] Specifically, such as Figures 11 to 15As shown, the first source / drain and second source / drain electrodes, channel regions, and internal electrodes of the first transistor and second transistor in the first-layer DRAM cell structure C111 and the second-layer DRAM cell structure C211 connected to the first row, first column bit line BL11 are formed from the same semiconductor material layer. Similarly, the first source / drain and second source / drain electrodes, channel regions, and internal electrodes of the first transistor and second transistor in the first-layer DRAM cell structure C112 and the second-layer DRAM cell structure C212 connected to the first row, second column bit line BL12 are formed from the same semiconductor material layer. Similarly, the first source / drain and second source / drain electrodes, channel regions, and internal electrodes of the first transistor and second transistor in the first-layer DRAM cell structure C121 and the second-layer DRAM cell structure C221 connected to the second row, first column bit line BL21 are formed from the same semiconductor material layer. Similarly, the first source / drain and second source / drain of the first transistor and the second source / drain of the second transistor, the channel region and the internal electrode of the storage capacitor in the first layer DRAM cell structure C122 and the second layer DRAM cell structure C222 connected to the second row and second column bit line BL22 are formed by the same semiconductor material layer.

[0102] According to embodiments of this disclosure, the common electrode trench can extend in the first horizontal direction (y-direction) and penetrate the L-layer DRAM array structure in the vertical direction (z-direction). In this case, the L source lines SL corresponding to the L-layer DRAM cell structure can be connected together in the vertical direction (z-direction). Furthermore, according to embodiments of this disclosure, adjacent rows of DRAM cell structures in the second horizontal direction (x-direction) can share the common electrode trench. Additionally, as described above, the capacitor dielectric and external electrodes of the storage capacitors in each DRAM cell structure of the DRAM array structure 200 can be disposed in the common electrode trench.

[0103] Alternatively, according to embodiments of the present disclosure, the common electrode slot may be omitted in the DRAM array structure 200. In this case, the source line SL may extend only in the first horizontal direction (y direction) and be connected together commonly or in groups outside the DRAM array structure 200.

[0104] The DRAM array structure according to this disclosure can achieve three-dimensional vertical integration by stacking multiple layers of DRAM cells, thereby increasing integration density. Furthermore, the DRAM array structure according to this disclosure can be stacked on a circuit board including multiple circuits, thus enabling system-level three-dimensional vertical integration and significantly reducing the area overhead of the circuit system.

[0105] Figure 16 This is an equivalent circuit diagram illustrating a DRAM array structure 200' with an alternative configuration of word lines according to an embodiment of the present disclosure. Figure 16 In, with Figure 8 Identical parts are indicated by the same reference numerals, and repeated descriptions thereof will be omitted.

[0106] Combination Figure 8 Reference Figure 16 , Figure 16 The DRAM array structure 200' shown is... Figure 8 The difference in the DRAM array structure 200 shown is that, in the l-th layer DRAM cell structure, M first word lines WLAl1 to WLAlM can be connected together via a common first word line GWLAl extending in the second horizontal direction (x direction), and M second word lines WLBl1 to WLBlM can be connected together via a common second word line GWLBl extending in the second horizontal direction (x direction). Specifically, as... Figure 16 As shown, the first word lines WLA11 to WLA1M of the first-layer DRAM cell structure can be connected together via a first-layer common first word line GWLA1 extending in the second horizontal direction (x direction), and the second word lines WLB11 to WLB1M of the first-layer DRAM cell structure can be connected together via a first-layer common second word line GWLB1 extending in the second horizontal direction (x direction). Similarly, the first word lines WLA21 to WLA2M of the second-layer DRAM cell structure can be connected together via a second-layer common first word line GWLA2 extending in the second horizontal direction (x direction), and the second word lines WLB21 to WLB2M of the second-layer DRAM cell structure can be connected together via a second-layer common second word line GWLB2 extending in the second horizontal direction (x direction). And so on, until the first word lines WLAL1 to WLALM of the Lth layer DRAM cell structure can be connected together by the Lth layer common first word line GWLAL extending in the second horizontal direction (x direction), and the second word lines WLBL1 to WLBLM of the Lth layer DRAM cell structure can be connected together by the Lth layer common second word line GWLBL extending in the second horizontal direction (x direction).

[0107] At this time, according to the embodiments of the present disclosure, the DRAM array structure 200' has L common first word lines GWLA1 to GWLAL, L common second word lines GWLB1 to GWLBL, and M×N bit lines BL11 to BLMN. According to the embodiments of the present disclosure, the selection operation of each DRAM cell structure Clmn in the DRAM array structure 200' can be implemented through the common first word line GWLA1, the common second word line GWLB1, and the bit line BLmn.

[0108] Furthermore, according to embodiments of this disclosure, in each row of an M-row DRAM array structure, if L first word lines WLA1m to WLALm are respectively connected to L second word lines WLB1m to WLBLm, Figure 16 The DRAM array structure 200' shown can be further simplified to L common word lines GWL1 to GWLL. In this case, according to the embodiments of this disclosure, the selection operation of each DRAM cell structure Clmn in the DRAM array structure 200' can be implemented through the common word line GWL1 and the bit line BLmn.

[0109] therefore, Figure 16 The DRAM array structure 200' shown is compared to Figure 8 The DRAM array structure 200 shown simplifies word line configuration.

[0110] Figure 17 This is an equivalent circuit diagram showing a DRAM array structure 200" with an alternative configuration of bit lines according to an embodiment of the present disclosure. Figure 17 In, with Figure 8 Identical parts are indicated by the same reference numerals, and repeated descriptions thereof will be omitted.

[0111] Combination Figure 8 Reference Figure 17 , Figure 17 The DRAM array structure shown is 200". Figure 8 The difference in the DRAM array structure 200 shown is that, in the nth column DRAM cell structure, M bit lines BL1n to BLMn can be connected together via the nth column common bit line GBLn extending in the second horizontal direction (x direction). Specifically, as... Figure 17 As shown, bit lines BL11 to BLM1 of the first column of DRAM cell structure can be connected together via a first column common bit line GBL1 extending in the second horizontal direction (x direction). Similarly, bit lines BL12 to BLM2 of the second column of DRAM cell structure can be connected together via a second column common bit line GBL2 extending in the second horizontal direction (x direction). And so on, bit lines BL1N to BLMN of the Nth column of DRAM cell structure can be connected together via a Nth column common bit line GBLN extending in the second horizontal direction (x direction).

[0112] At this time, according to the embodiments of the present disclosure, the DRAM array structure 200" has L×M first word lines WLA11 to WLALM, L×M second word lines WLB11 to WLBLM, and N common bit lines GBL1 to GBLN. According to the embodiments of the present disclosure, the selection operation of each DRAM cell structure Clmn in the DRAM array structure 200" can be implemented by the first word line WLAlm, the second word line WLBlm, and the common bit line GBLn.

[0113] Furthermore, according to embodiments of this disclosure, in each row of an M-row DRAM array structure, if L first word lines WLA1m to WLALm are respectively connected to L second word lines WLB1m to WLBLm, Figure 17 The DRAM array structure 200" shown can be further simplified to L×M word lines WL11 to WLLM. In this case, according to the embodiments of this disclosure, the selection operation of each DRAM cell structure Clmn in the DRAM array structure 200" can be implemented by word line WLlm and common bit line GBLn.

[0114] therefore, Figure 17 The DRAM array structure shown is 200", compared to Figure 8 The DRAM array structure 200 shown can simplify bit line configuration.

[0115] Figure 18 This is an equivalent circuit diagram showing a DRAM array structure 200"' with an alternative configuration of word lines and bit lines according to an embodiment of the present disclosure. Figure 18 In, with Figure 8 Identical parts are indicated by the same reference numerals, and repeated descriptions thereof will be omitted.

[0116] Combination Figure 8 , Figure 16 and Figure 17 Reference Figure 18 , Figure 18 The DRAM array structure 200"' shown can be considered as Figure 16 The DRAM array structure 200' shown is... Figure 17 The DRAM array structure 200" shown is a combination. Specifically, according to embodiments of this disclosure, an M-row DRAM cell structure can be divided into several row groups, that is, two or more rows of DRAM cell structures can be combined into one row group. This is by way of example and not limitation. Figure 18The diagram illustrates that in a DRAM array structure 200"', an M-row DRAM cell structure can include M / 2 row groups, meaning that every two rows of DRAM cell structures can be combined into a row group. Those skilled in the art will recognize that each row group in an M-row DRAM cell structure can also include three or more rows.

[0117] According to embodiments of this disclosure, the word lines of the DRAM cell structures comprising multiple rows in each row group can be connected together by a common word line extending in a second horizontal direction (x direction). Specifically, in Figure 18 In the DRAM array structure 200"' shown, in the first row group, the first word lines and second word lines of the two rows of DRAM cell structures in the first layer can be connected together via a common first word line GWLA11 and a common second word line GWLB11, respectively. Similarly, the first word lines and second word lines of the two rows of DRAM cell structures in the second layer can be connected together via a common first word line GWLA21 and a common second word line GWLB21, respectively. Likewise, in the first row group, the first word lines and second word lines of the two rows of DRAM cell structures in the Lth layer can be connected together via a common first word line GWLAL1 and a common second word line GWLBL1, respectively. Figure 18 In the DRAM array structure 200"' shown, in the second row group, the first word lines and second word lines of the two rows of DRAM cell structures in the first layer can be connected together through a common first word line GWLA12 and a common second word line GWLB12, respectively. Similarly, the first word lines and second word lines of the two rows of DRAM cell structures in the second layer can be connected together through a common first word line GWLA22 and a common second word line GWLB22, respectively. Likewise, in the second row group, the first word lines and second word lines of the two rows of DRAM cell structures in the Lth layer can be connected together through a common first word line GWLAL2 and a common second word line GWLBL2, respectively.

[0118] Furthermore, according to embodiments of this disclosure, corresponding rows in each row group, i.e., the same columns of the DRAM cell structure having the same row number in each row group, i.e., bit lines having the same column number, can be connected together. In this specification, the serial number indicates the number in each subset of the set, while the number indicates the number in the set.

[0119] Specifically, in Figure 18In the DRAM array structure 200"' shown, the bit lines of the DRAM cell structures in the first row (i.e., row number 1) and first column (i.e., column number 1) of each row group can be connected together by a common bit line GBL11 extending in the second horizontal direction (x direction). Similarly, the bit lines of the DRAM cell structures in the first row and second column of each row group can be connected together by a common bit line GBL12 extending in the second horizontal direction (x direction), and so on, until the bit lines of the DRAM cell structures in the first row and Nth column of each row group can be connected together by a common bit line GBL1N extending in the second horizontal direction (x direction). Figure 18 In the DRAM array structure 200"' shown, the bit lines of the DRAM cell structure in the second row and first column of each row group can be connected together by a common bit line GBL21 extending in the second horizontal direction (x direction), and the bit lines of the DRAM cell structure in the second row and second column of each row group can be connected together by a common bit line GBL22 extending in the second horizontal direction (x direction), until the bit lines of the DRAM cell structure in the second row and Nth column of each row group can be connected together by a common bit line GBL2N extending in the second horizontal direction (x direction).

[0120] At this time, according to the embodiments of the present disclosure, the DRAM array structure 200"' has L×M / 2 common first word lines GWLA11 to GWLAL(M / 2), L×M / 2 common second word lines GWLB11 to GWLBL(M / 2), and 2N common bit lines GBL11 to GBL2N.

[0121] Furthermore, according to embodiments of this disclosure, in each layer of the L-layer DRAM cell structure, the common first word line GWLA and common second word line GWLB of the DRAM cell structures in each row group can be further connected together. Figure 18 The DRAM array structure 200"' shown can be further simplified to have L×M / 2 common word lines GWL11 to GWLL(M / 2).

[0122] therefore, Figure 18 The DRAM array structure shown is 200"', compared to Figure 8 The DRAM array structure 200 shown can simplify both bit line and word line configurations.

[0123] Compare Figure 8 and Figures 16 to 18 The DRAM array structure shown has the corresponding first word line WLA and second word line WLB connected together. Figure 8 The operation of the DRAM array structure 200 shown requires L×M word lines and M×N bit lines, that is, a total of L×M+M×N lines are required. Figure 16 The operation of the DRAM array structure 200' shown requires L word lines and M×N bit lines, that is, a total of L + M×N lines are required. Figure 17 The operation of the DRAM array structure 200" shown requires L×M word lines and N bit lines, that is, a total of L×M + N lines are required. Figure 18 The operation of the DRAM array structure 200"' shown requires L×M / 2 word lines and 2N bit lines, that is, a total of L×M / 2 + 2N lines are required. As is well known to those skilled in the art, the number of L (i.e., the number of layers) is usually less than the number of M (i.e., the number of rows) and the number of N (i.e., the number of columns). For example, the DRAM array structure may include a 1024-row × 1024-column cell structure with 64 layers, that is, L = 64, M = N = 1024. Obviously, in this example, Figure 8 and Figures 16 to 18 The sizes of the numbers of lines required for the operations of the DRAM array structures shown are sorted as follows, Figure 8 of L×M + M×N = <1114112> Figure 16 of L + M×N = <1048640> Figure 17 of L×M + N = 66560> Figure 18 of L×M / 2 + 2N = 34816. Obviously, Figure 18 The operation of the DRAM array structure 200"' shown requires the least number of lines.

[0124] In addition, as described above, although Figure 18 shows that in the DRAM array structure 200"', each row group includes two rows, but the present disclosure is not limited thereto, and each row group may also include three or more rows. That is, Figure 18 The number of lines required for the operation of the DRAM array structure 200"' shown may be L×M / S + N×S, where S is a natural number greater than 1 that can divide M. That is, in Figure 18 , S takes the value of 2. Alternatively, the value of S may also be other natural numbers that can divide M, for example, 4. In the case of S = 4, the M-row DRAM cell structure is divided into M / 4 row groups, and each row group has a DRAM cell structure of 4 rows.

[0125] The upper limit of S is determined by factors such as the manufacturing process. By adjusting the size of S, the number of lines required for the operation of the DRAM array structure 200"' can be minimized, and thus the area overhead of the corresponding memory peripheral drive circuit can be reduced and the parasitic capacitance of the bit lines can be reduced.

[0126] As is well known in the art, the parasitic capacitance generated by bit lines BL (referred to as bit line parasitic capacitance, denoted by CBL) can adversely affect the performance of DRAM array structures, such as power consumption and speed. To solve the above problem, the DRAM array structure according to this disclosure can have M×N selection transistors disposed above and / or below the L-layer DRAM cell structure to select M×N bit lines respectively.

[0127] Figure 19 It shows in Figure 1 The equivalent circuit diagram of adding a selection transistor ST to the DRAM cell structure 100 shown.

[0128] like Figure 1 As shown, according to embodiments of this disclosure, the selection transistor ST can be connected in series with a DRAM cell structure having a 2T1C form. For example, see the following description... Figure 22 The described transistor ST can be positioned vertically (z-direction) above the topmost DRAM cell in each column of DRAM cell structure and connected in series with it.

[0129] According to embodiments of this disclosure, such as Figure 19 As shown, the first source / drain S / D1 of the selection transistor ST is connected to the bit line BL, and the second source / drain S / D2 of the selection transistor ST is connected to the common bit line GBL extending in the second horizontal direction (x direction). Figure 22 (one of GBL1 to GBLN shown), and the gate G of the select transistor ST is connected to the common select line GBLS (e.g., Figure 22 (One of GBLS1 to GBLSM shown).

[0130] Figure 20 It shows in Figure 4 A cross-sectional view of the selected transistor is added above the DRAM cell structure shown. Figure 21 It shows in Figure 5 A cross-sectional view of the selected transistor is added above the DRAM cell structure shown.

[0131] Combination Figure 19 Reference Figure 20 and Figure 21 According to embodiments of this disclosure, similar to the first transistor T1 and the second transistor T2 in a DRAM cell structure, the selection transistor ST can also be in the form of a transistor. Furthermore, as... Figure 20 and Figure 21As shown, according to an embodiment of this disclosure, the select transistor ST can share the first dielectric layer 106 and the semiconductor material layer 107 with the first transistor T1 and the second transistor T2. Similar to the first transistor T1 and the second transistor T2, the gate dielectric of the select transistor ST can be formed by the first dielectric layer 106, and its first source / drain S / D1 and second source / drain S / D2, as well as its channel region, can be formed by the semiconductor material layer 107.

[0132] like Figure 20 and Figure 21 As shown, according to an embodiment of this disclosure, the conductor line 109, serving as the bit line BL, extends only to and contacts the portion of the semiconductor material layer 107 that serves as the first source / drain S / D1 of the selection transistor ST. Furthermore, as... Figure 20 and Figure 21 As shown, according to an embodiment of this disclosure, a portion of the semiconductor material layer 107 serving as the second source / drain S / D2 of the select transistor ST contacts the conductive plug 121, which can be connected to the common bit line 124. According to an embodiment of this disclosure, the material used to form the conductive plug 121 may include, for example, tungsten silicide (WSi), tungsten nitride (WN), tungsten (W), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), or combinations thereof. Furthermore, as... Figure 20 and Figure 21 As shown, according to an embodiment of the present disclosure, the conductive plug 121 and the conductor line 109 used as the bit line BL are separated from and insulated from each other by an insulating plug 122. According to an embodiment of the present disclosure, the material used to form the insulating plug 122 may include, for example, silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, glass phosphate, or combinations thereof.

[0133] In addition, such as Figure 20 and Figure 21 As shown, according to an embodiment of the present disclosure, the gate layer 120 serving as the gate G of the select transistor ST can be formed as a tubular structure surrounding a portion of the first dielectric layer 106 that serves as the gate dielectric layer of the select transistor ST. According to an embodiment of the present disclosure, the material used to form the gate layer 120 may include titanium nitride (TiN), tantalum nitride (TaN), aluminum titanium carbide (TiAlC), aluminum (Al), copper (Au), titanium (Ti), palladium (Pd), molybdenum (Mo), platinum (Pt), tungsten (W), doped polycrystalline / amorphous silicon, indium tin oxide (ITO), indium zinc oxide (IZO), or combinations thereof.

[0134] In addition, such as Figure 20 and Figure 21As shown, according to an embodiment of the present disclosure, a capping layer 123 covers the select transistor ST, and a conductive plug 121 can pass through the capping layer 123 to connect to a common bit line 124 disposed on the capping layer 123. According to an embodiment of the present disclosure, the material used to form the capping layer 123 may include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, glass phosphate, or combinations thereof.

[0135] Reference Figure 20 and Figure 21 According to embodiments of this disclosure, the selected transistor ST can be formed simultaneously with each DRAM cell structure, compatible with three-dimensional vertical integration of multilayer cells.

[0136] Figure 22 An equivalent circuit diagram of a DRAM array structure with a selectable transistor layer according to an embodiment of the present disclosure is shown. Figure 20 and Figure 17 The difference in the DRAM array structure 200" shown is that, Figure 20 In addition, a selection transistor layer is provided above the DRAM array structure, which includes selection transistors disposed above each bit line BL.

[0137] In contrast, Figure 17 In the nth column DRAM cell structure, M bit lines BL1n to BLMn can be connected to the nth column common bit line GBLn, which extends in the second horizontal direction (x direction) and is located below the DRAM array structure. Figure 22 In the nth column DRAM cell structure, M bit lines BL1n to BLMn can be connected together with the nth column common bit line GBLn, which extends in the second horizontal direction (x direction), and is located above the DRAM array structure, through a selection transistor disposed above each bit line.

[0138] In addition, such as Figure 22 As shown, according to an embodiment of this disclosure, the gates of N selection transistors disposed above the m-th row bit lines BLm1 to BLmN are connected together via a common selection line GBLSm. In other words, the connection and disconnection of the m-th row bit lines BLm1 to BLmN with the corresponding common bit lines GBL1 to GBLN are controlled by the common selection line GBLSm.

[0139] like Figure 22As shown, according to an embodiment of this disclosure, the DRAM array structure includes a common bit line group. Each of the N common bit lines GBL1 to GBLN in the common bit line group is connected to a bit line with the same column number in each row of DRAM cell structures via a select transistor, and the gate of the select transistor in each row of DRAM cell structures is connected to a common select line. Therefore, according to an embodiment of this disclosure, when performing a read or write operation on the DRAM array structure, N DRAM cell structures in each layer of each row can be operated simultaneously through the N common bit lines GBL1 to GBLN in a common bit line group.

[0140] Despite Figure 22 In this configuration, all selection transistors are positioned above their respective bit lines, and therefore the common bit line is also positioned above the DRAM array structure. However, those skilled in the art will recognize that this disclosure is not limited thereto. Based on the teachings of this disclosure, those skilled in the art will realize that the selection transistors can be positioned below their respective bit lines, and therefore the common bit line can also be positioned below the DRAM array structure.

[0141] According to embodiments of this disclosure, the multiple DRAM cell structures included in the three-dimensional DRAM array structure can be disposed on a substrate. At this time, the selection transistor disposed below the bit line can also be disposed in the substrate, with its first source / drain connected to the bit line and its second source / drain connected to the common bit line.

[0142] Figure 23 An equivalent circuit diagram of a DRAM array structure with a selectable transistor layer according to another embodiment of the present disclosure is shown. Figure 22 Compared to the array structure shown, in Figure 23 In the DRAM array structure shown, a selection transistor is positioned above and below each bit line BL. Specifically, as... Figure 23 As shown, the first column bit line BL can be connected to the first column common bit line GBL1, which extends in the second horizontal direction (x direction) below the DRAM array structure, via a selection transistor disposed below each bit line BL. Similarly, the second column bit line BL can be connected to the second column common bit line GBL2, which extends in the second horizontal direction (x direction) above the DRAM array structure, via a selection transistor disposed above each bit line BL. Likewise, the (N-1)th column bit line BL can be connected to the (N-1)th column common bit line GBL1, which extends in the second horizontal direction (x direction) below the DRAM array structure, via a selection transistor disposed below each bit line BL. The Nth column bit line BL can be connected to the Nth column common bit line GBL2, which extends in the second horizontal direction (x direction) above the DRAM array structure, via a selection transistor disposed above each bit line BL. In other words, in Figure 23 In this configuration, the common bit lines of odd-numbered columns can be connected to the corresponding bit lines via selection transistors disposed below each bit line BL, while the common bit lines of even-numbered columns can be connected to the corresponding bit lines via selection transistors disposed above each bit line BL. Thus, according to embodiments of this disclosure, N common bit lines GBL1 to GBLN can be separately disposed above and below the DRAM array structure, thereby reducing the density of common bit lines and decreasing the parasitic capacitance introduced by the common bit lines.

[0143] Furthermore, since in each row of bit lines, the bit lines of odd-numbered columns are connected to the common bit line of odd-numbered columns through select transistors located below the bit lines, and the bit lines of even-numbered columns are connected to the common bit line of even-numbered columns through select transistors located above the bit lines, each row of DRAM cell structure requires two common select lines, GBLSA and GBLSB, to control the on and off states of the select transistors located above and below each bit line, thereby controlling the connection and disconnection of each bit line with the corresponding common bit line. Specifically, as... Figure 23 As shown, the gates of N selection transistors located below the m-th row bit lines BLm1 to BLmN are connected together via a common selection line GBLSAm to control the connection and disconnection of odd-numbered column bit lines with the odd-numbered column common bit lines. The gates of N selection transistors located above the m-th row bit lines BLm1 to BLmN are connected together via a common selection line GBLSBm to control the connection and disconnection of even-numbered column bit lines with the even-numbered column common bit lines.

[0144] Those skilled in the art should recognize that Figure 23 The configuration of common bit lines shown is merely an example, and this disclosure is not limited thereto. In fact, according to the teachings of this disclosure, in order to reduce the density of common bit lines, it is sufficient to place a portion of the common bit lines above the DRAM array structure and place the remaining portion of the common bit lines below the DRAM array structure.

[0145] Figure 24A and Figure 24B An equivalent circuit diagram of the first row group in a DRAM array structure having a select transistor layer according to an embodiment of the present disclosure is shown. Figure 24A and Figure 24B The DRAM array structure shown adopts the same as Figure 18 The illustrated DRAM array structure is similar to a 200'" array while simplifying the configuration of bit lines and word lines. Compared to... Figure 18 In this method, every two rows (i.e., S=2) of DRAM cell structure are combined into a row group. Figure 24A and Figure 24BIn this context, an M-row DRAM cell structure can include M / 4 row groups (i.e., S=4), meaning that every four rows of DRAM cells can be combined into a row group, and a selection transistor is added between the bit lines and the common bit line. For ease of description, Figure 24B It is shown in a flat, unfolded manner. Figure 24A The diagram shows the first row group of a four-row DRAM array structure. It should be noted that, according to embodiments of this disclosure, the other row groups of the DRAM array structure have... Figure 24A and Figure 24B The first row group shown has the same configuration.

[0146] like Figure 24A and Figure 24B As shown, similar to Figure 18 The DRAM array structure 200'" shown has word lines of the first to fourth rows of DRAM cell structures in the first row group that can be connected together by a common word line extending in the second horizontal direction (x direction). Specifically, in Figure 24A and Figure 24B In the first row group shown, the first word lines and second word lines of the two rows of DRAM cell structures in the first layer can be connected together via common first word line GWLA11 and second word line GWLB11, respectively. Similarly, the first word lines and second word lines of the two rows of DRAM cell structures in the second layer can be connected together via common first word line GWLA21 and common second word line GWLB21, respectively. Likewise, in the first row group, the first word lines and second word lines of the two rows of DRAM cell structures in the Lth layer can be connected together via common first word line GWLAL1 and common second word line GWLBL1, respectively.

[0147] In addition, Figure 24A and Figure 24B In, similar to Figure 18In the DRAM array structure 200'" shown, corresponding rows in each row group, i.e., the same columns of DRAM cell structures with the same row number, i.e., the same column number, can be connected together. Specifically, the bit lines of the first row (i.e., row number 1) and first column (i.e., column number 1) DRAM cell structures in each row group can be connected together through a common bit line GBL11 extending in the second horizontal direction (x direction), and the bit lines of the first row and second column DRAM cell structures in each row group can be connected together through a common bit line GBL12 extending in the second horizontal direction (x direction), until the bit lines of the first row and Nth column DRAM cell structures in each row group can be connected together. The common bit lines GBL1N extending in the second horizontal direction (x direction) are connected together, and these common bit lines can be represented together as GBL1 or GBL1<1:N>. Similarly, the bit lines of the DRAM cell structure in the first column of the second row (i.e., row number 2) in each row group can be connected together by the common bit line GBL21 extending in the second horizontal direction (x direction), and the bit lines of the DRAM cell structure in the second row and second column of each row group can be connected together by the common bit line GBL22 extending in the second horizontal direction (x direction), until the bit lines of the DRAM cell structure in the Nth column of the second row in each row group can be connected together by the common bit line GBL22 extending in the second horizontal direction (x direction). The common bit lines GBL2N are connected together, and these common bit lines can be represented together as GBL2 or GBL2<1:N>. Similarly, the bit lines of the DRAM cell structure in the third row and first column of each row group can be connected together by the common bit line GBL31 extending in the second horizontal direction (x direction), the bit lines of the DRAM cell structure in the third row and second column of each row group can be connected together by the common bit line GBL32 extending in the second horizontal direction (x direction), and so on, until the bit lines of the DRAM cell structure in the third row and Nth column of each row group can be connected together by the common bit line GBL3N extending in the second horizontal direction (x direction). These can be represented together as GBL3 or GBL3<1:N>. Similarly, the bit lines of the DRAM cell structure in the fourth row and first column of each row group can be connected together by a common bit line GBL41 extending in the second horizontal direction (x direction), the bit lines of the DRAM cell structure in the fourth row and second column of each row group can be connected together by a common bit line GBL42 extending in the second horizontal direction (x direction), and so on, until the bit lines of the DRAM cell structure in the fourth row and Nth column of each row group can be connected together by a common bit line GBL4N extending in the second horizontal direction (x direction). These common bit lines can be represented together as GBL4 or GBL4<1:N>.

[0148] In other words, Figure 24A and Figure 24BIn the DRAM cell array of each row group, the bit lines BL are connected together through four sets of common bit lines GBL1<1:N> to GBL4<1:N>, and each set of common bit lines GBL includes N common bit lines GBL.

[0149] In addition, such as Figure 24A and Figure 24B As shown, according to an embodiment of this disclosure, selection transistors corresponding to each bit line BL are disposed above the L-layer DRAM cell structure. Specifically, as... Figure 24A and Figure 24B As shown, the source and drain of each selection transistor are connected to the corresponding bit line BL and the common bit line GBL. Furthermore, Figure 24B The parasitic capacitance of each bit line BL is also shown; for example, the parasitic capacitance of bit line BL11 in the first row and first column can be represented by C11. It should be understood here that... Figure 24B The parasitic capacitances shown for each bit line BL are equivalent capacitances in the circuit, not actual capacitors. The values ​​of the parasitic capacitances for each bit line BL can be assumed to be the same and uniformly denoted as CBL. Furthermore, as mentioned above, the 4N common bit lines GBL1<1:N> to GBL4<1:N> all extend in the second horizontal direction (x-direction), which will also result in corresponding parasitic capacitances for the common bit lines. The values ​​of the parasitic capacitances for each common bit line GBL can also be assumed to be the same and uniformly denoted as CGBL.

[0150] In addition, such as Figure 24A and Figure 24B As shown, the gates of all the selection transistors in the first row are connected to the common selection line GBLS1. That is, in Figure 24A and Figure 24B In an embodiment of this disclosure, the selection transistors of each bit line BL in each row group are controlled to be turned on and off by a common selection line corresponding to that row group, so as to connect or disconnect the bit line BL and the common bit line GBL.

[0151] In addition, such as Figure 24A and Figure 24B As shown, the selection transistors (and their corresponding parasitic capacitances) disposed above the L-layer DRAM cell structure can be collectively referred to as the selection transistor layer (STL). Although the selection transistor layer STL is disposed above the L-layer DRAM cell structure in FIG. 24, this disclosure is not limited thereto. According to embodiments of this disclosure, the selection transistor layer STL may also be disposed below the L-layer DRAM cell structure.

[0152] like Figure 24A and Figure 24BAs shown, according to embodiments of this disclosure, the M-row DRAM cell structure of the DRAM array can be divided into M / S row groups, where S is a natural number greater than 1 that is divisible by M, and each row group has S rows of DRAM cell structures. Furthermore, the first word lines of each layer in each row group are connected via a common first word line, and the second word lines of each row group are connected via a common second word line. Additionally, the DRAM array structure may include S common bit line groups, each of the N common bit lines included in each of the S common bit line groups being connected via a select transistor to a bit line in each row group having the same row number and the same column number, and the gate of the select transistor of the DRAM cell structure in each row group being connected to a common select line. Therefore, according to embodiments of this disclosure, when performing a read or write operation on the DRAM array structure, the S×N DRAM cell structures of each layer in each row group can be operated simultaneously through the S common bit line groups.

[0153] According to embodiments of this disclosure, as described below. Figure 25 and Figure 26 In more detail, by introducing a Select Transistor Layer (STL), the adverse effects of bit-line parasitic capacitance on the performance of the DRAM array structure can be reduced.

[0154] Figure 25 It shows Figure 24A and Figure 24B The timing diagram shows the read operation of the DRAM cell structure in the first row group. According to an embodiment of this disclosure, read operations can be performed simultaneously on four rows of DRAM cell structures in the first row group (i.e., row numbers s = 1 to 4 in the row group, where 1 ≤ s ≤ S). According to an embodiment of this disclosure, it is possible to use... Figure 25 The same read operation is performed on the DRAM cell structure of other row groups of the DRAM array structure.

[0155] exist Figure 25 In the diagram, BL-PREC indicates the pre-charge period during which all bit lines and the common bit line are pre-charged to the reference voltage VPREC, where VPREC is typically half the supply voltage, i.e., VDD / 2. Furthermore, in... Figure 25 In this context, SAEN represents the sense amplifier enable signal, and DQout represents the data read. Furthermore, in... Figure 25 In this context, VCS represents the voltage of the storage node (the internal electrode of the storage capacitor) in the DRAM cell structure. More specifically, VCS(1) represents the voltage of the storage node when the DRAM cell structure stores data "1", while VCS(0) represents the voltage of the storage node when the DRAM cell structure stores data "0".

[0156] In addition, Figure 25 In the diagram, GBLref / BLref are common bit lines / bit lines used as references (not shown). Furthermore, in... Figure 25 In GBL / BL(1), the data stored in the DRAM cell structure connected to the bit line is "1", while GBL / BL(0) indicates that the data stored in the DRAM cell structure connected to the bit line is "0".

[0157] Figure 25 The read operation of the DRAM cell structure in the first row shown can be performed in a manner similar to the read operation of a conventional DRAM cell structure. Specifically, according to the embodiments of this disclosure, such as Figure 25 As shown, the common selection line GBLS1 is selected and activated to a logic high level, causing the bit lines BL of each DRAM cell structure in the first row group to be connected to the corresponding common bit line GBL. During the precharge period BL-PREC, all common bit lines GBL and bit lines BL can be precharged to the reference voltage VPREC, i.e., VDD / 2. At this time, word lines WLAl1 and WLBl1 (where 1≤l≤L) and the sense amplifier enable signal SAEN are not enabled.

[0158] Subsequently, as Figure 25 As shown, after the precharge period BL-PREC, word lines WLAl1 and WLBl1 are selected and activated to a logic high level, causing the gating transistors of the DRAM cell structures of the first row group connected to word lines WLAl1 and WLBl1 to turn on. This connects the storage capacitors of these DRAM cell structures to the corresponding common bit line / bit line GBL / BL, resulting in charge transfer.

[0159] If the data stored in the storage capacitor of the DRAM cell structure connected by the common bit line / bit line GBL / BL is "1", that is... Figure 25 In the case shown by VCS(1), the voltage of the common bit line / bit line GBL / BL increases slightly relative to the reference bit line GBLref / BLref due to the charge flowing from the common bit line / bit line GBL / BL to the storage capacitor. The increase is ΔVBL=(VCS-VPREC)×CS / (CS+CBL+CGBL), where CS represents the capacitance of the storage capacitor. At this time, the voltage VCS(1) of the storage capacitor in these DRAM cell structures decreases due to the charge inflow.

[0160] Similarly, if the data stored in the storage capacitor of the DRAM cell structure connected by the common bit line / bit line GBL / BL is "0", that is... Figure 25In the case shown by VCS(0), the voltage of the common bit line / bit line GBL / BL decreases slightly relative to the reference bit line GBLref / BLref due to the charge flowing from the storage capacitor to the common bit line / bit line GBL / BL. The decrease is ΔVBL. At this time, the voltage VCS(0) of the storage capacitor in these DRAM cell structures increases due to the charge outflow.

[0161] In any of the above cases, the data stored in the storage capacitors of the selected DRAM cell structure is corrupted due to charge transfer, so the stored data should be reconstructed after reading the data from the DRAM cell structure.

[0162] Therefore, the enable signal SAEN of the sense amplifier (not shown in the figure) connected to the common bit line is then enabled to a logic high level, causing the sense amplifier connected to the selected common bit line / bit line GBL / BL and the reference bit line GBLref / BLref to amplify the voltage difference between them, i.e., ΔVBL. Specifically, in the case of GBL / BL(1), the sense amplifier pulls up the voltage of the selected common bit line / bit line GBL / BL to VDD and pulls down the voltage of the reference bit line GBLref / BLref to ground, i.e., GND. In addition, in the case of GBL / BL(0), the sense amplifier pulls down the voltage of the selected common bit line / bit line GBL / BL to GND and pulls up the voltage of the reference bit line GBLref / BLref to VDD. At this time, as Figure 25 As shown in VCS(1) and VCS(0), the data is rewritten to the storage capacitors of the DRAM cell structure after being read to reconstruct the original data.

[0163] Simultaneously, the data amplified by the sensing amplifier is transmitted to the input / output buffer via the input / output lines, and a stable data DQout is output. This completes one read operation. Figure 25 The read operation can be divided into four steps: pre-charge bit line, charge transfer, sensing amplification / data write-back, and data output. This is similar to the read operation method of existing DRAM memory.

[0164] As mentioned above, during the read operation, the voltage change ΔVBL due to charge transfer on the common bit line / bit line GBL / BL is ΔVBL = (VCS - VDD / 2) × CS / (CS + CBL + CGBL), where CS is the capacitance of the storage capacitor, CBL is the parasitic capacitance of the selected bit line, CGBL is the parasitic capacitance of the common bit line, and CBL + CGBL is the total parasitic capacitance of the common bit line. Defining the charge transfer ratio CTR = CS / (CS + CBL + CGBL), then ΔVBL = (VCS - VDD / 2) × CTR. Clearly, the larger CBL and / or CGBL are, the smaller the obtained signal ΔVBL is, resulting in poorer read operation speed and reliability. If no selection transistor layer is used to isolate the common bit line GBL and bit line BL, the total parasitic capacitance of the common bit line is M / S × CBL + CGBL, which will result in very small CTR and ΔVBL, making the read operation difficult to perform correctly. Because of the presence of the Selective Transistor Layer (STL), when the DRAM cell structure of the first row group is read, the bit lines BL of the DRAM cell structures of other row groups are disconnected from the common bit line GBL, which greatly reduces the total parasitic capacitance CBL+CGBL of the common bit line, allowing the magnitude of ΔVBL to be increased, thereby improving the overall performance of the DRAM array structure, such as power consumption and speed.

[0165] Figure 26 It shows Figure 24A and Figure 24B The timing diagram for write operations of the DRAM cell structure in the first row shown. Figure 26 Zhongyu Figure 25 The same reference numerals have the same meaning as those in the reference figures. Figure 25 The same physical meaning. According to embodiments of this disclosure, write operations can be performed simultaneously on four rows of DRAM cell structures (i.e., s = 1 to 4) in the first row group. According to embodiments of this disclosure, it is possible to use... Figure 26 The write operation shown is performed on the DRAM cell structure of other row groups of the DRAM array structure in the same way.

[0166] exist Figure 26 In this context, DQin represents the data written, and DQm represents the original data stored in the storage capacitors of the DRAM cell structure obtained through the sense amplifier.

[0167] contrast Figure 25 Reference Figure 26 You can see Figure 26 The timing of the write operation shown is as follows Figure 25 The timing of most of the read operations shown is the same, so for the sake of brevity, it will not be described repeatedly; the difference lies in the timing of the read operations. Figure 26In the write operation shown, after the sense amplifier is enabled and the voltage difference ΔVBL between the common bit line / bit line GBL / BL and the reference bit line GBLref / BLref is amplified, the external data applied to the selected common bit line / bit line GBL / BL is forcibly written into the storage capacitor of the corresponding DRAM cell structure.

[0168] Figure 26 Only the case where the externally written data is different from the original data stored in the storage capacitor of the DRAM cell structure is shown, i.e., the case where it is written from "0" to "1". Figure 26 The cases of "0→1" and "0" being written from "1" (in the original text) Figure 26 (1→0 in the context of the DRAM cell structure). For cases where the externally written data is identical to the original data stored in the memory capacitors of the DRAM cell structure, the timing diagrams of signals other than DQin are different. Figure 25 Same, therefore Figure 26 And not shown. According to Figure 26 The write operation can be divided into four steps: precharge bit line, charge transfer, sense amplification / data write-back, and data writing. This is similar to the write operation method of existing DRAM memory.

[0169] According to the embodiments of this disclosure, in the write operation, the voltage change ΔVBL caused by charge transfer on the selected bit line GBL / BL is ΔVBL = (VCS-VDD / 2)×CS / (CS+CBL+CGBL). Due to the presence of the selected transistor layer STL, when the DRAM cell structure of the first row group is read, the bit lines BL of the DRAM cell structures of other row groups are disconnected from the common bit line GBL, thereby greatly reducing the total parasitic capacitance CBL+CGBL of the common bit line. This effectively increases the voltage difference ΔVBL during reading, thereby improving the overall performance of the DRAM array structure, such as power consumption and speed.

[0170] Figure 27A and Figure 27B An equivalent circuit diagram of the first row group in a DRAM array structure having a selectable transistor layer according to another embodiment of the present disclosure is shown. Figure 27A and Figure 27B The DRAM array structure shown adopts the same as Figure 18 The illustrated DRAM array structure is similar to a 200'" array while simplifying the configuration of bit lines and word lines. Compared to... Figure 18 In this method, every two rows (i.e., S=2) of DRAM cell structure are combined into a row group. Figure 27A and Figure 27B In this context, an M-row DRAM cell structure can comprise M / 4 row groups (i.e., S = 4), meaning that every four rows of DRAM cell structures can be combined into one row group. For ease of description, Figure 27B It is shown in a flat, unfolded manner. Figure 27A The diagram shows the first row group of a four-row DRAM array structure. It should be noted that, according to embodiments of this disclosure, the other row groups of the DRAM array structure have... Figure 27A and Figure 27B The first row group shown has the same configuration.

[0171] like Figure 27A and Figure 27B As shown, similar to Figure 18 The DRAM array structure 200'" shown has word lines of the first to fourth rows of DRAM cell structures in the first row group connected together by common word lines extending in the second horizontal direction (x direction). Specifically, in the first row group shown in Figure 27, the first and second word lines of the two rows of DRAM cell structures in the first layer can be connected together by common first word line GWLA11 and second word line GWLB11, respectively, and the first and second word lines of the two rows of DRAM cell structures in the second layer can be connected together by common first word line GWLA21 and common second word line GWLB21, respectively. Similarly, in the first row group, the first and second word lines of the two rows of DRAM cell structures in the Lth layer can be connected together by common first word line GWLAL1 and common second word line GWLBL1, respectively.

[0172] In addition, Figure 27A and Figure 27B In China, unlike Figure 24A and Figure 24B The bit lines BL of the DRAM cell array in each row group are connected together by two sets (instead of four sets) of common bit lines GBL1<1:N> to GBL2<1:N>. Each set of common bit lines GBL includes N common bit lines. The first set of common bit lines GBL1<1:N> is connected to the bit lines BL of the first and third rows of DRAM cell structures in each row group, respectively. The second set of common bit lines GBL2<1:N> is connected to the bit lines BL of the second and fourth rows of DRAM cell structures in each row group, respectively. For example, the bit lines BL1<1:N> and BL3<1:N> of the first row of DRAM cell structures in the first row group are connected to the first set of common bit lines GBL1<1:N>, and the bit lines BL2<1:N> and BL4<1:N> of the second and fourth rows of DRAM cell structures in the first row group are connected to the second set of common bit lines GBL2<1:N>.

[0173] In addition, such as Figure 27A and Figure 27BAs shown, according to an embodiment of this disclosure, selection transistors corresponding to each bit line BL are disposed above the L-layer DRAM cell structure. Specifically, as... Figure 27A and Figure 27B As shown, the source and drain of each selection transistor are connected to the corresponding bit line BL. Furthermore, Figure 27B The parasitic capacitance of each bit line BL is also shown; for example, the parasitic capacitance of bit line BL11 in the first row and first column can be represented by C11. It should be understood here that... Figure 27B The parasitic capacitances shown for each bit line BL are equivalent capacitances in the circuit, not actual capacitors. The values ​​of the parasitic capacitances for each bit line BL can be assumed to be the same and uniformly denoted as CBL. Furthermore, as mentioned above, the 2N common bit lines GBL1<1:N> to GBL2<1:N> all extend in the second horizontal direction (x-direction), which will also result in corresponding common bit line parasitic capacitances. The values ​​of the parasitic capacitances for each common bit line GBL can also be assumed to be the same and uniformly denoted as CGBL.

[0174] exist Figure 27A and Figure 27B In order to achieve independent addressing of the bit lines BL of each DRAM cell structure, the number of common selection lines is increased accordingly. Specifically, such as... Figure 27A and Figure 27B As shown, the gates of all selection transistors in the first and second rows of the first group are connected to the common selection line GBLS11, and the gates of all selection transistors in the third and fourth rows of the first group are connected to the common selection line GBLS12. That is, in Figure 27A and Figure 27B In an embodiment of this disclosure, the selection transistors of each bit line BL of each row group are controlled to be turned on and off by two common selection lines corresponding to that row group.

[0175] In addition, such as Figure 27A and Figure 27B As shown, the selection transistors (and their corresponding parasitic capacitances) positioned above the L-layer DRAM cell structure can be collectively referred to as the selection transistor layer (STL). Although in Figure 27A and Figure 27B In this embodiment, the Select Transistor Layer (STL) is disposed above the L-layer DRAM cell structure; however, this disclosure is not limited thereto. According to embodiments of this disclosure, the Select Transistor Layer (STL) may also be disposed below the L-layer DRAM cell structure.

[0176] Compared to Figure 24A and Figure 24B The configuration of the DRAM array structure shown is as follows: Figure 27A and Figure 27BThe configuration of the DRAM array structure shown can further simplify the configuration of common bit lines. Specifically, for an M-row, N-column, L-layer DRAM array structure, refer to the above and combine... Figure 18 As described, Figure 24A and 24B The DRAM array structure shown requires L×M / 4 common word lines, 4N common bit lines, and M / 4 common select lines to operate, which means a total of L×M / 4 + 4N + M / 4 lines are needed. Figure 27A and Figure 27B The DRAM array structure shown requires L×M / 4 common word lines, 2N common bit lines, and M / 2 common select lines to operate, totaling L×M / 4 + 2N + M / 2 lines. For example, in a DRAM array structure comprising 64 layers of 1024 rows × 1024 columns (L = 64, M = N = 1024), Figure 24A and Figure 24B The DRAM array structure shown requires 20,736 lines to operate, while Figure 27A and Figure 27B The DRAM array structure shown requires 18,944 lines to operate.

[0177] Refer to Figure 24 and Figure 24B According to embodiments of this disclosure, the M-row DRAM cell structure is divided into M / S row groups, where S is a natural number greater than 1 that can divide M (in Figure 24A and Figure 24B In this configuration, S = 4), each row group has an S-row DRAM cell structure. Furthermore, the DRAM array structure includes S common bit line groups, and each of the N common bit lines included in each of the S common bit line groups is connected via a select transistor to a bit line in each row group that has the same row number and the same column number. Additionally, the gate of the select transistor in the DRAM cell structure of each row group is connected to a common select line.

[0178] For comparison, refer to Figure 27A and Figure 27B According to embodiments of this disclosure, the M-row DRAM cell structure is divided into M / S row groups, where S is a natural number greater than 1 that divides M. Figure 27A and Figure 27B In this context, S=4, meaning each row group has an S-row DRAM cell structure. Furthermore, compared to Figure 24 and... Figure 24B Each row group is further divided into S / T sub-row groups, where T is a natural number greater than 1 that divides S. Figure 27A and Figure 27BIn this configuration, T = 2, meaning each sub-row group has T rows of DRAM cell structures. Furthermore, the DRAM array structure includes T common bit line groups. Each of the N common bit lines included in each of the T common bit line groups is connected via a select transistor to a bit line in each sub-row group that has the same row number and column number. Additionally, the gate of the select transistor in the DRAM cell structure of each sub-row group is connected to a common select line.

[0179] like Figure 27A and Figure 27B As shown, according to embodiments of this disclosure, the M-row DRAM cell structure of the DRAM array can be divided into M / S row groups, where S is a natural number greater than 1 that divides M, and each row group has S rows of DRAM cell structures. Furthermore, each row group can be further divided into S / T sub-row groups, where T is a natural number greater than 1 that divides S, and each sub-row group has T rows of DRAM cell structures. Additionally, the first word lines of each layer in each row group are connected via a common first word line, and the second word lines of each layer in each row group are connected via a common second word line. Furthermore, the DRAM array structure includes T common bit line groups, and each of the N common bit lines included in each of the T common bit line groups is connected via a selection transistor to a bit line having the same row number and column number in each sub-row group, and the gate of the selection transistor of the DRAM cell structure in each sub-row group is connected to a common selection line. Therefore, according to the embodiments of this disclosure, when performing read or write operations on the DRAM array structure, the S×N DRAM cell structures of each layer in each row group can be operated step by step through the T common bit line groups.

[0180] According to embodiments of this disclosure, as described below. Figure 28 and Figure 29 In more detail, by introducing a Select Transistor Layer (STL), the adverse effects of bit-line parasitic capacitance on the performance of the DRAM array structure can be reduced.

[0181] Figure 28 It shows Figure 27A and Figure 27B The diagram shows the timing of the read operation of the DRAM cell structure in the first row group. According to an embodiment of this disclosure, the read operation can be performed twice on the four rows of DRAM cell structures in the first row group (i.e., row numbers s = 1 to 4, where 1 ≤ s ≤ S). The first sub-read operation can be performed on the first sub-row group, i.e., the first and second rows (i.e., s = 1 and 2) of the DRAM cell structure, while the second sub-read operation can be performed on the second sub-row group, i.e., the third and fourth rows (i.e., s = 3 and 4) of the DRAM cell structure. According to an embodiment of this disclosure, it can be used with... Figure 28The same read operation is performed on the DRAM cell structure of other row groups of the DRAM array structure.

[0182] exist Figure 28 In the diagram, BL-PREC indicates the pre-charge period during which all bit lines and the common bit line are pre-charged to the reference voltage VPREC, where VPREC is typically half the supply voltage, i.e., VDD / 2. Furthermore, in... Figure 28 In this context, SAEN represents the sense amplifier enable signal, and DQout represents the data read. Furthermore, in... Figure 28 In this diagram, VCS1n to VCS4n represent the voltages of the storage nodes (internal electrodes of the storage capacitors) in the DRAM cell structures of the first to fourth rows, respectively. Furthermore, VCS1n(1) and VCS3n(1) represent the voltages of the storage nodes in the first and third rows of the DRAM cell structures when storing data "1", respectively, while VCS2n(0) and VCS4n(0) represent the voltages of the storage nodes in the second and fourth rows of the DRAM cell structures when storing data "0", respectively.

[0183] In addition, Figure 28 In the diagram, BL1n to BL4n represent the bit lines BL of the DRAM cell structure in the first to fourth rows, respectively, where 1 ≤ n ≤ N, and GBLref and BLref are the common bit line and the reference bit line used as references, respectively (not shown in the diagram). Furthermore, in... Figure 28 In the diagram, GBL1(1) indicates that the DRAM cell structure connected to the common bit line GBL1 stores "1" data, while GBL2(0) indicates that the DRAM cell structure connected to the selected common bit line GBL2 stores "0" data. For the sake of simplicity, the timing diagrams corresponding to the cases of GBL1(0) and GBL2(1) are omitted here.

[0184] In addition, Figure 28 In this diagram, BL1n(1) and BL3n(1) indicate that the data stored in the DRAM cell structure connected to bit lines BL1n and BL3n is "1", while BL2n(0) and BL4n(0) indicate that the data stored in the DRAM cell structure connected to bit lines BL2n and BL4n is "0". For the sake of simplicity, the timing diagrams corresponding to the cases of BL1n(0), BL2n(1), BL3n(0), and BL4n(1) are omitted here.

[0185] First, according to the embodiments of this disclosure, such as Figure 28As shown, common selection lines GBLS11 and GBLS12 are selected and activated to a logic high level, causing the bit lines BL of the DRAM cell structures in the first row group to be connected to the corresponding common bit line GBL1 or GBL2. During the precharge period BL-PREC, all common bit lines GBL and BL, as well as the common bit line GBLref and the bit line BLref used as references, can be precharged to the reference voltage VPREC, i.e., VDD / 2. At this time, word lines WLAl1 and WLBl1 (where 1≤l≤L) and the sense amplifier enable signal SAEN are not enabled.

[0186] Subsequently, as Figure 28 As shown, after the precharge period BL-PREC, the common selection lines GBLS11 and GBLS12 are disabled to logic low, causing the bit lines BL of the DRAM cell structures in the first row group to be disconnected from the corresponding common bit lines GBL1 or GBL2. Furthermore, as... Figure 28 As shown, after the precharge period BL-PREC, word lines WLA11 and WLBl1 are selected and activated to logic high, causing the gating transistors of the DRAM cell structure of the first row group of the first layer connected to word lines WLA11 and WLBl1 to turn on. This connects the storage capacitors of the DRAM cell structure to the corresponding bit line BL, resulting in the first charge transfer. It should be noted that since the common select lines GBLS11 and GBLS12 are disabled to logic low at this time, the bit line BL of the DRAM cell structure of the first row group of the first layer is not connected to the corresponding common bit line GBL. Therefore, the first charge transfer only involves the capacitance CS of the storage capacitor and the parasitic capacitance CBL of the bit line BL. Define the first charge transfer ratio CTR1 = CS / (CS+CBL), then the signal difference ΔVBL1 obtained on the bit line BL after the first charge transfer is ΔVBL1 = (VCS-VDD / 2) × CTR1 = (VCS-VDD / 2) × CS / (CS+CBL).

[0187] If the data stored in the storage capacitor of the DRAM cell structure connected to bit line BL is "1", for example Figure 28 In the cases shown by VCS1n(1) and VCS3n(1), the voltages of the corresponding bit lines BL1n and BL3n rise slightly relative to the reference bit line BLref due to the charge flowing from the corresponding bit lines BL1n and BL3n to the storage capacitor. The rise is ΔVBL1=(VCS-VPREC)×CS / (CS+CBL). At this time, the voltages of the storage capacitors VCS1n(1) and VCS3n(1) of the DRAM cell structure storing the data "1" decrease due to the charge inflow.

[0188] Similarly, if the data stored in the storage capacitor of the DRAM cell structure connected by the bit line BL is "0", for example... Figure 28 In the cases shown by VCS2n(0) and VCS4n(0), the voltages of bit lines BL2n and BL4n decrease slightly relative to the reference bit line BLref due to the charge flowing from the storage capacitor to the corresponding bit lines BL2n and BL4n, with a decrease of ΔVBL1. At this time, the voltages of the storage capacitors VCS2n(0) and VCS4n(0) of the DRAM cell structure storing data "0" increase due to the charge outflow.

[0189] Subsequently, as Figure 28 As shown, during the period when the first sub-read operation is performed on the DRAM cell structure of the first sub-row group (i.e., the first row and the second row) of the first row group, the common select line GBLS11 is activated to a logic high level, causing the bit lines BL1n and BL2n of the DRAM cell structure of the first sub-row group (i.e., the first row and the second row) of the first row group to be reconnected to the common bit lines GBL1 and GBL2, respectively. At this time, due to the introduction of the parasitic capacitance CGBL of the common bit lines GBL1 and GBL2, a second charge transfer occurs. Unlike the first charge transfer, the second charge transfer involves the capacitance CS of the storage capacitor, the parasitic capacitance CBL of the bit line BL, and the parasitic capacitance CGBL of the common bit line. Define the second charge transfer ratio CTR2 = (CS + CBL) / (CS + CBL + CGBL). Then, the signal difference ΔVBL2 obtained on the bit line BL after the second charge transfer is ΔVBL1 × CTR2 = (VCS - VDD / 2) × CS / (CS + CBL + CBL), where the total charge transfer ratio CTR after the two charge transfers is CTR1 × CTR2 = CS / (CS + CBL + CBL). Figure 25 The definitions in the read operation methods are consistent.

[0190] At this time, if the data stored in the storage capacitor of the DRAM cell structure connected to bit line BL is "1", for example... Figure 28 In the case shown by VCS1n(1), due to the flow of charge from the common bit line GBL1 to the storage capacitor and bit line BL1n, the voltage of the common bit line GBL1 increases slightly relative to the common bit line GBLref used as a reference, with an increase of ΔVGBL=ΔVBL2=(VCS-VPREC)×CS / (CS+CBL+CGBL). At this time, the voltage VCS1n(1) of the storage capacitor of the DRAM cell structure storing data "1" further decreases due to the inflow of charge. Correspondingly, since the charge of the common bit line GBL1 also flows to the bit line BL1n, the voltage of the bit line BL1n also decreases slightly, with a decrease of ΔVBL1-ΔVBL2.

[0191] Similarly, if the data stored in the storage capacitor of the DRAM cell structure connected by the bit line BL is "0", for example... Figure 28 In the case shown by VCS2n(0), the voltage of the common bit line GBL1 decreases slightly relative to the reference common bit line GBLref due to the charge flowing from the storage capacitor and bit line BL2n to the common bit line GBL1, with a decrease of ΔVGBL. At this time, the voltage of the storage capacitor VCS2n(0) of the DRAM cell structure storing data "0" increases further due to the charge outflow. Correspondingly, since the charge of bit line BL2n also flows to the common bit line GBL1, the voltage of bit line BL2n also increases slightly, with an increase of -(ΔVBL1-ΔVBL2).

[0192] It should be noted that since the common selection line GBLS12 is still disabled at logic low level at this time, the bit lines BL3n and BL4n of the DRAM cell structure of the second sub-row group (i.e., the third and fourth rows) of the first row group are still disconnected from the common bit line GBL2. Therefore, the voltage of bit line BL3n remains at VPREC+ΔVBL1, while the voltage of bit line BL4n remains at VPREC-ΔVBL1.

[0193] Subsequently, the sense amplifier enable signal SAEN is enabled to a logic high level, causing the sense amplifiers of the common bit line / bit line GBL / BL and the reference common bit line / reference bit line GBLref / BLref of the DRAM cell structure connected to the first sub-row group (i.e., the first row and the second row) of the first row group to amplify the voltage difference, ΔVGBL, between them. Specifically, the sense amplifier pulls up the voltage of the common bit line GBL1(1) to VDD, pulls down the voltage of the reference common bit line GBLref to GND, and pulls up the voltage of bit line BL1n(1) to VDD, and pulls down the voltage of the reference bit line BLref to GND. In addition, the sense amplifier pulls down the voltage of the common bit line GBL2(0) to GND, pulls up the voltage of the reference common bit line GBLref to VDD, and pulls down the voltage of bit line BL2n(0) to GND, and pulls up the voltage of the reference bit line BLref to VDD. At this time, as Figure 28 As shown in VCS1n(1) and VCS2n(0), the data is rewritten to the storage capacitors of the selected DRAM cell structure to reconstruct the original data.

[0194] Simultaneously, the bitline data amplified by the sense amplifier is transmitted to the input / output buffer DQ via the input / output line and outputs stable data DQout (m=1,2) of the DRAM cell structure of the first sub-row group (i.e., the first row and the second row) of the first row group. Subsequently, the common selection line GBLS11 and the sense amplifier enable signal SAEN are disabled to logic low, thereby completing the read operation of the DRAM cell structure of the first sub-row group (i.e., the first row and the second row) of the first row group.

[0195] Subsequently, as Figure 28 As shown, during the period when the second sub-read operation is performed on the DRAM cell structure of the second sub-row group (i.e., the third and fourth rows) of the first row group, the common select line GBLS12 is activated to a logic high level, causing the bit lines BL3n and BL4n of the DRAM cell structure of the second sub-row group (i.e., the third and fourth rows) of the first row group to be reconnected to the common bit lines GBL1 and GBL2, respectively. At this time, due to the introduction of the parasitic capacitance CGBL of the common bit lines GBL1 and GBL2, a second charge transfer occurs. Unlike the first charge transfer, the second charge transfer involves the capacitance CS of the storage capacitor, the parasitic capacitance CBL of the bit line BL, and the parasitic capacitance CGBL of the common bit line.

[0196] like Figure 28 As shown, the operation method of the second sub-read operation is the same as that of the first sub-read operation described above; therefore, for the sake of brevity, it will not be described in more detail. According to Figure 28 The read operation in this embodiment may include the following steps: pre-charge bit lines, first charge transfer, sensing amplification / data write-back of the first sub-row group, data output of the first sub-row group, sensing amplification / data write-back of the second sub-row group, and data output of the second sub-row group. This is significantly different from the read operation method of existing DRAM memory, namely... Figure 28 In the read operation shown, the charge transfer includes two charge transfers: a first charge transfer and a second charge transfer. The first charge transfer operates on all rows of the entire row group, while the second charge transfer operates on different sub-row groups at different times.

[0197] Figure 29 It shows Figure 27A and Figure 27B The timing diagram for write operations of the DRAM cell structure in the first row shown. Figure 29 Zhongyu Figure 28 The same reference numerals have the same meaning as those in the reference figures. Figure 28The same physical meaning. According to embodiments of this disclosure, a write operation can be performed twice on the four rows of DRAM cell structures (i.e., s = 1 to 4) in the first row group. The first sub-write operation can be performed on the first sub-row group, i.e., the first and second rows (i.e., s = 1 and 2) of the DRAM cell structures, while the second sub-write operation can be performed on the second sub-row group, i.e., the third and fourth rows (i.e., s = 3 and 4) of the DRAM cell structures. According to embodiments of this disclosure, it is possible to use... Figure 29 The write operation shown is performed in the same manner on the DRAM cell structure of other row groups in the DRAM array structure. Figure 29 In this context, DQin represents the data being written.

[0198] contrast Figure 28 Reference Figure 29 You can see Figure 29 The timing of the write operation shown is as follows Figure 28 The timing of most of the read operations shown is the same, so for the sake of brevity, it will not be described repeatedly; the difference lies in the timing of the read operations. Figure 29 In the write operation shown, after the sense amplifier is enabled and the voltage difference ΔVGBL between the common bit line / bit line GBL / BL and the reference bit line GBLref / BLref is amplified, the external data applied to the selected common bit line / bit line GBL / BL is forcibly written into the storage capacitor of the corresponding DRAM cell structure.

[0199] Figure 29 Only the case where the externally written data is different from the original data stored in the storage capacitor of the DRAM cell structure is shown, i.e., the case where it is written from "0" to "1". Figure 29 The cases of "0→1" and "0" being written from "1" (in the original text) Figure 29 (1→0 in the context of the DRAM cell structure). For cases where the externally written data is identical to the original data stored in the memory capacitors of the DRAM cell structure, the timing diagrams of signals other than DQin are different. Figure 28 Same, therefore Figure 28 And not shown. According to Figure 29 The write operation in this embodiment may include the following steps: pre-charge bit lines, first charge transfer, sensing amplification / data write-back of the first sub-row group, data writing of the first sub-row group, sensing amplification / data write-back of the second sub-row group, and data writing of the second sub-row group. This is significantly different from the write operation method of existing DRAM memory.

[0200] According to embodiments of this disclosure, when each row group includes two sub-row groups, each sub-row group includes two rows of DRAM cell structures (i.e., S=4, T=2), and column addressing of the four rows of DRAM cell structures is performed using two sets of common bit lines (each set of common bit lines includes N common bit lines), the read operation of each row group can be implemented by performing two sub-read operations on each of the two sub-row groups using two common select lines. As another example, when each row group includes four sub-row groups, each sub-row group includes two rows of DRAM cell structures (i.e., S=8, T=2), and column addressing of the eight rows of DRAM cell structures is performed using two sets of common bit lines (each set of common bit lines includes N common bit lines), the read operation of each of the four sub-row groups can be implemented by performing four sub-read operations on each row group using four common select lines. The same applies to write operations. That is, as described above, when each row group includes S rows, operations can be performed on each row group using T sets of common bit lines (each set of common bit lines includes N common bit lines) and S / T common select lines. Thus, by adding a Select Transistor Layer (STL), the number of lines required to operate the DRAM array structure can be further simplified. That is, in the case where each row group includes an eight-row DRAM cell structure (S=8), the row group can be operated through four sets of common bit lines and two sub-operations (T=2). Alternatively, in the case where each row group includes an eight-row DRAM cell structure (S=8), the row group can also be operated through two sets of common bit lines and four sub-operations (T=4). More generally, according to the embodiments of this disclosure, assuming each row group includes S rows and each sub-row group includes T rows (1≤T≤S), and S is divisible by T, then the number of common bit line sets is T, and the number of sub-operations is S / T. Clearly, the smaller T is, the smaller the number of common bit line sets, the lower the GBL arrangement density, and the better the read / write performance; however, the larger the number of sub-operations, the longer the read / write operation time.

[0201] In addition, refer to Figures 27A to 29 According to the embodiments of this disclosure, since the number of common bit lines GBL is reduced, the spacing between common bit lines GBL can be increased, resulting in a reduction in the parasitic capacitance CGBL of the common bit lines GBL. This effectively increases the read voltage difference ΔVGBL, thereby further improving the overall performance of the DRAM array structure, such as power consumption, speed, and reliability.

[0202] Although this document contains numerous details, these details should not be construed as limiting the scope of this disclosure or any potentially claimed protection, but rather as descriptions of features that may be specific to a particular implementation. Some features described herein in the context of separate implementations may also be implemented in combination in a single implementation. Conversely, various features described in the context of a single implementation may also be implemented separately or in any suitable sub-combination in multiple implementations. Furthermore, although features may be described above as functioning in certain combinations, and even initially stated so, in some cases one or more features may be removed from the claimed combination, and the claimed combination may involve sub-combinations or variations thereof.

Claims

1. A three-dimensional dynamic random access memory (DRAM) array structure, comprising: Multiple DRAM cell structures are arranged in L layers, M rows, and N columns, where L, M, and N are natural numbers greater than 0. Each of the multiple DRAM cell structures includes: The first transistor and the second transistor each have a tubular channel and a gate surrounding the channel, which are sequentially arranged in a vertical direction and electrically connected in parallel. A storage capacitor having a tubular structure is disposed vertically between the first transistor and the second transistor, its inner electrode being connected to the first source / drain of the first transistor and the second transistor, and its outer electrode being connected to the source line; M×N bit lines extend vertically inside the tubular structure formed by the first transistor, the second transistor, and the storage capacitor in the M-row N-column DRAM cell structure, and are respectively connected to the second source / drain of the first transistor and the second transistor in the M-row N-column DRAM cell structure. L×M first word lines extend along the first horizontal direction and are respectively connected to the gates of the first transistors in the L-layer M-row DRAM cell structure; L×M second word lines, extending along the first horizontal direction and respectively connected to the gates of the second transistors in the L-layer M-row DRAM cell structure; and One or more common bit line groups extend along a second horizontal direction perpendicular to the first horizontal direction, and each common bit line group includes N common bit lines. Each of the M×N bit lines has a selection transistor above and / or below it for connecting the bit line and the common bit line.

2. The three-dimensional DRAM array structure according to claim 1, in, When the selection transistor is disposed above and below each of the M×N bit lines, a portion of the common bit lines in the one or more common bit line groups are disposed above the M×N bit lines, and the remaining portion of the common bit lines in the one or more common bit line groups are disposed below the M×N bit lines.

3. The three-dimensional DRAM array structure according to claim 1, in, The three-dimensional DRAM array structure includes a common bit line group. Each of the N common bit lines included in the common bit line group is connected via a selection transistor to a bit line with the same column number in each row of the DRAM cell structure, and In this configuration, the gate of the select transistor in each row of DRAM cell structures is connected to a common select line.

4. The three-dimensional DRAM array structure according to claim 3, wherein, The N DRAM cell structures in each row and each layer operate simultaneously through the N common bit lines.

5. The three-dimensional DRAM array structure according to claim 1, in, The M-row DRAM cell structure is divided into M / S row groups, where S is a natural number greater than 1 that is divisible by M. Each row group has an S-row DRAM cell structure. In this configuration, the first character line of each layer in each row group is connected by a common first character line, and the second character line of each row group is connected by a common second character line. The three-dimensional DRAM array structure includes S common bit line groups. Each of the N common bit lines in each of the S common bit line groups is connected via a select transistor to a bit line having the same row number and column number in each row group. In this configuration, the gate of the selection transistor in each row group of the DRAM cell structure is connected to a common selection line.

6. The three-dimensional DRAM array structure according to claim 5, wherein, Each row group contains S×N DRAM cell structures in each layer that operate simultaneously through the S common bit line groups.

7. The three-dimensional DRAM array structure according to claim 1, in, The M-row DRAM cell structure is divided into M / S row groups, where S is a natural number greater than 1 that is divisible by M. Each row group has an S-row DRAM cell structure. Each row group is divided into S / T sub-row groups, where T is a natural number greater than 1 that divides S. Each sub-row group has a T-row DRAM cell structure. In this configuration, the first character line of each layer in each row group is connected by a common first character line, and the second character line of each layer in each row group is connected by a common second character line. The three-dimensional DRAM array structure includes T common bit line groups. Each of the N common bit lines in each of the T common bit line groups is connected via a select transistor to a bit line in each sub-row group that has the same row number and the same column number. In this configuration, the gate of the selection transistor in the DRAM cell structure of each sub-row is connected to a common selection line.

8. The three-dimensional DRAM array structure according to claim 7, wherein, The S×N DRAM cell structure of each layer in each row group is operated stepwise through the T common bit lines in sub-row groups.

9. The three-dimensional DRAM array structure according to claim 7, wherein, Each of the plurality of DRAM cell structures undergoes two charge transfers during read and write operations, wherein, Each row group's S×N DRAM cell structure in each layer undergoes its first charge transfer simultaneously during read and write operations, and Each layer of the T×N DRAM cell structure in each sub-row group undergoes a second charge transfer simultaneously during read and write operations.

10. The three-dimensional DRAM array structure according to claim 1, wherein, The selection transistor is a transistor having a tubular channel and a gate surrounding the channel, with its first source / drain connected to a bit line and its second source / drain connected to a common bit line.

11. The three-dimensional DRAM array structure according to claim 10, wherein, The first source / drain and second source / drain of the first transistor and the second source / drain of the second transistor, the channel region and the internal electrode of the storage capacitor of the L-layer DRAM cell structure of each of the M rows and N columns, as well as the first source / drain, second source / drain and channel region of the selection transistor of each of the M rows and N columns, are formed from the same semiconductor material layer.

12. The three-dimensional DRAM array structure according to claim 1, wherein, The plurality of DRAM cell structures are disposed on the substrate, and The selection transistor below the bit line is disposed in the substrate, with its first source / drain connected to the bit line and its second source / drain connected to the common bit line.

13. A method for operating the three-dimensional DRAM array structure of claim 1, in, The three-dimensional DRAM array structure includes a common bit line group. Each of the N common bit lines included in the common bit line group is connected via a selection transistor to a bit line with the same column number in each row of the DRAM cell structure, and In this configuration, the gate of the selection transistor in each row of DRAM cells is connected to a common selection line. The method includes: The N common bit lines simultaneously operate the N DRAM cell structures of each layer in each row.

14. A method for operating the three-dimensional DRAM array structure of claim 1, in, The M-row DRAM cell structure is divided into M / S row groups, where S is a natural number greater than 1 that is divisible by M. Each row group has an S-row DRAM cell structure. In this configuration, the first character line of each layer in each row group is connected by a common first character line, and the second character line of each row group is connected by a common second character line. The three-dimensional DRAM array structure includes S common bit line groups. Each of the N common bit lines in each of the S common bit line groups is connected via a select transistor to a bit line having the same row number and column number in each row group. In this configuration, the gate of the selection transistor in each row group of the DRAM cell structure is connected to a common selection line. The method includes: The S common bit line groups simultaneously operate the S×N DRAM cell structure of each layer in each row group.

15. A method for operating the three-dimensional DRAM array structure of claim 1, in, The M-row DRAM cell structure is divided into M / S row groups, where S is a natural number greater than 1 that is divisible by M. Each row group has an S-row DRAM cell structure. Each row group is divided into S / T sub-row groups, where T is a natural number greater than 1 that divides S. Each sub-row group has a T-row DRAM cell structure. In this configuration, the first character line of each layer in each row group is connected by a common first character line, and the second character line of each layer in each row group is connected by a common second character line. The three-dimensional DRAM array structure includes T common bit line groups. Each of the N common bit lines in each of the T common bit line groups is connected via a select transistor to a bit line in each sub-row group that has the same row number and the same column number. In this configuration, the gate of the selection transistor in the DRAM cell structure of each sub-row is connected to a common selection line. The method includes: The S×N DRAM cell structure of each layer in each row group is operated step-by-step through the T common bit line groups.

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