Memory device and manufacturing method

Abstract

The invention provides a memory device and a manufacturing method, and the memory device comprises the components of a semiconductor body which is provided with a first end and a second end which are oppositely arranged in a first direction; the grid structure comprises a grid main body extending along a second direction and a connecting end positioned at one end of the grid main body in the second direction; the connecting end is connected with the gate main body, the gate main body surrounds at least part of the side wall, extending in the first direction, of the semiconductor main body, and the connecting end is provided with a first part extending in the direction intersecting with the second direction and deviating from the gate main body; the first connecting structure is positioned on the connecting end and is in contact with at least partial area of the connecting end; a bit line extending in a third direction, the bit line coupled to a first end of the semiconductor body; the third direction intersects with the second direction, and a plane formed by the third direction and the second direction intersects with the first direction.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a storage device and a method for manufacturing it. Background Technology

[0002] Some memory devices may include memory arrays and peripheral circuitry. The peripheral circuitry controls the memory array, performing read, write, or refresh operations. A memory array comprises multiple memory cells arranged in rows and columns. Each memory cell may include coupled transistors and memory structures. Turning on the transistors selects and accesses the memory cell. The memory cell may include capacitors, phase-change capacitors, and resistive switching capacitors, among other memory structures. There is considerable room for improvement in both memory devices and their fabrication methods to enhance their performance. Summary of the Invention

[0003] According to some aspects of embodiments of this application, a memory device is provided, comprising: a semiconductor body having a first end and a second end disposed opposite to each other in a first direction; a gate structure including a gate body extending along a second direction and a connection end located at one end of the gate body in the second direction; the connection end being connected to the gate body, the gate body surrounding at least a portion of a sidewall of the semiconductor body extending along the first direction, the connection end having a first portion extending in a direction intersecting the second direction and away from the gate body; a first connection structure located on the connection end and in contact with at least a portion of the connection end; a bit line extending along a third direction, the bit line being coupled to the first end of the semiconductor body; the third direction intersecting the second direction, and the plane formed by the third direction and the second direction intersecting the first direction.

[0004] According to some aspects of embodiments of this application, a method for fabricating a memory device is provided, comprising: forming a plurality of semiconductor bodies extending along a first direction; forming an annular trench extending at least along a second direction, wherein adjacent semiconductor bodies in a third-third upward direction are respectively located in regions of the annular trench extending along the second direction; the regions of the annular trench extending along the second direction surround at least a portion of the sidewalls of the semiconductor bodies extending along the first direction; the annular trench surrounds a dielectric material between adjacent semiconductor bodies in a third-third upward direction; based on the annular trench, oxidizing the sidewalls of the semiconductor bodies exposed in the annular trench to form a gate dielectric layer; filling the annular trench to form an annular gate; and etching two regions of the annular gate extending along the second direction away from the plurality of semiconductor bodies at both ends of the annular gate in the second direction, respectively, to form two cuts; wherein the two cuts are misaligned in both the second direction and the third-third upward direction, and the two cuts divide the annular gate into two gate structures.

[0005] This application provides a memory device, including: a semiconductor body having a first end and a second end disposed opposite to each other in a first direction, and a gate structure including a gate body extending in a second direction and a connection end located at one end of the gate body in the second direction, the connection end being connected to one end of the gate body, the gate body surrounding at least a portion of a sidewall extending in the first direction of the semiconductor body, and the connection end having a first portion extending away from the gate body in a direction intersecting the second direction; further including a first connection structure located on the connection end and contacting at least a portion of the connection end, and a bit line including a bit line extending in a third direction and coupled to the first end of the semiconductor body; the application provides that a portion of the gate structure surrounds the sidewall of the semiconductor body to increase the control capability of the gate to the channel, while increasing the width of the gate to increase the landing and contact area of ​​the first connection structure to reduce contact resistance and contact failure; the connection end in the gate structure for landing the first connection structure has a first portion protruding in a direction intersecting the second direction, further increasing the width of the connection end, further increasing the landing area of ​​the first connection structure, and further reducing the contact resistance. Attached Figure Description

[0006] Figures 1 to 3 This is a schematic diagram of a storage device provided in an exemplary embodiment of this application; Figures 4 to 11 This is a schematic diagram of the storage device provided in the embodiments of this application; Figure 12 This is a schematic flowchart of a storage device manufacturing method provided in an embodiment of this application; Figures 13 to 25 This is a schematic diagram of a method for manufacturing a storage device provided in an embodiment of this application. Detailed Implementation

[0007] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this application. However, it will be apparent to those skilled in the art that this application can be practiced without one or more of these details. In other instances, to avoid confusion with this application, some technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0008] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this application, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this application.

[0009] Spatial relation terms such as “below,” “under,” “below,” “below,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0010] It should be understood that the phrases "some embodiments" or "an embodiment" throughout the specification mean that a specific feature, structure, or characteristic related to an embodiment is included in at least one embodiment of this application. Therefore, "some embodiments" or "an embodiment" appearing throughout the specification do not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this application, the sequence numbers of the above processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0011] The memory device in the embodiments of this application may be a DRAM memory device or device, or at least a portion of the memory devices in DRAM, or the memory device may include DRAM, and the DRAM may include the memory device of this application. It is applicable to DDR4 memory specifications, DDR5 memory specifications, double data rate synchronous dynamic random access memory, and LPDDR5 memory specifications, low power double data rate synchronous dynamic random access memory. It should be noted that the embodiments of this application are not limited to DRAM, but in the following description, for the sake of clarity, only DRAM will be used as an example.

[0012] In DRAM, memory arrays can be arranged in rows and columns, allowing memory cells to be addressed by specifying their rows and columns. A memory array includes multiple word lines corresponding to rows and multiple bit lines corresponding to columns. The word lines and bit lines intersect; selecting the memory cell at the intersection of the selected word line and bit line selects it for read, write, or refresh operations. Figure 1 As exemplified, the memory array may include multiple word lines WLn, WLn+1, WLn-1, and WLn-2, ​​and multiple bit lines BLn, BLn+1, BLn-1, and BLn-2, ​​with the word lines and bit lines intersecting. The memory cells in the memory array may include capacitors and transistors; a memory cell may include one transistor and one capacitor. The word lines may also be conductive structures such as gate layers, serving as the gates of transistors. One controlled terminal (source) of the transistor is coupled to one electrode of the capacitor, and the other controlled terminal (drain) of the transistor is coupled to the bit line. The other electrode of the capacitor may be grounded or have another voltage (such as Vcc / 2) applied to it. Figure 1 As shown, the memory cell array is arranged in an x-row, y-column configuration, with rows and columns that are either perpendicular or not. The extension direction of word lines or rows can be parallel to the x-direction or at an angle to it. The extension direction of bit lines or columns can be parallel to the y-direction or at an angle to it. The orthographic projection of the word line onto the xoy plane is perpendicular to the orthographic projection of the bit line onto the xoy plane, or they may be at an angle but not perpendicular; this embodiment does not impose any limitations on this. In the examples shown below, the z-direction can be a vertical direction, the wafer thickness direction, or the device thickness direction. The z-direction can be perpendicular to the xoy plane or intersect the xoy plane but not perpendicularly. The z-direction can be denoted as the first direction, the x-direction as the second direction, and the y-direction as the third direction. The x and y directions intersect perpendicularly. The second and third directions can be interchanged, which will not be elaborated further below.

[0013] In the storage array of this application embodiment, the storage cells are arranged in rows and columns. A row of the storage array may include transistors arranged along the x-direction and capacitors coupled to the transistors. A row may also be called a sub-storage array. A column of the storage array may include transistors arranged along the y-direction and capacitors coupled to the transistors. A column may also be called a sub-storage array.

[0014] In some embodiments, during read or write operations, a word line selection signal can be used to select the corresponding word line, and a column selection signal can be used to select the corresponding bit line. Simultaneous selection of the word line and bit line allows location of the selected memory cell. At this time, the transistor of the selected memory cell is turned on due to the operating voltage applied to the word line, thereby enabling read, write, or refresh operations on the selected memory cell. In some embodiments, the capacitor can be replaced with other memory structures, including but not limited to: phase-change memory structures, resistive switching memory structures, or magnetic switching memory structures.

[0015] In some embodiments, a capacitor represents a logical 1 or 0 by the amount of charge stored within it, or by the voltage difference across its terminals. A voltage signal on the word line is applied to the gate to control the transistor's on or off state, thus selecting or deselecting the capacitor. This allows data stored in the capacitor to be read via the bit line, or data to be written to the capacitor for storage via the bit line.

[0016] In some embodiments, the DRAM memory device or DRAM memory apparatus further includes... Figure 1 Peripheral circuitry coupled to the memory array. Exemplary examples of peripheral circuitry may include, but are not limited to: a sensing amplifier circuit, a row decoding circuit, a column decoding circuit, and a voltage generation circuit. The sensing amplifier circuit is coupled to bit lines and can be configured to capture weak voltage fluctuations on the bit lines and locally reconstruct the capacitor voltage of the memory cell based on the voltage fluctuations. The sensing amplifier circuit may include a latch to latch the reconstructed capacitor voltage value, thereby transferring the information stored in the memory cell from the capacitor to the amplifier circuit. The sensing amplifier circuit may include a differential sensing amplifier circuit coupled to two bit lines, operating using a selected bit line and a complementary bit line used as a reference line to detect and amplify the voltage difference between a pair of bit lines. The row decoding circuit is configured to address the memory array and apply an operating voltage to the word lines. The column decoding circuit is configured to column address the memory array, apply a bit line voltage, or receive a bit line voltage. The voltage generation circuit generates the required high and low voltages for each device.

[0017] According to some aspects of the embodiments of this application, Figure 2 A structural example of a storage device 10 is provided, the storage device 10 comprising: A plurality of semiconductor bodies 111 extending along the z-direction, each semiconductor body 111 having a first end (bottom end) and a second end (top end) disposed opposite each other in the z-direction; a gate structure 120 extending along the x-direction, the gate structure 120 being located on one side of the semiconductor bodies 111 along the y-direction; a gate dielectric layer 112 is provided between the gate structure 120 and the semiconductor bodies 111, the gate structure 120 at least covering the region between the first end and the second end; the region between the first end and the second end serves as the channel of a transistor, and the gate structure 120 serves as the control terminal of the transistor, controlling the transistor's conduction and cutoff by applying different voltages. Between two adjacent semiconductor bodies 111 in the y-direction, two gate structures 120 are disposed face-to-face, or the gate structure 120 is disposed at least around a portion of the sidewall of the semiconductor body 111 to increase the control force of the gate structure 120.

[0018] The cross-sectional shape of the semiconductor body 111 in the xoy plane may include, but is not limited to: rectangle, circle, ellipse, or other regular or irregular polygons and arcs; such as Figure 3 The rectangular shape of the semiconductor body 111 shown is merely an example; other shapes are also possible. The semiconductor body 111 has doped ends along the z-direction to form active regions, serving as the source or drain of a transistor, respectively. The region between the source and drain serves as the channel of the transistor, and the positions of the source and drain are interchangeable. The transistor may include the semiconductor body 111, a partial gate structure 120 corresponding to or overlapping the semiconductor body 111, and a gate dielectric layer 112 between the gate structure 120 and the semiconductor body 111. The gate structure 120 may serve as a word line of the memory device 10, extending along the x-direction, and may be coupled to or correspond to multiple semiconductor bodies 111 arranged in the x-direction.

[0019] Storage device 10 also includes Figure 2 The bit line 132 shown extends along the y direction and is coupled to a plurality of semiconductor bodies 111 arranged in the y direction. The bit line 132 is coupled to the first end of the semiconductor body 111. Figure 2As shown, the first ends of the plurality of semiconductor bodies 111 arranged in the y-direction are interconnected by semiconductor material. The semiconductor material at the bottom of the first end is used to form bit lines 132 or to carry bit lines 132. The semiconductor material is the leftover material from etching the semiconductor layer to make the semiconductor bodies 111, so as to reduce the etching depth; there may be no obvious physical boundary between the semiconductor material and each semiconductor body 111. The constituent materials of the semiconductor bodies 111 and the semiconductor material may include, but are not limited to: elemental semiconductor materials (e.g., silicon, germanium), III-V compound semiconductor materials, II-VI compound semiconductor materials, organic semiconductor materials, or other semiconductor materials known in the art. Bit lines 132 may include metallic conductive materials, and bit lines 132 may also include semiconductor metallization materials, such as titanium silicide, nickel silicide, and other metal silicides. Bit lines 132 may also be formed by heavily doping semiconductor materials to form conductive lines.

[0020] For example, the semiconductor material may include silicon, and the bit line 132 may include a metal silicide. The bit line 132 can be formed based on the semiconductor material, such as by metallizing the semiconductor material to form a metal compound to constitute the bit line 132, or by depositing a metal material on the side of the semiconductor material away from the semiconductor body 111 in the z-direction to form the bit line 132, or by heavily doping the side of the semiconductor material away from the semiconductor body 111 in the z-direction to form a conductive line. Depositing a metal material on the side of the semiconductor material away from the semiconductor body 111 in the z-direction and performing heat treatment allows a portion of the silicon in the semiconductor material to react with the metal material to form a metal silicide layer, thereby forming the bit line 132. The metal silicide may include, but is not limited to, titanium silicide, nickel silicide, etc. For example, conductive materials such as tungsten, aluminum, and titanium can be deposited on the metal silicide to form a bit line 132 with a composite material layer, improving the electrical connection performance between the bit line 132 and the semiconductor body 111 and reducing contact resistance. In other embodiments, the bottom of the first end of the semiconductor body 111 is not connected to any semiconductor material, the bottom of the semiconductor bodies 111 arranged in the y direction is not connected to any semiconductor material, and the bottom of the semiconductor bodies 111 arranged in the x direction is also not connected to any semiconductor material; a conductive material is deposited on the bottom (first end) of the semiconductor bodies 111 arranged in the y direction to form a bit line 132, and the bit line 132 is coupled to the first end of the semiconductor body 111.

[0021] In some embodiments, Figure 2The memory device 10 also includes a capacitor structure 131 located at one end of the semiconductor body 111 away from the bit line 132, and the capacitor structure 131 is coupled to the second end (top) of the semiconductor body 111. The capacitor structure 131 may include a first electrode coupled to the second end of the semiconductor body 111, with the source and drain electrodes interchangeable; it also includes a second electrode and a dielectric layer located between the second electrode and the first electrode; multiple capacitor structures 131 may share a second electrode and be connected to a common voltage, such as ground or other operating voltage. Selecting the semiconductor body 111 (or transistor) corresponding to both the gate layer and the bit line 132 simultaneously turns on the semiconductor body 111 to select the coupled capacitor structure 131, and performs write, refresh, or read operations by charging and discharging the capacitor structure 131 or sensing the amount of charge. The capacitor structure 131 may be directly coupled to the semiconductor body 111 or coupled through a contact portion, which may include, but is not limited to, metal, metal silicide, or a combination thereof.

[0022] In some embodiments, Figure 3 The diagram shows a partial layout of the storage device 10 in the xoy plane. The storage device 10 also includes a first connection structure 133, coupled to a corresponding gate structure 120 to provide power or output electrical signals to the gate structure 120. The first connection structure 133 is located at the end of the gate structure 120 in the x-direction. The first connection structures 133 on adjacent gate structures 120 are located at different ends of the gate structure 120 and are not aligned in the y-direction. The first connection structures 133 on odd-numbered gate structures 120 are at the first end (left end), and the first connection structures 133 on even-numbered rows of gate structures 120 are at the second end (right end). Figure 3 The first connection structure 133 may be located at the end, completely covering the end or inside the end and close to the semiconductor body 111. In this embodiment, the first connection structure 133 is located outside the outermost edge of the semiconductor body 111 and connected to the gate structure 120. There is no specific restriction on whether the first connection structure 133 is strictly located at or within the endpoint of the gate structure 120. The various first connection structures 133 in the y-direction can be aligned, substantially aligned, or misaligned and arranged in an alternating pattern. In another embodiment, at least some of the first connection structures 133 may be arranged at the same end of the gate structure 120, for example, located at... Figure 3 The left or right end of the central grid structure 120.

[0023] For example, the first connection structure 133 may extend along the z-direction and may include, but is not limited to, conductive plugs, conductive channels, and conductive pillars. The first connection structure 133 and the gate structure 120 may include, but are not limited to, conductive materials such as tungsten, gold, silver, copper, chromium, nickel, titanium, aluminum, titanium silicide, tungsten silicide, nickel silicide, titanium nitride, and tungsten nitride. The materials of the first connection structure 133 and the gate structure 120 may be the same or different.

[0024] In some embodiments, Figure 3 The gate structure 120 has a smaller width in the y direction, which increases the difficulty of aligning and landing the first connection structure 133 and results in a smaller contact area with the first connection structure 133, leading to a larger contact resistance. Figure 3 In the present invention, the gap between the first connection structure 133 and the non-target gate structure 120 is small, which increases the risk of discharge and accidental contact between the first connection structure 133 and the non-target gate structure 120. In view of this, the present invention provides a memory device 10 in which the gate structure 120 surrounds at least part of the sidewall of the semiconductor body 111, and optimizes the power supply scheme at both ends of the first connection structure 133, increases the width of the gate structure 120, reduces the landing difficulty of the first connection structure 133, increases the contact area between the gate structure 120 and the first connection structure 133, and reduces the risk of accidental contact between the first connection structure 133 and the non-target gate structure 120.

[0025] According to some aspects of the embodiments of this application, Figure 4 A front view or projection schematic diagram of a storage device (or a portion thereof) on the yoz plane is provided. Figure 5 Provides a schematic diagram of the layout of storage device 10 in the xoy plane; storage device 10 includes at least: Semiconductor body 111 has a first end (bottom end) and a second end (top end) disposed opposite each other in a first direction (z direction); gate structure 120 includes a gate body 121 extending in a second direction (x direction) and a connection end 122 located at one end of the gate body 121 in the x direction; the connection end 122 is connected to the gate body 121, the gate body 121 surrounds at least a portion of a sidewall of the semiconductor body 111 extending in the z direction, and the connection end 122 has a first portion extending in a direction intersecting the x direction and away from the gate body 121; a first connection structure 133 is located on the connection end 122 and contacts at least a portion of the connection end 122; bit line 132 extends in the y direction and is coupled to the first end of the semiconductor body 111; the y direction intersects the x direction, and the plane formed by the y direction and the x direction intersects the z direction.

[0026] In some embodiments, Figure 4 As shown, the memory device 10 further includes: a gate dielectric layer 112 located between the semiconductor body 111 and the gate structure 120; a capacitor structure 131 located on one side of the semiconductor body 111 away from the bit line 132; and the capacitor structure 131 is coupled to the second end of the semiconductor body 111.

[0027] Figure 4 For an explanation of the semiconductor body 111, bit line 132, and capacitor structure 131, please refer to the previous text. Figure 2As previously mentioned, this will not be repeated here. Figure 4 In the diagram, the gate structure 120 surrounds the sidewall of the semiconductor body 111 along a direction perpendicular to the z-axis. The gate dielectric layer 112 is located between the gate structure 120 and the semiconductor body 111 but is obscured by the gate structure 120 and is not shown. The gate dielectric layer 112 is... Figure 5 As shown in the image. Figure 6 It shows Figure 5 A schematic diagram of the cross-section along the z-direction at point AA'. Figure 6 The diagram shows a gate dielectric layer 112; wherein the gate dielectric layer 112 may be the same as or different from the filling dielectric material between the semiconductor body 111. When the gate dielectric layer 112 and the filling dielectric material are the same, there may be no obvious physical boundary between the two film layers; similarly, there is also no obvious physical boundary after other identical dielectric materials come into contact.

[0028] Reference Figure 5 As shown, the gate structure 120 extends along the x-direction as a whole, and has a portion protruding at one end of the gate structure 120 in a direction intersecting the x-direction, such as protruding along the y-direction or in a direction having a certain angle with the y-direction. The end with the protruding portion is used to land and couple to the first connection structure 133 to increase the contact area and reduce the contact resistance.

[0029] In some embodiments, Figure 7 A partial enlarged schematic diagram of the gate structure is shown. Figure 7In the process, two gate structures 120 closely arranged in the y direction, such as the first gate structure 120a and the second gate structure 120b, can be formed by cutting and breaking two sides extending in the x direction from a ring gate. The ring gate is surrounded by two regions extending in the x direction and two regions extending in directions intersecting the x direction (such as in the y direction). The gate cuts 143 (or gaps) are located at both ends of the ring gate and outside the outermost semiconductor body 111. The two cuts 143 are staggered vertically and are not aligned in the x and y directions. The two cuts 143 can be filled with dielectric material for isolation; or the first gate structure 120a and the second gate structure 120b are deposited and formed respectively, and there is a gap between the two gate structures 120. The position of the cut 143 or the centerline can be used as a boundary to divide a gate structure 120 (such as the first gate structure 120a) into two parts: a gate body 121 extending along the x-direction, and a connecting end 122 located at one end of the gate body 121 in the x-direction. The connecting end 122 is the end of the gate structure 120 on one side in the x-direction. The connecting end 122 has a first part (123a or 123b) extending along the x-direction and protruding away from the gate body 121. In this embodiment, the first part (123a or 123b) extending along the y-direction is used as an example for illustration. The division of the gate body 121, the connecting end 122, the first part, and other parts of the gate structure 120 is only for illustrative purposes. There are no physical boundaries between the components; they are manufactured as a single unit.

[0030] Reference Figure 7 As shown, the semiconductor body 111 has a rectangular or nearly rectangular cross-sectional shape in the xoy plane. The semiconductor body 111 has four sidewalls extending along the z direction. The gate body 121 (or a portion of the gate structure 120) surrounds three sidewalls of the semiconductor body 111, or in other examples, it may surround four sidewalls of the semiconductor body 111. Figure 7 The gate dielectric layer 112 is located between the semiconductor body 111 and the gate body 121, and surrounds the three sidewalls of the semiconductor body 111. Compared with the gate structure 120 located on one side of the semiconductor body 111 and not surrounding the semiconductor body 111, the gate structure 120 surrounding the semiconductor body 111 is beneficial to increase the control capability of the gate to the channel, and at the same time increases the width of the gate, thereby increasing the landing and contact area of ​​the first connection structure 133 to reduce contact resistance and contact failure; the connection end 122 of the gate structure 120 may include at least a first portion extending in the y direction, further increasing the width of the connection end 122, further increasing the landing area of ​​the first connection structure 133, and further reducing the contact resistance.

[0031] In some embodiments, Figure 7As shown, the connection end 122 includes: a second part 124a and a third part 125a extending along the x direction; the second part 124a and the third part 125a are connected through a first part 123a; the second part 124a is connected to the gate body 121, and the third part 125a is located on the side of the first part 123a away from the second part 124a.

[0032] Figure 7 In this configuration, the gate structure 120 can be formed by dividing an annular gate into a first gate structure 120a and a second gate structure 120b by two cuts 143; or the first gate structure 120a and the second gate structure 120b can be deposited separately. For example, using... Figure 7 Taking the first gate structure 120a as an example, the first gate structure 120a includes a first gate body 121a and a first connecting end 122a connected to one end of the first gate body 121a. The first connecting end 122a includes a second portion 124a connected to the end of the first gate body 121a and extending along the x-direction, a third portion 125a extending along the x-direction, and a first portion 123a extending along the y-direction and protruding away from the direction of the first gate body 121a. The first portion 123a is located between the second portion 124a and the third portion 125a and connects these two portions. (Comparison) Figure 3 The layout scheme Figure 7 The first connection structure 133 has a larger landing area, and the end of the gate structure 120 is cut off, which increases the distance between the first connection structure 133 and the non-target gate, reducing the risk of accidental contact.

[0033] In some embodiments, the first connection end 122a may be at least away from the first portion 123a of the gate body 121 along the y-direction, and if the cutout 143 is close to the end of the first gate structure 120a, the connection end may only include the first portion 123a. For example... Figure 7 The cut shown is on the side of the annular gate along the x-direction, relatively close to the outermost semiconductor body 111 but not in contact with the semiconductor body 111, so that the first connection terminal 122a has a first portion 123a extending along the y-direction and a second portion 124a and a third portion 125a extending along the x-direction.

[0034] In some embodiments, the first portion is connected to the end of the second portion opposite to the gate body, and the first portion is connected to the end of the third portion opposite to the gate body 121. Figure 7Taking the first connection terminal 122a of the first gate structure 120a as an example, the first part 123a of the first connection terminal 122a is connected to the ends of the second part 124a and the third part 125a that are away from the gate body 121 (or away from the outermost semiconductor body 111), so that the cross-sectional shape of the first connection terminal 122 in the xoy plane is U-shaped or close to U-shaped, and the opening of the U-shape faces the outermost semiconductor body 111; or the first connection terminal 122 has an opening facing the outermost semiconductor body 111.

[0035] In some embodiments, Figure 8 The example illustrates another gate structure 120, where the middle regions of the first and second parts are connected, and the middle regions of the first and third parts are also connected. Figure 8 Taking the first connection terminal 122a of the first gate structure 120a as an example, the first part 123a of the first connection terminal 122a is connected to the middle part of the second part 124a and the third part 125a respectively, that is, it approaches the outermost semiconductor body 111 from the end, so that the cross-sectional shape of the first connection terminal 122a in the xoy plane is I-shaped or close to I-shaped. The I-shape has two openings that are opposite to each other in the x direction and are arranged back to back, one of which faces the outermost semiconductor body 111. Or Figure 8 The first connection terminal 122a is an H-shape rotated 90°, with one opening of the H-shape facing the outermost semiconductor body 111.

[0036] In some embodiments, refer to Figure 7 and Figure 8 As shown, a ring gate is divided by two cuts 143 to form a first gate structure 120a and a second gate structure 120b. The first gate structure 120a includes a first gate body 121a and a first connecting end 122a. The second gate structure 120b includes a second gate body 121b and a second connecting end 122b.

[0037] In some embodiments, refer to Figure 7 and Figure 8 As shown, a gate body surrounds a portion of the sidewall extending along the z-direction of the semiconductor body 111. The semiconductor body 111 includes a first semiconductor body 111a and a second semiconductor body 111b disposed adjacent to each other in the y-direction. The memory device 10 includes a first gate body 121a and a second gate body 121b disposed at a distance in the y-direction. The sidewall of the first semiconductor body 111a exposed from the first gate body 121a and the sidewall of the second semiconductor body 111b exposed from the second gate body 121b are disposed back-to-back in the y-direction. Figure 7 and Figure 8In the semiconductor body 111 array, taking the first semiconductor body 111a and the second semiconductor body 111b in two adjacent rows as an example, the first gate body 121a surrounds the three sidewalls of the first semiconductor body 111a and exposes one sidewall in the positive x direction, and the second gate body 121b surrounds the three sidewalls of the second semiconductor body 111b and exposes one sidewall in the negative x direction; the two gate bodies 121 cover the portion of one row of semiconductor bodies 111 and are arranged face to face between the two rows of semiconductor bodies 111.

[0038] In some embodiments, refer to Figure 7 and Figure 8 As shown, the storage device 10 further includes: a first connection terminal 122a connected to the first gate body 121a, and a second connection terminal 122b connected to the second gate body 121b; wherein the first connection terminal 122a and the second connection terminal 122b are respectively located on opposite sides of the semiconductor body 111 in the x-direction, and the first connection terminal 122a and the second connection terminal 122b are aligned along the x-direction. The first connection terminal 122a and the second connection terminal 122b are respectively located on opposite sides of the two rows of semiconductor bodies 111 in the x-direction, and are aligned or substantially aligned along the x-direction.

[0039] In some embodiments, refer to Figure 7 and Figure 8 As shown, the third portion 125a of the first connecting end 122a is aligned with the end of the second gate body 121b opposite to the second connecting end 122b; the third portion 125b of the second connecting end 122b is aligned with the end of the first gate body 121a opposite to the first connecting end 122a. The third portion 125a of the first connecting end 122a and the second gate body 121b can be formed by breaking a continuous structure or by deposition separately, and the third portion 125a of the first connecting end 122a and the second gate body 121b are aligned or substantially aligned along the x-direction; similarly, the third portion 125b of the second connecting end 122b and the first gate body 121a are aligned or substantially aligned along the x-direction.

[0040] In some embodiments, Figure 9 Example Figure 8 Layout diagram of the central grid structure 120 and the first connecting structure 133; see reference. Figure 5 and Figure 9 As shown, the first connecting structure 133 can land on the first portion (123a or 123b) extending in the y-direction of the target connecting end 122, and the first connecting structure 133 contacts at least a portion of the first portion. In some embodiments, refer to Figure 10 As shown, it can be Figure 8 The outward-facing opening of the connecting end 122 is closed, but the opening is not filled. Figure 10The connecting end 122 may include two first portions 123 extending along the y-direction, and a second portion 124 and a third portion 125 extending along the x-direction. The two first portions 123 are spaced apart, and the outermost first portion 123 is connected to the ends of the second portion 124 and the third portion 125, respectively. (See reference...) Figure 11 As shown, the first connecting structures 133 in the y-direction can be staggered according to the two first parts 123 to increase the spacing of the first connecting structures 133 in the y-direction and reduce crosstalk. For example, the odd-numbered rows of first connecting structures 133 land on the inner first part 123, and the even-numbered rows of first connecting structures 133 land on the outer first part 123.

[0041] According to some aspects of the embodiments of this application, Figure 12 A method for manufacturing a storage device 10 is provided, comprising: Multiple semiconductor bodies extending along the first direction are formed; An annular trench is formed extending at least along a second direction, with each of the third-adjacent semiconductor bodies located in a region of the annular trench extending along the second direction; the region of the annular trench extending along the second direction surrounds at least a portion of a sidewall of the semiconductor body extending along the first direction; the annular trench surrounds a dielectric material between the third-adjacent semiconductor bodies. Based on the annular trench, the sidewalls of the semiconductor body exposed from the annular trench are oxidized to form a gate dielectric layer; The annular groove is filled to form an annular grid; At both ends of the annular gate away from the plurality of semiconductor bodies along the second direction, two regions extending along the second direction of the annular gate are etched and cut off to form two cuts; wherein the two cuts are not aligned in the second direction and in the third direction, and the two cuts divide the annular gate into two gate structures.

[0042] The semiconductor layer is etched to form multiple trenches extending along the x and y directions, dividing the semiconductor layer into multiple semiconductor bodies. The bottom of the semiconductor bodies arranged along the y direction may have remaining semiconductor material connected, or it may not be connected. The semiconductor layer can be a wafer (or substrate), or a semiconductor film epitaxially grown on a wafer. The semiconductor layer can be thinned on the back side. The formed semiconductor bodies can be similar to those described later. Figure 14 In an array configuration example, dielectric material or sacrificial material is filled into the gaps between semiconductor bodies 111, a patterned mask layer is formed according to the pattern of the annular gate 153, and the dielectric material is etched using the mask layer as an etch mask to form... Figure 20 The annular groove 160 shown, or forming Figure 25The annular trench 160 shown; adjacent semiconductor bodies 111 in the y-direction are respectively located in regions of the annular trench 160 extending in the x-direction; the region of the annular trench 160 extending in the x-direction surrounds at least a portion of the sidewalls of the semiconductor bodies 111 extending in the z-direction, such as surrounding the three sidewalls of the semiconductor bodies 111; the annular trench 160 surrounds the dielectric material between adjacent semiconductor bodies 111 in the y-direction. Figure 21 As shown, an oxidant, such as oxygen, hydrogen peroxide, or nitric acid, is introduced into the annular trench 160, and the sidewalls of the semiconductor body 111 are self-oxidized to form a gate dielectric layer 112.

[0043] Figure 22 In the process, an annular gate 153 is formed by filling the annular trench 160 with conductive material; the filling process may include, but is not limited to, physical vapor deposition, chemical vapor deposition, atomic layer deposition, electroplating, or any combination thereof. Figure 23 As shown, at both ends of the annular gate 153 away from the plurality of semiconductor bodies 111 along the x-direction, two regions extending along the x-direction of the annular gate 153 are etched and cut off, forming two notches 143. The two notches 143 are misaligned in both the x and y directions, dividing the annular gate 153 into two gate structures 120. The notches 143 are subsequently filled with dielectric material to electrically isolate the two gate structures 120. The notches 143 are located at the two x-direction extending side ends of the annular gate 153, away from the outermost semiconductor body 111. The two notches 143 are staggered in the y-direction, with one notch 143 located on the rightmost side of the odd-numbered rows of semiconductor bodies 111 and the other notch 143 located on the leftmost side of the even-numbered rows of semiconductor bodies 111. Other fabrication methods may also be used for the semiconductor bodies 111 and the annular trench 160.

[0044] In some embodiments, the method of forming the semiconductor body 111 includes: Figure 13 As shown, a plurality of semiconductor strips 101 are formed at intervals along the x-direction, and the semiconductor strips 101 extend along the y-direction; a first sacrificial material 102 is formed surrounding the plurality of semiconductor strips 101; the semiconductor strips 101 are formed by etching a semiconductor layer; Figure 14 As shown, the semiconductor strip 101 and the first sacrificial material 102 are etched to form a plurality of first trenches extending along the x-direction and a second trench 142 surrounding the plurality of first trenches 141; the first trenches 141 divide the semiconductor strip 101 into a plurality of semiconductor bodies 111; the remaining first sacrificial material 102 between the second trenches 142 and the first trenches 141 forms a first sacrificial structure 151; the outer contour shape of the first sacrificial structure 151 is the same as the outer contour shape of the annular gate 153. Figure 14As shown, the second trench 142 is an annular trench, and the second trench 142 is surrounded by the first sacrificial material 102. The second trench 142 can be used to fill dielectric material and isolate it from other device structures, such as to isolate the memory array from the peripheral circuit. Figure 14 The second annular groove 142 includes a strip groove region located between adjacent first sacrificial structures 151 in the y-direction, the strip groove extending in the x-direction.

[0045] Figure 14 The film material at the bottom of the first trench 141 and the second trench 142 is not shown; only the location and extension direction of the trench are illustrated. The bottom of the trench can be a semiconductor substrate, a dielectric layer, or a wafer, etc. The bottom material of each trench and other structure described below is also not shown and does not affect the implementation of the fabrication method of this application.

[0046] In some embodiments, refer to Figure 15 As shown, a second sacrificial material 103 is deposited in the second trench 142 and the first trench 141. The second sacrificial material 103 and the first sacrificial material 102 have a large difference in etch selectivity or etch rate in a certain etching process. The first sacrificial material 102 and the second sacrificial material 103 are different materials. For example, the first sacrificial material 102 may include, but is not limited to, silicon oxide; the second sacrificial material 103 may include, but is not limited to, carbon, such as amorphous carbon or spin-coated carbon. (Refer to...) Figure 16 As shown, the second sacrificial material 103 of the second trench 142 is replaced with dielectric material 104, such as etching to remove the second sacrificial material 103 to release the second trench 142, and the second trench 142 is filled with dielectric material. The dielectric material is different from the first sacrificial material 102. The dielectric material 104 has a large difference in etch selectivity with the first sacrificial material 102. For example, the dielectric material 104 may include, but is not limited to, silicon nitride or silicon oxynitride. Figure 17 In the process, etching removes the second sacrificial material 103 to release the first trench 141.

[0047] In some embodiments, the method of forming the annular groove 160 includes: exist Figure 17 The first sacrificial material 102 is deposited on the inner wall of the first trench 141, forming a first sacrificial structure 151. Figure 18 The second sacrificial structure 152; Figure 19 In the middle, the remaining first trench 141 is filled with dielectric material 104; Figure 20The second sacrificial structure 152, at least a portion of its thickness, is removed along the z-direction to form an annular trench 160. If the second sacrificial structure 152 is etched back to a portion of its thickness to adjust the position of the gate structure 120 on the semiconductor body 111, and the top of the annular gate 153 is subsequently etched back after the conductive material is deposited to form the annular gate 153, the annular gate 153 can be positioned in the middle of the semiconductor body 111. Figure 20 When the second sacrificial structure 152 is removed, the first sacrificial material 102 on the periphery is also removed and the periphery isolation trench is released.

[0048] In some embodiments, it may be possible Figure 14 In the first step, a first sacrificial material 102 is deposited on the inner wall of the first trench 141. At this time, the first sacrificial material 102 can also be formed on the outer contour sidewall of the first sacrificial structure 151. The second sacrificial structure 152 formed by the first sacrificial material 102 and the first sacrificial structure 151 completely surrounds the semiconductor body 111. Subsequently, the annular gate 153 formed by replacing the second sacrificial structure 152 surrounds the semiconductor body 111 on all four sides. Subsequently, the gate structure 120 also surrounds the semiconductor body 111 on all four sides.

[0049] In some embodiments, Figure 21 As shown, based on the annular trench 160, the sidewalls of the oxidized semiconductor body 111 exposed in the annular trench 160 form a gate dielectric layer 112; an oxidant (including gas and liquid), such as oxygen, hydrogen peroxide, nitric acid, etc., is introduced into the annular trench 160, and the sidewalls of the semiconductor body 111 are self-oxidized to form the gate dielectric layer 112, such as including but not limited to silicon oxide. Figure 22 As shown, an annular gate 153 is formed by filling the annular trench 160 with conductive material. Figure 23 As shown, at both ends of the annular gate 153, two regions extending along the x direction of the annular gate 153 are cut off to form two cuts 143; the two cuts 143 are not aligned in the x direction and the y direction, and one annular gate 153 is divided into two gate structures 120, which fit together vertically. Figure 23 In the process, the annular gate 153 or the cut gate structure 120 can be etched back in the z-direction, and the top of the gate can be partially etched, so that the final gate structure 120 is as shown. Figure 4 The image shows the position located in the middle of the semiconductor body 111; at this time... Figure 22 The conductive material surrounding the memory array is also etched back to remove it, and then dielectric material is filled in the area surrounding the memory array to electrically isolate the memory array from the peripheral circuit area.

[0050] In some embodiments, refer to Figure 21As shown, the annular groove 160 includes two first sub-grooves 161 extending along the x-direction and two second sub-grooves 162 extending along a direction intersecting the x-direction; the first sub-grooves 161 and the second sub-grooves 162 are connected to form the annular groove 160.

[0051] In some embodiments, for Figure 5 and Figure 7 The illustrated gate structure 120 adapter fabrication method uses a patterned mask as an etching mask pair. Figure 13 The structure is etched to form Figure 24 The plurality of first grooves 141 shown and the second grooves 142 surrounding the plurality of first grooves 141 are shown in sequence; see also similar ones. Figures 15 to 20 The process steps are formed Figure 25 The annular groove 160 shown is followed by similar grooves. Figures 21 to 23 The process steps are formed Figure 5 and Figure 7 The example gate structure 120 and the first connection structure 133 on the gate structure 120.

[0052] In some embodiments, refer to Figure 21 and Figure 25 As shown, the two second sub-grooves 162 are located at both ends of the first sub-grooves 161 along the x-direction; Figure 25 The second sub-groove 162 communicates with the end of the first sub-groove 161, and the end of the annular groove 160 may be U-shaped; and / or, Figure 21 As shown, the end of the first sub-groove 161 protrudes outward from the second sub-groove 162 along the x-direction, and the end of the annular groove 160 can be I-shaped. In some embodiments, one end of an annular groove 160 can be U-shaped, and the other end can be I-shaped; correspondingly Figure 7 One of the first connecting ends 122a is U-shaped, and the other connecting end 122b is changed to an I-shape.

[0053] In some embodiments, Figure 23 The illustrated gate structure 120 includes: a gate body 121 extending in the x-direction, and a connection end 122 located at one end of the gate body 121 in the x-direction; the connection end 122 is connected to the gate body 121, the gate body 121 surrounds at least a portion of a sidewall extending in the z-direction of a semiconductor body 111, and the connection end 122 has a first portion 123 extending in a direction intersecting the x-direction and away from the gate body 121; the fabrication method further includes: Figure 9 As shown, a first connection structure 133 is formed on the connection end 122, and the first connection structure 133 is in contact with at least a portion of the connection end 122.

[0054] In some embodiments, the semiconductor body 111 has a first end and a second end disposed opposite to each other in the z-direction; the fabrication method further includes: forming a bit line 132 on a side near the first end of the semiconductor body 111, the bit line 132 being coupled to the first end of the semiconductor body 111; and forming a capacitor structure 131 on a side near the second end of the semiconductor body 111, the capacitor structure 131 being coupled to the second end of the semiconductor body 111. The bit line 132 and the capacitor structure 131 are referenced to... Figure 4 As shown. Figure 4 As shown, the first ends of the plurality of semiconductor bodies 111 arranged in the y-direction are interconnected by semiconductor material. The semiconductor material at the bottom of the first end is used to form bit lines 132 or to carry bit lines 132. Bit lines 132 can be formed by deposition or by forming metal silicides through semiconductor metallization processes. In other embodiments, there is no semiconductor material connection at the bottom of the first end of the semiconductor body 111, no semiconductor material connection at the bottom of the semiconductor bodies 111 arranged in the y-direction, and no semiconductor material connection at the bottom of the semiconductor bodies 111 arranged in the x-direction. Conductive material is deposited on the bottom (first end) of the semiconductor bodies 111 arranged in the y-direction to form bit lines 132, and the bit lines 132 are coupled to the first end of the semiconductor bodies 111.

[0055] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application.

Claims

1. A storage device, characterized in that, include: A semiconductor body having a first end and a second end disposed opposite to each other in a first direction; A gate structure includes a gate body extending along a second direction, and a connecting end located at one end of the gate body in the second direction; The connection terminal is connected to the gate body, the gate body surrounds at least a portion of a sidewall extending along the first direction of the semiconductor body, and the connection terminal has a first portion extending in a direction intersecting the second direction and away from the gate body; A first connection structure is located on the connection end and is in contact with at least a portion of the connection end; Bit lines extend along a third direction and are coupled to a first end of the semiconductor body; the third direction intersects with the second direction, and the plane formed by the third direction and the second direction intersects with the first direction.

2. The storage device according to claim 1, characterized in that, The connection end includes: A second portion and a third portion extending along the second direction; the second portion and the third portion are connected through the first portion; the second portion is connected to the gate body, and the third portion is located on the side of the first portion opposite to the second portion.

3. The storage device according to claim 2, characterized in that, The first part is connected to the end of the second part that is away from the gate body, and the first part is connected to the end of the third part that is away from the gate body.

4. The storage device according to claim 2, characterized in that, The first part is connected to the middle region of the second part, and the first part is connected to the middle region of the third part.

5. The storage device according to claim 2, characterized in that, The gate body surrounds a portion of the sidewall extending along the first direction of the semiconductor body, and the semiconductor body includes a first semiconductor body and a second semiconductor body disposed adjacent to each other in a third-direction upward direction; the memory device includes: The first gate body and the second gate body are arranged at an upward interval from the third party; The first semiconductor body is disposed back-to-back with the sidewall exposed from the first gate body and the second semiconductor body is disposed back-to-back with the sidewall exposed from the second gate body along the third direction.

6. The storage device according to claim 5, characterized in that, The storage device further includes: A first connection terminal connected to the first gate body, and a second connection terminal connected to the second gate body; wherein the first connection terminal and the second connection terminal are respectively located on opposite sides of the semiconductor body in the second direction, and the first connection terminal and the second connection terminal are aligned along the second direction.

7. The storage device according to claim 6, characterized in that, The third portion of the first connecting end is aligned with the end of the second gate body that is away from the second connecting end; The third portion of the second connection end is aligned with the end of the first gate body that is away from the first connection end.

8. The storage device according to any one of claims 1 to 7, characterized in that, The first connection structure is in contact with at least a portion of the area of ​​the first part.

9. The storage device according to any one of claims 1 to 7, characterized in that, The storage device further includes: A gate dielectric layer is located between the semiconductor body and the gate structure; A capacitor structure is located on the side of the semiconductor body away from the bit line; the capacitor structure is coupled to a second end of the semiconductor body.

10. A method for manufacturing a storage device, characterized in that, include: Multiple semiconductor bodies extending along the first direction are formed; An annular trench extending at least along a second direction is formed, and the semiconductor bodies adjacent to each other on the third upward direction are respectively located in the region of the annular trench extending along the second direction; The region of the annular trench extending in the second direction surrounds at least a portion of the sidewall of the semiconductor body extending in the first direction; The annular trench surrounds the dielectric material between the third-order, upwardly adjacent semiconductor bodies; Based on the annular trench, the sidewalls of the semiconductor body exposed from the annular trench are oxidized to form a gate dielectric layer; The annular groove is filled to form an annular grid; At both ends of the annular gate away from the plurality of semiconductor bodies along the second direction, two regions extending along the second direction of the annular gate are etched and cut off to form two cuts; wherein the two cuts are not aligned in the second direction and in the third direction, and the two cuts divide the annular gate into two gate structures.

11. The manufacturing method according to claim 10, characterized in that, The method of forming the semiconductor body includes: A plurality of semiconductor strips are formed and spaced apart along the second direction, the semiconductor strips extending along the third direction; A first sacrificial material is formed surrounding the plurality of semiconductor strips; The semiconductor strip and the first sacrificial material are etched to form a plurality of first trenches extending along the second direction and a second trench surrounding the plurality of first trenches; the first trenches divide the semiconductor strip into a plurality of semiconductor bodies; The second trench and the remaining first sacrificial material between the first trench form a first sacrificial structure; the outer contour shape of the first sacrificial structure is the same as the outer contour shape of the annular gate.

12. The manufacturing method according to claim 11, characterized in that, The method for forming the annular groove includes: A first sacrificial material is deposited on the inner wall of the first trench to form a second sacrificial structure with the first sacrificial structure; the remaining first trench is filled with the dielectric material. At least a portion of the thickness of the second sacrificial structure is removed along the first direction to form the annular groove.

13. The manufacturing method according to claim 10, characterized in that, The annular groove includes two first sub-grooves extending along the second direction, and two second sub-grooves extending along a direction intersecting the second direction; the first sub-grooves and the second sub-grooves are connected and enclose each other to form the annular groove.

14. The manufacturing method according to claim 13, characterized in that, The two second sub-grooves are respectively located at both ends of the first sub-grooves along the second direction; the second sub-grooves are connected to the ends of the first sub-grooves; and / or, The end of the first sub-groove protrudes out of the second sub-groove along the second direction.

15. The manufacturing method according to any one of claims 10 to 14, characterized in that, The gate structure includes: A gate body extending along a second direction, and a connection end located at one end of the gate body in the second direction; the connection end is connected to the gate body, and the gate body surrounds at least a portion of a sidewall extending along the first direction of the semiconductor body. The connecting end has a first portion extending in a direction intersecting the second direction and away from the gate body; The manufacturing method further includes: A first connection structure is formed on the connection end, and the first connection structure is in contact with at least a portion of the connection end.

16. The manufacturing method according to claim 15, characterized in that, The semiconductor body has a first end and a second end disposed opposite to each other in a first direction; the fabrication method further includes: A bit line is formed on one side near the first end of the semiconductor body, and the bit line is coupled to the first end of the semiconductor body; A capacitor structure is formed on one side near the second end of the semiconductor body, and the capacitor structure is coupled to the second end of the semiconductor body.

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