Semiconductor device and manufacturing method thereof

By setting hexagonal gaps within the contact isolation layer surrounding the contact pad array, the problems of structural reliability and excessive parasitic capacitance of the contact pads are solved, thereby improving the performance of semiconductor devices.

CN121751639APending Publication Date: 2026-03-27FUJIAN JINHUA INTEGRATED CIRCUIT CO LTD
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Patent Information

Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
Filing Date
2025-12-29
Publication Date
2026-03-27

AI Technical Summary

Technical Problem

Existing technologies in high-integration and high-density semiconductor devices, especially in DRAM with recessed gate structures, suffer from insufficient structural reliability of contact pads and excessively high parasitic capacitance, making it difficult to improve performance.

Method used

Hexagonal gaps are formed within the contact isolation layer surrounding the contact pad array, encircling the periphery of each individual contact pad, to optimize the structural reliability of the contact pads and reduce parasitic capacitance.

Benefits of technology

By setting hexagonal gaps, the structural reliability of the contact pads is significantly improved, parasitic capacitance is reduced, and thus the overall performance of semiconductor devices is enhanced.

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Abstract

The invention discloses a semiconductor device and a manufacturing method thereof. The semiconductor device comprises a substrate, a contact pad array, a contact isolation layer and at least one hexagonal gap. The contact pad array is located on the substrate and comprises a plurality of contact pads. The contact isolation layer is located on the substrate and surrounds the contact pad array. At least one hexagonal gap is located in the contact isolation layer and surrounds one contact pad. Therefore, the at least one hexagonal gap is arranged around the contact pad, so that the structure of the contact pad is effectively optimized, the parasitic capacitance is greatly reduced, and the performance of the semiconductor device is further improved.
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