Memory unit, forming method thereof and memory array

Abstract

The invention discloses a memory unit, a forming method thereof and a memory array. The memory unit comprises a substrate; the first floating gate structure and the second floating gate structure are located on the active region; the barrier layer is positioned on the surfaces of the first floating gate structure and the second floating gate structure; the common source layer, the first drain layer and the second drain layer are located in the active region; the word line layer is located on the substrate and covers the first floating gate structure and the second floating gate structure; the first bit line layer is electrically connected with the first leakage layer; and the second bit line layer is electrically connected with the second leakage layer. The adjacent first floating gate structure and second floating gate structure share one word line layer, so that the word line layer has a larger forming space, the volume of the word line layer is increased, and the resistance of the word line layer is effectively reduced. In addition, the volume of the word line layer is increased, and the control capability on the first floating gate structure and the second floating gate structure is enhanced, so that the coupling effect of the device structure is improved. The memory unit can be fused with the existing production line only by changing the connection scheme.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a memory cell and its formation method, and a memory array. Background Technology

[0002] With the rapid popularization of electronic products, flash memory has become the mainstream storage medium and its technology has developed very rapidly.

[0003] Flash memory is a type of non-volatile memory, meaning data is not lost when power is off, which has led to its widespread use. Flash memory includes NOR flash memory and NAND flash memory. NOR flash memory allows independent read and write operations on each memory cell, providing full random access functionality, and therefore can be used for non-volatile storage of executable programs.

[0004] However, existing NOR memory cells still have many problems. Summary of the Invention

[0005] The technical problem solved by this invention is to provide a memory cell and its formation method, and a memory array, so as to reduce the resistance of the word line layer.

[0006] To address the aforementioned problems, the present invention provides a memory cell comprising: a substrate having an active region extending along a first direction; a first floating gate structure and a second floating gate structure arranged along the first direction on the active region; a barrier layer located on the sidewalls and top surface of the first floating gate structure and the sidewalls and top surface of the second floating gate structure; a common source layer, a first drain layer, and a second drain layer located within the active region, wherein the first drain layer and the common source layer are located on opposite sides of the first floating gate structure, the second drain layer and the common source layer are located on opposite sides of the second floating gate structure, and the common source layer is located between the first floating gate structure and the second floating gate structure; a word line layer located on the substrate, the word line layer extending along a second direction, the word line layer covering the first floating gate structure and the second floating gate structure, wherein the first direction is perpendicular to the second direction; a first bit line layer, the first bit line layer extending along the first direction and electrically connected to the first drain layer; and a second bit line layer extending along the first direction and electrically connected to the second drain layer.

[0007] Optionally, the barrier layer includes: a first oxide layer, a nitrided layer located on the surface of the first oxide layer, and a second oxide layer located on the surface of the nitrided layer.

[0008] Optionally, it further includes: a first conductive plug, which is electrically connected to the first drain layer; a second conductive plug, which is electrically connected to the second drain layer; a third conductive plug, which is electrically connected to the first conductive plug and the first bit line layer respectively; and a fourth conductive plug, which is electrically connected to the second conductive plug and the second bit line layer respectively.

[0009] Optionally, the first conductive plug has a first axis of symmetry extending along the first direction, the second conductive plug has a second axis of symmetry extending along the first direction, and the first axis of symmetry coincides with the second axis of symmetry; the third conductive plug is in partial contact with the first conductive plug; and the fourth conductive plug is in partial contact with the second conductive plug.

[0010] Optionally, the first conductive plug has a first axis of symmetry extending along the first direction, the second conductive plug has a second axis of symmetry extending along the first direction, and the first axis of symmetry and the second axis of symmetry do not coincide; the third conductive plug is in complete contact with the first conductive plug; and the fourth conductive plug is in complete contact with the second conductive plug.

[0011] Optionally, it may also include a metal contact layer located on the word line layer.

[0012] Accordingly, the present invention also provides a method for forming a memory cell, comprising: providing a substrate having an active region extending along a first direction; forming a first floating gate structure and a second floating gate structure arranged along the first direction on the active region; forming a barrier layer on the sidewalls and top surface of the first floating gate structure and the sidewalls and top surface of the second floating gate structure; forming a common source layer, a first drain layer and a second drain layer in the active region, wherein the first drain layer and the common source layer are located on both sides of the first floating gate structure, the second drain layer and the common source layer are located on both sides of the second floating gate structure, and the common source layer is located between the first floating gate structure and the second floating gate structure; a word line layer on the substrate, the word line layer extending along a second direction, the word line layer covering the first floating gate structure and the second floating gate structure, wherein the first direction is perpendicular to the second direction; forming a first bit line layer and a second bit line layer, wherein both the first bit line layer and the second bit line layer extend along the first direction, the first bit line layer is electrically connected to the first drain layer, and the second bit line layer is electrically connected to the second drain layer.

[0013] Optionally, the barrier layer includes: a first oxide layer, a nitrided layer located on the surface of the first oxide layer, and a second oxide layer located on the surface of the nitrided layer.

[0014] Optionally, the first floating gate structure and the second floating gate structure are formed simultaneously; the method for forming the first floating gate structure and the second floating gate structure includes: forming a floating gate material layer on the substrate; and performing patterned etching on the floating gate material layer to form the first floating gate structure and the second floating gate structure.

[0015] Optionally, the method for forming the common source layer, the first drain layer, and the second drain layer includes: using the first floating gate structure and the second floating gate structure as masks, injecting source and drain ions into the active region to form the common source layer, the first drain layer, and the second drain layer.

[0016] Optionally, the method for electrically connecting the first bit line layer to the first drain layer and the second bit line layer to the second drain layer includes: forming a first conductive plug and a second conductive plug, wherein the first conductive plug is electrically connected to the first drain layer and the second conductive plug is electrically connected to the second drain layer; forming a third conductive plug and a fourth conductive plug, wherein the third conductive plug is electrically connected to the first conductive plug and the first bit line layer respectively, and the fourth conductive plug is electrically connected to the second conductive plug and the second bit line layer respectively.

[0017] Optionally, the first conductive plug has a first axis of symmetry extending along the first direction, the second conductive plug has a second axis of symmetry extending along the first direction, and the first axis of symmetry coincides with the second axis of symmetry; the third conductive plug is in partial contact with the first conductive plug; and the fourth conductive plug is in partial contact with the second conductive plug.

[0018] Optionally, the first conductive plug has a first axis of symmetry extending along the first direction, the second conductive plug has a second axis of symmetry extending along the first direction, and the first axis of symmetry and the second axis of symmetry do not coincide; the third conductive plug is in complete contact with the first conductive plug; and the fourth conductive plug is in complete contact with the second conductive plug.

[0019] Optionally, the first bit line layer and the second bit line layer are formed simultaneously; the method for forming the first bit line layer and the second bit line layer includes: forming a first bit line groove and a second bit line groove; forming the first bit line layer in the first bit line groove and forming the second bit line layer in the second bit line groove.

[0020] Optionally, the first bit groove and the second bit groove are formed using a self-aligned dual imaging process.

[0021] Optionally, after forming the word line layer, the method further includes forming a metal contact layer on the word line layer.

[0022] Accordingly, the present invention also provides a memory array, comprising: a plurality of memory groups arranged in parallel along a first direction, each memory group comprising a plurality of memory cells as described in any of the above technical solutions, the plurality of memory cells arranged along a second direction, the first direction being perpendicular to the second direction; wherein, in each memory group, the plurality of memory cells share the word line layer; in each memory group, the common source layer of the plurality of memory cells is electrically connected; adjacent memory groups are mirror-symmetrically distributed; adjacent memory groups share the first drain layer or the second drain layer; adjacent memory groups share the first bit line layer and the second bit line layer.

[0023] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0024] In the memory cell of this invention, the word line layer covers both the first floating gate structure and the second floating gate structure. That is, adjacent first and second floating gate structures share one word line layer, allowing for a larger formation space and increasing the volume of the word line layer, thereby effectively reducing its resistance. Furthermore, the increased volume of the word line layer enhances the control over the first and second floating gate structures, thus improving the coupling effect of the device structure. This memory cell, by only changing the interconnection scheme, can be integrated with existing production lines.

[0025] Furthermore, the barrier layer comprises: a first oxide layer, a nitride layer located on the surface of the first oxide layer, and a second oxide layer located on the surface of the nitride layer. By setting the barrier layer as a multilayer structure, the dielectric constant of the barrier layer is increased, thereby enhancing the electric field distributed to the tunneling oxide layer, and thus enhancing the coding effect of the write-and-erase of the device structure.

[0026] Furthermore, it also includes a metal contact layer located on the word line layer. The metal contact layer reduces the contact resistance between the conductive plug and the word line layer.

[0027] In the method for forming a memory cell according to the present invention, the word line layer covers the first floating gate structure and the second floating gate structure, meaning that adjacent first and second floating gate structures share one word line layer. This provides the word line layer with a larger forming space, thereby increasing its volume and effectively reducing its resistance. Furthermore, the increased volume of the word line layer enhances the control over the first and second floating gate structures, thus improving the coupling effect of the device structure. The memory cell only requires a change in the interconnection scheme and can be integrated with existing production lines.

[0028] Furthermore, the barrier layer comprises: a first oxide layer, a nitride layer located on the surface of the first oxide layer, and a second oxide layer located on the surface of the nitride layer. By setting the barrier layer as a multilayer structure, the dielectric constant of the barrier layer is increased, thereby enhancing the electric field distributed to the tunneling oxide layer, and thus enhancing the coding effect of the write-and-erase of the device structure.

[0029] Furthermore, after forming the word line layer, the method further includes forming a metal contact layer on the word line layer. The metal contact layer reduces the contact resistance between the conductive plug and the word line layer.

[0030] In the memory array of this invention, the word line layer covers both the first and second floating gate structures. That is, adjacent first and second floating gate structures share one word line layer, providing a larger formation space and increasing the volume of the word line layer, thereby effectively reducing its resistance. Furthermore, the increased volume of the word line layer enhances the control over the first and second floating gate structures, thus improving the coupling effect of the device structure. The memory cell only requires a change in the connection scheme and can be integrated with existing production lines. Attached Figure Description

[0031] Figure 1 A schematic diagram of the structure of a memory cell;

[0032] Figure 2 yes Figure 1 Schematic diagram of the cross section along line AA;

[0033] Figures 3 to 13 This is a schematic diagram of the structure of each step in the method for forming a memory cell in an embodiment of the present invention;

[0034] Figure 14 This is a schematic diagram of the structure of a memory cell in another embodiment of the present invention;

[0035] Figure 15 This is a schematic diagram of the structure of a memory cell in another embodiment of the present invention;

[0036] Figure 16 This is a schematic diagram of the structure of a memory cell in another embodiment of the present invention;

[0037] Figure 17 This is a schematic diagram of the memory array structure in an embodiment of the present invention. Detailed Implementation

[0038] As described in the background section, existing NOR memory cells still have many problems. These will be explained in detail below with reference to the accompanying drawings.

[0039] Figure 1 A schematic diagram of the structure of a memory cell; Figure 2 yes Figure 1 Schematic diagram of the cross section along line AA.

[0040] Please refer to Figure 1 and 2 A memory cell includes: a substrate 100 having an active region 1001 extending along a first direction X; a first floating gate structure 101 and a second floating gate structure 102 arranged along the first direction X on the active region 1001; a barrier layer 103 located on the top surface of the first floating gate structure 101 and the top surface of the second floating gate structure 102; a common source layer 104, a first drain layer 105, and a second drain layer 106 located within the active region 1001, wherein the first drain layer 105 and the common source layer 104 are located on both sides of the first floating gate structure 101, and the second drain layer 106 and the common source layer 104 are located on both sides of the second floating gate structure 102. Layer 104 is located between the first floating gate structure 101 and the second floating gate structure 102; a first word line layer 107 is located on the substrate 100, extending along the second direction Y, and controlling the first floating gate structure 101, wherein the first direction X is perpendicular to the second direction Y; a second word line layer 108 is located on the substrate 100, extending along the second direction Y, and controlling the second floating gate structure 102; a bit line layer 109 extends along the first direction X, and is electrically connected to the first drain layer 105 and the second drain layer 106 respectively.

[0041] In this embodiment, each floating gate structure (i.e., the first floating gate structure 101 and the second floating gate structure 102) is controlled by one word line layer (i.e., the first word line layer 107 and the second word line layer 108), which makes the volume of the first word line layer 107 and the second word line layer 108 relatively small.

[0042] As NOR memory has evolved and nodes have shrunk, word line resistance has increased due to size reduction and the increase in series-connected memory cells, ultimately slowing down write and read speeds. However, NOR memory has high speed requirements, so reducing word line resistance is also a limiting factor for NOR memory.

[0043] Currently, the industry has implemented several measures to improve word line layer resistance, such as using lower resistance word line layer materials or thicker metal silicide layers; optimizing programming algorithms such as multilevel programming (MTP) or parallel programming, which can reduce dependence on individual word line layers and thus lower the requirements for word line layer resistance; and changing the structure of NOR memory, etc.

[0044] However, using low-resistance word line layer materials has limited effect on improving word line layer resistance; optimizing programming algorithms only optimizes the program itself, and the improvement would be more significant if the word line layer resistance could be reduced; changing the NOR memory structure and integrating it with existing production lines requires separate analysis based on the specific solution.

[0045] Based on this, the present invention provides a memory cell and its formation method, and a memory array. The word line layer covers the first floating gate structure and the second floating gate structure, that is, adjacent first and second floating gate structures share one word line layer, giving the word line layer a larger formation space, thereby increasing the volume of the word line layer and effectively reducing its resistance. Furthermore, the increased volume of the word line layer enhances the controllability over the first and second floating gate structures, thereby improving the coupling effect of the device structure. The memory cell only requires a change in the connection scheme and can be integrated with existing production lines.

[0046] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0047] Figures 3 to 13 This is a schematic diagram of the structure of each step in the method for forming a memory cell in an embodiment of the present invention; Figure 14 This is a schematic diagram of the structure of a memory cell in another embodiment of the present invention; Figure 15 This is a schematic diagram of the structure of a memory cell in another embodiment of the present invention; Figure 16 This is a schematic diagram of the structure of a memory cell in another embodiment of the present invention.

[0048] Please refer to Figure 3 and Figure 4 , Figure 4 yes Figure 3 A schematic cross-sectional view along the BB line shows a substrate 200 having an active region 2001 extending along a first direction X.

[0049] In this embodiment, the substrate 200 is made of silicon.

[0050] In other embodiments, the substrate material may also be germanium, silicon germanide, silicon carbide, gallium arsenide, or indium galliumide.

[0051] In this embodiment, channel ions are implanted in the active region 2001, and the channel ions can be N-type ions or P-type ions.

[0052] Please refer to Figure 5 and Figure 6 , Figure 6 yes Figure 5A schematic diagram of a cross-section along the CC line shows that a first floating gate structure 201 and a second floating gate structure 202 are formed on the active region 2001 along the first direction X.

[0053] In this embodiment, the first floating gate structure 201 and the second floating gate structure 202 are formed simultaneously; the method for forming the first floating gate structure 201 and the second floating gate structure 202 includes: forming a floating gate material layer (not shown) on the substrate 200; and performing patterned etching on the floating gate material layer to form the first floating gate structure 201 and the second floating gate structure 202.

[0054] In this embodiment, the floating gate material layer includes a tunneling oxide material layer and a gate material layer located on the tunneling oxide material layer. The corresponding first floating gate structure 201 and second floating gate structure 202 each include a tunneling oxide layer (not shown) formed by patterning and etching the tunneling oxide material layer, and a floating gate layer (not shown) formed by patterning and etching the gate material layer.

[0055] In this embodiment, the material of the tunneling oxide layer is silicon oxide, and the material of the floating gate layer is polycrystalline silicon.

[0056] Please refer to Figure 7 , Figure 7 and Figure 6 With the view direction consistent, after forming the first floating gate structure 201 and the second floating gate structure 202, a common source layer 204, a first drain layer 205 and a second drain layer 206 are formed in the active region 2001. The first drain layer 205 and the common source layer 204 are located on both sides of the first floating gate structure 201, the second drain layer 206 and the common source layer 204 are located on both sides of the second floating gate structure 202, and the common source layer 204 is located between the first floating gate structure 201 and the second floating gate structure 202.

[0057] In this embodiment, the method for forming the common source layer 204, the first drain layer 205, and the second drain layer 206 includes: using the first floating gate structure 201 and the second floating gate structure 202 as masks, injecting source and drain ions into the active region 2001 to form the common source layer 204, the first drain layer 205, and the second drain layer 206.

[0058] In this embodiment, the electrical type of the source / drain ions is opposite to that of the channel ions, that is, the source / drain ions can be P-type ions or N-type ions.

[0059] In this embodiment, it should be noted that after forming the common source layer 204, the first drain layer 205 and the second drain layer 206, it is necessary to form corresponding metal silicide layers or perform ion heavy doping (not shown) on the surface of the common source layer 204, the first drain layer 205 and the second drain layer 206 to reduce their contact resistance.

[0060] Please refer to Figure 8 After the common source layer 204, the first drain layer 205 and the second drain layer 206 are formed, a barrier layer 203 is formed on the sidewall and top surface of the first floating gate structure 201 and the sidewall and top surface of the second floating gate structure 202.

[0061] The barrier layer 203 is also formed on the top surface of the substrate 200, and the barrier layer 203 located on the top surface of the substrate 200 can be retained or removed.

[0062] In this embodiment, the barrier layer 203 located on the top surface of the substrate 200 is removed.

[0063] In this embodiment, the barrier layer 203 has a multilayer structure, that is, the barrier layer 203 includes: a first oxide layer (not shown), a nitride layer (not shown) located on the surface of the first oxide layer, and a second oxide layer (not shown) located on the surface of the nitride layer.

[0064] By setting the barrier layer 203 as a multilayer structure, the dielectric constant of the barrier layer 203 is increased, thereby enhancing the electric field distributed to the tunneling oxide layer and thus strengthening the coupling effect of writing and erasing the device structure. In addition, the first silicon oxide layer and the second silicon oxide layer can bond well with the substrate, while the silicon nitride layer in the middle can block the extension of defects (such as pinholes). Therefore, the three-layer structure design can complement each other.

[0065] Please refer to Figure 9 After the barrier layer 203 is formed, a word line layer 207 is formed on the substrate 200. The word line layer 207 extends along the second direction Y and covers the first floating gate structure 201 and the second floating gate structure 202. The first direction X is perpendicular to the second direction Y.

[0066] In this embodiment, before forming the word line layer 207, a gate dielectric layer 208 needs to be formed on the common source layer 204. The height of the gate dielectric layer 208 cannot exceed the height of the barrier layer 203 located on the top surface of the first floating gate structure 201 and the second floating gate structure 202, and the height of the gate dielectric layer 208 should be sufficient to ensure that there is no obvious coupling between the word line layer 207 and the common source layer 204.

[0067] In this embodiment, the gate dielectric layer 208 is made of silicon oxide.

[0068] In this embodiment, the method for forming the word line layer 207 includes: forming a word line material layer (not shown) on the substrate 200, the word line material layer covering the barrier layer 203, the first floating gate structure 201 and the second floating gate structure 202; and performing patterned etching on the word line material layer to form the word line layer 207.

[0069] In this embodiment, during the patterning etching of the word line material layer, the blocking layer 203 located on the opposite outer sidewalls of the first floating gate structure 201 and the second floating gate structure 202 is also removed, and the edge of the word line layer 207 is aligned with the edges of the first floating gate structure 201 and the second floating gate structure 202, respectively.

[0070] Please refer to Figure 14 In other embodiments, during the patterning etching of the word line material layer, the blocking layer 203 located on the opposite outer sidewalls of the first floating gate structure 201 and the second floating gate structure 202 may also be retained, and the edge of the word line layer 207 is aligned with the edge of the first floating gate structure 201 and the second floating gate structure 202, respectively.

[0071] Please refer to Figure 15 In other embodiments, during the patterning etching of the word line material layer, the blocking layer 203 located on the opposite outer sidewalls of the first floating gate structure 201 and the second floating gate structure 202 may also be retained, and the edge of the word line layer 207 is aligned with the edge of the blocking layer 203 on the opposite outer sidewalls of the first floating gate structure 201 and the second floating gate structure 202, respectively.

[0072] Please refer to Figure 16 In other embodiments, during the patterning etching of the word line material layer, the blocking layer 203 located on the opposite outer sidewalls of the first floating gate structure 201 and the second floating gate structure 202, as well as a portion of the blocking layer 203 on the top surface of the first floating gate structure 201 and the second floating gate structure 202, may also be removed, and the edge of the word line layer 207 may not be aligned with the edge of the first floating gate structure 201 and the second floating gate structure 202, respectively.

[0073] In this embodiment, the word line layer 207 is made of polycrystalline silicon.

[0074] Please continue to refer to this. Figure 9In this embodiment, after forming the word line layer 207, the method further includes forming a metal contact layer 209 (i.e., a metal silicide layer) on the word line layer 207. The metal contact layer 209 reduces the contact resistance between the conductive plug and the word line layer 207.

[0075] Please refer to Figures 10 to 12 , Figure 11 yes Figure 10 Schematic diagram of the cross section along the DD line. Figure 12 yes Figure 10 A schematic diagram of the cross-section along the EE line shows that after the word line layer 207 is formed, a first bit line layer 210 and a second bit line layer 211 are formed. Both the first bit line layer 210 and the second bit line layer 211 extend along the first direction X. The first bit line layer 210 is electrically connected to the first drain layer 205, and the second bit line layer 211 is electrically connected to the second drain layer 206.

[0076] The word line layer 207 covers the first floating gate structure 201 and the second floating gate structure 202, meaning that adjacent first floating gate structures 201 and second floating gate structures 202 share one word line layer 207. This allows the word line layer 207 to have a larger formation space, thereby increasing its volume and effectively reducing its resistance. Furthermore, the increased volume of the word line layer 207 enhances the control over the first floating gate structure 201 and the second floating gate structure 202, thus improving the coupling effect of the device structure. The memory cell 20 only requires a change in the connection scheme and can be integrated with existing production lines.

[0077] Please continue to refer to this. Figures 10 to 12 and in conjunction with references Figure 13 In this embodiment, the method for electrically connecting the first bit line layer 210 to the first drain layer 205 and the second bit line layer 211 to the second drain layer 206 includes: forming a first conductive plug 212 and a second conductive plug 213, wherein the first conductive plug 212 is electrically connected to the first drain layer 205 and the second conductive plug 213 is electrically connected to the second drain layer 206; forming a third conductive plug 214 and a fourth conductive plug 215, wherein the third conductive plug 214 is electrically connected to the first conductive plug 212 and the first bit line layer 210 respectively, and the fourth conductive plug 215 is electrically connected to the second conductive plug 213 and the second bit line layer 211 respectively.

[0078] It should be noted that, in this embodiment, during the formation of the first conductive plug 212, the second conductive plug 213, the third conductive plug 214, the fourth conductive plug 215, the first bit line layer 210, and the second bit line layer 211, a corresponding interlayer dielectric layer (not shown) also needs to be formed on the substrate 200. The first conductive plug 212, the second conductive plug 213, the third conductive plug 214, the fourth conductive plug 215, the first bit line layer 210, and the second bit line layer 211 are all formed by patterning and etching the interlayer dielectric layer and then filling it with metal.

[0079] Please continue to refer to this. Figure 13 The first conductive plug 212 has a first axis of symmetry (not shown) extending along the first direction X, and the second conductive plug 213 has a second axis of symmetry (not shown) extending along the first direction X. The first axis of symmetry coincides with the second axis of symmetry. The third conductive plug 214 is in partial contact with the first conductive plug 212. The fourth conductive plug 215 is in partial contact with the second conductive plug 213.

[0080] In other embodiments, the first conductive plug has a first axis of symmetry extending along the first direction, the second conductive plug has a second axis of symmetry extending along the first direction, and the first axis of symmetry and the second axis of symmetry do not coincide; the third conductive plug is in complete contact with the first conductive plug; and the fourth conductive plug is in complete contact with the second conductive plug.

[0081] In this embodiment, the first bit line layer 210 and the second bit line layer 211 are formed simultaneously; the method for forming the first bit line layer 210 and the second bit line layer 211 includes: forming a first bit line groove (not shown) and a second bit line groove (not shown); forming the first bit line layer 210 in the first bit line groove and forming the second bit line layer 211 in the second bit line groove.

[0082] It should be noted that, in this embodiment, both the first bit groove and the second bit groove are formed after etching the interlayer dielectric layer. If the exposure capability allows, the formation process of the first bit groove and the second bit groove can be based on direct exposure; if the exposure capability does not allow, the formation process of the first bit groove and the second bit groove can adopt a self-aligned double patterning (SADP) process.

[0083] Accordingly, this embodiment of the invention also provides a memory unit 20, please refer to [further details]. Figures 10 to 13The system includes: a substrate 200 having an active region 2001 extending along a first direction X; a first floating gate structure 201 and a second floating gate structure 202 arranged along the first direction X on the active region 2001; a barrier layer 203 located on the sidewalls and top surface of the first floating gate structure 201 and the sidewalls and top surface of the second floating gate structure 202; a common source layer 204, a first drain layer 205, and a second drain layer 206 located within the active region 2001, wherein the first drain layer 205 and the common source layer 204 are located on both sides of the first floating gate structure 201, and the second drain layer 206 and the common source layer 204 are located on both sides of the second floating gate structure 202. The common source layer 204 is located between the first floating gate structure 201 and the second floating gate structure 202; a word line layer 207 is located on the substrate 200, the word line layer 207 extends along the second direction Y, the word line layer 207 covers the first floating gate structure 201 and the second floating gate structure 202, the first direction X is perpendicular to the second direction Y; a first bit line layer 210 extends along the first direction X, and the first bit line layer 210 is electrically connected to the first drain layer 205; a second bit line layer 211 extends along the first direction X, and the second bit line layer 211 is electrically connected to the second drain layer 206.

[0084] The word line layer 207 covers the first floating gate structure 201 and the second floating gate structure 202, meaning that adjacent first floating gate structures 201 and second floating gate structures 202 share one word line layer 207. This allows the word line layer 207 to have a larger formation space, thereby increasing its volume and effectively reducing its resistance. Furthermore, the increased volume of the word line layer 207 enhances the control over the first floating gate structure 201 and the second floating gate structure 202, thus improving the coupling effect of the device structure. The memory cell 20 only requires a change in the connection scheme and can be integrated with existing production lines.

[0085] In this embodiment, the barrier layer 203 includes: a first oxide layer, a nitride layer located on the surface of the first oxide layer, and a second oxide layer located on the surface of the nitride layer. By setting the barrier layer 203 as a multilayer structure, the dielectric constant of the barrier layer 203 is increased, thereby enhancing the electric field distributed to the tunneling oxide layer and thus enhancing the coding effect of the write-and-erase mechanism of the device structure. In addition, the first silicon oxide layer and the second silicon oxide layer can bond well with the substrate, while the silicon nitride layer, located in the middle, can block the propagation of defects (such as pinholes). Therefore, the three-layer structure design can complement each other.

[0086] In this embodiment, the device further includes: a first conductive plug 212, which is electrically connected to the first drain layer 205; a second conductive plug 213, which is electrically connected to the second drain layer 206; a third conductive plug 214, which is electrically connected to the first conductive plug 212 and the first bit line layer 210 respectively; and a fourth conductive plug 215, which is electrically connected to the second conductive plug 213 and the second bit line layer 211 respectively.

[0087] In this embodiment, the first conductive plug 212 has a first axis of symmetry extending along the first direction X, the second conductive plug 213 has a second axis of symmetry extending along the first direction X, and the first axis of symmetry coincides with the second axis of symmetry; the third conductive plug 214 is in partial contact with the first conductive plug 212; and the fourth conductive plug 215 is in partial contact with the second conductive plug 213.

[0088] In other embodiments, the first conductive plug has a first axis of symmetry extending along the first direction, the second conductive plug has a second axis of symmetry extending along the first direction, and the first axis of symmetry and the second axis of symmetry do not coincide; the third conductive plug is in complete contact with the first conductive plug; and the fourth conductive plug is in complete contact with the second conductive plug.

[0089] In this embodiment, a metal contact layer 209 is also included on the word line layer 207. The metal contact layer 209 reduces the contact resistance between the conductive plug and the word line layer 207.

[0090] In this embodiment, the first floating gate structure 201 and the second floating gate structure 202 do not have the blocking layer 203 on their outer sidewalls, and the edge of the word line layer 207 is aligned with the edge of the first floating gate structure 201 and the second floating gate structure 202, respectively.

[0091] Please refer to Figure 14 In other embodiments, the first floating gate structure 201 and the second floating gate structure 202 may also have the blocking layer 203 on their outer sidewalls, and the edge of the word line layer 207 is aligned with the edge of the first floating gate structure 201 and the second floating gate structure 202, respectively.

[0092] Please refer to Figure 15In other embodiments, the first floating gate structure 201 and the second floating gate structure 202 may also have the blocking layer 203 on their opposite outer sidewalls, and the edge of the word line layer 207 is aligned with the edge of the blocking layer 203 on the opposite outer sidewalls of the first floating gate structure 201 and the second floating gate structure 202, respectively.

[0093] Please refer to Figure 16 In other embodiments, the first floating gate structure 201 and the second floating gate structure 202 may not have the blocking layer 203 on their outer sidewalls, and a portion of the top surface of the first floating gate structure 201 and the second floating gate structure 202 may have the blocking layer 203, and the edge of the word line layer 207 may not be aligned with the edge of the first floating gate structure 201 and the second floating gate structure 202 respectively.

[0094] Accordingly, this embodiment of the invention also provides a memory array 30, please refer to [further details]. Figures 10 to 13 and in conjunction with references Figure 17 The system includes: a plurality of memory groups 300 arranged parallel to a first direction X, each memory group including a plurality of memory cells 20 as described in any of the above embodiments, the plurality of memory cells 20 being arranged along a second direction Y, the first direction X being perpendicular to the second direction Y; wherein, in each memory group 300, the plurality of memory cells 20 share the word line layer 207; in each memory group 300, the common source layer 204 of the plurality of memory cells 20 is electrically connected; adjacent memory groups 300 are mirror-symmetrically distributed; adjacent memory groups 300 share the first drain layer 205 or the second drain layer 206; adjacent memory groups 300 share the first bit line layer 210 and the second bit line layer 211.

[0095] The word line layer 207 covers the first floating gate structure 201 and the second floating gate structure 202, meaning that adjacent first floating gate structures 201 and second floating gate structures 202 share one word line layer 207. This allows the word line layer 207 to have a larger formation space, thereby increasing its volume and effectively reducing its resistance. Furthermore, the increased volume of the word line layer 207 enhances the control over the first floating gate structure 201 and the second floating gate structure 202, thus improving the coupling effect of the device structure. The memory cell 20 only requires a change in the connection scheme and can be integrated with existing production lines.

[0096] In this embodiment, each storage transistor in the memory array 30 can be read and written independently, providing full random access functionality.

[0097] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A memory cell, characterized in that, include: A substrate having an active region extending along a first direction; A first floating gate structure and a second floating gate structure are arranged along the first direction on the active region; Barrier layers located on the sidewalls and top surfaces of the first floating grid structure and the sidewalls and top surfaces of the second floating grid structure; The common source layer, the first drain layer, and the second drain layer are located within the active region. The first drain layer and the common source layer are located on both sides of the first floating gate structure, and the second drain layer and the common source layer are located on both sides of the second floating gate structure. The common source layer is located between the first floating gate structure and the second floating gate structure. A word line layer located on the substrate, the word line layer extending along a second direction, the word line layer covering the first floating gate structure and the second floating gate structure, the first direction being perpendicular to the second direction; The first bit line layer extends along the first direction and is electrically connected to the first drain layer; The second bit line layer extends along the first direction and is electrically connected to the second drain layer.

2. The memory cell as claimed in claim 1, characterized in that, The barrier layer includes: a first oxide layer, a nitrided layer located on the surface of the first oxide layer, and a second oxide layer located on the surface of the nitrided layer.

3. The memory cell as claimed in claim 1, characterized in that, Also includes: A first conductive plug, which is electrically connected to the first drain layer; The second conductive plug is electrically connected to the second drain layer; The third conductive plug is electrically connected to the first conductive plug and the first bit line layer respectively; The fourth conductive plug is electrically connected to the second conductive plug and the second bit line layer, respectively.

4. The memory cell as claimed in claim 3, characterized in that, The first conductive plug has a first axis of symmetry extending along the first direction, and the second conductive plug has a second axis of symmetry extending along the first direction, wherein the first axis of symmetry coincides with the second axis of symmetry. The third conductive plug is in partial contact with the first conductive plug; the fourth conductive plug is in partial contact with the second conductive plug.

5. The memory cell as claimed in claim 3, characterized in that, The first conductive plug has a first axis of symmetry extending along the first direction, the second conductive plug has a second axis of symmetry extending along the first direction, and the first axis of symmetry and the second axis of symmetry do not coincide; the third conductive plug is in complete contact with the first conductive plug; and the fourth conductive plug is in complete contact with the second conductive plug.

6. The memory cell as claimed in claim 1, characterized in that, Also includes: A metal contact layer located on the word line layer.

7. A method for forming a memory cell, characterized in that, include: A substrate is provided having an active region extending along a first direction; A first floating gate structure and a second floating gate structure are formed on the active region along the first direction; A barrier layer is formed on the sidewall and top surface of the first floating gate structure and on the sidewall and top surface of the second floating gate structure; A common source layer, a first drain layer, and a second drain layer are formed in the active region. The first drain layer and the common source layer are located on both sides of the first floating gate structure, and the second drain layer and the common source layer are located on both sides of the second floating gate structure. The common source layer is located between the first floating gate structure and the second floating gate structure. A word line layer on the substrate, the word line layer extending along a second direction, the word line layer covering the first floating gate structure and the second floating gate structure, the first direction being perpendicular to the second direction; A first bit line layer and a second bit line layer are formed, both extending along the first direction. The first bit line layer is electrically connected to the first drain layer, and the second bit line layer is electrically connected to the second drain layer.

8. The method for forming a memory cell as described in claim 7, characterized in that, The barrier layer includes: a first oxide layer, a nitrided layer located on the surface of the first oxide layer, and a second oxide layer located on the surface of the nitrided layer.

9. The method for forming a memory cell as described in claim 7, characterized in that, The first floating gate structure and the second floating gate structure are formed simultaneously; the method for forming the first floating gate structure and the second floating gate structure includes: forming a floating gate material layer on the substrate; and performing patterned etching on the floating gate material layer to form the first floating gate structure and the second floating gate structure.

10. The method for forming a memory cell as described in claim 7, characterized in that, The method for forming the common source layer, the first drain layer, and the second drain layer includes: using the first floating gate structure and the second floating gate structure as masks, injecting source and drain ions into the active region to form the common source layer, the first drain layer, and the second drain layer.

11. The method for forming a memory cell as described in claim 7, characterized in that, The method of electrically connecting the first bit line layer to the first drain layer and the second bit line layer to the second drain layer includes: forming a first conductive plug and a second conductive plug, wherein the first conductive plug is electrically connected to the first drain layer and the second conductive plug is electrically connected to the second drain layer; forming a third conductive plug and a fourth conductive plug, wherein the third conductive plug is electrically connected to the first conductive plug and the first bit line layer respectively, and the fourth conductive plug is electrically connected to the second conductive plug and the second bit line layer respectively.

12. The method for forming a memory cell as described in claim 11, characterized in that, The first conductive plug has a first axis of symmetry extending along the first direction, and the second conductive plug has a second axis of symmetry extending along the first direction, wherein the first axis of symmetry coincides with the second axis of symmetry. The third conductive plug is in partial contact with the first conductive plug; the fourth conductive plug is in partial contact with the second conductive plug.

13. The method for forming a memory cell as described in claim 11, characterized in that, The first conductive plug has a first axis of symmetry extending along the first direction, the second conductive plug has a second axis of symmetry extending along the first direction, and the first axis of symmetry and the second axis of symmetry do not coincide; the third conductive plug is in complete contact with the first conductive plug; and the fourth conductive plug is in complete contact with the second conductive plug.

14. The method for forming a memory cell as described in claim 7, characterized in that, The first bit line layer and the second bit line layer are formed simultaneously; the method for forming the first bit line layer and the second bit line layer includes: forming a first bit line groove and a second bit line groove; forming the first bit line layer in the first bit line groove and forming the second bit line layer in the second bit line groove.

15. The method for forming a memory cell as described in claim 14, characterized in that, The first and second bit slots are formed using a self-aligned dual imaging process.

16. The method for forming a memory cell as described in claim 7, characterized in that, After forming the word line layer, the method further includes forming a metal contact layer on the word line layer.

17. A memory array, characterized in that, include: A plurality of memory groups are arranged parallel to each other along a first direction, each group comprising a plurality of memory cells as described in any one of claims 1 to 6, wherein the plurality of memory cells are arranged along a second direction, the first direction being perpendicular to the second direction; wherein... In each of the memory groups, a plurality of memory cells share the word line layer; In each of the memory groups, the common source layer is electrically connected to a plurality of the memory cells; The adjacent storage groups are distributed in a mirror-symmetric manner; Adjacent storage groups share either the first drain layer or the second drain layer; The adjacent memory groups share the first bit line layer and the second bit line layer.

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