Dividing process for integrated circuit layers with high accuracy bonding

Abstract

A singulation process for integrated circuit layers with high accuracy bonding is described. In an example, an integrated circuit structure includes a front end of line (FEOL) stack having an uppermost surface including a first conductive feature and a first dielectric feature. A back end of line (BEOL) stack is over the FEOL stack. The BEOL stack has a lowermost surface including a second conductive feature and a second dielectric feature in contact with a corresponding one of the first conductive feature and the first dielectric feature, respectively, of the uppermost surface of the FEOL stack. The second conductive features are laterally offset from the corresponding first conductive features.

Description

BACKGROUND

[0001] Over the past several decades, scaling of features in integrated circuits has been the driving force behind the ever-evolving semiconductor industry. Scaling to smaller and smaller features has enabled increasing the density of functional units on the limited footprint of a semiconductor chip. For example, shrinking transistor size allows incorporating an increased number of memory or logic devices on a chip, thereby facilitating the manufacture of products with increased capacity. However, the pursuit of greater capacity is not without problems. The necessity to optimize the performance of each device becomes increasingly significant.

[0002] The variability of conventional and currently known manufacturing processes can limit the possibility of further extending them to the 10-nanometer node or sub-10-nanometer node range. Therefore, the manufacture of functional components required for future technology nodes can require the introduction of new methods or the integration of new technologies into or in place of the current manufacturing processes.

[0003] As the size of these basic building blocks of microelectronic circuitry is reduced and as the absolute number of basic building blocks fabricated in a given area increases, the constraints on photolithography processes used to pattern these building blocks have become overwhelming. In particular, there can be a tradeoff between the minimum size (critical dimension) of features patterned in a semiconductor stack and the spacing between these features. Additionally, the absolute number of layers and operations used to manufacture an integrated circuit structure has dramatically increased. BRIEF DESCRIPTION OF DRAWINGS

[0004] Figures 1A-1B illustrates cross-sectional views representing various operations in a method in which two independent wafers are generated for front-end and back-end sections, in accordance with an embodiment of the disclosure.

[0005] Figure 1C illustrates a cross-sectional view of a structure composed of two bonded portions, in accordance with an embodiment of the disclosure.

[0006] Figures 1D-1E illustrates cross-sectional views representing various operations in a method in which three independent wafers are generated for front-end and backside power layers, in accordance with an embodiment of the disclosure.

[0007] Figure 2 illustrates cross-sectional views of an interconnect stack with frontside power delivery and an interconnect stack with backside power delivery, in accordance with an embodiment of the disclosure.

[0008] Figure 3 illustrates a cross-sectional view of an integrated circuit structure with a nanowire layer and backside power delivery, in accordance with an embodiment of the disclosure.

[0009] Figures 4A-4JFIG. illustrates cross-sectional views of various operations in a method of fabricating a gate-all-around integrated circuit structure, in accordance with an embodiment of the present disclosure.

[0010] Figure 5 FIG. illustrates a cross-sectional view of a non-planar integrated circuit structure taken along a gate line, in accordance with an embodiment of the present disclosure.

[0011] Figure 6 is a schematic diagram of a pitch quartering scheme for fabricating trenches for an interconnect structure, in accordance with an embodiment of the present disclosure.

[0012] Figure 7A FIG. illustrates a cross-sectional view of a metallization layer fabricated using a pitch quartering scheme, in accordance with an embodiment of the present disclosure.

[0013] Figure 7B FIG. illustrates a cross-sectional view of a metallization layer fabricated using a pitch halfing scheme over a metallization layer fabricated using a pitch quartering scheme, in accordance with an embodiment of the present disclosure.

[0014] Figure 8A FIG. illustrates a cross-sectional view of an integrated circuit structure having a metallization layer with metal line components over a metallization layer with different metal line components, in accordance with an embodiment of the present disclosure.

[0015] Figure 8B FIG. illustrates a cross-sectional view of an integrated circuit structure having a metallization layer with metal line components coupled to a metallization layer with different metal line components, in accordance with an embodiment of the present disclosure.

[0016] Figures 9A-9C FIG. illustrates cross-sectional views of individual interconnect lines having various liner and conductive cap structure arrangements, in accordance with an embodiment of the present disclosure.

[0017] Figure 10 FIG. illustrates a cross-sectional view of an integrated circuit structure having four metallization layers with metal line components and pitches over two metallization layers with different metal line components and smaller pitches, in accordance with an embodiment of the present disclosure.

[0018] Figure 11 FIG. illustrates a cross-sectional view of a metallization layer stack including a conductive line plug at a lower metal line location, in accordance with an embodiment of the present disclosure.

[0019] Figure 12 FIG. illustrates a computing device, in accordance with an implementation of the present disclosure.

[0020] Figure 13FIG. illustrates a dielectric layer including one or more embodiments of the present disclosure.

[0021] Figure 14 is an isometric view of a mobile computing platform that incorporates an integrated circuit (IC) made according to one or more processes described herein or including one or more features described herein according to embodiments of the present disclosure.

[0022] Figure 15 FIG. illustrates a cross-sectional view of a flip chip mounted die according to embodiments of the present disclosure. DETAILED DESCRIPTION

[0023] Advanced integrated circuit structure fabrication is described. In the following description, numerous specific details are set forth such as specific integrated and material regimes, in order to provide a thorough understanding of embodiments of the present disclosure. It will be apparent, however, to one skilled in the art, that embodiments of the present disclosure can be practiced without such specific details. In other instances, well-known features such as integrated circuit design layouts are not described in detail in order to not unnecessarily obscure embodiments of the present disclosure. Also, it is to be understood that the various embodiments shown in the figures are merely illustrative representations and are not necessarily drawn to scale.

[0024] The following detailed description is merely illustrative in nature and is not intended to limit the embodiments of the subject matter or the application and uses of such embodiments. As used herein, the word “exemplary” means “serving as an example, instance, or illustration.” Any implementation described herein as exemplary is not necessarily to be construed as preferred or advantageous over other implementations. Furthermore, there is no intention to be bound by any expressed or implied theory presented in the preceding technical field, background, summary or the following detailed description.

[0025] This specification includes recitations of “one embodiment” or “an embodiment.” The occurrence of the phrase “in one embodiment” or “in an embodiment” does not necessarily refer to the same embodiment. Particular features, structures, or characteristics can be combined in any suitable manner in one or more embodiments that are consistent with this disclosure.

[0026] Terminology. The following paragraphs provide definitions or context for terminology found in the present disclosure, including the appended claims:

[0027] “Comprise.” This term is open-ended. As used in the appended claims, this term does not foreclose additional structure or operations.

[0028] "Configured for". Various units or components can be described or claimed as being "configured for" performing one or more tasks. In such a context, by indicating that a unit or component includes a structure that performs those one or more tasks during operation, "configured for" refers to the structure. Thus, a unit or component can be said to be configured for performing a task even when the specified unit or component is not currently operable (e.g., not turned on or active). The statement that a unit or circuit or component is "configured for" performing one or more tasks is explicitly intended not to invoke paragraph 6 of 35 U.S.SC §112 for that unit or component.

[0029] "First," "second," etc. As used in this article, these terms serve as labels for the nouns preceding them and do not imply any type of order (e.g., spatial, temporal, logical, etc.).

[0030] "Coupling"—the following description refers to elements, nodes, or features that are "coupled" together. As used herein, unless otherwise expressly stated, "coupling" means that one element, node, or feature is directly or indirectly connected to (or communicates directly or indirectly with) another element, node, or feature, and not necessarily mechanically.

[0031] Furthermore, certain terms may be used in the following description for illustrative purposes only and are therefore not intended to be limiting. For example, terms such as “upper,” “lower,” “above,” and “below” refer to orientation in the referenced figures. Terms such as “front,” “rear,” “rear,” “side,” “outer,” and “inner” describe the orientation or position, or both orientation and position, of the parts of a component within a consistent but arbitrary frame of reference, which becomes clear by reference to the text describing the component under discussion and the associated figures. Such terms may include words specifically mentioned above, their derivatives, and words with similar meanings.

[0032] "Inhibition"—as used herein—is used to describe the reduction or minimization of an effect. When a component or feature is described as inhibiting an action, movement, or condition, it may completely prevent the result or consequence or future state. Additionally, "inhibition" may also refer to a reduction or mitigation of a consequence, performance, or effect that might otherwise occur. Accordingly, when a component, element, or feature is described as inhibiting a result or state, it is not necessary to completely prevent or eliminate the result or state.

[0033] The embodiments described herein may relate to front-end-of-line (FEOL) semiconductor processing and structures. FEOL is the first part of integrated circuit (IC) fabrication, in which individual devices (e.g., transistors, capacitors, resistors, etc.) are patterned in a semiconductor substrate or layer. FEOL typically covers all deposits up to (but not including) metal interconnect layers. After the final FEOL operation, the result is typically a wafer with isolated transistors (e.g., without any wires).

[0034] The embodiments described herein may relate to back-end-of-line (BEOL) semiconductor processing and structures. BEOL is the second part of IC manufacturing, where individual devices (e.g., transistors, capacitors, resistors, etc.) are interconnected with wiring (e.g., one or more metallization layers) on the wafer. BEOL includes contacts, insulating layers (dielectrics), metal layers, and bonding sites for chip-to-package connections. During the manufacturing phase, interconnects, vias, and dielectric structures are formed in the BEOL portion of the contacts (pads). For modern IC processes, more than 10 metal layers can be added to the BEOL.

[0035] The embodiments described below can be applied to FEOL processing and structure, BEOL processing and structure, or both FEOL and BEOL processing and structure. Specifically, although an FEOL processing scenario can be used to illustrate an exemplary processing scheme, such a method can also be applied to BEOL processing. Similarly, although a BEOL processing scenario can be used to illustrate an exemplary processing scheme, such a method can also be applied to FEOL processing.

[0036] It should be understood that FEOL is a technology driver for a given process. In other embodiments, FEOL is considered to be driven by BEOL 10nm or sub-10nm processing requirements. For example, the material selection and layout of the FEOL layer and devices may need to be adapted to BEOL processing. In one such embodiment, material selection and gate stack architecture are chosen to accommodate the high-density metallization of the BEOL layer, for example, to reduce edge capacitance in transistor structures formed in the FEOL layer but coupled together through the high-density metallization of the BEOL layer.

[0037] Back-to-line (BEOL) layers of integrated circuits typically include conductive microelectronic structures, referred to in the art as vias, used to electrically connect metal lines or other interconnects above the vias to metal lines or other interconnects below the vias. Vias can be formed using photolithography. Typically, a photoresist layer can be spin-coated onto a dielectric layer. The photoresist layer can be exposed to patterned photoluminescence through a patterned mask, and the exposed layer can then be developed to form openings in the photoresist layer. Next, the openings for the vias can be etched in the dielectric layer using the openings in the photoresist layer as an etching mask. These openings are referred to as via openings. Finally, the via openings can be filled with one or more metals or other conductive materials to form the via.

[0038] For at least some types of integrated circuits (e.g., advanced microprocessors, chipset components, graphics chips, etc.), the size and pitch of vias have been progressively decreasing, and this trend is expected to continue. Several challenges arise when patterning extremely small vias with very fine pitches using photolithography. One such challenge is that the overlay between vias and overlying interconnects, and between vias and underlying landing interconnects, typically requires high tolerances controlled to the order of a quarter of the via pitch. As via pitches become increasingly smaller over time, overlay tolerances tend to scale at a rate greater than that that photolithography equipment can keep up with.

[0039] Another challenge is that the critical size of via apertures typically tends to scale faster than the resolution capabilities of photolithography scanners. Shrinkage techniques exist to reduce the critical size of via apertures. However, the amount of shrinkage tends to be limited by the minimum via pitch and by the ability of the shrinkage process to be sufficiently optical proximity correction (OPC) neutral without significantly compromising line width roughness (LWR) or critical dimension uniformity (CDU), or both LWR and CDU. Yet another challenge is that as the critical size of via apertures decreases, the properties of the photoresist's LWR or CDU, or both LWR and CDU, often need to be improved to maintain the same overall fraction of the critical size budget.

[0040] The aforementioned factors also relate to the placement and scaling of non-conductive spaces or interruptions between metal wires (referred to as "plugs," "dielectric plugs," or "wire ends") within the metal wires of the back-end metal interconnect structure. Therefore, improvements are needed in the back-end metallization manufacturing technology used to manufacture metal wires, metal vias, and dielectric plugs.

[0041] One or more embodiments described herein relate to a dicing process for fabrication layers with high-accuracy bonding. One or more embodiments described herein relate to an integrated circuit structure formed using dicing and bonding, and including devices or circuits based on a full-around-gate. It should be understood that, unless otherwise stated, the designation of a nanowire may refer to a nanowire, nanoribbon, or nanosheet. One or more embodiments described herein relate to an integrated circuit structure formed using dicing and bonding, and including fin-based devices or circuits. One or more embodiments described herein relate to an integrated circuit structure formed using dicing and bonding, and including planar-based devices or circuits, wherein the devices are formed on a planar semiconductor surface rather than a non-planar surface.

[0042] To provide context, highly complex semiconductor manufacturing processes can take several months to go from FEOL to BEOL. This long processing time can impact throughput and yield learning. Since FEOL / BEOL are typically processed within the same microchip fabrication facility (fab), the fab space / capacity can be limited to handling the entire process within a single fab.

[0043] Currently, a key approach is to improve the cycle time of each operation to increase throughput. This is typically achieved by building multiple plants to meet the ever-growing demand for semiconductor processing. Each plant has replicas of FEOL and BEOL to support this demand.

[0044] One or more embodiments described herein relate to front-end and back-end processing on a separate wafer. In these embodiments, high-accuracy bonding techniques are used to bond wafers having front-end and back-end layers together to produce a final configuration. In these embodiments, the bonding process can be performed in a wafer-to-wafer (W2W) or chip-to-wafer (C2W) configuration.

[0045] Advantages of implementing one or more embodiments described herein may include enabling the independent processing of front-end (FE) and back-end (BE) wafers, which can significantly reduce manufacturing lead times and accelerate yield learning. FE / BE wafers can be processed in different microchip fabrication plants or according to different processing schedules and inventory management, thereby alleviating the yield constraints of a single plant. The FE-BE process can be decoupled, allowing additional BE processes such as annealing or plasma processing to not affect transistor performance. Optional removable layers can be added prior to bonding to functionally classify each wafer before bonding to achieve known good die solutions. In embodiments, one or more optional removable redistribution layers (RDLs) are included to classify each wafer.

[0046] Detection of implementations of one or more embodiments described herein may include observing the bonding structure between the front and rear ends using cross-section transmission electron microscopy (xTEM). Alignment marks available for bonding can be detected by cross-section scanning electron microscopy (xSEM) or xTEM. Any misaligned layers at the bonding interface can be indicators of the bonding layers, such as those described below. Figure 1C As described. If a chip-to-wafer approach is used, the bottom and top die sizes can differ, and additional inter-layer dielectric (ILD) features may exist in the scribe lines. Such features can be detected by xSEM. After FIB thinning, top-down inspection of the bonding structure can be used to identify the embodiments described herein.

[0047] As an example process Figures 1A-1B The figures illustrate cross-sectional views representing various operations in a method according to an embodiment of the present disclosure, in which two separate wafers are generated for a front-end segment and a back-end segment.

[0048] refer to Figure 1APart (a) of the initial structure 100 (which may be referred to as wafer 2 structure) includes a carrier wafer or substrate 102, such as a silicon wafer or substrate. A dielectric layer 104 (such as a silicon oxide or silicon dioxide layer) is on the carrier wafer or substrate 102. A back-to-office (BEOL) stack 106 is on the dielectric layer 104. The BEOL stack 106 includes one or more layers, such as conductive lines 108 and vias 110, for example, in the surrounding dielectric layers or the dielectric layer stack, which may be referred to as metallization layers.

[0049] refer to Figure 1A In part (b), the carrier wafer or substrate 114 (such as a silicon wafer or substrate) and the dielectric layer 112 (such as a silicon oxide or silicon dioxide layer) are coupled to the BEOL stack 106.

[0050] refer to Figure 1A Part (c), the starting structure 116 (which may be referred to as wafer 1 structure) includes a carrier wafer or substrate 118, such as a silicon wafer or substrate. A dielectric layer 120 (such as a silicon oxide or silicon dioxide layer) is on the carrier wafer or substrate 118. A front-end process (FEOL) stack 122 is on the dielectric layer 120. The FEOL stack 122 includes one or more layers of devices 124A and 124B (such as complementary metal oxide semiconductor (CMOS) devices), and one or more layers of device contacts 126A and 126B (e.g., in the surrounding dielectric layers or dielectric layer stack).

[0051] refer to Figure 1A Part (d), arrangement 130 includes initial structure 116 and structure 128. Structure 128 represents Figure 1A Part (b) has such a structure: the carrier wafer or substrate 102 and the dielectric layer 104 are removed, and the resulting structure is inverted to provide an inverted BEOL stack 106A.

[0052] refer to Figure 1B Part (e) will come from Figure 1A The arrangement of part (d) 130 is shown as the initial structure.

[0053] refer to Figure 1BPart (f) provides a unified structure 132 by incorporating the starting structure 116 into the structure 128. In one embodiment, the unified structure 132 is achieved using a metal-to-metal bond between the starting structure 116 and the structure 128. In one embodiment, the unified structure 132 is achieved using a dielectric-to-dielectric bond between the starting structure 116 and the structure 128. In one embodiment, the unified structure 132 is achieved using both a metal-to-metal bond and a dielectric-to-dielectric bond between the starting structure 116 and the structure 128. It should be understood that for hybrid bonding, both metal-to-metal bonding and dielectric-to-dielectric bonding are employed.

[0054] refer to Figure 1B Part (g) forms the integrated circuit structure 138 by removing the carrier wafer or substrate 114 from beneath the BEOL stack 106A. Conductive bumps 136 may be formed on the dielectric layer 134 and coupled to the conductive lines of the BEOL stack 106A. The dielectric layer 134 may be a patterned dielectric layer 112 or a new dielectric layer.

[0055] Refer again Figure 1A and Figure 1B According to embodiments of the present disclosure, an integrated circuit structure includes a front-end process (FEOL) stack 122 having a surface including a first conductive feature and a first dielectric feature. A back-end process (BEOL) stack 106A is coupled to the FEOL stack. The BEOL stack 106A has a surface including a second conductive feature and a second dielectric feature respectively contacting one of the first conductive feature and the first dielectric feature on the surface of the FEOL stack 122. In one embodiment, the second conductive feature is laterally offset from the corresponding first conductive feature, such as by bonding... Figure 1C Described.

[0056] In one embodiment, the first conductive feature and the second conductive feature comprise copper, and the first dielectric feature and the second dielectric feature comprise silicon and oxygen. In one embodiment, the FEOL stack 122 comprises a device based on a fully surrounding gate. In one embodiment, the FEOL stack 122 comprises a fin-based device. In one embodiment, the structure further comprises a back-side stack having a surface in contact with the surface of the FEOL stack 122, such as a bonding... Figure 1D and Figure 1E As described. It should be understood that although many embodiments involve the segmentation of the front-end and back-end layers, depending on the application, other embodiments may include a segmentation between a front-end having a lower back-end layer and a structure including one or more upper back-end layers.

[0057] Refer again Figure 1A andFigure 1B As a general overview, it should be understood that several arrangements are possible. In one embodiment, wafer 1 / wafer 2 can be bonded using a wafer-to-wafer or chip-to-wafer bonding scheme. In one embodiment, for wafer-to-wafer bonding, a fiducial is placed at the frame. In one embodiment, for chip-to-wafer bonding, the fiducial is included within the die. In one embodiment, additional singulation and passivation operations are included. In one embodiment, the BE layer in wafer 2 can be grown from small pitch to large pitch using conventional methods. In one embodiment, this scheme uses CW bonding and silicon polishing to flip the layer, such as... Figure 1A and Figure 1B As shown in the figure. In one embodiment, the BE layer in wafer 2 can be grown in reverse order from large pitch to small pitch, which can be achieved from... Figure 1A and Figure 1B This approach eliminates the carrier wafer bonding operation. Compared to conventional BE processing, this approach can result in the carrier layer being in the opposite position, which can be detected using failure analysis (FA). In one embodiment, the back-side power layer can be used for bonding, such as the bonding described below. Figure 1D and Figure 1E The aforementioned. In this configuration, the front-side, back-side, and rear-side power layers can constitute three distinct wafers and involve three different bonding operations. In one embodiment, the bonding layer is located between, but not limited to, the front / back-side boundary. For example, depending on the availability of bonding accuracy, the bonding layer can be formed within the EUV or DUV layers in the BE stack. In one embodiment, the bonding dielectric can be an oxide (e.g., silicon oxide) or one or more other dielectric materials including oxide nitride, SiCN, SiN, etc. In one embodiment, copper (Cu) is used for metal-to-metal bonding, but bonding between different types of metals can also be used. The following description... Figure 1C This describes a bonding process using oxide as the dielectric layer and Cu as the metal-to-metal bonding layer. In one embodiment, the process described herein allows for different dies within the same mask by bonding different FE / BE stacks on different dies. In one embodiment, the process described herein also allows for different BE routes for the same FE stack within the same SOC design, enabling different routing requirements to be achieved using the same FE design.

[0058] Refer again Figure 1A and Figure 1BAs a general overview, according to embodiments of this disclosure, the manufacturing process includes the independent processing of two distinct wafers having a front end (wafer 1) and a back end (wafer 2). In one embodiment, when processing wafer 2 with a BE layer, the BE layer is processed from small pitch to large pitch, leaving bulk silicon beneath the lowest pitch layer. In one embodiment, to achieve bonding, a carrier wafer is first attached, and the original bulk silicon is removed prior to bonding. In one embodiment, a bonding layer is located between the front / back end boundaries. In one embodiment, bonding is initiated between dielectric films, and an additional curing process facilitates bonding between metal layers. In one embodiment, wafer 1 and wafer 2 are attached using high-accuracy bonding without excessive overlay errors. In one embodiment, once bonding is complete, the silicon carrier wafer on wafer 2 is removed before a bump layer can be added to enable classification / category testing for yield learning.

[0059] It should be understood that the joining structures described herein may be slightly laterally offset from each other as a result of the bonding process. This offset can manifest as an artifact in the resulting structure. As an example, Figure 1C The figure shows a cross-sectional view of a structure 140 consisting of two joining portions 142 and 144 according to an embodiment of the present disclosure.

[0060] refer to Figure 1C The upper substrate or wafer 142 includes a carrier substrate 148 above conductors and vias 142A, 142B, 142C in one or more dielectric layers 145. The lower substrate or wafer 144 includes a carrier or dielectric layer below a stack of devices and / or metallization layers 144A, 144B, 144C, 144D, 144E in one or more dielectric layers 145. An interface 146 is located between the two bonding portions 142 and 144. The interface 146 may include a region or metal-to-metal bonding, a dielectric-to-dielectric bonding, or both metal-to-metal bonding and dielectric-to-dielectric bonding. In one embodiment, the two bonding portions 142 and 144 are slightly laterally offset from each other. For example, as shown, a conductive feature 144E bonds to and contacts an overlying similar feature, but the features are laterally offset from each other, for example, as depicted by the offsets on their corresponding central vertical axes 147A and 147B.

[0061] As an example process Figures 1D-1E The figure shows a cross-sectional view illustrating various operations in a method according to an embodiment of the present disclosure, in which three separate wafers are generated for the front-side and back-side power layers.

[0062] refer to Figure 1DPart (a) of the starting structure 150 (which may be referred to as wafer 2 structure) includes a carrier wafer or substrate 152, such as a silicon wafer or substrate. A back-to-office (BEOL) stack 154 is placed on the carrier wafer or substrate 152. The BEOL stack 154 includes one or more layers, such as conductive lines and vias in a surrounding dielectric layer or dielectric layer stack, which may be referred to as a metallization layer. A dielectric layer 156 (such as a silicon oxide or silicon dioxide layer) is placed on the BEOL stack 154.

[0063] Refer again Figure 1D Part (a) of the initial structure 158 (which may be referred to as wafer 1 structure) includes a carrier wafer or substrate 160, such as a silicon wafer or substrate. A dielectric layer 162 (such as a silicon oxide or silicon dioxide layer) is on the carrier wafer or substrate 160. A front-end process (FEOL) stack 164 is on the dielectric layer 162. The FEOL stack 164 includes one or more layers of devices (such as complementary metal-oxide-semiconductor (CMOS) devices) and one or more layers of device contacts (e.g., in the surrounding dielectric layers or dielectric layer stack).

[0064] refer to Figure 1D In part (b), the carrier wafer or substrate 152 is removed from the starting structure 150. The resulting structure is bonded to the starting structure 158 to form a unified structure 166. In one embodiment, the unified structure 166 is implemented using a metal-to-metal bond between the starting structure 158 and the BEOL stack 154. In one embodiment, the unified structure 166 is implemented using a dielectric-to-dielectric bond between the starting structure 158 and the BEOL stack 154. In one embodiment, the unified structure 166 is implemented using both a metal-to-metal bond and a dielectric-to-dielectric bond between the starting structure 158 and the BEOL stack 154. It should be understood that for hybrid bonding, both metal-to-metal bonding and dielectric-to-dielectric bonding are used.

[0065] refer to Figure 1E In part (c), a unified structure 166 is shown above the starting structure 168 (which may be referred to as wafer 3 structure). The starting structure 168 includes a carrier wafer or substrate 170, such as a silicon wafer or substrate. A back-to-office (BEOL) stack 172 is on the carrier wafer or substrate 170. The BEOL stack 172 includes one or more layers, such as conductive lines and vias in a surrounding dielectric layer or dielectric layer stack, which may be referred to as a metallization layer. A dielectric layer 174 (such as a silicon oxide or silicon dioxide layer) is on the BEOL stack 172.

[0066] refer to Figure 1EIn part (d), the carrier wafer or substrate 170 is removed from the starting structure 168, and the resulting structure is inverted to include an inverted BEOL stack 172A. The carrier wafer or substrate 160 and the dielectric layer 162 are removed from the starting structure 166. The remaining structures are joined together to form a unified structure. In one embodiment, a metal-to-metal bonding between the FEOL stack 164 and the BEOL stack 172 is used to achieve the unified structure. In one embodiment, a dielectric-to-dielectric bonding between the FEOL stack 164 and the BEOL stack 172 is used to achieve the unified structure. In one embodiment, both metal-to-metal bonding and dielectric-to-dielectric bonding between the FEOL stack 164 and the BEOL stack 172 are used to achieve the unified structure. The integrated circuit structure 180 may be formed to include a back-side conductive bump 176 on the dielectric layer 174A and conductive lines coupled to the BEOL stack 172A. The dielectric layer 174A may be a patterned dielectric layer 174 or it may be a new dielectric layer. Front-side conductive bumps may also be formed to contact the BEOL stack 154.

[0067] Refer again Figure 1A and Figure 1B According to embodiments of the present disclosure, an integrated circuit structure includes a front-end process (FEOL) stack 164 having a surface including a first conductive feature and a first dielectric feature. A back-side stack 172A is coupled to the FEOL stack 164. The back-side stack 172A has a surface including a second conductive feature and a second dielectric feature respectively contacting one of the first conductive feature and the first dielectric feature on the surface of the FEOL stack 164. In one embodiment, the second conductive feature is laterally offset from the corresponding first conductive feature, such as by bonding... Figure 1C Described.

[0068] In one embodiment, the first conductive feature and the second conductive feature comprise copper, and the first dielectric feature and the second dielectric feature comprise silicon and oxygen. In one embodiment, the FEOL stack 164 comprises a device based on a fully surrounding gate. In one embodiment, the FEOL stack 164 comprises a fin-based device. In one embodiment, the structure further comprises a front-end process (FEOL) stack 154 having a surface in contact with the surface of the FEOL stack 164.

[0069] In order to provide a combination Figures 1D-1EFurther background to the described process: conventionally, power is delivered from the front-side interconnect. At the standard cell level, power can be delivered directly on top of the transistor or from the top and bottom cell boundaries. Power delivered from the top and bottom cell boundaries results in a relatively short standard cell height and a slightly higher power network resistance. However, the front-side power network shares the interconnect stack with signal routing and reduces signal routing tracks. Furthermore, for high-performance designs, the power metal lines at the top and bottom cell boundaries must be wide enough to reduce power network resistance and improve performance. This typically leads to an increase in cell height. According to one or more embodiments of this disclosure, power can be delivered from the back side of the wafer or substrate to address area and performance issues. At the cell level, wider metal zero power lines at the top and bottom cell boundaries are no longer needed, and therefore the cell height can be reduced. Furthermore, the power network resistance can be significantly reduced, thereby improving performance. At the block and chip levels, the front-side signal routing tracks are increased due to the removal of power routing, and the power network resistance is significantly reduced due to very wide wires, large vias, and reduced interconnect layers.

[0070] In earlier technologies, the power delivery network from bumps to transistors required significant block resources. This resource usage on the metal stack manifested at some process nodes as a standard cell architecture with layout versioning or cell placement constraints at the block level. In this embodiment, eliminating the power delivery network from the front-side metal stack allows for free sliding cell placement within the block without power delivery complexity and placement-related timing variations.

[0071] In comparison, Figure 2 The figures illustrate cross-sectional views of an interconnect stack having front-side power delivery and an interconnect stack having back-side power delivery according to embodiments of the present disclosure.

[0072] refer to Figure 2 The interconnect stack 200 with front-side power delivery includes transistors 202 and signal and power delivery metallization 204. Transistor 202 includes a body substrate 206, semiconductor fins 208, terminals 210, and device contacts 212. Signal and power delivery metallization 204 includes conductive vias 214, conductive lines 216, and metal bumps 218.

[0073] Refer again Figure 2 The interconnect stack 250 with back-side power delivery includes transistors 252, front-side signal metallization 254A, and power delivery metallization 254B. Transistor 252 includes semiconductor nanowires or nanoribbons 258, terminals 260, device contacts 262, and boundary deep vias 263. Front-side signal metallization 254A includes conductive vias 264A and conductive lines 266A. Power delivery metallization 254B includes conductive vias 264B, conductive lines 266B, and metal bumps 268.

[0074] To provide further context, one of the ultimate goals in standard cell design is to minimize the impact of power delivery on signal routing in terms of area, while maintaining a robust power delivery scheme with minimal voltage drop from the power supply. For front-side power delivery, commercial standard cell architectures must allocate routing tracks for power and ground from the top of the front-side stack to the first metal routing layer M0. This approach utilizes metal routing tracks. This means that a tighter metal pitch is required to deliver power while routing signals. The tighter metal pitch results in higher cover and resistance, leading to higher power dissipation. Furthermore, a larger voltage drop occurs from the top of the stack to the transistor source due to resistance.

[0075] On the other hand, direct power connection to the back side is achieved through a deep through-hole structure or a back-side contact. Power gating is performed at the front end. As an example structure, Figure 3 The figure illustrates a cross-sectional view of an integrated circuit structure having a nanowire layer and back-side power delivery according to an embodiment of the present disclosure. It should be understood that, although in Figure 3 Nanowires (or nanoribbons or nanosheets) are depicted, but fin-based or planar architectures can also be used.

[0076] refer to Figure 3 The integrated circuit structure 300 includes a front structure 304 on a back structure 302. The front structure 304 includes a device layer 306 and a plurality of metallization layers 308 on the device layer 306. The structure 300 may be supported by a carrier wafer 310 on the front structure 304. The back structure 302 includes a stack of back conductive structures terminating at conductive bumps 312. In one embodiment, the upper metallization layer 308 (e.g., the metallization layer 308 above metal O) or all of the metallization layers 308 are formed as a separate BEOL wafer or chip, and the device layer 306 and the lower metallization layer (e.g., metal O) or only the device layer are formed as a separate FEOL wafer or chip.

[0077] In an embodiment, device layer 306 includes a field-effect transistor (FET), such as a nanowire-based (shown) or fin-based transistor. In one such embodiment, the FET is used for memory. In an embodiment, device layer 306 further includes a trench contact (TCN), a gate contact (GCN), and a contact via (VCX). In an embodiment, device layer 306 is on the deep via (DV) layer of the front-side structure 304, as depicted. In an embodiment, the plurality of metallization layers 308 include additional metal layers (e.g., M0-M12) and associated via layers (e.g., ...). Figure 3 (V0-V3 as indicated in the text).

[0078] In one embodiment, the back-side structure 302 includes multiple back-side metal layers (e.g., BMO-BM3) and associated vias. In another embodiment, the back-side structure 302 includes one or more power structures, such as ground metal lines (e.g., GM0 and GM1). In yet another embodiment, the back-side structure 302 includes one or more capacitor structures, such as metal-insulator-metal (MIM) capacitors. In one embodiment, the lower back-side metal layer (e.g., the back-side metal layer below BMO) or all back-side metal layers (e.g., BMO-BM3) are formed as a separate wafer or chip.

[0079] On the other hand, the aforementioned metallization structure or stack can be fabricated or bonded to the underlying or overlying device layer. Such a device layer can be a full-around gate device layer, a FinFET layer, or a planar device layer, or may include a full-around gate device layer, a FinFET layer, or a planar device layer.

[0080] It should be understood that, in certain embodiments, nanowires or nanoribbons, or fins, or sacrificial interlayers may be composed of silicon. As used throughout, silicon layers can be used to describe silicon materials composed of a very large amount (if not all) of silicon. However, it should be understood that, in practice, 100% pure Si may be difficult to form, and therefore may include very small percentages of carbon, germanium, or tin. Such impurities may be included as unavoidable impurities or components during Si deposition, or may “contaminate” Si during diffusion during post-deposition processing. Therefore, embodiments involving silicon layers described herein may include silicon layers containing relatively small amounts (e.g., “impurity” levels) of non-Si atoms or substances (such as Ge, C, or Sn). It should be understood that silicon layers as described herein may be undoped or may be doped with dopant atoms such as boron, phosphorus, or arsenic.

[0081] It should be understood that, in certain embodiments, the nanowires or nanoribbons, or fins, or sacrificial interlayers may be composed of silicon-germanium. As used throughout, a silicon-germanium layer can be used to describe a silicon-germanium material composed of a substantial portion of both silicon and germanium (such as at least 5% of both). In some embodiments, the amount of germanium is greater than the amount of silicon. In a particular embodiment, the silicon-germanium layer comprises about 60% germanium and about 40% silicon (Si). 40 Ge 60 In other embodiments, the amount of silicon is greater than the amount of germanium. In a particular embodiment, the silicon-germanium layer comprises about 30% germanium and about 70% silicon (Si). 70 Ge 30 However, it should be understood that in practice, 100% pure silicon germanium (commonly referred to as SiGe) may be difficult to form, and therefore may include very small percentages of carbon or tin. Such impurities may be included as unavoidable impurities or components during SiGe deposition, or may “contaminate” SiGe during diffusion during post-deposition processing. Therefore, the embodiments involving silicon germanium layers described herein may include silicon germanium layers containing relatively small amounts (e.g., “impurity” levels) of non-Ge and non-Si atoms or substances (such as carbon or tin). It should be understood that silicon germanium layers as described herein may be undoped or may be doped with dopant atoms such as boron, phosphorus, or arsenic.

[0082] It should be understood that the embodiments described herein may also include other implementations, such as nanowires and / or nanoribbons and / or fins having various widths, thicknesses and / or materials (including but not limited to Si and SiGe). For example, group III-V materials may be used.

[0083] Various devices and processing schemes that can be used to manufacture devices are described below. It should be understood that exemplary embodiments do not necessarily require all the features described, or may include more features than described. For example, nanowire release processing can be performed by replacing the gate trench. Examples of such release processes are described below. Additionally, in another aspect, back-side (BE) interconnect scaling can lead to lower performance and higher manufacturing costs due to patterning complexity. The embodiments described herein can be implemented to enable front-side and back-side interconnect integration of nanowire transistors. The embodiments described herein can provide methods for achieving relatively wide interconnect pitches. The result can be improved product performance and lower patterning costs. The embodiments can be implemented to enable robust functionality of scaled nanowire or nanoribbon transistors with low power and high performance.

[0084] One or more embodiments described herein are for oriented epitaxial (EPI) interconnects of nanowire or nanoribbon transistors using partial source or drain (SD) and asymmetric trench contact (TCN) depths. In the embodiments, an integrated circuit structure is fabricated by forming a source-drain opening in a nanowire / nanoribbon transistor partially filled with SD epitaxy. The remaining portion of the opening is filled with a conductive material. Deep trench formation on either the source or drain side enables direct contact to the back-side interconnect level.

[0085] As an exemplary process flow for manufacturing all-around gate integrated circuit structures, Figures 4A-4J The figures illustrate cross-sectional views of various operations in a method of manufacturing a gate-all-around integrated circuit structure according to embodiments of the present disclosure.

[0086] refer to Figure 4A A method for fabricating an integrated circuit structure includes forming an initial stack comprising alternating sacrificial layers 404 and nanowires 406 over a fin 402 (such as a silicon fin). The nanowires 406 may be referred to as a vertically arranged nanowire. As depicted, a protective cap 408 may be formed over the alternating sacrificial layers 404 and nanowires 406. A relaxation buffer layer 452 and a defect modification layer 450 may be formed beneath the alternating sacrificial layers 404 and nanowires 406, also as depicted.

[0087] refer to Figure 4B Gate stack 410 is formed above the vertical arrangement of horizontal nanowires 406. The vertically arranged portion of the horizontal nanowires 406 is then released by removing a portion of the sacrificial layer 404 to provide a recessed sacrificial layer 404' and cavity 412, as... Figure 4C As depicted in the text.

[0088] It should be understood that Figure 4C The structure can be fabricated without first performing the deep etching and asymmetric contact processing described below. In either case (e.g., with or without asymmetric contact processing), in the embodiments, the fabrication process involves using a process scheme that provides a gate-all-around integrated circuit structure having epitaxial blocks, which may be vertically discrete source or drain structures.

[0089] refer to Figure 4D An upper gate spacer 414 is formed at the sidewall of the gate structure 410. A cavity spacer 416 is formed in a cavity 412 below the upper gate spacer 414. Optionally, deep trench contact etching is then performed to form a trench 418 and a recessed nanowire 406'. A patterned relaxation buffer layer 452' and a patterned defect modification layer 450' may also be present, as depicted.

[0090] Then, sacrificial material 420 is formed in the trench 418, such as Figure 4E As depicted in the text. In other process solutions, an isolated trench bottom or a silicon trench bottom can be used.

[0091] refer to Figure 4F A first epitaxial source or drain structure (e.g., left-side feature 422) is formed at a first end of a vertically arranged horizontal nanowire 406'. A second epitaxial source or drain structure (e.g., right-side feature 422) is formed at a second end of a vertically arranged horizontal nanowire 406'. In embodiments, as depicted, the epitaxial source or drain structure 422 is a vertically discrete source or drain structure and may be referred to as an epitaxial blob. In other embodiments, the epitaxial source or drain structure 422 is a vertically non-discrete source or drain structure, wherein a single merged structure replaces multiple blobs.

[0092] Then, an interlayer dielectric (ILD) material 424 is formed on the side of the gate electrode 410 and adjacent to the source or drain structure 422, such as Figure 4G As depicted in [the text]. Reference Figure 4H A replacement gate process is used to form the permanent gate dielectric 428 and the permanent gate electrode 426. Then, the ILD material 424 is removed, as shown below. Figure 4I As depicted in the diagram. The sacrificial material 420 is then removed from one of the source and drain locations (e.g., the right-hand side) to form the trench 432, but the sacrificial material 420 is not removed from the other source and drain location to form the trench 430.

[0093] refer to Figure 4J The first conductive contact structure 434 is formed to couple to a first epitaxial source or drain structure (e.g., left-side feature 422). The second conductive contact structure 436 is formed to couple to a second epitaxial source or drain structure (e.g., right-side feature 422). The second conductive contact structure 436 is formed to be deeper along the fin 402 than the first conductive contact structure 434. In the embodiment, although... Figure 4J Not depicted, but the method further includes forming an exposed surface of a second conductive contact structure 436 at the bottom of the fin 402. The conductive contact may include a contact resistance reduction layer and a main contact electrode layer, wherein examples may include Ti, Ni, Co (for the former) and W, Ru, Co (for the latter).

[0094] In one embodiment, the second conductive contact structure 436 is deeper along the fin 402 than the first conductive contact structure 434, as depicted. In one such embodiment, the first conductive contact structure 434 is not along the fin 402, as depicted. In another such embodiment not depicted, the first conductive contact structure 434 is partially along the fin 402.

[0095] In one embodiment, the second conductive contact structure 436 extends along the entire fin 402. In another embodiment, although not depicted, the second conductive contact structure 436 has an exposed surface at the bottom of the fin 402 if the bottom of the fin 402 is exposed via a backside substrate removal process.

[0096] On the other hand, in order to access both conductive contact structures in a pair of asymmetric source and drain contact structures, the integrated circuit structure described herein can be fabricated using back-side exposure using a front-side fabrication method. In some exemplary embodiments, back-side exposure of transistors or other device structures requires wafer-level back-side processing. In contrast to conventional TSV-type techniques, back-side exposure of transistors as described herein can be performed at device cell density and even within sub-regions of the device. Furthermore, such back-side exposure of transistors can be performed to substantially remove the entire donor substrate, on which the device layer is disposed during front-side device processing. Thus, micrometer-deep TSVs become unnecessary, as the thickness of the semiconductor in the device cell may be only tens or hundreds of nanometers after back-side exposure of the transistor.

[0097] The exposure techniques described in this article enable a paradigm shift from "bottom-up" device fabrication to "center-out" fabrication, where "center" refers to any layer that is used in front-side fabrication, exposed from the back side, and reused in back-side fabrication. When relying primarily on front-side processing, processing both the front and exposed back sides of the device structure can address many of the challenges associated with manufacturing 3D ICs.

[0098] For example, a back-side exposure using a transistor approach can be used to remove at least a portion of the carrier layer and intermediate layer of a donor-host substrate assembly. The process flow begins with the input of the donor-host substrate assembly. A carrier layer of a certain thickness in the donor-host substrate is polished (e.g., chemical mechanical polishing (CMP)) and / or etched using a wet or dry (e.g., plasma) etching process. Any grinding, polishing, and / or wet / dry etching process known to be suitable for the components of the carrier layer can be used. For example, in the case where the carrier layer is a group IV semiconductor (e.g., silicon), a CMP paste known to be suitable for thinning semiconductors can be used. Similarly, any wet etchant or plasma etching process known to be suitable for thinning group IV semiconductors can also be used.

[0099] In some embodiments, prior to the above-described process, the carrier layer is peeled off along a fracture plane substantially parallel to the intermediate layer. The peeling or fracture process can be used to remove a large portion of the carrier layer as a bulk, thereby reducing the polishing or etching time required to remove the carrier layer. For example, in the case of a carrier layer thickness of 400-900 μm, 100-700 μm can be peeled off by practicing any known blanket implant that promotes wafer-level fracture. In some exemplary embodiments, a lightweight element (e.g., H, He, or Li) is implanted into the carrier layer at a uniform target depth within the desired fracture plane. After such a peeling process, the thickness of the carrier layer remaining in the donor-host substrate assembly can then be polished or etched to complete the removal. Alternatively, in the case where the carrier layer is not fractured, grinding, polishing, and / or etching operations can be used to remove a larger thickness of the carrier layer.

[0100] Next, the exposure of the intermediate layer is detected. Detection is used to identify points when the back surface of the donor substrate has approached the device layer. Any endpoint detection technique known to be suitable for detecting transitions between materials used for the carrier layer and the intermediate layer can be practiced. In some embodiments, one or more endpoint criteria are based on detecting changes in optical absorption or emission of the back surface of the donor substrate during polishing or etching performance. In some other embodiments, the endpoint criteria are associated with changes in the optical absorption or emission of byproducts during polishing or etching of the back surface of the donor substrate. For example, the absorption or emission wavelengths associated with carrier layer etching byproducts can vary depending on the different components of the carrier layer and the intermediate layer. In other embodiments, the endpoint criteria are associated with changes in the mass of material in the byproducts of polishing or etching the back surface of the donor substrate. For example, the processed byproducts can be sampled using a quadrupole mass analyzer, and the changes in the mass of the material can be associated with different components of the carrier layer and the intermediate layer. In another exemplary embodiment, the endpoint criteria are associated with changes in friction between the back surface of the donor substrate and a polished surface that is in contact with the back surface of the donor substrate.

[0101] When the removal process is selective for the carrier layer relative to the intermediate layer, the detection of the intermediate layer can be enhanced because the inhomogeneities in the carrier removal process can be mitigated by the etch rate increment between the carrier layer and the intermediate layer. If the grinding, polishing, and / or etching operations remove the intermediate layer at a rate sufficiently lower than that at which the carrier layer is removed, detection can even be skipped. Without an endpoint criterion, grinding, polishing, and / or etching operations can be stopped on the intermediate layer material for a predetermined fixed duration if the thickness of the intermediate layer is sufficient for selective etching. In some examples, the carrier etch rate:intermediate layer etch rate is 3:1 to 10:1 or greater.

[0102] When exposing the intermediate layer, at least a portion of the intermediate layer can be removed. For example, one or more constituent layers of the intermediate layer can be removed. For example, the thickness of the intermediate layer can be removed uniformly by polishing. Alternatively, the thickness of the intermediate layer can be removed using a masking or full-coverage etching process. This process can employ the same polishing or etching process used for thinning the carrier, or it can be a different process with different process parameters. For example, in cases where the intermediate layer provides an etch stop for the carrier removal process, the latter operation can employ a different polishing or etching process that favors removing the intermediate layer rather than the device layer. When removing intermediate layer thicknesses of less than a few hundred nanometers, the removal process can be relatively slow, optimized for cross-wafer uniformity, and more precisely controlled than the process used for removing the carrier layer. The CMP process employed can, for example, employ a paste that provides very high selectivity (e.g., 100:1-300:1 or higher) between the semiconductor (e.g., silicon) and the dielectric material (e.g., SiO), which surrounds the device layer and is embedded within the intermediate layer, for example, as electrical isolation between adjacent device regions.

[0103] For embodiments that expose the device layer by completely removing the intermediate layer, the back-side processing can begin on the exposed back side of the device layer or on a specific device region therein. In some embodiments, the back-side device layer processing includes further polishing or wet / dry etching through the thickness of the device layer disposed between the intermediate layer and a device region (such as a source or drain region) previously fabricated in the device layer.

[0104] In some embodiments where wet and / or plasma etching is used to recess the back side of a carrier layer, intermediate layer, or device layer, this etching can be patterned etching or material-selective etching, which imparts significant non-planarity or morphology to the back side surface of the device layer. As further described below, patterning can be within a device cell (i.e., “intra-cell” patterning) or across device cells (i.e., “inter-cell” patterning). In some patterned etching embodiments, at least a portion of the thickness of the intermediate layer is used as a hard mask for patterning the back side device layer. Therefore, the masking etching process can precede the etching of the corresponding masked device layer.

[0105] The above processing scheme can produce a donor-host substrate assembly including an IC device, wherein the back side of the intermediate layer of the IC device, the back side of the device layer, and / or the back side and / or front side metallization of one or more semiconductor regions within the device layer are exposed. Additional back-side processing of any of these exposed regions can then be performed during downstream processing.

[0106] It should be understood that the structure generated by the above exemplary processing scheme can be used in the same or similar form for subsequent processing operations to complete device fabrication, such as PMOS and / or NMOS device fabrication. As an example of the completed device, Figure 5 The figure shows a cross-sectional view of a non-planar integrated circuit structure taken along the gate line according to an embodiment of the present disclosure.

[0107] refer to Figure 5 The semiconductor structure or device 500 includes a nonplanar active region within a trench isolation region 506 (e.g., a fin structure including a protruding fin portion 504 and a sub-fin region 505). In one embodiment, instead of a solid fin, the nonplanar active region is divided into nanowires (such as nanowires 504A and 504B) above the sub-fin region 505, as indicated by dashed lines. In either case, for ease of description of the nonplanar integrated circuit structure 500, the nonplanar active region 504 is hereinafter referred to as the protruding fin portion. In one embodiment, the sub-fin region 505 further includes a relaxation buffer layer 542 and a defect modification layer 540, as depicted.

[0108] Gate line 508 is disposed above a protrusion 504 of a non-planar active region (including, if applicable, surrounding nanowires 504A and 504B), and above a portion of a trench isolation region 506. As shown, gate line 508 includes a gate electrode 550 and a gate dielectric layer 552. In one embodiment, gate line 508 may also include a dielectric capping layer 554. From this viewpoint, gate contact 514 and overlying gate contact via 516, as well as overlying metal interconnect 560, are also visible, all disposed within an interlayer dielectric stack or layer 570. Also from... Figure 5 From this perspective, in one embodiment, the gate contact 514 is disposed above the trench isolation region 506, but not above the non-planar active region. In another embodiment, the gate contact 514 is above the non-planar active region.

[0109] In this embodiment, the semiconductor structure or device 500 is a non-planar device, such as, but not limited to, a fin-FET device, a tri-gate device, a nanoribbon device, or a nanowire device. In such an embodiment, the corresponding semiconductor channel region is constituted by or formed within a three-dimensional body. In one such embodiment, the gate electrode stack of the gate line 508 at least surrounds the top surface and a pair of sidewalls of the three-dimensional body.

[0110] Similarly, Figure 5As depicted, in an embodiment, an interface 580 exists between the protruding fin portion 504 and the sub-fin region 505. Interface 580 may be a transition region between the doped sub-fin region 505 and the lightly doped or undoped upper fin portion 504. In one such embodiment, each fin is approximately 10 nanometers wide or less, and the sub-fin dopant may optionally be supplied from an adjacent solid-state doped layer at the sub-fin location. In certain such embodiments, each fin is less than 10 nanometers wide.

[0111] although Figure 5 Not shown, but it should be understood that the source or drain region of the protruding fin portion 504, or the source or drain region adjacent to the protruding fin portion 504, is on either side of the gate line 508, i.e., in and out of the page. In one embodiment, the material of the protruding fin portion 504 in the source or drain location is removed and replaced with another semiconductor material, for example by epitaxial deposition to form an epitaxial source or drain structure. The source or drain region may extend below the height of the dielectric layer of the trench isolation region 506, i.e., into the sub-fin region 505. According to embodiments of the present disclosure, the more heavily doped sub-fin region (i.e., the doped portion of the fin below interface 580) suppresses source-to-drain leakage through this portion of the bulk semiconductor fin. In embodiments, the source and drain regions have associated asymmetric source and drain contact structures, as described above. Figure 4J As stated above.

[0112] Refer again Figure 5 In an embodiment, the fins 504 / 505 (and possibly nanowires 504A and 504B) are composed of a crystalline silicon-germanium layer, which may be doped with charge carriers such as, but not limited to, phosphorus, arsenic, boron, gallium or combinations thereof.

[0113] In embodiments, trench isolation region 506 and the trench isolation region (trench isolation structure or trench isolation layer) throughout this document may be made of a material suitable for ultimately electrically isolating portions of a permanent gate structure from the underlying bulk substrate, or facilitating the electrical isolation of portions of a permanent gate structure from the underlying bulk substrate, or isolating active regions formed within the underlying bulk substrate (such as isolation fin active regions). For example, in one embodiment, trench isolation region 506 is made of a dielectric material such as, but not limited to, silicon dioxide, silicon oxynitride, silicon nitride, or carbon-doped silicon nitride.

[0114] Gate line 508 may be formed by a gate electrode stack, which includes a gate dielectric layer 552 and a gate electrode layer 550. In an embodiment, the gate electrodes of the gate electrode stack are made of metal gates, and the gate dielectric layer is made of a high-k material. For example, in one embodiment, the gate dielectric layer 552 is made of a material such as, but not limited to, hafnium oxide, hafnium oxynitride, hafnium silicate, lanthanum oxide, zirconium oxide, zirconium silicate, tantalum oxide, barium strontium titanate, barium titanate, strontium titanate, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, or combinations thereof. Furthermore, a portion of the gate dielectric layer 552 may include a native oxide layer formed from the top layers of the substrate fin 504. In an embodiment, the gate dielectric layer 552 is formed by a top high-k portion and a lower portion made of an oxide of a semiconductor material. In one embodiment, the gate dielectric layer 552 is formed by a top portion of hafnium oxide and a bottom portion of silicon dioxide or silicon oxynitride. In some implementations, the gate dielectric portion is a "U"-shaped structure, comprising a bottom portion substantially parallel to the surface of the substrate and two sidewall portions substantially perpendicular to the top surface of the substrate.

[0115] In one embodiment, the gate electrode layer 550 is composed of a metal layer, such as, but not limited to, metal nitrides, metal carbides, metal silicides, metal aluminides, hafnium, zirconium, titanium, tantalum, aluminum, ruthenium, palladium, platinum, cobalt, nickel, or conductive metal oxides. In a particular embodiment, the gate electrode layer 550 is composed of a non-work function set fill material formed over a metal work function set layer. The gate electrode layer 550 may be composed of a P-type work function metal or an N-type work function metal, depending on whether the transistor is a PMOS or NMOS transistor. In some implementations, the gate electrode layer 550 may be composed of a stack of two or more metal layers, wherein one or more metal layers are work function metal layers, and at least one metal layer is a conductive fill layer. For PMOS transistors, metals that can be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, tungsten, and conductive metal oxides, such as ruthenium oxide. The P-type metal layer will enable the formation of a PMOS gate electrode with a work function between about 4.9 eV and about 5.2 eV. For NMOS transistors, metals that can be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals, such as hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide. An N-type metal layer will enable the formation of an NMOS gate electrode with a power function between approximately 3.9 eV and approximately 4.2 eV. In some implementations, the gate electrode may consist of a U-shaped structure including a bottom portion substantially parallel to the surface of the substrate and two sidewall portions substantially perpendicular to the top surface of the substrate. In another implementation, at least one of the metal layers forming the gate electrode may simply be a planar layer substantially parallel to the top surface of the substrate and excluding the sidewall portions substantially perpendicular to the top surface of the substrate. In further implementations of this disclosure, the gate electrode may consist of a combination of a U-shaped structure and a planar non-U-shaped structure. For example, the gate electrode may consist of one or more U-shaped metal layers formed on top of one or more planar non-U-shaped layers.

[0116] The spacers associated with the gate electrode stack can be made of materials suitable for ultimately electrically isolating the permanent gate structure from adjacent conductive contacts (such as self-aligned contacts) or facilitating the isolation of the permanent gate structure from adjacent conductive contacts (such as self-aligned contacts). For example, in one embodiment, the spacers are made of dielectric materials such as, but not limited to, silicon dioxide, silicon oxynitride, silicon nitride, or carbon-doped silicon nitride.

[0117] The gate contact 514 and the overlying gate contact via 516 may be made of a conductive material. In embodiments, one or more of the contacts or vias may be made of a metallic material. The metallic material may be a pure metal, such as tungsten, nickel, or cobalt, or it may be an alloy, such as a metal-metal alloy or a metal-semiconductor alloy (e.g., a silicide material).

[0118] In an embodiment (though not shown), a contact pattern is formed that is substantially perfectly aligned with the existing gate pattern 508, while eliminating the need for photolithography operations with extremely tight registration budgets. In this embodiment, the contact pattern is either a vertically symmetrical contact pattern or an asymmetrical contact pattern, such as a combination of... Figure 4J As described. In other embodiments, all contacts are front-connected and not asymmetrical. In one such embodiment, the self-aligned method enables the use of inherently highly selective wet etching (e.g., compared to dry or plasma etching in conventional implementations) to generate the contact openings. In an embodiment, the contact pattern is formed using existing gate patterns by incorporating contact plugging lithography operations. In one such embodiment, the method enables the elimination of the need for lithography operations critical in other cases to generate the contact pattern, as used in conventional methods. In an embodiment, the trench contact mesh is not patterned separately but formed between the gate lines. For example, in one such embodiment, the trench contact mesh is formed after gate grating patterning but before gate grating dicing.

[0119] In an embodiment, providing structure 500 involves fabricating a gate stack structure 508 using a gate replacement process. In this approach, a dummy gate material, such as polysilicon or silicon nitride pillar material, can be removed and replaced with a permanent gate electrode material. In one such embodiment, a permanent gate dielectric layer is also formed in this process, contrary to what is carried over from a previous process. In an embodiment, the dummy gate is removed using a dry etching or wet etching process. In one embodiment, the dummy gate is made of polysilicon or amorphous silicon and is removed using a dry etching process including the use of SF6. In another embodiment, the dummy gate is made of polysilicon or amorphous silicon and is removed using a wet etching process including the use of aqueous NH4OH or tetramethylammonium hydroxide. In one embodiment, the dummy gate is made of silicon nitride and is removed using a wet etching process including an aqueous phosphoric acid solution.

[0120] Refer again Figure 5 The arrangement of the semiconductor structure or device 500 places the gate contact above the isolation region. This arrangement can be considered an inefficient use of layout space. However, in another embodiment, the semiconductor device has a contact structure that contacts a portion of the gate electrode formed above the active region (e.g., above the fin 505) and in the same layer as the trench contact via.

[0121] It should be understood that not all aspects of the above-described processes need to be practiced to fall within the spirit and scope of the embodiments of this disclosure. Furthermore, the processes described herein can be used to fabricate one or more semiconductor devices. Semiconductor devices can be transistors or similar devices. For example, in embodiments, the semiconductor device is a metal-oxide-semiconductor (MOS) transistor for logic or memory, or a bipolar transistor. Furthermore, in embodiments, the semiconductor device has a three-dimensional architecture, such as a nanowire device, a nanoribbon device, a tri-gate device, an independently accessible dual-gate device, or a FIN-FET. One or more embodiments may be particularly useful for fabricating semiconductor devices at sub-10 nanometer (10nm) technology nodes.

[0122] In embodiments, as used throughout this specification, the interlayer dielectric (ILD) material comprises or includes layers of dielectric or insulating material. Examples of suitable dielectric materials include, but are not limited to, oxides of silicon (e.g., silicon dioxide (SiO2)), doped oxides of silicon, fluorinated oxides of silicon, carbon-doped oxides of silicon, various low-k dielectric materials known in the art, and combinations thereof. The interlayer dielectric material can be formed by conventional techniques such as, for example, chemical vapor deposition (CVD), physical vapor deposition (PVD) or by other deposition methods.

[0123] In embodiments, as used throughout this specification, the metal wire or interconnect material (and via material) is composed of one or more metals or other conductive structures. A common example is the use of copper wires and structures that may or may not include a barrier layer between copper and the surrounding ILD material. As used herein, the term metal includes alloys, stacks, and other combinations of multiple metals. For example, a metal interconnect may include a barrier layer (e.g., a layer comprising one or more of Ta, TaN, Ti, or TiN), a stack of different metals or alloys, etc. Thus, an interconnect may be a single layer of material or may be formed from several layers including a conductive liner layer and a filler layer. Any suitable deposition process (such as electroplating, chemical vapor deposition, or physical vapor deposition) may be used to form the interconnect. In embodiments, the interconnect is composed of a conductive material such as, but not limited to, Cu, Al, Ti, Zr, Hf, V, Ru, Co, Ni, Pd, Pt, W, Ag, Au, or alloys thereof. Interconnects are sometimes also referred to in the art as traces, wires, lines, metals, or simply interconnects.

[0124] In embodiments, as used throughout this specification, the hard mask material, capping layer, or plug is made of a dielectric material different from the interlayer dielectric material. In one embodiment, different hard mask, capping, or plug materials may be used in different regions to provide different growth or etching selectivity toward each other and toward the underlying dielectric and metal layers. In some embodiments, the hard mask layer, capping, or plug layer comprises a silicon nitride layer (e.g., silicon nitride) or a silicon oxide layer, or both, or a combination thereof. Other suitable materials may include carbon-based materials. Depending on the specific implementation, other hard mask, capping, or plug layers known in the art may be used. The hard mask, capping, or plug layer may be formed by CVD, PVD, or other deposition methods.

[0125] In embodiments, as used throughout this specification, lithography operations are performed using 193nm immersion lithography (i193), extreme ultraviolet (EUV), and / or electron beam direct write (EBDW) lithography. Positive or negative resists can be used. In one embodiment, the lithographic mask is a three-layer mask consisting of a topography masking portion, an anti-reflective coating (ARC) layer, and a photoresist layer. In a particular embodiment of this type, the topography masking portion is a carbon hard mask (CHM) layer, and the anti-reflective coating layer is a silicon ARC layer.

[0126] On the other hand, a pitch quartering method is implemented for patterning trenches in (permanent or sacrificial) dielectric layers to form BEOL interconnect structures, or for directly patterning metal features using a subtractive method. According to embodiments of this disclosure, pitch division is applied to fabricate metal lines in a BEOL manufacturing process. The embodiments enable continuous scaling of the pitch of the metal layers, exceeding the resolution capabilities of prior art lithography equipment.

[0127] Figure 6 This is a schematic diagram of a pitch quartering 600 for manufacturing trenches for interconnect structures according to an embodiment of the present disclosure.

[0128] refer to Figure 6 At operation (a), the backbone feature 602 is formed using direct photolithography. For example, a photoresist layer or stack can be patterned, and the pattern is transferred into a hard mask material to ultimately form the backbone feature 602. The photoresist layer or stack used to form the backbone feature 602 can be patterned using standard photolithography techniques such as 193 immersion lithography. A first spacer feature 604 is then formed adjacent to the sidewalls of the backbone feature 602.

[0129] At operation (b), the backbone feature 602 is removed to leave only the first spacer feature 604. At this stage, the first spacer feature 604 is essentially a bi-spacing mask, for example, representing a bi-spacing process. The first spacer feature 604 can either be used directly in a quartic pitch process, or the pattern of the first spacer feature 604 can be first transferred to a new hard mask material, as depicted in the latter approach.

[0130] At operation (c), the pattern of the first spacer feature 604 is transferred into a new hard mask material to form the first spacer feature 604'. Then, the second spacer feature 606 is formed adjacent to the sidewall of the first spacer feature 604'.

[0131] At operation (d), the first spacer feature 604' is removed to leave only the second spacer feature 606. At this stage, the second spacer feature 606 is actually a quarter-pitch mask, for example, representing a quarter-pitch process.

[0132] At operation (e), the second spacer feature 606 is used as a mask to pattern a plurality of trenches 608 in a dielectric or hard mask layer. The trenches may ultimately be filled with a conductive material to form conductive interconnects in the metallization layer of the integrated circuit. The trench 608 labeled "B" corresponds to the trunk feature 602. The trench 608 labeled "S" corresponds to the first spacer feature 604 or 604'. The trench 608 labeled "C" corresponds to the complementary region 607 between the trunk features 602.

[0133] It should be understood that, due to Figure 6 Each groove in the groove 608 has a similar Figure 6 The patterning origin corresponds to one of the main feature 602, the first spacer feature 604 or 604', or the complementary region 607; therefore, differences in the width and / or spacing of these features may manifest as artifacts of the spacing quartzing process in the conductive interconnects ultimately formed in the metallization layer of the integrated circuit. As an example, Figure 7A The figure illustrates a cross-sectional view of a metallization layer manufactured using a pitched quartering scheme according to an embodiment of the present disclosure. It should be understood that, in conjunction with... Figure 7A The described metal layer can be used in processes or included in structures manufactured using dicing processes that employ integrated circuit layers with high-precision bonding, such as bonding. Figures 1A-1E As described.

[0134] refer to Figure 7AThe integrated circuit structure 700 includes an interlayer dielectric (ILD) layer 704 above a substrate 702. A plurality of conductive interconnects 706 are located in the ILD layer 704, and each conductive interconnect in the plurality of conductive interconnects 706 is spaced apart from each other through a portion of the ILD layer 704. Each conductive interconnect in the plurality of conductive interconnects 706 includes a conductive barrier layer 708 and a conductive filler material 710.

[0135] refer to Figure 6 and Figure 7A Both, conductive interconnect 706B is formed in a trench having a pattern originating from the independent feature 602. Conductive interconnect 706S is formed in a trench having a pattern originating from the first spacer feature 604 or 604'. Conductive interconnect 706C is formed in a trench having a pattern having a complementary region 607 originating from the independent feature 602.

[0136] Refer again Figure 7A In one embodiment, the plurality of conductive interconnects 706 include a first interconnect 706B having a width (W1). A second interconnect 706S is adjacent to the first interconnect 706B and has a width (W2) different from the width (W1) of the first interconnect 706B. The third interconnect 706C is adjacent to the second interconnect 706S, and the third interconnect 706C has a width (W3). The fourth interconnect (second 706S) is adjacent to the third interconnect 706C, and the fourth interconnect has the same width (W2) as the second interconnect 706S. The fifth interconnect (second 706B) is adjacent to the fourth interconnect (second 706S), and the fifth interconnect (second 706B) has the same width (W1) as the first interconnect 706B.

[0137] In one embodiment, the width (W3) of the third interconnect 706C is different from the width (W1) of the first interconnect 706B. In another such embodiment, the width (W3) of the third interconnect 706C is different from the width (W2) of the second interconnect 706S. In yet another such embodiment, the width (W3) of the third interconnect 706C is the same as the width (W2) of the second interconnect 706S. In yet another embodiment, the width (W3) of the third interconnect 706C is the same as the width (W1) of the first interconnect 706B.

[0138] In one embodiment, the spacing (P1) between the first interconnect 706B and the third interconnect 706C is the same as the spacing (P2) between the second interconnect 706S and the fourth interconnect (second 706S). In another embodiment, the spacing (P1) between the first interconnect 706B and the third interconnect 706C is different from the spacing (P2) between the second interconnect 706S and the fourth interconnect (second 706S).

[0139] Refer again Figure 7A In another embodiment, the plurality of conductive interconnects 706 include a first conductive interconnect 706B having a width (W1). A second interconnect 706S is adjacent to the first interconnect 706B and has a width (W2). A third interconnect 706C is adjacent to the second interconnect 706S and has a width (W3) different from the width (W1) of the first interconnect 706B. A fourth interconnect (second 706S) is adjacent to the third interconnect 706C and has the same width (W2) as the second interconnect 706S. A fifth interconnect (second 706B) is adjacent to the fourth interconnect (second 706S) and has the same width (W1) as the first interconnect 706B.

[0140] In one embodiment, the width (W2) of the second interconnect 706S is different from the width (W1) of the first interconnect 706B. In one such embodiment, the width (W3) of the third interconnect 706C is different from the width (W2) of the second interconnect 706S. In another such embodiment, the width (W3) of the third interconnect 706C is the same as the width (W2) of the second interconnect 706S.

[0141] In one embodiment, the width (W2) of the second interconnect 706S is the same as the width (W1) of the first interconnect 706B. In another embodiment, the spacing (P1) between the first interconnect 706B and the third interconnect 706C is the same as the spacing (P2) between the second interconnect 706S and the fourth interconnect (second 706S). In yet another embodiment, the spacing (P1) between the first interconnect 706B and the third interconnect 706C is different from the spacing (P2) between the second interconnect 706S and the fourth interconnect (second 706S).

[0142] Figure 7B The figure illustrates a cross-sectional view of a metallization layer manufactured using a two-part spacing scheme above a metallization layer manufactured using a four-part spacing scheme, according to an embodiment of the present disclosure. It should be understood that, in conjunction with... Figure 7B The described metal layer can be used in processes or included in structures manufactured using dicing processes that employ integrated circuit layers with high-precision bonding, such as bonding. Figures 1A-1E As described.

[0143] refer to Figure 7BThe integrated circuit structure 750 includes a first interlayer dielectric (ILD) layer 754 above a substrate 754. A first plurality of conductive interconnects 756 are located in the first ILD layer 754, and each conductive interconnect in the first plurality of conductive interconnects 756 is spaced apart from each other through a portion of the first ILD layer 754. Each conductive interconnect in the plurality of conductive interconnects 756 includes a conductive barrier layer 758 and a conductive filler material 760. The integrated circuit structure 750 further includes a second interlayer dielectric (ILD) layer 774 above a substrate 752. A second plurality of conductive interconnects 776 are located in the second ILD layer 774, and each conductive interconnect in the second plurality of conductive interconnects 776 is spaced apart from each other through a portion of the second ILD layer 774. Each conductive interconnect in the plurality of conductive interconnects 776 includes a conductive barrier layer 778 and a conductive filler material 780.

[0144] Based on embodiments of this disclosure, and referring again to Figure 7B A method of fabricating an integrated circuit structure includes forming a first plurality of conductive interconnects 756 in a first interlayer dielectric (ILD) layer 754 above a substrate 752, wherein the first plurality of conductive interconnects 756 are spaced apart by the first interlayer dielectric (ILD) layer 754. The first plurality of conductive interconnects 756 employ a spacer-based pitch quarting process (e.g., combined with...) Figure 6 The second plurality of conductive interconnects 776 are formed using the methods described in operations (a)-(e). The second plurality of conductive interconnects 776 are formed in and spaced apart by the second ILD layer 774 above the first ILD layer 754. Figure 6 The operations described in (a) and (b) are formed by the methods.

[0145] In one embodiment, the first plurality of conductive interconnects 756 have a spacing of less than 40 nanometers between adjacent lines (P1). The second plurality of conductive interconnects 776 have a spacing of 44 nanometers or greater between adjacent lines (P2). In another embodiment, the spacer-based spacing quarting process and the spacer-based spacing bisecting process are based on an immersion 193nm lithography process.

[0146] In one embodiment, each conductive interconnect in the first plurality of conductive interconnects 754 includes a first conductive barrier liner 758 and a first conductive filler material 760. Each conductive interconnect in the second plurality of conductive interconnects 756 includes a second conductive barrier liner 778 and a second conductive filler material 780. In one such embodiment, the composition of the first conductive filler material 760 differs from that of the second conductive filler material 780. In another embodiment, the composition of the first conductive filler material 760 is the same as that of the second conductive filler material 780. In another embodiment, the first conductive barrier liner 758 and / or the second conductive barrier liner 778 is a single nitrogen-free tantalum (Ta) barrier layer.

[0147] Although not depicted, in an embodiment, the method further includes forming a third plurality of conductive interconnects in a third ILD layer above the second ILD layer 774 and spaced apart by the third ILD layer. The third plurality of conductive interconnects are formed without using spacing division.

[0148] Although not depicted, in an embodiment, the method further includes: forming a third plurality of conductive interconnects in a third ILD layer above the first ILD layer 754 and spaced apart by the third ILD layer before forming the second plurality of conductive interconnects 776. The third plurality of conductive interconnects are formed using a spacer-based pitch quartering process. In one such embodiment, after forming the second plurality of conductive interconnects 776, forming a fourth plurality of conductive interconnects in a fourth ILD layer above the second ILD layer 774 and spaced apart by the fourth ILD layer. The fourth plurality of conductive interconnects are formed using a spacer-based pitch bisecting process. In an embodiment, the method further includes forming a fifth plurality of conductive interconnects in a fifth ILD layer above the fourth ILD layer and spaced apart by the fifth ILD layer, the fifth plurality of conductive interconnects being formed using a spacer-based pitch bisecting process. Then forming a sixth plurality of conductive interconnects in a sixth ILD layer above the fifth ILD layer and spaced apart by the sixth ILD layer, the sixth plurality of conductive interconnects being formed using a spacer-based pitch bisecting process. Then, a seventh plurality of conductive interconnects are formed in the seventh ILD layer above the sixth ILD layer and separated by the seventh ILD layer. The seventh plurality of conductive interconnects are formed without using spacing.

[0149] On the other hand, the composition of the metal wire varies between the metallization layers. This arrangement can be referred to as heterogeneous metallization. In an embodiment, copper is used as the conductive filler material for relatively large interconnects, while cobalt is used as the conductive filler material for relatively small interconnects. Smaller wires with cobalt as the filler material can provide reduced electromigration while maintaining low resistivity. Using cobalt instead of copper for smaller interconnects solves the scaling problem of copper wires, where the conductive barrier layer consumes a larger amount of interconnect volume and copper is reduced, essentially negating the advantages typically associated with copper interconnects.

[0150] In the first example, Figure 8A The figure illustrates a cross-sectional view of an integrated circuit structure according to an embodiment of the present disclosure, the integrated circuit structure having: a metallization layer having metal line components, the metallization layer being above a metallization layer having different metal line components. It should be understood that, in conjunction with... Figure 8A One or more of the described interconnects or interconnect layers can be used in a process or included in a structure manufactured using a partitioning process of integrated circuit layers with high-precision bonding, such as bonding Figures 1A-1E As described.

[0151] refer to Figure 8A The integrated circuit structure 800 includes a first plurality of conductive interconnects 806 spaced apart by a first interlayer dielectric (ILD) layer 804 above a substrate 802. One of the conductive interconnects 806A is shown having a down-facing via 807. Each of the first plurality of conductive interconnects 806 includes a first conductive barrier material 808 along the sidewalls and bottom of a first conductive fill material 810.

[0152] The second plurality of conductive interconnects 816 are located in and spaced apart by the second ILD layer 814 above the first ILD layer 804. One of the conductive interconnects 816A is shown having a down-facing via 817. Each conductive interconnect in the second plurality of conductive interconnects 816 includes a second conductive barrier material 818 along the sidewalls and bottom of the second conductive fill material 820. The composition of the second conductive fill material 820 differs from that of the first conductive fill material 810. In an embodiment, the second conductive barrier material 818 is a single nitrogen-free tantalum (Ta) barrier layer.

[0153] In one embodiment, the second conductive filler material 820 is substantially composed of copper, and the first conductive filler material 810 is substantially composed of cobalt. In one such embodiment, the composition of the first conductive barrier material 808 differs from that of the second conductive barrier material 818. In another such embodiment, the composition of the first conductive barrier material 808 is the same as that of the second conductive barrier material 818.

[0154] In one embodiment, the first conductive filling material 810 comprises copper having a first concentration of dopant impurity atoms, and the second conductive filling material 820 comprises copper having a second concentration of dopant impurity atoms. The second concentration of dopant impurity atoms is less than the first concentration of dopant impurity atoms. In one such embodiment, the dopant impurity atoms are selected from the group consisting of aluminum (Al) and manganese (Mn). In one embodiment, the first conductive barrier material 810 and the second conductive barrier material 820 have the same composition. In another embodiment, the first conductive barrier material 810 and the second conductive barrier material 820 have different compositions.

[0155] Refer again Figure 8A The second ILD layer 814 is on the etch stop layer 822. A conductive via 817 is located in the second ILD layer 814 and in an opening in the etch stop layer 822. In an embodiment, the first ILD layer 804 and the second ILD layer 814 comprise silicon, carbon, and oxygen, and the etch stop layer 822 comprises silicon and nitrogen. In an embodiment, each conductive interconnect in the first plurality of conductive interconnects 806 has a first width (W1), and each conductive interconnect in the second plurality of conductive interconnects 816 has a second width (W2) greater than the first width (W1).

[0156] In the second example, Figure 8B The figure illustrates a cross-sectional view of an integrated circuit structure according to an embodiment of the present disclosure, the integrated circuit structure having: a metallization layer having metal line components, the metallization layer being coupled to a metallization layer having different metal line components. It should be understood that, in conjunction with... Figure 8B One or more of the described interconnects or interconnect layers can be used in a process or included in a structure manufactured using a partitioning process of integrated circuit layers with high-precision bonding, such as bonding Figures 1A-1E As described.

[0157] refer to Figure 8B The integrated circuit structure 850 includes a first plurality of conductive interconnects 856 spaced apart by a first interlayer dielectric (ILD) layer 854 above a substrate 852. One of the conductive interconnects 856A is shown having a down-facing via 857. Each of the first plurality of conductive interconnects 856 includes a first conductive barrier material 858 along the sidewalls and bottom of a first conductive fill material 860.

[0158] The second plurality of conductive interconnects 866 are located in and spaced apart by the second ILD layer 864 above the first ILD layer 854. One of the conductive interconnects 866A is shown as having a down-facing via 867. Each conductive interconnect in the second plurality of conductive interconnects 866 includes a second conductive barrier material 868 along the sidewalls and bottom of a second conductive filler material 870. The composition of the second conductive filler material 870 differs from that of the first conductive filler material 860. In an embodiment, the second conductive barrier material 868 is a single nitrogen-free tantalum (Ta) barrier layer.

[0159] In one embodiment, the conductive via 867 is electrically coupled to and on a single conductive interconnect 856B among a first plurality of conductive interconnects 856, thereby electrically coupling a single conductive interconnect 866A among a second plurality of conductive interconnects 866 to the single conductive interconnect 856B among the first plurality of conductive interconnects 856. In one embodiment, each conductive interconnect in the first plurality of conductive interconnects 856 is along a first direction 898 (e.g., entering and exiting a page), and each conductive interconnect in the second plurality of conductive interconnects 866 is along a second direction 899 orthogonal to the first direction 898, as depicted. In one embodiment, the conductive via 867 includes a second conductive barrier material 868 along the sidewalls and bottom of a second conductive filler material 870, as depicted.

[0160] In one embodiment, the second ILD layer 864 is on an etch stop layer 872 on the first ILD layer 854. A conductive via 867 is located in the second ILD layer 864 and in an opening in the etch stop layer 872. In one embodiment, the first ILD layer 854 and the second ILD layer 864 comprise silicon, carbon, and oxygen, and the etch stop layer 872 comprises silicon and nitrogen. In one embodiment, each conductive interconnect in the first plurality of conductive interconnects 856 has a first width (W1), and each conductive interconnect in the second plurality of conductive interconnects 866 has a second width (W2) greater than the first width (W1).

[0161] In one embodiment, the second conductive filler material 870 is substantially composed of copper, and the first conductive filler material 860 is substantially composed of cobalt. In one such embodiment, the composition of the first conductive barrier material 858 differs from that of the second conductive barrier material 868. In another such embodiment, the composition of the first conductive barrier material 858 is the same as that of the second conductive barrier material 868.

[0162] In one embodiment, the first conductive filler material 860 comprises copper having a first concentration of dopant impurity atoms, and the second conductive filler material 870 comprises copper having a second concentration of dopant impurity atoms. The second concentration of dopant impurity atoms is less than the first concentration of dopant impurity atoms. In one such embodiment, the dopant impurity atoms are selected from the group consisting of aluminum (Al) and manganese (Mn). In one embodiment, the first conductive barrier material 860 and the second conductive barrier material 870 have the same composition. In another embodiment, the first conductive barrier material 860 and the second conductive barrier material 870 have different compositions.

[0163] Figures 9A-9C The figures illustrate cross-sectional views of various interconnects having various barrier liner and conductive capping arrangements according to embodiments of the present disclosure, the various barrier liner and conductive capping arrangements being adapted to combine Figure 8A and Figure 8B The structure described.

[0164] refer to Figure 9A The interconnect 900 in the dielectric layer 901 includes a conductive barrier material 902 and a conductive filler material 904. The conductive barrier material 902 includes an outer layer 906 away from the conductive filler material 904 and an inner layer 908 close to the conductive filler material 904. In one embodiment, the conductive filler material includes cobalt, the outer layer 906 includes titanium and nitrogen, and the inner layer 908 includes tungsten, nitrogen, and carbon. In one such embodiment, the outer layer 906 has a thickness of approximately 2 nanometers, and the inner layer 908 has a thickness of approximately 0.5 nanometers. In another embodiment, the conductive filler material includes cobalt, the outer layer 906 includes tantalum, and the inner layer 908 includes ruthenium. In one such embodiment, the outer layer 906 further includes nitrogen.

[0165] refer to Figure 9B The interconnects 920 in the dielectric layer 921 include a conductive barrier material 922 and a conductive filler material 924. A conductive capping layer 930 is on top of the conductive filler material 924. In one such embodiment, the conductive capping layer 930 is further on top of the conductive barrier material 922, as depicted. In another embodiment, the conductive capping layer 930 is not on top of the conductive barrier material 922. In this embodiment, the conductive capping layer 930 is substantially composed of cobalt, and the conductive filler material 924 is substantially composed of copper.

[0166] refer to Figure 9CThe interconnect 940 in the dielectric layer 941 includes a conductive barrier material 942 and a conductive filler material 944. The conductive barrier material 942 includes an outer layer 946 away from the conductive filler material 944 and an inner layer 948 close to the conductive filler material 944. A conductive capping layer 950 is on top of the conductive filler material 944. In one embodiment, the conductive capping layer 950 is only on top of the conductive filler material 944. However, in another embodiment, the conductive capping layer 950 is further on top of the inner layer 948 of the conductive barrier material 942, i.e., at location 952. In such an embodiment, the conductive capping layer 950 is further on top of the outer layer 946 of the conductive barrier material 942, i.e., at location 954.

[0167] In the embodiment, reference Figure 9B and 9C A method for manufacturing an integrated circuit structure includes forming an interlayer dielectric (ILD) layer 921 or 941 over a substrate. A plurality of conductive interconnects 920 or 940 are formed in trenches spaced apart within and by the ILD layer, each conductive interconnect 920 or 940 corresponding to a trench within the trench. The plurality of conductive interconnects are formed by first forming a conductive barrier material 922 or 924 on the bottom and sidewalls of the trench, then forming conductive fill materials 924 or 944 on the conductive barrier materials 922 or 942 respectively, and filling the trench, wherein the conductive barrier material 922 or 942 is located along the bottom and sidewalls of the conductive fill materials 930 or 950 respectively. The top of the conductive fill materials 924 or 944 is then treated with a gas comprising oxygen and carbon. After treating the top of the conductive filler material 924 or 944 with a gas including oxygen and carbon, a conductive capping layer 930 or 950 is formed on the top of the conductive filler material 924 or 944, respectively.

[0168] In one embodiment, treating the top of the conductive filler material 924 or 944 with a gas including oxygen and carbon includes treating the top of the conductive filler material 924 or 944 with carbon monoxide (CO). In one embodiment, the conductive filler material 924 or 944 includes copper, and forming a conductive capping layer 930 or 950 on the top of the conductive filler material 924 or 944 includes forming a layer including cobalt using chemical vapor deposition (CVD). In one embodiment, the conductive capping layer 930 or 950 is formed on the top of the conductive filler material 924 or 944, but not on the top of the conductive barrier material 922 or 924.

[0169] In one embodiment, forming the conductive barrier material 922 or 944 includes forming a first conductive layer on the bottom and sidewalls of the trench, the first conductive layer comprising tantalum. A first portion of the first conductive layer is first formed using atomic layer deposition (ALD), and then a second portion of the first conductive layer is formed using physical vapor deposition (PVD). In one such embodiment, forming the conductive barrier material further includes forming a second conductive layer on the first conductive layer on the bottom and sidewalls of the trench, the second conductive layer comprising ruthenium, and the conductive filler material comprising copper. In one embodiment, the first conductive layer further comprises nitrogen.

[0170] Figure 10 The figure illustrates a cross-sectional view of an integrated circuit structure according to an embodiment of the present disclosure, the integrated circuit structure having: four metallization layers having metal line components and spacing, the four metallization layers being above two metallization layers having different metal line components and smaller spacing. It should be understood that, in conjunction with... Figure 10 One or more of the described interconnects or interconnect layers can be used in a process or included in a structure manufactured using a partitioning process of integrated circuit layers with high-precision bonding, such as bonding Figures 1A-1E As described.

[0171] refer to Figure 10 The integrated circuit structure 1000 includes a first plurality of conductive interconnects 1004 spaced apart by a first interlayer dielectric (ILD) layer 1002 above a substrate 1001. Each conductive interconnect in the first plurality of conductive interconnects 1004 includes a first conductive barrier material 1006 along the sidewalls and bottom of a first conductive fill material 1008. Each conductive interconnect in the first plurality of conductive interconnects 1004 is along a first direction 1098 (e.g., entering and leaving a page).

[0172] The second plurality of conductive interconnects 1014 are located in and spaced apart by the second ILD layer 1012 above the first ILD layer 1002. Each conductive interconnect in the second plurality of conductive interconnects 1014 includes a first conductive barrier material 1006 along the sidewalls and bottom of the first conductive filler material 1008. Each conductive interconnect in the second plurality of conductive interconnects 1014 is along a second direction 1099 orthogonal to the first direction 1098.

[0173] The third plurality of conductive interconnects 1024 are located in and spaced apart by the third ILD layer 1022 above the second ILD layer 1012. Each conductive interconnect in the third plurality of conductive interconnects 1024 includes a second conductive barrier material 1026 along the sidewalls and bottom of the second conductive filler material 1028. The composition of the second conductive filler material 1028 differs from that of the first conductive filler material 1008. Each conductive interconnect in the third plurality of conductive interconnects 1024 is along a first direction 1098. In an embodiment, the second conductive barrier material 1026 is a single nitrogen-free tantalum (Ta) barrier layer.

[0174] The fourth plurality of conductive interconnects 1034 are located in and spaced apart by the fourth ILD layer 1032 above the third ILD layer 1022. Each conductive interconnect in the fourth plurality of conductive interconnects 1034 includes a second conductive barrier material 1026 along the sidewalls and bottom of the second conductive filler material 1028. Each conductive interconnect in the fourth plurality of conductive interconnects 1034 is along a second direction 1099.

[0175] The fifth plurality of conductive interconnects 1044 are located in and spaced apart by the fifth ILD layer 1042 above the fourth ILD layer 1032. Each conductive interconnect in the fifth plurality of conductive interconnects 1044 includes a second conductive barrier material 1026 along the sidewalls and bottom of the second conductive filler material 1028. Each conductive interconnect in the fifth plurality of conductive interconnects 1044 is along a first direction 1098.

[0176] The sixth plurality of conductive interconnects 1054 are located in and spaced apart by the sixth ILD layer 1052 above the fifth ILD layer. Each conductive interconnect in the sixth plurality of conductive interconnects 1054 includes a second conductive barrier material 1026 along the sidewalls and bottom of the second conductive filler material 1028. Each conductive interconnect in the sixth plurality of conductive interconnects 1054 is along a second direction 1099.

[0177] In one embodiment, the second conductive filler material 1028 is substantially composed of copper, and the first conductive filler material 1008 is substantially composed of cobalt. In another embodiment, the first conductive filler material 1008 comprises copper having a first concentration of dopant impurity atoms, and the second conductive filler material 1028 comprises copper having a second concentration of dopant impurity atoms, the second concentration of dopant impurity atoms being less than the first concentration of dopant impurity atoms.

[0178] In one embodiment, the composition of the first conductive barrier material 1006 differs from that of the second conductive barrier material 1026. In another embodiment, the first conductive barrier material 1006 and the second conductive barrier material 1026 have the same composition.

[0179] In one embodiment, the first conductive via 1019 is on and electrically coupled to a single conductive interconnect 1004A among the first plurality of conductive interconnects 1004. A single conductive interconnect 1014A among the second plurality of conductive interconnects 1014 is on and electrically coupled to the first conductive via 1019.

[0180] The second conductive via 1029 is on and electrically coupled to a single conductive interconnect 1014B among the second plurality of conductive interconnects 1014. A single conductive interconnect 1024A among the third plurality of conductive interconnects 1024 is on and electrically coupled to the second conductive via 1029.

[0181] The third conductive via 1039 is on and electrically coupled to a single conductive interconnect 1024B among the third plurality of conductive interconnects 1024. The fourth conductive interconnect 1034A is on and electrically coupled to the third conductive via 1039 among the fourth plurality of conductive interconnects 1034.

[0182] The fourth conductive via 1049 is on and electrically coupled to a single conductive interconnect 1034B among the fourth plurality of conductive interconnects 1034. The fifth conductive interconnect 1044A is on and electrically coupled to the fourth conductive via 1049 among the fifth plurality of conductive interconnects 1044.

[0183] The fifth conductive via 1059 is on and electrically coupled to a single conductive interconnect 1044B among the fifth plurality of conductive interconnects 1044. The sixth conductive interconnect 1054A is on the fifth conductive via 1059 and electrically coupled to the third conductive via 1059.

[0184] In one embodiment, the first conductive via 1019 includes a first conductive barrier material 1006 along the sidewalls and bottom of the first conductive filler material 1008. The second conductive via 1029, the third conductive via 1039, the fourth conductive via 1049, and the fifth conductive via 1059 include a second conductive barrier material 1026 along the sidewalls and bottom of the second conductive filler material 1028.

[0185] In this embodiment, the first ILD layer 1002, the second ILD layer 1012, the third ILD layer 1022, the fourth ILD layer 1032, the fifth ILD layer 1042, and the sixth ILD layer 1052 are separated from each other by corresponding etch stop layers 1090 between adjacent ILD layers. In this embodiment, the first ILD layer 1002, the second ILD layer 1012, the third ILD layer 1022, the fourth ILD layer 1032, the fifth ILD layer 1042, and the sixth ILD layer 1052 comprise silicon, carbon, and oxygen.

[0186] In an embodiment, each of the first plurality of conductive interconnects 1004 and the second plurality of conductive interconnects 1014 has a first width (W1). Each of the third plurality of conductive interconnects 1024, the fourth plurality of conductive interconnects 1034, the fifth plurality of conductive interconnects 1044 and the sixth plurality of conductive interconnects 1054 has a second width (W2) greater than the first width (W1).

[0187] In one aspect, one or more embodiments described herein relate to methods for constructing non-conductive spaces or breaks between metal lines (referred to as “line ends,” “plugs,” or “cutouts”) and, in some embodiments, associated conductive vias. By definition, conductive vias are used to land on a preceding metal pattern. In this case, the embodiments described herein achieve a more robust interconnect fabrication scheme because it relies less on alignment via photolithography equipment. This interconnect fabrication scheme can be used to relax constraints on alignment / exposure, can be used to improve electrical contacts (e.g., by reducing via resistance), and can be used to reduce the total process operations and processing time required to pattern such features using conventional methods in other cases.

[0188] It should be understood that these dielectric plugs, which differ in composition from the ILD material housing the dielectric plug, may be included only in selected metallization layers, such as in the lower metallization layer. As an example, Figure 11 The figure illustrates a cross-sectional view of a metallization layer stack according to an embodiment of the present disclosure, the metallization layer stack including a conductive wire plug at a lower metal wire location. It should be understood that, in conjunction with... Figure 11 One or more of the described interconnects or interconnect layers can be used in a process or included in a structure manufactured using a partitioning process of integrated circuit layers with high-precision bonding, such as bonding Figures 1A-1E As described.

[0189] refer to Figure 11The integrated circuit structure 1150 includes a first plurality of conductive interconnects 1156 spaced apart in and within a first interlayer dielectric (ILD) layer 1154 above a substrate 1152. Each conductive interconnect in the first plurality of conductive interconnects 1156 has continuity interrupted by one or more dielectric plugs 1158. In an embodiment, the one or more dielectric plugs 1158 comprise a material different from that of the ILD layer 1152. A second plurality of conductive interconnects 1166 are located in and spaced apart in a second ILD layer 1164 above the first ILD layer 1154. In an embodiment, each conductive interconnect in the second plurality of conductive interconnects 1166 has continuity interrupted by one or more portions 1168 of the second ILD layer 1164. It should be understood that, as depicted, other metallization layers may be included in the integrated circuit structure 1150.

[0190] In one embodiment, one or more dielectric plugs 1158 comprise a metal oxide material. In one such embodiment, the metal oxide material is aluminum oxide. In one embodiment, the first ILD layer 1154 and the second ILD layer 1164 (and therefore one or more portions 1168 of the second ILD layer 1164) comprise a carbon-doped silicon oxide material.

[0191] In one embodiment, each conductive interconnect in the first plurality of conductive interconnects 1156 includes a first conductive barrier liner 1156A and a first conductive filler material 1156B. Each second conductive interconnect in the second plurality of conductive interconnects 1166 includes a second conductive barrier liner 1166A and a second conductive filler material 1166B. In one such embodiment, the composition of the first conductive filler material 1156B differs from that of the second conductive filler material 1166B. In a particular such embodiment, the first conductive filler material 1156B comprises cobalt, and the second conductive filler material 1166B comprises copper.

[0192] In one embodiment, a first plurality of conductive interconnects 1156 have a first spacing (P1, as shown in layer 1170). A second plurality of conductive interconnects 1166 have a second spacing (P2, as shown in layer 1180). The second spacing (P2) is greater than the first spacing (P1). In one embodiment, each conductive interconnect in the first plurality of conductive interconnects 1156 has a first width (W1, as shown in layer 1170). Each conductive interconnect in the second plurality of conductive interconnects 1166 has a second width (W2, as shown in layer 1180). The second width (W2) is greater than the first width (W1).

[0193] It should be understood that the layers and materials associated with the aforementioned back-to-office (BEOL) structures and processes can be formed on or over an underlying semiconductor substrate or structure (such as one or more underlying device layers of an integrated circuit). In embodiments, the underlying semiconductor substrate refers to a general workpiece object used to manufacture integrated circuits. Semiconductor substrates typically include wafers or other silicon wafers or other semiconductor materials. Suitable semiconductor substrates include, but are not limited to, single-crystal silicon, polycrystalline silicon, and silicon-on-insulator (SOI), as well as similar substrates formed from other semiconductor materials, such as substrates comprising germanium, carbon, or group III-V materials. Depending on the manufacturing stage, semiconductor substrates typically include transistors, integrated circuit systems, etc. The substrate may also include semiconductor materials, metals, dielectrics, dopants, and other materials typically found in semiconductor substrates. Furthermore, the depicted structure can be fabricated on an underlying interconnect layer.

[0194] Although the foregoing methods for manufacturing BEOL metallization layers or portions thereof have been described in detail with respect to the selection of operations, it should be understood that additional or intermediate operations for manufacturing may include standard microelectronics manufacturing processes such as photolithography, etching, thin film deposition, planarization (such as chemical mechanical polishing (CMP)), diffusion, metrology, use of sacrificial layers, use of etch stop layers, use of planarization stop layers, or any other actions associated with the manufacture of microelectronic components. Furthermore, it should be understood that the process operations described with respect to the foregoing process flow may be practiced in an alternative sequence; not every operation needs to be performed, or additional process operations may be performed.

[0195] In embodiments, as used throughout this specification, the interlayer dielectric (ILD) material comprises or includes layers of dielectric or insulating material. Examples of suitable dielectric materials include, but are not limited to, oxides of silicon (e.g., silicon dioxide (SiO2)), doped oxides of silicon, fluorinated oxides of silicon, carbon-doped oxides of silicon, various low-k dielectric materials known in the art, and combinations thereof. The interlayer dielectric material can be formed by techniques such as, for example, chemical vapor deposition (CVD), physical vapor deposition (PVD) or by other deposition methods.

[0196] In embodiments, as used throughout this specification, the metal wire or interconnect material (and via material) is composed of one or more metals or other conductive structures. A common example is the use of copper wires and structures that may or may not include a barrier layer between copper and the surrounding ILD material. As used herein, the term metal includes alloys, stacks, and other combinations of multiple metals. For example, a metal interconnect may include a barrier layer (e.g., a layer comprising one or more of Ta, TaN, Ti, or TiN), a stack of different metals or alloys, etc. Thus, an interconnect may be a single layer of material or may be formed from several layers including a conductive liner layer and a filler layer. Any suitable deposition process (such as electroplating, chemical vapor deposition, or physical vapor deposition) may be used to form the interconnect. In embodiments, the interconnect is composed of a conductive material such as, but not limited to, Cu, Al, Ti, Zr, Hf, V, Ru, Co, Ni, Pd, Pt, W, Ag, Au, or alloys thereof. Interconnects are sometimes also referred to in the art as traces, wires, lines, metals, or simply interconnects.

[0197] In embodiments, as used throughout this specification, the hard mask material is composed of a dielectric material different from the interlayer dielectric material. In one embodiment, different hard mask materials may be used in different regions to provide different growth or etching selectivity toward each other and toward the underlying dielectric and metal layers. In some embodiments, the hard mask layer comprises a silicon nitride layer (e.g., silicon nitride) or a silicon oxide layer, or both, or a combination thereof. Other suitable materials may include carbon-based materials. In another embodiment, the hard mask material comprises a metallic substance. For example, the hard mask or other overlay material may comprise a layer of titanium or another metal nitride (e.g., titanium nitride). One or more of these layers may potentially include smaller amounts of other materials, such as oxygen. Alternatively, depending on the specific implementation, other hard mask layers known in the art may be used. The hard mask layer may be formed by CVD, PVD, or by other deposition methods.

[0198] In embodiments, as used throughout this specification, lithography operations are performed using 193nm immersion lithography (i193), extreme ultraviolet (EUV), and / or electron beam direct writing (EBDW) lithography. Positive or negative resists can be used. In one embodiment, the lithographic mask is a three-layer mask consisting of a topography masking portion, an antireflective coating (ARC) layer, and a photoresist layer. In a particular embodiment of this type, the topography masking portion is a carbon hard mask (CHM) layer, and the antireflective coating layer is a silicon ARC layer.

[0199] The embodiments disclosed herein can be used to manufacture various types of integrated circuits or microelectronic devices. Examples of such integrated circuits include, but are not limited to, processors, chipset components, graphics processors, digital signal processors, microcontrollers, etc. In other embodiments, semiconductor memory can be manufactured. Furthermore, integrated circuits or other microelectronic devices can be used in a wide variety of electronic devices known in the art, such as computer systems (e.g., desktop computers, laptops, servers), cellular phones, personal electronic products, etc. Integrated circuits can be coupled to buses and other components in the system. For example, a processor can be coupled to memory, chipsets, etc., via one or more buses. Each of the processor, memory, and chipset can potentially be manufactured using the methods disclosed herein.

[0200] Figure 12 The figure illustrates a computing device 1200 according to one implementation of the present disclosure. The computing device 1200 houses a board 1202. The board 1202 may include multiple components, including but not limited to a processor 1204 and at least one communication chip 1206. The processor 1204 is physically and electrically coupled to the board 1202. In some implementations, at least one communication chip 1206 is also physically and electrically coupled to the board 1202. In a further implementation, the communication chip 1206 is part of the processor 1204.

[0201] Depending on its application, computing device 1200 may include other components that may be physically and electrically coupled to board 1202 or may not be physically and electrically coupled to board 1202. These other components include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, graphics processor, digital signal processor, cryptographic processor, chipset, antenna, display, touch screen display, touch screen controller, battery, audio codec, video codec, power amplifier, global positioning system (GPS) device, compass, accelerometer, gyroscope, speaker, camera, and mass storage devices (such as hard disk drives, compact disks (CDs), digital versatile disks (DVDs), etc.).

[0202] Communication chip 1206 implements wireless communication for transferring data to and from computing device 1200. The term "wireless" and its derivatives can be used to describe circuits, devices, systems, methods, techniques, communication channels, etc., that enable data transmission through a non-solid-state medium using modulated electromagnetic radiation. This term does not imply that the associated device does not contain any wires, but in some embodiments, the associated device may not contain any wires. Communication chip 1206 can implement any of a variety of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 series), WiMAX (IEEE 802.16 series), IEEE 802.20, Long Term Evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, its derivatives, and any other wireless protocols referred to as 3G, 4G, 5G, and higher generations. Computing device 1200 may include multiple communication chips 1206. For example, the first communication chip 1206 can be dedicated to shorter-range wireless communication, such as Wi-Fi and Bluetooth; and the second communication chip 1206 can be dedicated to longer-range wireless communication, such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, etc.

[0203] The processor 1204 of the computing device 1200 includes an integrated circuit die packaged within the processor 1204. In some implementations of embodiments of this disclosure, the processor's integrated circuit die includes one or more structures, such as integrated circuit structures constructed according to implementations of this disclosure. The term "processor" may refer to any device or part of a device that processes electronic data from registers or memory, or both registers and memory, to convert such electronic data into other electronic data that can be stored in registers or memory, or both registers and memory.

[0204] The communication chip 1206 also includes an integrated circuit die packaged within the communication chip 1206. According to another implementation of this disclosure, the integrated circuit die of the communication chip is constructed according to an implementation of this disclosure.

[0205] In a further implementation, another component housed within the computing device 1200 may comprise an integrated circuit die constructed according to an implementation of an embodiment of the present disclosure.

[0206] In various embodiments, computing device 1200 may be a laptop, netbook, notebook computer, ultrabook, smartphone, tablet device, personal digital assistant (PDA), ultra-mobile PC, mobile phone, desktop computer, server, printer, scanner, monitor, set-top box, entertainment control unit, digital camera, portable music player, or digital video recorder. In further implementations, computing device 1200 may be any other electronic device that processes data.

[0207] Figure 13 The figure illustrates an interposer 1300 including one or more embodiments of the present disclosure. Interposer 1300 is an intermediate substrate for bridging a first substrate 1302 to a second substrate 1304. The first substrate 1302 may be, for example, an integrated circuit die. The second substrate 1304 may be, for example, a memory module, a computer motherboard, or another integrated circuit die. Generally, the purpose of interposer 1300 is to extend connections to wider spacing or to reroute connections to different connections. For example, interposer 1300 may couple an integrated circuit die to a ball grid array (BGA) 1306, which may then be coupled to the second substrate 1304. In some embodiments, the first substrate 1302 and the second substrate 1304 are attached to opposite sides of interposer 1300. In other embodiments, the first substrate 1302 and the second substrate 1304 are attached to the same side of interposer 1300. And in a further embodiment, three or more substrates are interconnected by means of interposer 1300.

[0208] Interposer 1300 may be formed of epoxy resin, glass fiber reinforced epoxy resin, ceramic material, or polymer material (such as polyimide). In a further embodiment, interposer 1300 may be formed of a rigid or flexible material, which may include the same materials described above for use in semiconductor substrates (such as silicon, germanium, and other group III-V and IV materials).

[0209] Interposer 1300 may include metal interconnects 1308 and vias 1310, including but not limited to through-silicon vias (TSVs) 1312. Interposer 1300 may further include embedded devices 1314, which may include both passive and active devices. Such devices include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, and electrostatic discharge (ESD) devices. More complex devices, such as radio-frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and MEMS devices, may also be formed on interposer 1300. According to embodiments of this disclosure, the apparatus or processes disclosed herein may be used to manufacture interposer 1300 or components included in interposer 1300.

[0210] Figure 14 This is an isometric view of a mobile computing platform 1400 manufactured using one or more processes described herein or including one or more features described herein, according to embodiments of this disclosure.

[0211] Mobile computing platform 1400 can be any portable device configured for each of electronic data display, electronic data processing, and wireless electronic data transmission. For example, mobile computing platform 1400 can be any of a tablet, smartphone, laptop, etc., and includes a display 1405, a chip-level (SoC) or package-level integrated system 1410, and a battery 1413. In an exemplary embodiment, display 1405 is a touchscreen (capacitive, inductive, resistive, etc.). As illustrated, the higher the level of integration in system 1410, achieved with a higher transistor package density, the larger the portion of mobile computing platform 1400 that can be occupied by battery 1413 or non-volatile storage devices (such as solid-state drives), or the larger the transistor gate count for improved platform functionality. Similarly, the greater the carrier mobility of each transistor in system 1410, the greater the functionality. Therefore, the techniques described herein can achieve performance and form factor improvements in mobile computing platform 1400.

[0212] The integrated system 1410 is further illustrated in expanded view 1420. In an exemplary embodiment, package device 1477 includes at least one memory chip (e.g., RAM) or at least one processor chip (e.g., a multi-core microprocessor and / or graphics processor) manufactured according to one or more processes described herein or including one or more features described herein. Package device 1477, together with one or more of the following: power management integrated circuit (PMIC) 1415, broadband RF integrated circuit (RFIC) 1425 including a broadband RF (wireless) transmitter and / or receiver (e.g., including a digital baseband and analog front-end module, further including a power amplifier on the transmit path and a low-noise amplifier on the receive path), and controller 1411, is further coupled to board 1460. Functionally, PMIC 1415 performs battery power regulation, DC-DC conversion, etc., and therefore has an input coupled to battery 1413 and an output providing current supply to all other functional modules. As further illustrated, in an exemplary embodiment, RFIC 1425 has an output coupled to an antenna for implementing any of a variety of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 series), WiMAX (IEEE 802.16 series), IEEE 802.20, Long Term Evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, its derivatives, and any other wireless protocols referred to as 3G, 4G, and higher generations. In an alternative implementation, each of these board-level modules may be integrated onto a separate IC coupled to the package substrate of the packaged device 1477, or integrated into a single IC (SoC) coupled to the package substrate of the packaged device 1477.

[0213] On the other hand, semiconductor packages are used to protect integrated circuit (IC) chips or dies and also provide electrical interfaces for the dies to external circuit systems. With the increasing demand for smaller electronic devices, semiconductor packages are being designed to be more compact and must support greater circuit density. Furthermore, the need for higher-performance devices has led to the need for improved semiconductor packages that achieve thinner package profiles and lower overall warpage compatible with subsequent component handling.

[0214] In one embodiment, wire bonding is used with a ceramic or organic packaging substrate. In another embodiment, a C4 process is used to mount the die to a ceramic or organic packaging substrate. Specifically, C4 solder ball connections can be implemented to provide a flip-chip interconnect between the semiconductor device and the substrate. Flip-chip or controlled collapse chip connection (C4) is a mounting type for semiconductor devices such as integrated circuit (IC) chips, MEMS, or components that utilizes solder bumps instead of wire bonding. Solder bumps are deposited on C4 pads located on the top side of the substrate package. To mount the semiconductor device onto the substrate, it is flipped so that the active side is facing down on the mounting area. Solder bumps are used to directly connect the semiconductor device to the substrate.

[0215] Figure 15 The figure shows a cross-sectional view of a flip-chip mounting die according to an embodiment of the present disclosure.

[0216] refer to Figure 15 The device 1500 includes a die 1502, such as an integrated circuit (IC) manufactured using one or more processes described herein or including one or more features described herein, according to embodiments of the present disclosure. The die 1502 includes metallized pads 1504 thereon. A package substrate 1506, such as a ceramic or organic substrate, includes connections 1508 thereon. The die 1502 and the package substrate 1506 are electrically connected via solder balls 1510 coupled to the metallized pads 1504 and the connections 1508. An underfill material 1512 surrounds the solder balls 1510.

[0217] Handling flip chips can be similar to conventional IC manufacturing, with some additional steps. Near the end of the manufacturing process, the attachment pads are metallized to make them more receptive to solder. This typically consists of several processes. A small dot of solder is then deposited on each metallized pad. The chip is then cut normally from the wafer. To attach the flip chip to the circuitry, the chip is inverted to bring the solder dots down onto the underlying electronics or connector on the circuit board. The solder is then remelted to create the electrical connection, typically using ultrasonic welding or alternatively a reflow solder process. This also leaves a small space between the chip's circuitry and the underlying mounting. In most cases, an electrical insulating adhesive is then "underfilled" to provide a stronger mechanical bond, provide thermal bridging, and ensure that the solder joints are not stressed due to the different heating of the chip and the rest of the system.

[0218] In other embodiments, according to embodiments of this disclosure, newer packaging and die-to-die interconnect methods (such as through-silicon vias (TSVs) and silicon interposers) are implemented to fabricate high-performance multi-chip modules (MCMs) and systems-in-packages (SiPs) that incorporate integrated circuits (ICs) fabricated according to one or more processes described herein or include one or more features described herein.

[0219] Therefore, a dicing process for integrated circuit layers with high-accuracy bonding has been disclosed.

[0220] The above description of the illustrated implementations of this disclosure (including those described in the abstract) is not intended to be exhaustive, nor is it intended to limit this disclosure to the precise forms disclosed. Although specific implementations and examples of this disclosure have been described herein for illustrative purposes, various equivalent modifications are possible within the scope of this disclosure, as will be appreciated by those skilled in the art. These modifications may be made to this disclosure in light of the above detailed description. The terminology used in the appended claims should not be construed as limiting this disclosure to the specific implementations disclosed in the specification and claims.

[0221] Although specific embodiments have been described above, these embodiments are not intended to limit the scope of this disclosure, even where only a single embodiment has been described for a particular feature. Unless otherwise stated, the examples of features provided in this disclosure are intended to be illustrative rather than restrictive. The foregoing description is intended to cover such alternatives, modifications, and equivalents that will be apparent to those skilled in the art benefiting from this disclosure.

[0222] The scope of this disclosure includes any feature or combination of features disclosed herein (explicitly or implicitly), or any generalization thereof, whether or not it alleviates any or all of the problems addressed herein. Therefore, during the examination of this application (or an application claiming priority thereto), new claims may be made for any such combination of features. Specifically, with reference to the appended claims, features from dependent claims may be combined with features from independent claims, and features from individual independent claims may be combined in any suitable manner, not just in the specific combinations listed in the appended claims.

[0223] Various embodiments or aspects of this disclosure are described herein. In some implementations, different embodiments are practiced separately. However, embodiments are not limited to those practiced individually. For example, two or more different embodiments may be combined together to be practiced as a single device, process, structure, etc. In some instances, the entirety of the embodiments may be combined together. In other instances, portions of a first embodiment may be combined with portions of one or more different embodiments. For example, portions of a first embodiment may be combined with portions of a second embodiment, or portions of a first embodiment may be combined with portions of a second embodiment and portions of a third embodiment, etc. The following examples relate to further embodiments. Various features of different embodiments can be combined in various ways with some included features and other excluded features to suit a variety of different applications.

[0224] Example 1: An integrated circuit structure includes: a front-end process (FEOL) stack having an uppermost surface including a first conductive feature and a first dielectric feature. A back-end process (BEOL) stack is stacked above the FEOL stack. The BEOL stack has a lowermost surface including a second conductive feature and a second dielectric feature respectively contacting one of the first conductive feature and the first dielectric feature on the uppermost surface of the FEOL stack. The second conductive feature is laterally offset from the corresponding first conductive feature.

[0225] Example 2: According to the integrated circuit structure of Example 1, the first conductive feature and the second conductive feature include copper, and the first dielectric feature and the second dielectric feature include silicon and oxygen.

[0226] Example 3: An integrated circuit structure according to Example 1 or 2, wherein the FEOL stack includes devices based on a fully surrounding gate.

[0227] Example 4: An integrated circuit structure according to Example 1 or 2, wherein the FEOL stack includes fin-based devices.

[0228] Example 5: The integrated circuit structure according to Example 1, 2, 3 or 4 further includes a back-side stack having an uppermost surface in contact with the lowermost surface of the FEOL stack.

[0229] Example 6: An integrated circuit structure includes: a front-end process (FEOL) stack having a lowermost surface including a first conductive feature and a first dielectric feature. A back-side stack is located below the FEOL stack. The back-side stack has a uppermost surface including a second conductive feature and a second dielectric feature respectively contacting one of the first conductive feature and the first dielectric feature on the lowermost surface of the FEOL stack. The second conductive feature is laterally offset from the corresponding first conductive feature.

[0230] Example 7: According to the integrated circuit structure of Example 6, the first conductive feature and the second conductive feature include copper, and the first dielectric feature and the second dielectric feature include silicon and oxygen.

[0231] Example 8: An integrated circuit structure according to Example 6 or 7, wherein the FEOL stack includes devices based on a fully surrounding gate.

[0232] Example 9: An integrated circuit structure according to Example 6 or 7, wherein the FEOL stack includes fin-based devices.

[0233] Example 10: The integrated circuit structure according to Example 6, 7, 8 or 9 further includes a back-end process (BEOL) stack having a lowermost surface in contact with the uppermost surface of the FEOL stack.

[0234] Example 11: A computing device includes: a board, and a component coupled to the board. The component includes an integrated circuit structure including a front-end process (FEOL) stack having a surface including a first conductive feature and a first dielectric feature. The computing device includes a back-end process (BEOL) stack above the FEOL stack, the BEOL stack having a lowermost surface including a second conductive feature and a second dielectric feature respectively contacting a corresponding one of the first conductive feature and the first dielectric feature of the surface of the FEOL stack, wherein the second conductive feature is laterally offset from the corresponding first conductive feature; or the computing device includes a back-side stack below the FEOL stack, the back-side stack having a uppermost surface including a second conductive feature and a second dielectric feature respectively contacting a corresponding one of the first conductive feature and the first dielectric feature of the surface of the FEOL stack, wherein the second conductive feature is laterally offset from the corresponding first conductive feature.

[0235] Example 12: A computing device according to Example 11, including a BEOL stack above a FEOL stack.

[0236] Example 13: A computing device according to Example 11, including a back-side stack below the FEOL stack.

[0237] Example 14: The computing device according to Example 11, 12 or 13 further includes a memory coupled to the board.

[0238] Example 15: The computing device according to Example 11, 12, 13 or 14 further includes a communication chip coupled to the board.

[0239] Example 16: The computing device according to Example 11, 12, 13, 14 or 15 further includes a battery coupled to a plate.

[0240] Example 17: The computing device according to Example 11, 12, 13, 14, 15 or 16 further includes a camera coupled to the board.

[0241] Example 18: The computing device according to Example 11, 12, 13, 14, 15, 16 or 17 further includes a display coupled to the board.

[0242] Example 19: A computing device according to Example 11, 12, 13, 14, 15, 16, 17 or 18, wherein the component is a packaged integrated circuit die.

[0243] Example 20: A computing device according to Example 11, 12, 13, 14, 15, 16, 17, 18 or 19, wherein the components are selected from the group consisting of a processor, a communication chip and a digital signal processor.

Claims

1. An integrated circuit structure, comprising: The preceding process is FEOL stacking, the FEOL stack having an uppermost surface including a first conductive feature and a first dielectric feature; as well as The subsequent process BEOL stack above the FEOL stack has a bottom surface, the bottom surface including a second conductive feature and a second dielectric feature that are in contact with a corresponding one of the first conductive feature and the first dielectric feature of the top surface of the FEOL stack, wherein the second conductive feature is laterally offset from the corresponding first conductive feature.

2. The integrated circuit structure according to claim 1, wherein, The first conductive feature and the second conductive feature include copper, and the first dielectric feature and the second dielectric feature include silicon and oxygen.

3. The integrated circuit structure according to claim 1 or 2, wherein, The FEOL stack includes devices based on a fully surrounding gate.

4. The integrated circuit structure according to claim 1 or 2, wherein, The FEOL stack includes fin-based devices.

5. The integrated circuit structure according to claim 1 or 2, further comprising: A back-side stack having an uppermost surface that contacts the lowermost surface of the FEOL stack.

6. An integrated circuit structure, comprising: The preceding process is FEOL stacking, the FEOL stack having a bottom surface including a first conductive feature and a first dielectric feature; as well as A back-side stack below the FEOL stack, the back-side stack having an uppermost surface, the uppermost surface including a second conductive feature and a second dielectric feature respectively contacting one of the first conductive feature and the first dielectric feature of the lowermost surface of the FEOL stack, wherein the second conductive feature is laterally offset from the corresponding first conductive feature.

7. The integrated circuit structure according to claim 6, wherein, The first conductive feature and the second conductive feature include copper, and the first dielectric feature and the second dielectric feature include silicon and oxygen.

8. The integrated circuit structure according to claim 6 or 7, wherein, The FEOL stack includes devices based on a fully surrounding gate.

9. The integrated circuit structure according to claim 6 or 7, wherein, The FEOL stack includes fin-based devices.

10. The integrated circuit structure according to claim 6 or 7, further comprising: The subsequent process involves BEOL stacking, wherein the BEOL stack has a lower surface that contacts the uppermost surface of the FEOL stack.

11. A computing device, comprising: plate; as well as Components, coupled to the board, the components including an integrated circuit structure, the integrated circuit structure comprising: The preceding process is FEOL stacking, the FEOL stack having a surface including a first conductive feature and a first dielectric feature; as well as A subsequent BEOL stack is placed above the FEOL stack. The BEOL stack has a bottom surface, which includes a second conductive feature and a second dielectric feature that are in contact with a corresponding first conductive feature and a first dielectric feature of the surface of the FEOL stack, respectively. The second conductive feature is laterally offset from its corresponding first conductive feature. A back-side stack below the FEOL stack, the back-side stack having an uppermost surface, the uppermost surface including a second conductive feature and a second dielectric feature respectively contacting one of the first conductive feature and the first dielectric feature of the surface of the FEOL stack, wherein the second conductive feature is laterally offset from the corresponding first conductive feature.

12. The computing device of claim 11, comprising the BEOL stack above the FEOL stack.

13. The computing device of claim 11, including the back-side stack below the FEOL stack.

14. The computing device according to claim 11, 12 or 13, further comprising: The memory is coupled to the board.

15. The computing device according to claim 11, 12 or 13, further comprising: A communication chip is coupled to the board.

16. The computing device according to claim 11, 12 or 13, further comprising: The battery is coupled to the plate.

17. The computing device according to claim 11, 12 or 13, further comprising: The camera is coupled to the plate.

18. The computing device according to claim 11, 12 or 13, further comprising: The display is coupled to the board.

19. The computing device according to claim 11, 12 or 13, wherein, The component is a packaged integrated circuit die.

20. The computing device according to claim 11, 12 or 13, wherein, The component is selected from a group consisting of a processor, a communication chip, and a digital signal processor.

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