Semiconductor device and method of manufacturing the same

Abstract

The invention provides a semiconductor device and a manufacturing method thereof. A method for manufacturing a semiconductor device (1) provided with a superstructure is provided with: a step for patterning an ion implantation mask on second conductivity-type semiconductor layers (14A, 14B); and a step in which, after the step in which the ion implantation mask is patterned, a first-conductivity-type impurity is ion-implanted into the second-conductivity-type semiconductor layer through the openings (54, 154) of the ion implantation mask to form first-conductivity-type pillars (14a) and second-conductivity-type pillars (14b). The step for patterning the ion implantation mask comprises: a step for forming mask forming layers (42, 142) on the second conductivity-type semiconductor layer; a step for forming grooves (52, 152) extending from the upper surface of the mask forming layer toward the second conductivity-type semiconductor layer; a step for embedding shielding parts (46, 146) containing metal in the grooves; and a step of removing the mask forming layer between the shielding parts to form an opening.

Description

TECHNICAL FIELD

[0001] The technology disclosed in this specification relates to a semiconductor device and a manufacturing method thereof. BACKGROUND

[0002] A semiconductor device provided with a superstructure in which p-type columns and n-type columns are alternately and repeatedly arranged in at least one direction has been proposed. The semiconductor device provided with the superstructure can have a high withstand voltage with a low on-resistance. An example of the semiconductor device provided with the superstructure is disclosed in Patent Literature 1.

[0003] PRIOR ART DOCUMENTS PATENT LITERATURE Patent Literature 1: Japanese Patent Application Publication No. 2023-176409 SUMMARY

[0004] In order to further improve the characteristics of a low on-resistance and a high withstand voltage, it is desirable to increase the aspect ratio of each of the p-type columns and the n-type columns. The superstructure is formed by ion implanting impurities of one conduction type (for example, p-type impurities) into a semiconductor layer of the other conduction type (for example, an n-type semiconductor layer). In the past, a photoresist that is opened in correspondence with an ion implantation region has been used as a mask for ion implantation. In order to shield the conduction type impurities for ion implantation and form columns with a high aspect ratio, it is necessary to increase the thickness of the photoresist and reduce the pitch of openings formed in the photoresist. Therefore, the aspect ratio of the openings formed in the photoresist for forming columns with a high aspect ratio is also high. According to the inventors’ studies, if the aspect ratio of the openings formed in the photoresist is high, there is a concern that the photoresist collapses.

[0005] The present specification provides technology that can be applied to a superstructure composed of columns with a high aspect ratio.

[0006] The first technical solution of the present disclosure provides a manufacturing method of a semiconductor device having a superstructure obtained by alternately and repeatedly arranging first conductive pillars and second conductive pillars in at least one direction. The manufacturing method includes the following steps: a step of patterning an ion implantation mask on a second conductive semiconductor layer; and a step of forming the first conductive pillars and the second conductive pillars by ion implanting a first conductive impurity into the second conductive semiconductor layer through an opening of the ion implantation mask after the step of patterning the ion implantation mask. The step of patterning the ion implantation mask includes the following steps: a step of forming a mask forming layer on the second conductive semiconductor layer; a step of forming a groove extending from an upper surface of the mask forming layer toward the second conductive semiconductor layer; a step of embedding a metal-containing shielding portion in the groove; and a step of removing the mask forming layer between the shielding portions to form the opening. The ion implantation mask used in the manufacturing method has the metal-containing shielding portion. The shielding property of the metal-containing shielding portion to the first conductive impurity is high. Therefore, the film thickness of the ion implantation mask can be made thinner. As a result, the aspect ratio of the opening formed in the ion implantation mask is lower, and therefore the collapse of the ion implantation mask can be suppressed. Furthermore, the opening of the ion implantation mask is formed by removing the mask forming layer between the shielding portions embedded in the mask forming layer in advance. Therefore, the opening of the ion implantation mask is not formed by directly etching the shielding portion. Instead, in the case where the opening is formed by directly etching the metal-containing shielding portion, the maximum surface roughness of the side surface of the opening increases because the etching progresses along the grain boundary of the shielding portion. In the above manufacturing method, the maximum surface roughness of the opening of the ion implantation mask is reduced because the shielding portion is not directly etched. As a result, the maximum surface roughness of the interface between the first conductive pillars and the second conductive pillars formed in the second conductive semiconductor layer is also reduced. The semiconductor device manufactured by the above manufacturing method can suppress the destruction of the charge balance of the superstructure and has the characteristic of high withstand voltage.

[0007] The second technical solution of the present disclosure provides a semiconductor device having a superstructure obtained by alternately and repeatedly arranging first conductive pillars and second conductive pillars in at least one direction. The first conductive pillars and the second conductive pillars are each composed of silicon carbide. The pitch of the repeating direction of the first conductive pillars and the second conductive pillars is 0.4 nm or less. The maximum surface roughness of the interface between the first conductive pillars and the second conductive pillars is less than 30 nm. BRIEF DESCRIPTION OF DRAWINGS

[0008] Figure 1A main-part cross-sectional view schematically showing a semiconductor device disclosed in the present specification.

[0009] Figure 2 A main-part cross-sectional view schematically showing a first manufacturing method of a semiconductor device disclosed in the present specification in one step.

[0010] Figure 3 A main-part cross-sectional view schematically showing a first manufacturing method of a semiconductor device disclosed in the present specification in one step.

[0011] Figure 4 A main-part cross-sectional view schematically showing a first manufacturing method of a semiconductor device disclosed in the present specification in one step.

[0012] Figure 5 A main-part cross-sectional view schematically showing a first manufacturing method of a semiconductor device disclosed in the present specification in one step.

[0013] Figure 6 A main-part cross-sectional view schematically showing a first manufacturing method of a semiconductor device disclosed in the present specification in one step.

[0014] Figure 7 A main-part cross-sectional view schematically showing a first manufacturing method of a semiconductor device disclosed in the present specification in one step.

[0015] Figure 8 A main-part cross-sectional view schematically showing a first manufacturing method of a semiconductor device disclosed in the present specification in one step.

[0016] Figure 9 A main-part cross-sectional view schematically showing a first manufacturing method of a semiconductor device disclosed in the present specification in one step.

[0017] Figure 10 A main-part cross-sectional view schematically showing a first manufacturing method of a semiconductor device disclosed in the present specification in one step.

[0018] Figure 11 A main-part cross-sectional view schematically showing a first manufacturing method of a semiconductor device disclosed in the present specification in one step.

[0019] Figure 12 A main-part cross-sectional view schematically showing a second manufacturing method of a semiconductor device disclosed in the present specification in one step.

[0020] Figure 13 A main-part cross-sectional view schematically showing a second manufacturing method of a semiconductor device disclosed in the present specification in one step.

[0021] Figure 14 A main-part cross-sectional view in one step of a second manufacturing method of the semiconductor device disclosed in this specification is schematically shown.

[0022] Figure 15 A main-part cross-sectional view in one step of a second manufacturing method of the semiconductor device disclosed in this specification is schematically shown.

[0023] Figure 16 A main-part cross-sectional view in one step of a second manufacturing method of the semiconductor device disclosed in this specification is schematically shown.

[0024] Figure 17 A main-part cross-sectional view in one step of a second manufacturing method of the semiconductor device disclosed in this specification is schematically shown.

[0025] Figure 18 A main-part cross-sectional view in one step of a second manufacturing method of the semiconductor device disclosed in this specification is schematically shown.

[0026] Figure 19 A main-part cross-sectional view in one step of a second manufacturing method of the semiconductor device disclosed in this specification is schematically shown.

[0027] Figure 20 A main-part cross-sectional view in one step of a second manufacturing method of the semiconductor device disclosed in this specification is schematically shown. DETAILED DESCRIPTION

[0028] Hereinafter, a semiconductor device disclosed in this specification will be described with reference to the drawings. Further, for the purpose of illustration, for the repeatedly arranged constituent elements, only one of them is sometimes labeled with a reference numeral.

[0029] Figure 1 A main-part cross-sectional view of the semiconductor device 1 is schematically shown. The semiconductor device 1 is a power semiconductor device of a kind called MOSFET (Metal Oxide Semiconductor Field Effect Transistor), and has a semiconductor layer 10, a drain electrode 22 covering a lower surface of the semiconductor layer 10, a source electrode 24 covering an upper surface of the semiconductor layer 10, and a plurality of trench gates 30 provided in an upper layer portion of the semiconductor layer 10.

[0030] The semiconductor layer 10 is a wide bandgap semiconductor. The semiconductor layer 10 is not particularly limited, and can be, for example, a 4H silicon carbide layer. The semiconductor layer 10 can also be not a silicon carbide layer but, for example, a nitride semiconductor layer, a gallium oxide layer, a diamond layer, or the like. The semiconductor layer 10 has n-type conductivity.+ p-type body region 16, n + p-type source region 18, and p + p-type body contact region 19.

[0031] Drain region 12 is disposed in a lower portion of semiconductor layer 10, at a position exposed on a lower surface of semiconductor layer 10. Drain region 12 is in ohmic contact with drain electrode 22 covering the lower surface of semiconductor layer 10. As explained later in the manufacturing method, drain region 12 includes n + type silicon carbide substrate and an n + type epitaxial layer grown from the upper surface thereof.

[0032] Drift region 14 is disposed between drain region 12 and body region 16, and has a plurality of p-type pillars 14a and a plurality of n-type pillars 14b. P-type pillar 14a is an example of a first conductive type pillar, and n-type pillar 14b is an example of a second conductive type pillar. That is, in this example, p-type is an example of a first conductive type, and n-type is an example of a second conductive type. P-type pillars 14a and n-type pillars 14b are alternately and repeatedly disposed in at least one direction in a cross section of semiconductor layer 10, constituting a superlattice structure. The plurality of p-type pillars 14a and the plurality of n-type pillars 14b, when viewed from a direction orthogonal to the upper surface of semiconductor layer 10 (hereinafter referred to as "when viewed from above"), can be disposed, for example, in a strip shape, without particular limitation.

[0033] P-type pillar 14a has a height 14H, which is a height measured along the thickness direction of semiconductor layer 10 from the lower surface of p-type pillar 14a to the interface of p-type pillar 14a with body region 16, that is, the upper surface of p-type pillar 14a. P-type pillar 14a has a width 14W measured along the repeating direction of the superlattice structure between the interface with n-type pillar 14b, that is, the side surface. The height 14H of p-type pillar 14a is not particularly limited, and is, for example, 3.4 μm or more. The width 14W of p-type pillar 14a is not particularly limited, and is, for example, 0.4 μm or less. Thus, the aspect ratio of p-type pillar 14a is 8.5 or more. The width 14W of p-type pillar 14a is not particularly limited, and is, for example, 0.2 μm or more. The aspect ratio of p-type pillar 14a is not particularly limited, and is, for example, 17.8 or less. The same applies to the height and width of n-type pillar 14b. Thus, the pitch in the repeating direction of p-type pillar 14a and n-type pillar 14b is, for example, 0.4 μm or less. In addition, the pitch in the repeating direction of p-type pillar 14a and n-type pillar 14b is, for example, 0.2 μm or more. With the superlattice structure of such dimensions, the withstand voltage of semiconductor device 1 calculated from the insulating breakdown field of silicon carbide is 850 V or more.

[0034] The body region 16 is provided on the drift region 14, and is disposed in the upper layer portion of the semiconductor layer 10. The body region 16 is provided between the n-type pillar 14b of the drift region 14 and the source region 18, and separates the n-type pillar 14b from the source region 18. The concentration of the p-type impurities of the body region 16 is adjusted according to the desired gate threshold voltage.

[0035] The source region 18 is provided on the body region 16, and is disposed in the upper layer portion of the semiconductor layer 10, at a position exposed on the upper surface of the semiconductor layer 10. The source region 18 is in contact with the side surface of the trench gate 30. The source region 18 is in ohmic contact with the source electrode 24 that covers the upper surface of the semiconductor layer 10.

[0036] The body contact region 19 is provided on the body region 16, and is disposed in the upper layer portion of the semiconductor layer 10, at a position exposed on the upper surface of the semiconductor layer 10. The body contact region 19 is in ohmic contact with the source electrode 24 that covers the upper surface of the semiconductor layer 10.

[0037] The trench gate 30 is embedded in the trench formed in the upper layer portion of the semiconductor layer 10, and penetrates the source region 18 and the body region 16 to reach the n-type pillar 14b of the drift region 14. In this example, when the semiconductor layer 10 is viewed from above, the trench gate 30 extends along the length direction of the p-type pillar 14a and the n-type pillar 14b, that is, along a direction orthogonal to the repetition direction of the superlattice. Instead of this example, the trench gate 30 can also extend along the repetition direction of the p-type pillar 14a and the n-type pillar 14b when the semiconductor layer 10 is viewed from above. The trench gate 30 has a gate electrode 32 and a gate insulating film 34. The gate electrode 32 is formed of polycrystal silicon containing impurities, and is opposed to the semiconductor layer 10 with the gate insulating film 34 interposed therebetween. In particular, the gate electrode 32 is opposed to the portion of the body region 16 that separates the n-type pillar 14b of the drift region 14 from the source region 18, with the gate insulating film 34 interposed therebetween. The gate insulating film 34 is formed of silicon oxide, and covers the inner wall of the trench.

[0038] Next, the operation of the semiconductor device 1 will be described with reference to Figure 1 The semiconductor device 1 is turned on in a state where the potential of the drain electrode 22 is positive with respect to the potential of the source electrode 24, and the potential of the gate electrode 32 of the trench gate 30 is positive with respect to the source electrode 24 and is controlled to be higher than a threshold value. At this time, a reverse type layer is formed in the portion of the body region 16 that separates the n-type pillar 14b of the drift region 14 from the source region 18. Electrons supplied from the source region 18 reach the n-type pillar 14b of the drift region 14 via the channel of the reverse type layer. The electrons that have reached the n-type pillar 14b flow to the drain region 12 via the n-type pillar 14b. The n-type pillar 14b has a high concentration of n-type impurities, and therefore the semiconductor device 1 can have a low on-resistance characteristic.

[0039] When the potential of the gate electrode 32 of the trench gate 30 is controlled to be the same as the potential of the source electrode 24, the channel of the inversion layer disappears, and the semiconductor device 1 is turned off. The plurality of p-type pillars 14a and n-type pillars 14b constituting the superstructure are substantially completely depleted, and the drift region 14 is largely depleted. Furthermore, since the drift region 14 has a superstructure, the electric field distribution of the drift region 14 is equalized in the depth direction. Therefore, the drift region 14 can withstand a large potential difference, so the semiconductor device 1 can have high withstand voltage characteristics.

[0040] (Method for manufacturing semiconductor devices) Hereinafter, with reference to the accompanying drawings, a first manufacturing method and a second manufacturing method for manufacturing semiconductor device 1 will be described. The step of forming a superstructure in the manufacturing method of semiconductor device 1 will be described below. As detailed below, the superstructure is formed by connecting p-type pillars and n-type pillars formed on the lower epitaxial layer and the upper epitaxial layer respectively. Other steps for manufacturing semiconductor device 1 can utilize known manufacturing techniques as needed.

[0041] (First manufacturing method) The following is for reference Figures 2-11 The first manufacturing method of semiconductor device 1 will be described. First, as follows... Figure 2 As shown, drain region 12 is prepared. Drain region 12 is connected to n + Surface crystal growth of type n silicon carbide substrate + An n-type lower epitaxial layer 14A is formed. Next, using epitaxial growth techniques, an n-type lower epitaxial layer 14A is crystallized and grown from the surface of the drain region 12. The thickness of the lower epitaxial layer 14A is not particularly limited, and can be, for example, 1.8 μm. Furthermore, the lower epitaxial layer 14A constitutes at least a portion of the semiconductor layer 10, and is sometimes referred to as an n-type semiconductor layer. The lower epitaxial layer 14A is an example of a second conductivity type semiconductor layer.

[0042] Next, as Figure 3 As shown, a mask forming layer 42 is formed on the lower epitaxial layer 14A using a vapor deposition technique such as CVD. The mask forming layer 42 is not particularly limited, and can be, for example, an oxide film such as silicon oxide. The film thickness of the mask forming layer 42 is not particularly limited, and can be, for example, 1.1 μm.

[0043] Next, as Figure 4As shown, multiple grooves 52 are formed in the mask forming layer 42 using etching techniques such as RIE or wet etching. A portion of the mask forming layer 42 remaining between the grooves 52 is referred to as a mask forming wall 43. The grooves 52 extend from the upper surface of the mask forming layer 42 toward the lower epitaxial layer 14A. The grooves 52 do not penetrate the mask forming layer 42. Therefore, a portion of the mask forming layer 42 remains on the lower epitaxial layer 14A. This portion of the mask forming layer 42 remaining on the lower epitaxial layer 14A is referred to as a release film 40. Alternatively, the grooves 52 may penetrate the mask forming layer 42.

[0044] Next, as Figure 5 As shown, a sidewall film 44 is formed on the inner wall of the tank 52 using a vapor deposition technique such as sputtering. The sidewall film 44 is also formed on the top surface of the mask forming wall 43. The sidewall film 44 is a film containing metal. The sidewall film 44 is not particularly limited, and can be, for example, a metal nitride film. In this example, the sidewall film 44 is titanium nitride (TiN). In the sputtering method for forming titanium nitride film, titanium (Ti) can be used as the target, nitrogen (N2) as the reactive gas, and argon (Ar) as the inert gas. Instead of this example, the sidewall film 44 can also be formed on the inner wall of the tank 52 using atomic layer deposition, for example. As explained in the second manufacturing method described later, the coverage of the sidewall film 44 formed by atomic layer deposition is improved. Therefore, the sidewall film 44 can be formed well even if the spacing of the tank 52 is narrow.

[0045] Next, as Figure 6 As shown, for example, using an atomic layer deposition (ALD) or other vapor deposition techniques, a shielding portion 46 is embedded in the tank 52. The shielding portion 46 is also formed on the top surface of the mask forming wall 43, completely embedded in the tank 52. The shielding portion 46 is a film containing metal. The shielding portion 46 is not particularly limited; for example, it can be a single film of metal. In this example, the shielding portion 46 is made of tungsten (W). In the atomic layer deposition method for forming the tungsten film, tungsten hexafluoride (WF6) as a metal precursor gas and hydrogen (H2) as a reducing gas can be used; there are no particular limitations. Alternatively, the material of the shielding portion 46 can also be tungsten silicide (WSi2).

[0046] Next, as Figure 7 As shown, the obstruction portion 46 formed on the top surface of the mask forming wall 43 is removed using a planarization technique such as CMP. In this planarization process, the sidewall film 44 formed on the top surface of the mask forming wall 43 is also removed, exposing the mask forming wall 43.

[0047] Next, as Figure 8As shown, the mask forming walls 43 present between the shielding portions 46 are removed using etching techniques such as RIE or wet etching to form openings 54, thus patterning the ion implantation mask. This ion implantation mask is an example of a first ion implantation mask. In this etching process, only the mask forming walls 43 are removed, without removing the release film 40 remaining on the lower epitaxial layer 14A. Alternatively, the openings 54 may also penetrate the release film 40.

[0048] Next, as Figure 9 As shown, using ion implantation technology, p-type impurities are ion implanted into the lower epitaxial layer 14A through the opening 54 of the ion implantation mask. The p-type impurity is not particularly limited; for example, it can be aluminum. The regions in the lower epitaxial layer 14A where p-type impurities have been introduced are called p-type pillars 14a, and the regions sandwiched between the p-type pillars 14a are called n-type pillars 14b. Thus, within the lower epitaxial layer 14A, a structure is formed in which p-type pillars 14a and n-type pillars 14b are alternately and repeatedly arranged in one direction.

[0049] Next, as Figure 10 As shown, the release film 40, sidewall film 44, and shielding portion 46 deposited on the lower epitaxial layer 14A are removed using a lift-off method. Specifically, the release film 40 is etched using an etchant (e.g., hydrofluoric acid) with a higher etching rate for the release film 40 than for the sidewall film 44 and shielding portion 46, thereby removing the sidewall film 44 and shielding portion 46 stacked on the release film 40.

[0050] Next, as Figure 11 As shown, after the upper epitaxial layer 14B is crystallized and grown on the lower epitaxial layer 14A using epitaxial growth technology, a structure in which p-type pillars 14a and n-type pillars 14b are alternately and repeatedly arranged along one direction is formed in the upper epitaxial layer 14B. The upper epitaxial layer 14B is an example of a second conductivity type epitaxial layer. Such an upper epitaxial layer 14B is further implemented on... Figures 2-10 The structure is formed through the processes described herein. Specifically, the process includes patterning a second ion implantation mask on the upper epitaxial layer 14B, implanting p-type impurities into the upper epitaxial layer 14B through the opening of the second ion implantation mask to form p-type pillars 14a and n-type pillars 14b within the upper epitaxial layer 14B, and peeling off the second ion implantation mask. Thus, the p-type pillars 14a and n-type pillars 14b formed on the lower epitaxial layer 14A and the upper epitaxial layer 14B, respectively, are connected vertically to form a superstructure.

[0051] Subsequently, using epitaxial growth technology, a body region 16 containing p-type impurities is formed on the upper epitaxial layer 14B. Using ion implantation technology, a source region 18 and a body contact region 19 are formed in a specified area within the body region 16, forming various electrode structures (trench gate 30, drain electrode 22, and source electrode 24), thereby completing the semiconductor device 1.

[0052] The ion implantation mask used in the above manufacturing method has a metal-containing shielding portion 46. The metal-containing shielding portion 46 has high shielding ability against p-type impurities (aluminum in this example). Therefore, even if the shielding portion 46 is thin, it can sufficiently shield against p-type impurities, preventing the implantation of p-type impurities in the non-ion implantation regions of the epitaxial layers 14A and 14B. Because the shielding portion 46 is thin, the aspect ratio of the openings 54 formed in the shielding portion 46 is lower. As a result, the collapse of the shielding portion 46 between the openings 54 can be suppressed.

[0053] The opening 54 of the ion implantation mask used in the above manufacturing method is formed by removing the mask forming wall 43 pre-embedded between the shielding portions 46 of the mask forming layer 42. Alternatively, consider the case where the opening 54 is formed by directly etching the shielding portions 46 containing tungsten. For example, if the shielding portions 46 are directly etched using the RIE method, the etching proceeds along the grain boundaries of the shielding portions 46. Since the tungsten grain size is relatively large, the maximum surface roughness of the side surface of the opening 54 becomes larger. On the other hand, in the above manufacturing method, since the shielding portions 46 are not directly etched, the maximum surface roughness of the opening 54 of the ion implantation mask is small. As a result, the maximum surface roughness of the interface between the p-type pillars 14a and the n-type pillars 14b formed in the epitaxial layers 14A and 14B is also reduced. The semiconductor device 1 manufactured by the above manufacturing method can suppress the disruption of charge balance in the superstructure and has high withstand voltage characteristics.

[0054] The ion implantation mask used in the above manufacturing method has a sidewall film 44 covering the side of the shielding portion 46. The shielding portion 46 is made of tungsten, and the sidewall film 44 is made of titanium nitride. The sidewall film 44 is made of a material with a crystal grain size smaller than that of the shielding portion 46. By covering the side of the shielding portion 46 with the sidewall film 44, the sidewall film 44 with a small crystal grain size is exposed on the side of the opening 54 of the ion implantation mask. Therefore, the maximum surface roughness of the side of the opening 54 of the ion implantation mask is suppressed to a smaller extent. As a result, the maximum surface roughness of the interface between the p-type pillar 14a and the n-type pillar 14b formed in the epitaxial layers 14A and 14B is also reduced. The semiconductor device 1 manufactured by the above manufacturing method can suppress the disruption of charge balance in the superstructure and has high withstand voltage characteristics.

[0055] The tungsten crystal grain size of the material used for the shielding portion 46 varies from 17 nm to 30 nm depending on the crystal orientation. For example, when the shielding portion 46 is directly etched using the RIE method to form the opening of the ion implantation mask, various crystal orientations are exposed on the side of the opening 54 of the ion implantation mask, so the maximum surface roughness of the opening 54 of the ion implantation mask becomes 30 nm. It can be assumed that the maximum surface roughness of the interface between the p-type pillar 14a and the n-type pillar 14b formed using such an ion implantation mask is also 30 nm. For example, when the spacing between the p-type pillar 14a and the n-type pillar 14b in the repeating direction is a narrow spacing of 0.4 μm or less, if the maximum surface roughness of the interface between the p-type pillar 14a and the n-type pillar 14b is as high as 30 nm, the charge balance of the superstructure may be disrupted. On the other hand, according to the ion implantation mask manufactured by the above method, since the shielding portion 46 is not directly etched, the maximum surface roughness of the opening 54 of the ion implantation mask is less than 30 nm. Therefore, the maximum surface roughness of the interface between the p-type pillar 14a and the n-type pillar 14b is also less than 30 nm. Furthermore, since a small-grain-size sidewall film 44 is exposed on the side of the opening 54 of the ion implantation mask, the maximum surface roughness of the opening 54 of the ion implantation mask is further reduced, and can be set to less than 25 nm, less than 20 nm, less than 15 nm, or less than 10 nm. The maximum surface roughness of the interface between the p-type pillar 14a and the n-type pillar 14b is not particularly limited, for example, it is 0.42 nm or more. In this way, the above manufacturing method can suppress the disruption of the charge balance of the superstructure even when the spacing in the repeating direction of the p-type pillar 14a and the n-type pillar 14b is less than 0.4 μm, and has high withstand voltage characteristics.

[0056] In the above manufacturing method, when the groove 52 is formed in the mask forming layer 42, and then the mask forming wall 43 is removed, a release film 40 remains on the epitaxial layers 14A and 14B. According to this method, the release film 40 can function as a protective film. Therefore, damage to the upper surfaces of the epitaxial layers 14A and 14B can be suppressed. Furthermore, the release film 40 remaining on the epitaxial layers 14A and 14B can function as a through-film during ion implantation of p-type impurities. Therefore, damage to the upper surfaces of the epitaxial layers 14A and 14B during ion implantation can also be suppressed.

[0057] The ion implantation mask used in the above manufacturing method has a release film 40 remaining on the epitaxial layers 14A and 14B. Due to the presence of the release film 40, metal contamination caused by the metal (tungsten in this example) contained in the shielding portion 46 penetrating into the epitaxial layers 14A and 14B can be suppressed. For example, if the metal contained in the shielding portion 46 remains between the lower epitaxial layer 14A and the upper epitaxial layer 14B, the charge balance of the superstructure may be disrupted, resulting in a decrease in the breakdown voltage of the semiconductor device 1. Therefore, the above manufacturing method is particularly useful when forming a superstructure in two stages.

[0058] (Second manufacturing method) The following is for reference Figures 12-20 A second manufacturing method for manufacturing semiconductor device 1 will be described. Figure 2 The process shown up to the end is the same as the first manufacturing method.

[0059] Next, as Figure 12 As shown, a release film 140 is formed on the lower epitaxial layer 14A using a vapor deposition technique such as sputtering. The release film 140 is not particularly limited and can be, for example, an oxide film such as silicon oxide. The thickness of the release film 140 is not particularly limited and can be, for example, 20 nm.

[0060] Next, as Figure 13 As shown, a diffusion barrier film 141 is formed on the release film 140 using a vapor deposition technique such as sputtering. The diffusion barrier film 141 is not particularly limited, and can be, for example, a silicon nitride (SiN) film. The thickness of the diffusion barrier film 141 is not particularly limited, and can be, for example, 20 nm.

[0061] Next, as Figure 14 As shown, a mask forming layer 142 is formed on the diffusion barrier film 141 using a vapor deposition technique such as CVD. The mask forming layer 142 is not particularly limited, and can be, for example, an oxide film such as silicon oxide. The film thickness of the mask forming layer 142 is not particularly limited, and can be, for example, 1.1 μm.

[0062] Next, as Figure 15 As shown, multiple grooves 152 are formed in the mask forming layer 142 using etching techniques such as RIE or wet etching. A portion of the mask forming layer 142 remaining between the grooves 152 is referred to as a mask forming wall 143. The grooves 152 extend from the upper surface of the mask forming layer 142 toward the diffusion barrier film 141. In this example, the grooves 152 penetrate the mask forming layer 142 and reach the diffusion barrier film 141. Alternatively, in this example, the grooves 152 may not penetrate the mask forming layer 142, and a portion of the mask forming layer 42 may remain on the diffusion barrier film 141.

[0063] Next, as Figure 16As shown, a sidewall film 144 is formed on the inner wall of the tank 152 using a vapor deposition technique such as atomic layer deposition (ALD). The sidewall film 144 is also formed on the top surface of the mask forming wall 143. The sidewall film 144 is not particularly limited; for example, it can be a metal nitride film. In this example, the sidewall film 144 is titanium nitride (TiN). In the ALD process for forming the titanium nitride film, titanium tetrachloride (TiCl4) as a metal precursor gas and ammonia (NH4) as a nitrogen precursor gas can be used; there are no particular limitations.

[0064] In the second manufacturing method, the sidewall film 144 is formed using atomic layer deposition (ALD). Compared to the first manufacturing method, which forms the sidewall film 44 using sputtering, the sidewall film 144 formed by ALD can be well deposited on the inner wall of the trench 152 even if the width of the trench 152 is narrow. Therefore, the spacing of the trenches 152 can be narrowed, thereby narrowing the spacing of the superstructure. On the other hand, in ALD, metal chloride is used as the metal precursor gas. Therefore, chlorine contained in the metal chloride may diffuse into the lower epitaxial layer 14A. The chlorine diffused into the lower epitaxial layer 14A may cause changes in the gate threshold voltage during periodic operation. In the second manufacturing method, a diffusion barrier film 141 is provided between the trench 152 and the lower epitaxial layer 14A. The diffusion barrier film 141 is a material with less chlorine diffusion compared to the release film 140. Because of the diffusion barrier film 141, even if the sidewall film 144 is formed by atomic layer deposition, the diffusion of chlorine contained in the metal chloride into the lower epitaxial layer 14A can be suppressed.

[0065] Next, as Figure 17 As shown, for example, using an atomic layer deposition (ALD) or other vapor deposition technique, a shielding portion 146 is embedded in the tank 152. The shielding portion 146 is also formed on the top surface of the mask forming wall 143, completely embedded in the tank 152. The shielding portion 146 is a film containing metal. The shielding portion 146 is not particularly limited; for example, it can be a single film of metal. In this example, the shielding portion 146 is tungsten (W). In the ALD process, tungsten hexafluoride (WF6) as the metal precursor gas and hydrogen (H2) as the reducing gas can be used; there are no particular limitations. Alternatively, the material of the shielding portion 146 can also be tungsten silicide (WSi2).

[0066] Next, as Figure 18 As shown, the masking portion 146 formed on the top surface of the mask forming wall 143 is removed using a planarization technique such as CMP. In this planarization process, the sidewall film 144 formed on the top surface of the mask forming wall 143 is also removed, exposing the mask forming wall 143.

[0067] Next, as Figure 19As shown, using etching techniques such as RIE or wet etching, the mask forming walls 143 present between the shielding portions 146 are removed to form openings 154, allowing the ion implantation mask to be patterned. The diffusion barrier film 141 is exposed at the bottom surface of the opening 154. Alternatively, a portion of the mask forming wall 143 may remain.

[0068] Next, as Figure 20 As shown, using ion implantation technology, p-type impurities are ion implanted into the lower epitaxial layer 14A through the opening 154 of the ion implantation mask. The p-type impurity is not particularly limited; for example, it can be aluminum. The regions in the lower epitaxial layer 14A where p-type impurities have been introduced are called p-type pillars 14a, and the regions sandwiched between the p-type pillars 14a are called n-type pillars 14b. Thus, within the lower epitaxial layer 14A, a structure is formed in which p-type pillars 14a and n-type pillars 14b are alternately and repeatedly arranged in one direction.

[0069] Next, similar to the first manufacturing method, the release film 140, diffusion barrier film 141, sidewall film 144, and blocking portion 146 formed on the lower epitaxial layer 14A are removed using a peeling method. This forms... Figure 10 The lower epitaxial layer 14A is shown in the diagram. Furthermore, after growing the upper epitaxial layer 14B on the lower epitaxial layer 14A using epitaxial growth technology, a structure is formed within the upper epitaxial layer 14B in which p-type pillars 14a and n-type pillars 14b are alternately and repeatedly arranged in one direction. This upper epitaxial layer 14B is then further processed... Figures 12-20 The semiconductor device 1 is formed through the processes described herein. Thus, p-type pillars 14a and n-type pillars 14b, respectively formed in the lower epitaxial layer 14A and the upper epitaxial layer 14B, are connected vertically to form a superstructure. Then, through the same processes as in the first manufacturing method, the semiconductor device 1 is completed.

[0070] As described above, the second manufacturing method, by providing a diffusion barrier film 141, can suppress chlorine diffusion during the formation of the sidewall film 144 using atomic layer deposition, thereby suppressing fluctuations in the gate threshold voltage during periodic operation. Furthermore, since the second manufacturing method forms the sidewall film 144 using atomic layer deposition, it can achieve good coverage, thus narrowing the spacing of the grooves 152 in the mask forming layer 142, and consequently, narrowing the spacing of the superstructure. Therefore, the second manufacturing method is a useful technique for miniaturizing superstructures.

[0071] The specific examples of the present invention have been described in detail above, but these are merely illustrative and do not limit the scope of the claims. The technology described in the claims includes technologies obtained by various modifications and alterations to the specific examples described above. Furthermore, the technical elements illustrated in this specification or drawings exert their technical usefulness individually or in various combinations, and are not limited to the combinations described in the claims at the time of application. In addition, the technology illustrated in this specification or drawings can achieve multiple objectives simultaneously, and achieving one of these objectives is itself technically useful.

Claims

1. A method for manufacturing a semiconductor device, the semiconductor device having a superstructure obtained by alternately and repeatedly arranging first conductive pillars and second conductive pillars along at least one direction, characterized in that... It includes the following processes: The process of patterning an ion implantation mask on a second conductive semiconductor layer; and Following the patterning process of the ion implantation mask, a first conductivity type impurity is implanted into the second conductivity type semiconductor layer through the opening of the ion implantation mask to form the first conductivity type pillar and the second conductivity type pillar. The process of patterning the ion implantation mask includes the following steps: The process of forming a mask forming layer on the second conductive semiconductor layer; The process of forming a trench extending from the upper surface of the mask forming layer toward the second conductive semiconductor layer; The process of embedding a metal shielding part in the groove; as well as The process of removing the mask forming layer between the obstructing portions to form the opening.

2. The method for manufacturing a semiconductor device according to claim 1, characterized in that, The process of patterning the ion implantation mask also includes a process of forming a sidewall membrane on the inner wall of the groove between the process of forming the groove and the process of embedding the shielding part. The crystal grain size of the sidewall membrane is smaller than that of the shielding portion.

3. The method for manufacturing a semiconductor device according to claim 2, characterized in that, The sidewall film is formed using atomic layer deposition.

4. The method for manufacturing a semiconductor device according to claim 2, characterized in that, The sidewall membrane is titanium nitride.

5. The method for manufacturing a semiconductor device according to claim 1, characterized in that, In the process of forming the trench and the process of forming the opening, a portion of the mask forming layer is left on the second conductive semiconductor layer to form a release film.

6. The method for manufacturing a semiconductor device according to claim 3, characterized in that, In the process of patterning the ion implantation mask, the process of forming the mask forming layer includes the process of sequentially forming a release film, a diffusion barrier film and the mask forming layer on the second conductive semiconductor layer; The diffusion barrier film is a material that diffuses less chlorine compared to the stripping film.

7. The method for manufacturing a semiconductor device according to claim 6, characterized in that, The diffusion barrier film is made of silicon nitride.

8. The method for manufacturing a semiconductor device according to claim 5 or 6, characterized in that, After the process of forming the first conductive pillar and the second conductive pillar, there is also a process of etching the release film to remove the ion implantation mask.

9. The method for manufacturing a semiconductor device according to claim 8, characterized in that, The ion implantation mask is a first ion implantation mask; After the process of peeling off the first ion implantation mask, there is also a process of forming a second conductivity epitaxial layer on the second conductivity semiconductor layer; The process further includes a step of patterning a second ion implantation mask on the second conductive epitaxial layer, a step of ion implanting a first conductive impurity into the second conductive epitaxial layer through an opening in the second ion implantation mask to form the first conductive pillar and the second conductive pillar within the second conductive epitaxial layer, and a step of peeling off the second ion implantation mask. The first conductive pillar and the second conductive pillar formed on the second conductive semiconductor layer and the second conductive epitaxial layer are connected to form the superstructure.

10. The method for manufacturing a semiconductor device according to claim 1, characterized in that, The metal contained in the shielding portion includes at least tungsten.

11. A semiconductor device comprising a superstructure obtained by alternately and repeatedly arranging first conductive pillars and second conductive pillars along at least one direction, characterized in that... The first conductive pillar and the second conductive pillar are both made of silicon carbide. The spacing between the first conductive post and the second conductive post in the repeating direction is less than 0.4 μm. The maximum surface roughness of the interface between the first conductive pillar and the second conductive pillar is less than 30 nm.

12. The semiconductor device according to claim 11, characterized in that, The aspect ratio of the first conductive column and the second conductive column is 8.5 or higher.

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