MOS device and preparation method thereof

Abstract

The invention relates to the technical field of semiconductors, and provides an MOS device and a preparation method thereof, and the preparation method of the MOS device comprises the steps: providing an epitaxial wafer which comprises a substrate and an epitaxial layer located on the substrate, and the epitaxial layer is provided with a first doping type; a plurality of base regions arranged at intervals are formed in the epitaxial layer, the base regions have a second doping type, and the second doping type is opposite to the first doping type; forming a well region with a second doping type in each base region; forming a source region with a first doping type in each base region, wherein the source region is positioned on one side, close to the edge of the base region, of the well region and is spaced from the edge of the base region; an adjusting region is formed in the interval between the edges of the source region and the base region through two times of ion implantation, ions of the first time of ion implantation have a first doping type, ions of the second time of ion implantation have a second doping type, and the implantation dosage of the first time of ion implantation is larger than that of the second time of ion implantation.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically, to a MOS device and a method for fabricating the same. Background Technology

[0002] Metal-oxide-semiconductor field-effect transistors (MOSFETs) are key power electronic components widely used in various high-voltage and high-power applications, including but not limited to new energy vehicles and photovoltaic inverter systems. MOSFETs utilize the properties of semiconductor materials to control the flow of charge carriers between the source and drain by applying an external voltage, thereby realizing the switching function in a circuit.

[0003] Silicon carbide (SiC), as an outstanding representative of third-generation semiconductor materials, has gained widespread attention in the field of power electronics due to its excellent physical and electronic properties. SiC's wide bandgap, high breakdown electric field strength, high thermal conductivity, and high saturated electron drift velocity make it a good choice for manufacturing high-performance MOSFETs.

[0004] Balancing the switching performance and conduction capability of a device is a problem that needs to be solved in SiC-based MOSFETs.

[0005] The information disclosed above in the background section is only intended to enhance the understanding of the background art of the art described herein. Therefore, the background art may contain certain information that does not constitute prior art known to those skilled in the art in this country. Summary of the Invention

[0006] The main objective of this application is to provide a MOS device and its fabrication method to solve the problem of how to achieve a balance between the switching performance and conduction capability of MOS devices in the prior art.

[0007] To achieve the above objectives, according to one aspect of this application, a method for fabricating a MOS device is provided, comprising: providing an epitaxial wafer, the epitaxial wafer including a substrate and an epitaxial layer located on the substrate, the epitaxial layer having a first doping type; forming a plurality of spaced-apart base regions within the epitaxial layer, the base regions having a second doping type, the second doping type being opposite to the first doping type; forming a well region having the second doping type within each of the base regions; forming a source region having the first doping type within each of the base regions, the source region being located on the side of the well region near the edge of the base region and spaced from the edge of the base region; forming an adjustment region in the interval between the edge of the source region and the edge of the base region by two ion implantations, wherein the ions implanted in the first ion implantation have the first doping type, the ions implanted in the second ion implantation have the second doping type, and the implantation dose of the first ion implantation is greater than the implantation dose of the second ion implantation.

[0008] In some embodiments of this application, the implantation depth of the first ion implantation is greater than the implantation depth of the second ion implantation.

[0009] In some embodiments of this application, during the step of forming the adjustment region, the implantation depth of both ion implantations is less than the depth of the source region.

[0010] In some embodiments of this application, the two ion implantations include: performing the first ion implantation using an ion beam with a first energy; and performing the second ion implantation using an ion beam with a second energy; wherein the first energy is greater than the second energy.

[0011] In some embodiments of this application, the step of forming the base region includes: implanting ions having the second doping type into the epitaxial layer to form the base region; the implantation doses of the two ion implantations in the step of forming the adjustment region are both less than the implantation dose in the step of forming the base region.

[0012] In some embodiments of this application, the implantation dose of the first ion implantation is 2.5 × 10⁻⁶. 17 ±50%cm -3 The implantation dose for the second ion implantation is 1.5 × 10⁻⁶. 17 ±50%cm -3 .

[0013] In some embodiments of this application, the implantation depth of the first ion implantation is 0.05-0.2 μm, and the implantation depth of the second ion implantation is 0.05-0.15 μm.

[0014] In some embodiments of this application, the first energy is 10~30keV and the second energy is 10~25keV.

[0015] According to another aspect of this application, a MOS device is provided, which is fabricated by the fabrication method of the MOS device described in any of the above embodiments. The MOS device includes: a substrate; an epitaxial layer located on the substrate and having a first doping type; a plurality of base regions disposed at intervals within the epitaxial layer and having a second doping type, the second doping type being opposite to the first doping type; a well region and a source region located within the base regions, the source region being located on the side of the well region near the edge of the base region and spaced from the edge of the base region, the well region having the second doping type, and the source region having the first doping type; and a conditioning region located within the base regions and in the interval between the edge of the source region and the edge of the base region, the conditioning region simultaneously having dopant ions of the first doping type and dopant ions of the second doping type.

[0016] In some embodiments of this application, the adjustment region includes a first region and a second region, the second region being located on the side of the first region away from the substrate, and the doping concentration of dopant ions having the second doping type in the second region being greater than the doping concentration of dopant ions having the second doping type in the first region.

[0017] The beneficial effects of this application are as follows:

[0018] This application relates to the field of semiconductor technology and provides a MOS device and a method for fabricating the same. The method for fabricating the MOS device includes: providing an epitaxial wafer, the epitaxial wafer including a substrate and an epitaxial layer located on the substrate, the epitaxial layer having a first doping type; forming a plurality of spaced base regions in the epitaxial layer, the base regions having a second doping type, the second doping type being opposite to the first doping type; forming a well region having a second doping type in each base region; forming a source region having a first doping type in each base region, the source region being located on the side of the well region near the edge of the base region and spaced from the edge of the base region; forming a conditioning region in the space between the edge of the source region and the edge of the base region by two ion implantations, wherein the ions implanted in the first ion implantation have a first doping type, the ions implanted in the second ion implantation have a second doping type, and the implantation dose of the first ion implantation is greater than the implantation dose of the second ion implantation. The conditioning region is formed by two ion implantations into the gap between the source and base regions (i.e., the channel). The first ion implantation has a first doping type, namely N-type, which is opposite to the doping type of the base region. Therefore, the first ion implantation can reduce the doping concentration of the P-type base region, thereby helping to reduce the threshold voltage. The second ion implantation has a second doping type, namely P-type, which is opposite to the doping type of the first ion implantation but the same as the doping type of the base region. The implantation dose of the first ion implantation is greater than that of the second ion implantation, so the second ion implantation can adjust the doping concentration of the implanted region, improve the quality of the inversion layer, and reduce the field termination effect and Coulomb scattering. Thus, the embodiments of this application improve the channel mobility and maintain a reasonable threshold voltage by performing two ion implantations with different implantation doses and different doping types in the channel. The synergistic effect of the two achieves precise control of the threshold voltage and improvement of the channel mobility. Attached Figure Description

[0019] One or more embodiments are illustrated by way of example with corresponding figures in the accompanying drawings. These illustrative descriptions do not constitute a limitation on the embodiments. Unless otherwise stated, the figures in the drawings are not proportionally limited. To more clearly illustrate the technical solutions in the embodiments of this application or in conventional technology, the drawings used in the embodiments will be briefly described below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. In the drawings:

[0020] Figure 1 This is a schematic flowchart of a method for fabricating a MOS device according to an embodiment of this application;

[0021] Figures 2 to 13This is a schematic diagram of the fabrication process of a MOS device provided according to an embodiment of this application.

[0022] The above figures include the following reference numerals:

[0023] 1. Substrate; 2. Epitaxial layer; 3. Base region; 4. Well region; 5. Source region; 6. Adjustment region; 7. JFET region; 81. Source; 82. Ohmic metal layer; 83. Gate; 84. Gate oxide layer; 85. Gate active layer; 86. Gate dielectric layer; 87. Drain. Detailed Implementation

[0024] It should be noted that the following detailed descriptions are illustrative and intended to provide further explanation of this application. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains.

[0025] It should be noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the exemplary embodiments according to this application. As used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise. Furthermore, it should be understood that when the terms "comprising" and / or "including" are used in this specification, they indicate the presence of features, steps, operations, devices, components, and / or combinations thereof.

[0026] When a component "includes" another component, unless otherwise stated, other components are not excluded, and may be further included. Furthermore, when a component such as a layer, film, region, or plate is said to be "on / located" on another component, it can be "directly on" the other component (i.e., located on the surface of the other component with no other components between them), or there can be another component present in between. Additionally, when a component such as a layer, film, region, or plate is "directly located" on another component, or when a component such as a layer, film, region, or plate is located on the surface of another component, it indicates that no other components are located in between.

[0027] The term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can mean: A exists, A and B exist simultaneously, or B exists. Additionally, the character " / " in this text generally indicates that the preceding and following related objects have an "or" relationship.

[0028] The terms "first," "second," etc., are used to distinguish similar objects and should not be construed as indicating or implying relative importance or implicitly specifying the number, specific order, or primary or secondary relationship of the indicated technical features. It should be understood that such terms can be used interchangeably where appropriate to describe embodiments of this application.

[0029] When an element (such as a layer, film, region, or substrate) is described as being "on" another element, the element may be directly on the other element, or there may be an intermediate element. Furthermore, in the specification and claims, terms such as "mounted," "connected," "joined," and "fixed" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two elements or the interaction between two elements. Those skilled in the art can understand the specific meaning of the above terms in the embodiments of this application according to the specific circumstances.

[0030] The orientations or positional relationships indicated by terms such as "center," "longitudinal," "lateral," "length," "width," "thickness," "up," "down," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," and "circumferential" are based on the orientations or positional relationships shown in the accompanying drawings. They are only for the convenience of describing the embodiments of this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the embodiments of this application. Furthermore, in the accompanying drawings corresponding to the embodiments of this application, the thickness and area of ​​the layers are enlarged for better understanding and ease of description.

[0031] Furthermore, the reference to "embodiment" herein means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0032] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention.

[0033] Figure 1 This is a schematic flowchart illustrating a method for fabricating a MOS device according to an embodiment of this application, as shown below. Figure 1 As shown, the fabrication method of the MOS device includes the following steps S1 to S5:

[0034] Step S1: Provide an epitaxial wafer, which includes a substrate 1 and an epitaxial layer 2 located on the substrate 1, the epitaxial layer 2 having a first doping type.

[0035] For example, Figure 2This is a schematic diagram of the fabrication process of a MOS device according to an embodiment of this application. After step S1 is completed, a structure as shown is formed. Figure 2 The structure is shown. In step S1, the substrate 1 has the same first doping type as the epitaxial layer 2, for example, N-type doping. The resistivity of the substrate 1 can be 0.02±20% Ω·cm. The epitaxial layer 2 is formed by epitaxial growth technology. A drift region can be formed in the epitaxial layer 2, serving as the main breakdown layer of the device. The doping concentration of the epitaxial layer 2 is 1E+15~1E+16 cm⁻¹. -3 The thickness is set according to product requirements. For example, in a MOS device with a withstand voltage requirement of 1200V, the thickness of its epitaxial layer 2 is 9~11μm, and in a MOS device with a withstand voltage requirement of 650V, the thickness of its epitaxial layer 2 is 5~7μm.

[0036] Step S2: A plurality of spaced base regions 3 are formed in the epitaxial layer 2. The base regions 3 have a second doping type, which is the opposite of the first doping type.

[0037] For example, Figure 3 This is a schematic diagram of the fabrication process of another MOS device according to an embodiment of this application. After completing step S2, a structure is formed as shown below. Figure 3 The structure shown is as follows. In step S2, the base region 3 is formed by ion implantation into the epitaxial layer 2. The implanted element is a dopant of the second doping type, which is opposite to the first doping element. For example, it is a p-type dopant element, aluminum (Al), and the implantation dose is 1E+17±50%cm. -3 The implantation depth is 0.7~0.8μm. In the following embodiments, the case where the first doping type is N-type doping and the second doping type is P-type doping is used as an example for illustration.

[0038] Step S3: Form a well region 4 with a second doping type in each base region 3.

[0039] For example, Figure 4 This is a schematic diagram of the fabrication process of another MOS device according to an embodiment of this application. After completing step S3, a structure is formed as shown below. Figure 4 The structure shown is as follows. In step S3, the well region 4 is formed by ion implantation into the base region 3. The implanted element is a second-type dopant, such as the p-type dopant aluminum (Al). The doping concentration of the well region 4 is greater than that of the base region 3, and its implantation dose is 1E+19±50%cm³. -3 The injection depth is 0.5~0.8μm.

[0040] Step S4: Form a source region 5 with a first doping type in each base region 3. The source region 5 is located on the side of the well region 4 near the edge of the base region 3 and is spaced from the edge of the base region 3.

[0041] For example, Figure 5 This is a schematic diagram of the fabrication process of another MOS device according to an embodiment of this application. After completing step S4, a structure is formed as shown below. Figure 5 The structure is shown. In step S4, the source region 5 is formed by ion implantation into the base region 3. The implanted element is an element of the first doping type, such as an N-type dopant, and the implantation dose is 1E+19~1E+20 cm⁻¹. -3 The injection depth is 0.2~0.3μm. The edges of the source region 5 and the base region 3 are spaced apart. When the MOS device is operating, the space between the source region 5 and the base region 3 can serve as a channel for carrier transport, with a channel width of 0.3~0.6μm. In the embodiments of this application, the injection depth of the well region 4 is greater than the injection depth of the source region 5, which is beneficial for improving the avalanche capability of the device.

[0042] Step S5: An adjustment region 6 is formed in the interval between the source region 5 and the base region 3 by two ion implantations, wherein the ions implanted in the first ion implantation have a first doping type, the ions implanted in the second ion implantation have a second doping type, and the implantation dose of the first ion implantation is greater than the implantation dose of the second ion implantation.

[0043] For example, Figure 7 This is a schematic diagram of the fabrication process of another MOS device according to an embodiment of this application. After completing step S5, a structure is formed as shown below. Figure 7 The structure is shown. In step S5, the adjustment region 6 is formed by two ion implantations into the gap (i.e., the channel) between the source region 5 and the base region 3. The first ion implantation has a first doping type, i.e., N-type, which is opposite to the doping type of the base region 3. Therefore, the first ion implantation can reduce the doping concentration of the P-type base region 3, thereby helping to reduce the threshold voltage. The second ion implantation has a second doping type, i.e., P-type, which is opposite to the doping type of the first ion implantation but the same as the doping type of the base region 3. The implantation dose of the first ion implantation is greater than that of the second ion implantation. Therefore, the second ion implantation can adjust the doping concentration of the implanted region, improve the quality of the inversion layer, and reduce the field termination effect and Coulomb scattering. Thus, the embodiments of this application improve the channel mobility and maintain a reasonable threshold voltage by performing two ion implantations with different implantation doses and different doping types in the channel. The synergistic effect of the two achieves precise control of the threshold voltage and improvement of the channel mobility.

[0044] In some embodiments of this application, in step S5 above, the implantation depth of the first ion implantation is greater than that of the second ion implantation. Thus, the implantation depth of the first doped ion (N-type doped ion) of the first ion implantation is relatively deeper, enabling it to provide enough free electrons to recombine with holes in the base region 3, thereby reducing the acceptor doping effect. The implantation depth of the second doped ion (P-type doped ion) of the second ion implantation is relatively shallower, thereby adjusting the Fermi level at the surface by locally increasing the P-type doping concentration, making it closer to the valence band top, thereby reducing the trapping of electrons by the interface states and suppressing the Coulomb scattering effect, thereby improving the channel mobility and improving the quality of the inversion layer.

[0045] In some embodiments of this application, in the step of forming the adjustment region 6 (i.e., step S5 above), the implantation depth of both ion implantations is less than the depth of the source region 5. That is, the depth of the adjustment region 6 formed in this step is less than the depth of the source region 5. Since the main purpose of designing the adjustment region 6 is to optimize the carrier distribution in the channel to improve important parameters such as threshold voltage and mobility, if the implantation depth of the adjustment region 6 is too deep, its impact on the channel will exceed the expected range, making it difficult to achieve precise performance control. In the embodiments of this application, setting the depth of the adjustment region 6 to be less than the depth of the source region 5 can ensure that the adjustment effect is concentrated in the channel region without affecting the deeper drift region or other structures, thereby maintaining good on-resistance and switching characteristics.

[0046] In some embodiments of this application, in step S5 above, the implantation depth of both the first and second ion implantations is 0.05-0.2 μm, exemplarily 0.05 μm, 0.06 μm, 0.07 μm, 0.08 μm, 0.09 μm, 0.1 μm, 0.11 μm, 0.12 μm, 0.13 μm, 0.14 μm, 0.15 μm, 0.16 μm, and 0.17 μm. The implantation depth of the second ion implantation is 0.05~0.15μm, exemplarily 0.05μm, 0.06μm, 0.07μm, 0.08μm, 0.09μm, 0.1μm, 0.11μm, 0.12μm, 0.13μm, 0.14μm, 0.15μm, or any value within the above range.

[0047] In some embodiments of this application, the two ion implantations in step S5 above include: performing a first ion implantation using an ion beam with a first energy; and performing a second ion implantation using an ion beam with a second energy; wherein the first energy is greater than the second energy. Using an ion beam with relatively higher energy during the first ion implantation allows for a relatively greater implantation depth, satisfying the design requirement of a wider ion coverage area for the first doping type. Conversely, using an ion beam with relatively lower energy during the second ion implantation allows for a relatively smaller implantation depth, satisfying the design requirement of using ions of the second doping type for surface conditioning.

[0048] In some embodiments of this application, in step S5 above, the first energy is 10~30keV, exemplarily 10keV, 15keV, 20keV, 25keV, 30keV or any other value within the above range, and the second energy is 10~25keV, exemplarily 10keV, 15keV, 20keV, 25keV or any other value within the above range.

[0049] In some embodiments of this application, the step of forming the base region 3 (i.e., step S2 above) includes: implanting ions with a second doping type into the epitaxial layer 2 to form the base region 3; wherein, the implantation dose of the two ion implantations in the step of forming the adjustment region 6 (i.e., step S5 above) is less than the implantation dose in the step of forming the base region 3.

[0050] In some embodiments of this application, in step S5 above, the implantation dose for the first ion implantation is 2.5 × 10⁻⁶. 17 ±50%cm -3 The implantation dose for the second ion implantation was 1.5 × 10⁻⁶. 17 ±50%cm -3 It should be understood that the implantation dose in the adjustment region 6 is of a different order of magnitude than the implantation dose in the base region 3. Therefore, the two ion implantations in the adjustment region 6 will not change its original doping type, but will adjust the performance of the region through a small amount of doping.

[0051] In embodiments of this application, between steps S4 and S5 described above, a JFET region 7 is further formed between adjacent base regions 3, wherein the JFET region 7 is located on the side of the source region 5 away from the well region 4. Exemplarily, Figure 6 This is a schematic diagram of the fabrication process of another MOS device according to an embodiment of this application. After completing the above steps, a structure is formed as shown below. Figure 6The structure shown is formed by ion implantation into the region between adjacent base regions 3 in the epitaxial layer 2. The implanted element is a first-type dopant, such as an N-type dopant, and the implantation dose is 1E+18±50%cm. -3 The implantation depth is 0.8~0.9μm, and the implanted elements are activated by annealing after implantation.

[0052] In the embodiments of this application, such as Figures 8 to 10 As shown, the fabrication method of this MOS device may further include sequentially forming a gate oxide layer 84, a gate active layer, and a gate dielectric layer 86 on the side of the JFET region 7 facing away from the substrate 1. Exemplarily, after completing the above steps, a MOS device is formed as shown... Figure 13 In the structure shown, the gate oxide layer 84 is made of an insulating material, such as silicon dioxide (SiO2), and is grown by thermal oxidation or chemical vapor deposition (CVD) processes, with a thickness of 300-800 Å. The gate active layer 85 is made of a semiconductor material, such as polysilicon, and is grown by CVD processes, with a thickness of 2000-8000 Å. After growing the entire gate oxide layer 84 and gate active layer 85, the desired pattern can be formed by etching processes. The gate dielectric layer 86 is made of an insulating dielectric material, such as SiO2, and is formed by deposition followed by etching, with a thickness of 600-1000 nm. The gate dielectric layer 86 covers the gate oxide layer 84 and the gate active layer 85, and can protect them in subsequent steps.

[0053] In the embodiments of this application, such as Figure 12 and 13 As shown, the fabrication method of this MOS device may further include forming a source 81, a gate 83, and a drain 87. The source 81 and gate 83 can be formed using a process of full-layer deposition followed by etching to form the desired pattern, and both can be formed in a single patterning process, thus saving process steps. Before forming the gate 83, an opening is first formed in the gate dielectric layer 86. (As shown...) Figure 11 As shown, before forming the source 81, an ohmic metal layer 82 can be formed first to reduce the contact resistance between the source 81 and the epitaxial layer 2. The ohmic metal layer 82 covers the well region 4 and part of the source region 5.

[0054] Based on the same concept, embodiments of this application also provide a MOS device, which is fabricated using the fabrication method of any of the above embodiments of the MOS device, such as... Figure 13As shown, the MOS device includes: a substrate 1, an epitaxial layer 2, multiple base regions 3, a well region 4, and a source region 5. The epitaxial layer 2 is located on the substrate 1 and has a first doping type; the multiple base regions 3 are spaced apart within the epitaxial layer 2 and have a second doping type, the second doping type being opposite to the first doping type; the well region 4 and the source region 5 are located within the base regions 3, with the source region 5 located on the side of the well region 4 near the edge of the base region 3 and spaced apart from the edge of the base region 3; the well region 4 has the second doping type, and the source region 5 has the first doping type; a regulating region 6 is located within the base region 3 and in the space between the source region 5 and the edge of the base region 3, and the regulating region 6 simultaneously contains dopant ions of both the first and second doping types. The embodiments of this application achieve a higher performance MOS device by doping the channel with two different types of dopant ions.

[0055] Upon testing, the threshold voltage control accuracy of the MOS device in this application can be optimized from ±0.3V to ±0.1V compared to conventional MOS devices, the channel mobility can be increased from 5~30 cm² / V·s to 40~70 cm² / V·s compared to conventional MOS devices, and the interface state density can be increased from greater than 1×10¹² c in conventional MOS devices. ²e ¹Reduced to less than 5 × 10¹¹ c ²e ¹, the batch-to-batch standard deviation of the threshold voltage is reduced from greater than 0.3V in conventional MOS device production to less than 0.1V. It can be seen that the MOS device in this application has better conduction performance and reliability compared to conventional MOS devices.

[0056] In some embodiments of this application, the adjustment region 6 includes a first region and a second region. The second region is located on the side of the first region facing away from the substrate. The doping concentration of dopant ions with a second doping type in the second region is greater than the doping concentration of dopant ions with a second doping type in the first region. Carriers with a first doping type (N-type) in the first region recombine with holes in the base region 3, thereby reducing the acceptor doping effect. Thus, the P-type doping concentration can be locally increased through the shallower second region (P-type), thereby adjusting the Fermi level at the surface to be closer to the valence band top. This reduces the trapping of electrons by interface states and suppresses the Coulomb scattering effect, thereby improving channel mobility and the quality of the inversion layer.

[0057] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0058] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A method for fabricating a MOS device, characterized in that, include: An epitaxial wafer is provided, the epitaxial wafer comprising a substrate and an epitaxial layer disposed on the substrate, the epitaxial layer having a first doping type; A plurality of spaced base regions are formed within the epitaxial layer, and the base regions have a second doping type, which is the opposite of the first doping type. A well region having the second doping type is formed within each of the base regions; A source region having the first doping type is formed within each of the base regions, the source region being located on the side of the well region near the edge of the base region and spaced from the edge of the base region; An adjustment region is formed by two ion implantations in the interval between the edge of the source region and the base region, wherein the ions implanted in the first ion implantation have the first doping type, the ions implanted in the second ion implantation have the second doping type, and the implantation dose of the first ion implantation is greater than the implantation dose of the second ion implantation.

2. The method for fabricating a MOS device according to claim 1, characterized in that, The implantation depth of the first ion implantation is greater than the implantation depth of the second ion implantation.

3. The method for fabricating a MOS device according to claim 1, characterized in that, In the step of forming the conditioning region, the implantation depth of both ion implantations is less than the depth of the source region.

4. The method for fabricating a MOS device according to claim 1, characterized in that, The two ion implantations include: The first ion implantation is performed using an ion beam with a first energy. The second ion implantation is performed using an ion beam with a second energy. Wherein, the first energy is greater than the second energy.

5. The method for fabricating a MOS device according to claim 1, characterized in that, The step of forming the base region includes: implanting ions having the second doping type into the epitaxial layer to form the base region; In the step of forming the conditioning region, the implantation dose of the two ion implantations is less than the implantation dose in the step of forming the base region.

6. The method for fabricating a MOS device according to claim 1, wherein the implantation dose of the first ion implantation is 2.5 × 10⁻⁶. 17 ±50%cm -3 The implantation dose for the second ion implantation is 1.5 × 10⁻⁶. 17 ±50%cm -3 .

7. The method for fabricating a MOS device according to claim 2, characterized in that, The first ion implantation has an implantation depth of 0.05-0.2 μm, and the second ion implantation has an implantation depth of 0.05-0.15 μm.

8. The method for fabricating a MOS device according to claim 4, characterized in that, The first energy is 10~30keV, and the second energy is 10~25keV.

9. A MOS device, characterized in that, The MOS device is fabricated by the method for fabricating a MOS device according to any one of claims 1 to 8, and the MOS device comprises: Substrate; An epitaxial layer, located on the substrate and having a first doping type; Multiple base regions are spaced apart within the epitaxial layer and have a second doping type, the second doping type being the opposite of the first doping type; A well region and a source region are located within the base region. The source region is located on the side of the well region near the edge of the base region and is spaced from the edge of the base region. The well region has the second doping type, and the source region has the first doping type. The adjustment region is located within the base region and in the interval between the source region and the edge of the base region, and the adjustment region simultaneously contains dopant ions of the first doping type and dopant ions of the second doping type.

10. The MOS device according to claim 9, characterized in that, The adjustment region includes a first region and a second region, the second region being located on the side of the first region away from the substrate, and the doping concentration of dopant ions with the second doping type in the second region being greater than the doping concentration of dopant ions with the second doping type in the first region.

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