Semiconductor device and manufacturing method thereof
By forming gate oxide layers of varying thicknesses in high-voltage integrated circuits and creating sloping steps at the junctions, the problem of etching residue at the gate oxide junctions was solved, thus improving device performance.
Patent Information
- Application Number
- CN202511792792.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-01
- Publication Date
- 2026-03-27
AI Technical Summary
In high-voltage integrated circuits, the steps at the gate oxide interface formed by the dual-gate process are deep or steep, resulting in polysilicon etching residue and sidewall etching residue, which affect device performance.
A first gate oxide layer and a second gate oxide layer of different thicknesses are formed on the substrate, and a dielectric layer is formed at the junction. Part of the dielectric layer is removed by etch-back, so that the step appears as a slope and the residue is reduced.
By creating gentle, sloping steps, polysilicon etching and sidewall etching residues are reduced, improving device performance.
Smart Images
Figure CN121751719A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor technology, and more specifically to a semiconductor device and a method for manufacturing the same. Background Technology
[0002] High-voltage integrated circuits are widely used in flat panel display drivers, power management, and power devices. Different applications require different gate voltages, and the gate oxide layer thickness varies for high-voltage devices with different voltage withstand levels. Typically, the gate oxide layer thickness is proportional to the gate voltage; if a higher voltage withstand is required, the corresponding gate oxide layer thickness should be increased proportionally. Therefore, to meet the gate voltage withstand requirements of high- and low-voltage devices in the circuit, gate oxide layers of different thicknesses need to be fabricated.
[0003] Typically, a dual-gate process is used to form a gate oxide layer that can adapt to different gate voltages. However, the formation of a dual gate results in the formation of gate oxide interfaces on the shallow trench isolation structure for different types of devices, i.e., the formation of steps. When these steps are deep or steep, they may cause polysilicon etching residues, sidewall etching residues, etc. These residues can affect the performance of the devices, thereby affecting the normal operation of the devices or circuits. Summary of the Invention
[0004] The summary section introduces a series of simplified concepts, which will be further explained in detail in the detailed description section. This summary section is not intended to limit the key and essential technical features of the claimed technical solution, nor is it intended to determine the scope of protection of the claimed technical solution.
[0005] To address the existing problems, the first aspect of this application provides a method for manufacturing a semiconductor device, the method comprising: A substrate is provided in which a shallow trench isolation structure is formed; A gate oxide layer is formed on the substrate, the gate oxide layer covering the surface of the substrate and the surface of the shallow trench isolation structure; A patterned mask layer is formed on the gate oxide material layer. The gate oxide material layer covered by the patterned mask layer serves as a first gate oxide layer, and the gate oxide material layer exposed by etching with the patterned mask layer as a mask forms a second gate oxide layer. The first gate oxide layer and the second gate oxide layer are connected. A dielectric layer covering the second gate oxide layer and the mask layer is formed using a deposition process; The dielectric layer is etched back to remove the dielectric layer on the mask layer and part of the second gate oxide layer while retaining part of the dielectric layer at the junction of the first gate oxide layer and the second gate oxide layer, so that the step at the junction appears as a slope. Remove the remaining mask layer; A first gate is formed on the first gate oxide layer and a second gate is formed on the second gate oxide layer.
[0006] In one embodiment, the method further includes: after forming the second gate oxide layer and before forming the dielectric layer, removing a portion of the mask layer to reduce the thickness of the mask layer. In one embodiment, the temperature range for forming the dielectric layer using a deposition process is 20°C to 200°C.
[0007] In one embodiment, forming a first gate on the first gate oxide layer and forming a second gate on the second gate oxide layer includes: A gate material layer is formed to cover the first gate oxide layer, the dielectric layer, and the second gate oxide layer; A patterned photoresist layer is formed on the gate material layer; Using a patterned photoresist layer as a mask, the gate material layer is etched using an etching process to form a first gate on the first gate oxide layer and a second gate on the second gate oxide layer. The first gate and the second gate are respectively located on both sides of the shallow trench isolation structure.
[0008] In one embodiment, the deposition process for forming the dielectric layer includes atomic layer deposition or chemical vapor deposition.
[0009] In one embodiment, the step is located above the shallow trench isolation structure.
[0010] In one embodiment, the dielectric layer is made of silicon oxide, and the thickness of the dielectric layer ranges from 5 nm to 500 nm.
[0011] In one embodiment, the gate is deposited at a temperature higher than that of the dielectric layer, and the remaining dielectric layer is densified during the formation of the gate.
[0012] A second aspect of this application also provides a semiconductor device, the semiconductor device comprising: A substrate in which a shallow trench isolation structure is formed; A first gate oxide layer is located on a portion of the substrate; A second gate oxide layer is located on another portion of the substrate, and the second gate oxide layer is connected to the first gate oxide layer; The dielectric layer is located at the junction of the first gate oxide layer and the second gate oxide layer, so that the step at the junction appears as a slope; The first gate is located on the first gate oxide layer; The second gate is located on the second gate oxide layer.
[0013] In one embodiment, the step is located above the shallow trench isolation structure; the thickness of the first gate oxide layer is greater than the thickness of the second gate oxide layer.
[0014] The semiconductor device and manufacturing method of the present application embodiment form a first gate oxide layer and a second gate oxide layer with different heights on a substrate. A dielectric layer is formed on the first gate oxide layer and the second gate oxide layer. Part of the dielectric layer is removed by etching back, and the dielectric layer at the junction of the first gate oxide layer and the second gate oxide layer is retained, so that the step at the junction presents a gentle slope morphology, thereby reducing the residue formed at the step in subsequent processes and improving device performance. Attached Figure Description
[0015] The following drawings, which are incorporated herein by reference and are used to understand this application, illustrate embodiments of the invention and their descriptions to explain the principles of the invention.
[0016] In the attached image: Figures 1A-1B A partial cross-sectional schematic diagram of a semiconductor device in the related art is shown; Figure 2 A flowchart illustrating a method for manufacturing a first semiconductor device according to a specific embodiment of this application is shown; Figures 3A-3I This diagram shows a cross-sectional view of a semiconductor device obtained by sequentially implementing a method for manufacturing a semiconductor device according to a specific embodiment of this application. Detailed Implementation
[0017] The present application will now be described more fully with reference to the accompanying drawings, in which embodiments of the present application are illustrated. However, the present application can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of the present application to those skilled in the art. In the drawings, for clarity, the dimensions and relative dimensions of layers and regions may be exaggerated. The same reference numerals denote the same elements throughout.
[0018] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this application, the first element, component, area, layer, or portion discussed below may be referred to as the second element, component, area, layer, or portion.
[0019] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “under” the other element or feature will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.
[0020] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.
[0021] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art. It will also be understood that terms as defined in commonly used dictionaries shall be interpreted as having a meaning consistent with their meaning in the relevant field and / or the context of this specification, and not as in an ideal or overly formal sense, unless expressly defined herein.
[0022] To fully understand this application, detailed steps and structures will be presented in the following description to illustrate the technical solutions proposed in this application. Preferred embodiments of this application are described in detail below; however, in addition to these detailed descriptions, this application may have other implementation methods.
[0023] High-voltage integrated circuits are widely used in flat panel display drivers, power management, and power devices. Different applications require different gate voltages, and the gate oxide layer thickness varies depending on the voltage withstand level of the high-voltage device. For example, when the gate voltage is 5V, the gate oxide layer thickness is typically between 10nm and 15nm; for higher voltage withstand levels, the gate oxide layer thickness should be increased proportionally.
[0024] To meet the gate withstand voltage requirements of high- and low-voltage devices in the circuit, such as Figures 1A-1B As shown, two or more gate oxide layers 10 of different thicknesses need to be fabricated. When fabricating the gate oxide layer 10 of these devices, a dual-gate (DG) process is typically used. This process results in the formation of gate oxide boundaries on the shallow trench isolation (STI) structure 20 for different types of devices, creating steps at the gate oxide boundaries. When these steps are deep or steep, it may cause problems such as... Figure 1B The polysilicon 30 etching residues and sidewall etching residues shown can affect the performance of the device, thereby affecting the normal operation of the device or circuit.
[0025] Therefore, in view of the aforementioned technical problems, this application proposes a method for manufacturing a semiconductor device, such as... Figure 2 As shown, it mainly includes the following steps: Step S110: Provide a substrate in which a shallow trench isolation structure is formed; Step S120: A gate oxide material layer is formed on the substrate, the gate oxide material layer covering the surface of the substrate and the surface of the shallow trench isolation structure; Step S130: A patterned mask layer is formed on the gate oxide material layer. The gate oxide material layer covered by the patterned mask layer serves as a first gate oxide layer, and the gate oxide material layer exposed by etching with the patterned mask layer as a mask forms a second gate oxide layer. The first gate oxide layer and the second gate oxide layer are connected. Step S140: A dielectric layer covering the second gate oxide layer and the mask layer is formed using a deposition process; Step S150: Etch back the dielectric layer to remove the dielectric layer on the mask layer and part of the second gate oxide layer while retaining part of the dielectric layer at the junction of the first gate oxide layer and the second gate oxide layer, so that the step at the junction appears as a slope; Step S160: Remove the remaining mask layer; Step S170: A first gate is formed on the first gate oxide layer and a second gate is formed on the second gate oxide layer.
[0026] The semiconductor device manufacturing method of this application embodiment forms a first gate oxide layer and a second gate oxide layer of different thicknesses on a substrate, forms a dielectric layer on the first gate oxide layer and the second gate oxide layer, and removes part of the dielectric layer by etching back, retaining the dielectric layer at the junction of the first gate oxide layer and the second gate oxide layer, so that the step at the junction presents a gentle slope morphology, thereby reducing the residue formed at the junction when forming the first gate and the second gate, and improving device performance.
[0027] Example 1 Below, for reference Figure 2 , Figures 3A to 3I The method for manufacturing the semiconductor device of this application is described in detail, wherein... Figure 2 A flowchart illustrating a method for manufacturing a semiconductor device according to a specific embodiment of this application is shown; Figures 3A-3I The diagram shows a cross-sectional view of a semiconductor device obtained by sequentially implementing a method for manufacturing a semiconductor device according to a specific embodiment of this application.
[0028] For example, the method for manufacturing a semiconductor device according to this application includes the following steps: First, such as Figure 2 As shown, step S110 is performed, in which a substrate is provided, wherein a shallow trench isolation structure is formed in the substrate.
[0029] For example, such as Figure 3A As shown, a trench mask layer (not shown) with predefined trench positions and sizes is formed on the substrate 200. The substrate 200 is etched using the trench mask layer as a mask to form shallow trenches in the substrate 200. The shallow trenches are then filled to form a shallow trench isolation structure 201.
[0030] For example, the substrate 200 can be any suitable semiconductor substrate, such as a silicon substrate, or at least one of the following materials: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP or other III / V compound semiconductors, including multilayer structures composed of these semiconductor materials, or silicon on insulator (SOI), silicon on insulator (SSOI), silicon on insulator (S-SiGeOI), silicon on insulator (SiGeOI), and germanium on insulator (GeOI), or it can be a double-side polished wafer (DSP), or a ceramic substrate such as alumina, a quartz or glass substrate, etc.
[0031] Then, continue as follows Figure 2 As shown, step S120 is performed to form a gate oxide material layer on the substrate, the gate oxide material layer covering the surface of the substrate and the surface of the shallow trench isolation structure.
[0032] For example, such as Figure 3B As shown, a gate oxide material layer 202 is formed on the substrate 200 by thermal oxidation or deposition process. The gate oxide material layer 202 covers the surface of the substrate 200 and the surface of the shallow trench structure 201. The material of the gate oxide material layer 202 may include, but is not limited to, silicon oxide, silicon oxynitride, and high-k dielectric.
[0033] Then, continue as follows Figure 2 As shown, in step 130, a patterned mask layer is formed on the gate oxide material layer. The gate oxide material layer covered by the patterned mask layer serves as a first gate oxide layer, and the gate oxide material layer exposed by etching with the patterned mask layer as a mask forms a second gate oxide layer. The first gate oxide layer and the second gate oxide layer are connected, and a step is formed at the connection between the first gate oxide layer and the second gate oxide layer.
[0034] For example, such as Figure 3C As shown, a mask layer 203 is formed on the gate oxide material layer 202 using a spin coating or deposition process. This mask layer 203 may include, but is not limited to, a photoresist layer; then, as... Figure 3D As shown, the mask layer 203 is patterned to form a patterned mask layer 204. This patterned mask layer 204 defines the position, shape, and dimensions of the subsequently formed first and second gate oxide layers. The gate oxide material layer covered by the patterned mask layer 204 serves as the first gate oxide layer 205; then as... Figure 3EAs shown, a second gate oxide layer 206 is formed by etching the exposed gate oxide material layer using a patterned mask layer 204 as a mask. The first gate oxide layer 205 and the second gate oxide layer 206 are connected to form a dual gate. Since the second gate oxide layer 206 is formed by etching the gate oxide material layer 202, its thickness is smaller than that of the gate oxide material layer, that is, smaller than that of the first gate oxide layer 205. In other words, the thickness of the first gate oxide layer is greater than that of the second gate oxide layer, so a step can be formed between the first gate oxide layer 205 and the second gate oxide layer 206. For example, the step is located above the shallow trench isolation structure 201. It is worth mentioning that the step is approximately a right-angle step at this time.
[0035] Next, for example, part of the patterned mask layer is removed to reduce the thickness of the mask layer, which facilitates the formation of a gentler slope at the step when the dielectric layer is subsequently formed.
[0036] Then, continue as follows Figure 2 As shown, step S140 is performed, in which a dielectric layer covering the second gate oxide layer and the mask layer is formed using a deposition process.
[0037] For example, such as Figure 3F As shown, the dielectric layer 207 can be formed using a deposition method with a relatively low deposition temperature, for example, a deposition temperature in the range of 20°C to 200°C. Specifically, the temperature range can be in the range of 50°C to 200°C, or even in the range of 100°C to 150°C. The above temperature range is only an example, and other suitable temperatures can also be applied to this application. The dielectric layer 207 can be formed in the range of 20°C to 200°C using atomic layer deposition or chemical vapor deposition processes. The suitable temperature range may vary for different deposition processes. The material of the dielectric layer 207 includes, but is not limited to, silicon oxide. The dielectric layer can be silicon oxide formed by low-temperature chemical vapor deposition using tetraethyl orthosilicate (TES) as a precursor, or silicon oxide formed by low-temperature atomic layer deposition using a combination of aminosilane and ozone as a precursor.
[0038] By depositing a dielectric layer 207, such as a low-temperature silicon oxide layer, the steepness of the steps is reduced to create a gentle slope at the steps. Exemplarily, the thickness of the dielectric layer ranges from 5 nm to 500 nm, for example, thicknesses of 5 nm, 20 nm, 50 nm, 150 nm, 200 nm, 300 nm, 400 nm, or 500 nm. It is worth noting that at lower temperatures, a dielectric layer, such as silicon oxide, is deposited to obtain a low-density silicon oxide layer. During the deposition process, the deposited ions soft-land, and under low-temperature conditions, the particles still have preferential migration ability on the substrate surface. They preferentially roll to fill the root or corner of the step, forming a microscopic rounded seed layer. The low-temperature silicon oxide network behaves like viscous glass. When the thickness is greater than a certain value (e.g., 20 nm), the internal tensile stress drives the surface to undergo viscous flow at the nanoscale, which increases the radius of curvature at the sharp corners, equivalent to nanoscale self-leveling. Therefore, the top of the step is rounded and the root is filled during the deposition stage, thereby reducing the steepness of the right-angle step and turning it into a gentle slope.
[0039] Then, continue as follows Figure 2 As shown, step S150 is performed to etch the dielectric layer back to remove the dielectric layer on the mask layer and part of the second gate oxide layer while retaining part of the dielectric layer at the step, and the remaining dielectric layer makes the step appear as a slope.
[0040] For example, a maskless etch-back process is employed, which involves global, isotropic etching across the entire wafer surface without the need for additional photomasks to define the pattern. Optionally, wet etching, dry etching, or a combination thereof is used to etch the dielectric layer without a mask, prioritizing the removal of protruding portions. Specifically, the dielectric layer on the first gate oxide layer is removed, and the dielectric layer on the second gate oxide layer is partially removed. The corners of the sidewalls are rounded before the dielectric layer is deposited, creating a gentle slope at the junction of the first and second gate oxide layers. This disperses the vertical drop caused by the original etching onto a longer slope, ultimately retaining only a portion of the dielectric layer at the step sidewalls. The remaining dielectric layer naturally forms a smoothly transitioned slope profile at the step, resulting in a shape resembling... Figure 3G The structure shown.
[0041] Then, continue as follows Figure 2 As shown, step S160 is performed to remove the remaining mask layer.
[0042] For example, a process combining dry ashing and wet stripping is used to remove the remaining mask layer. After removing the remaining mask layer, the substrate surface is cleaned to remove impurities and photoresist residue, thus cleaning the substrate surface and forming a substrate as shown in the image. Figure 3H The structure shown.
[0043] Next, step S170 is performed to form a first gate on the first gate oxide layer and a second gate on the second gate oxide layer.
[0044] Exemplarily, the first gate 208 and the second gate 209 are formed through the following steps: First, a gate material layer is formed, covering the first gate oxide layer 205, the second gate oxide layer 206, and the remaining dielectric layer 207. This material is preferably polysilicon or may be other suitable materials for the gate, and can be formed by a low-pressure chemical vapor deposition process. This deposition process is typically performed at a relatively high temperature (e.g., 550°C to 650°C) to ensure that the polysilicon has good crystal quality and conductivity. Photoresist is coated on the polysilicon layer, and a patterned photoresist layer is formed using photolithography. This pattern defines the position and size of the first gate 208 and the second gate 209. Using the patterned photoresist layer as a mask, the gate material layer is etched using an etching process, such as... Figure 3I As shown, a first gate 208 is formed on the first gate oxide layer 205, and a second gate 209 is formed on the second gate oxide layer 206. Specifically, for example, the exposed polysilicon layer is selectively etched using a dry etching process (e.g., plasma etching based on chlorine- or bromine-based chemical gases) until the surface of the underlying gate oxide layer is exposed. Optionally, the gate voltage of the first gate 208 is higher than the gate voltage of the second gate 209.
[0045] During the deposition of the first and second gates, the deposition temperature is higher than that of the dielectric layer. The atoms and bonds in the internal silicon-oxygen network are activated, rearranged, and relaxed, tending towards a more stable and compact stacking state. This process effectively reduces the micropores and dangling bonds inside the dielectric layer, causing a slight shrinkage in its volume and a significant increase in its mass density. After this heat treatment, the dielectric layer 207 transforms from its initial loose state into a dense and robust silicon oxide layer. This transformation directly leads to an improvement in its chemical stability.
[0046] Furthermore, since the remaining dielectric layer forms a slope transition at the step, eliminating the original right-angle "dead angle," it makes it less likely for gate material residue to form at the step, eliminating potential leakage paths caused by residue, and improving various electrical failure problems caused by gate material residue. This concludes the description of the key steps in the semiconductor device manufacturing method of this application. A complete semiconductor device manufacturing method may include other steps, which will not be elaborated here. It is worth mentioning that the order of the above steps can be adjusted without conflict.
[0047] The semiconductor device manufacturing method of this application embodiment forms a first gate oxide layer and a second gate oxide layer of different thicknesses on a substrate, forms a dielectric layer on the first gate oxide layer and the second gate oxide layer, forms a low-temperature dielectric layer using a low-temperature deposition process, and removes part of the dielectric layer by etching back, retaining the dielectric layer at the junction of the first gate oxide layer and the second gate oxide layer, so that the step at the junction presents a gentle slope morphology, thereby reducing the residue formed at the step when forming the first gate and the second gate, and improving device performance.
[0048] Example 2 This application also provides a semiconductor device that can be prepared by the manufacturing method of the semiconductor device described in the foregoing embodiments. Some details of this embodiment can be found in the relevant descriptions of the methods above, and will not be repeated here.
[0049] Specifically, such as Figure 3I As shown, the semiconductor device includes: a substrate 200, a shallow trench isolation structure 201, a first gate oxide layer 205, a second gate oxide layer 206, a dielectric layer 207, a first gate 208, and a second gate 209; the shallow trench isolation structure 201 is located in the substrate 200, the first gate oxide layer 205 is located on a portion of the substrate 200, the second gate oxide layer 206 is located on another portion of the substrate 200, and the second gate oxide layer 206 is connected to the first gate oxide layer 205; the dielectric layer 207 is located at the junction of the first gate oxide layer 205 and the second gate oxide layer 206, so that the step at the junction presents as a slope; the first gate 208 is located on the first gate oxide layer 205, and the second gate 209 is located on the second gate oxide layer 206.
[0050] In some examples, the step is located above the shallow trench isolation structure; the thickness of the first gate oxide layer is greater than the thickness of the second gate oxide layer. Optionally, the gate voltage of the first gate is higher than the gate voltage of the second gate.
[0051] Since the semiconductor device of this application is manufactured using the aforementioned semiconductor device manufacturing method, it also possesses the beneficial effects of the aforementioned method. That is, a first gate oxide layer and a second gate oxide layer of different thicknesses are formed on the substrate to form a device with different gate voltages. A dielectric layer is formed on the first gate oxide layer and the second gate oxide layer, and a low-temperature dielectric layer is formed using a low-temperature deposition process. Part of the dielectric layer is removed by etching back, while the dielectric layer at the junction of the first gate oxide layer and the second gate oxide layer is retained, so that the step at the junction presents a gentle slope morphology. This reduces the residue formed at the step when forming the first gate and the second gate, thereby improving the device performance.
[0052] Although several embodiments have been described herein, it should be understood that many other modifications and embodiments will arise in the mind of those skilled in the art, all of which will fall within the spirit and scope of the concept disclosed herein. More specifically, various modifications and changes may be made in terms of the arrangement and / or components of the subject matter within the scope of this disclosure, the drawings, and the appended claims. In addition to modifications and changes in the components and / or arrangement, the use of alternative methods will also be obvious to those skilled in the art.
Claims
1. A method for manufacturing a semiconductor device, characterized in that, The manufacturing method includes: A substrate is provided in which a shallow trench isolation structure is formed; A gate oxide layer is formed on the substrate, the gate oxide layer covering the surface of the substrate and the surface of the shallow trench isolation structure; A patterned mask layer is formed on the gate oxide material layer. The gate oxide material layer covered by the patterned mask layer serves as a first gate oxide layer, and the gate oxide material layer exposed by etching with the patterned mask layer as a mask forms a second gate oxide layer. The first gate oxide layer and the second gate oxide layer are connected. A dielectric layer covering the second gate oxide layer and the mask layer is formed using a deposition process; The dielectric layer is etched back to remove the dielectric layer on the mask layer and part of the second gate oxide layer while retaining part of the dielectric layer at the junction of the first gate oxide layer and the second gate oxide layer, so that the step at the junction appears as a slope. Remove the remaining mask layer; A first gate is formed on the first gate oxide layer and a second gate is formed on the second gate oxide layer.
2. The manufacturing method as described in claim 1, characterized in that, The method further includes: after forming the second gate oxide layer and before forming the dielectric layer, removing a portion of the patterned mask layer to reduce the thickness of the mask layer.
3. The manufacturing method as described in claim 1, characterized in that, The temperature range for forming the dielectric layer using the deposition process is 20℃-200℃.
4. The manufacturing method as described in claim 1, characterized in that, The process of forming a first gate on the first gate oxide layer and forming a second gate on the second gate oxide layer includes: A gate material layer is formed to cover the first gate oxide layer, the dielectric layer, and the second gate oxide layer; A patterned photoresist layer is formed on the gate material layer; Using a patterned photoresist layer as a mask, the gate material layer is etched using an etching process to form a first gate on the first gate oxide layer and a second gate on the second gate oxide layer. The first gate and the second gate are respectively located on both sides of the shallow trench isolation structure.
5. The manufacturing method as described in claim 1, characterized in that, The deposition process for forming the dielectric layer includes atomic layer deposition or chemical vapor deposition.
6. The manufacturing method as described in claim 1, characterized in that, The step is located above the shallow trench isolation structure.
7. The manufacturing method as described in claim 1, characterized in that, The dielectric layer is made of silicon oxide, and the thickness of the dielectric layer ranges from 5nm to 500nm.
8. The manufacturing method as described in claim 1, characterized in that, The deposition temperature of the first gate and the second gate is higher than the deposition temperature of the dielectric layer, and the remaining dielectric layer is densified during the formation of the first gate and the second gate.
9. A semiconductor device, characterized in that, The semiconductor device includes: A substrate in which a shallow trench isolation structure is formed; A first gate oxide layer is located on a portion of the substrate; A second gate oxide layer is located on another portion of the substrate, and the second gate oxide layer is connected to the first gate oxide layer; The dielectric layer is located at the junction of the first gate oxide layer and the second gate oxide layer, so that the step at the junction appears as a slope; The first gate is located on the first gate oxide layer; The second gate is located on the second gate oxide layer.
10. The semiconductor device as claimed in claim 9, characterized in that, The step is located above the shallow trench isolation structure; The thickness of the first gate oxide layer is greater than the thickness of the second gate oxide layer.