Semiconductor device and preparation method thereof

Abstract

The invention provides a semiconductor device and a preparation method thereof, and the method comprises the steps: providing a substrate which comprises a first region and a second region, forming a plurality of first isolation structures in the substrate, forming a second isolation structure in the substrate of the first region, and enabling the plurality of first isolation structures and the second isolation structure to be arranged at intervals in a first direction, the first direction is parallel to the surface of the substrate; a well region is formed in the substrate, a drift region is further formed in the substrate in the first region, and at least part of the second isolation structure is located in the drift region; third grooves are respectively formed in the substrate in the first region and the second region, and the third groove in the first region extends into the second isolation structure from the surface of the substrate and crosses a part of the drift region and a part of the well region in the first region; the third groove of the second region extends into the well region of the second region from the surface of the substrate and is positioned between the adjacent first isolation structures of the second region; and forming a gate structure in the third groove of the first region and the second region.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically to a semiconductor device and a method for fabricating the same. Background Technology

[0002] In the field of semiconductor technology, the bipolar-CMOS-DMOS (BCD) process is a key integrated manufacturing technology that integrates bipolar junction transistors (BJTs), complementary metal-oxide-semiconductor transistors (CMOS), and double-diffused metal-oxide-semiconductor transistors (DMOS) onto the same substrate. It is widely used in power management chips, motor drives, automotive electronics, and communication power ICs (integrated circuits). CMOS devices are used for logic signal processing, BJT devices provide signal gain and power amplification, while DMOS devices require high reverse voltage withstand and high output current, often occupying a large chip area.

[0003] In related technologies, the gate of DMOS devices mostly adopts a planar structure, and its core process has significant defects: On the one hand, the gate of DMOS devices needs to be fabricated on the surface of a silicon substrate. In order to achieve isolation between the gate and the source and drain and to form a lightly doped drain (LDD), a sidewall structure needs to be formed on the sidewall of the gate first, which increases the process complexity and is also prone to substrate damage due to sidewall etching, reducing device yield. In addition, the presence of sidewalls also limits the miniaturization of devices and makes it difficult to adapt to the development needs of high-density integration. On the other hand, LDD implantation and source-drain implantation usually require two separate photolithography and ion implantation processes, which leads to an increase in the number of masks and an increase in process cost.

[0004] Therefore, improvements are needed to at least partially address the aforementioned problems. Summary of the Invention

[0005] The summary section introduces a series of simplified concepts, which will be further explained in detail in the detailed description section. This summary section is not intended to limit the key and essential technical features of the claimed technical solution, nor is it intended to determine the scope of protection of the claimed technical solution.

[0006] To address the existing problems, this application provides a method for fabricating a semiconductor device, comprising: providing a substrate, the substrate including a first region and a second region, wherein a plurality of first isolation structures are formed in the substrates of the first region and the second region, and at least one second isolation structure is also formed in the substrate of the first region, wherein the plurality of first isolation structures and at least one second isolation structure are spaced apart in a first direction, the first direction being parallel to the surface of the substrate; forming a well region in the substrates of the first region and the second region, and further forming a drift region in the substrate of the first region, the drift region and the well region of the first region being adjacent to each other, and the second isolation structure being at least partially located within the drift region; forming third trenches in the substrates of the first region and the second region respectively, the third trench in the first region extending from the surface of the substrate to the interior of the second isolation structure and spanning a portion of the drift region and a portion of the well region of the first region, and the third trench in the second region extending from the surface of the substrate to the interior of the well region of the second region and located between adjacent first isolation structures in the second region; and forming a gate structure in the third trenches of the first region and the second region, the top of the gate structure being lower than the surface of the substrate.

[0007] For example, after forming the gate structure, the method further includes: forming a source and a drain in the substrates on opposite sides of the gate structure in the first region and the gate structure in the second region, respectively, and forming a lightly doped drain region below the source and the drain, wherein the source, the drain and the lightly doped drain region are formed by ion implantation through the same mask; the source in the first region is located in the well region of the first region, the drain in the first region is located in the drift region, and the source and drain in the second region are located in the well region of the second region.

[0008] For example, the top of the gate structure is lower than the bottom of the source and the drain.

[0009] Exemplarily, the steps of forming the first isolation structure and the second isolation structure include: forming a patterned first mask layer on the surface of the substrate; etching the substrate using the patterned first mask layer as a mask to form a plurality of first trenches in the substrates of the first region and the second region; forming a patterned second mask layer on the patterned first mask layer; etching the substrate using the patterned second mask layer as a mask to form at least one second trench in the substrate of the first region, the second trench being located between adjacent first trenches in the first region, the first trench and the second trench extending from the surface of the substrate to the interior of the substrate; and filling the first trench and the second trench with an isolation material to form the first isolation structure and the second isolation structure.

[0010] For example, the first region is used to form a DMOS device, and the second region is used to form a CMOS device.

[0011] For example, after the second trench is formed and before the insulating material is filled, the corners of the sidewalls and bottom of the second trench are rounded so that the corners of the sidewalls and bottom of the second trench are arc-shaped corners.

[0012] For example, a portion of the second isolation structure near the drain side of the first region is retained after the third trench of the first region is formed. The cross-sectional shape of the retained second isolation structure is L-shaped. The cross-sectional shapes of the third trench in the first region and the third trench in the second region are rectangular or U-shaped. When the cross-sectional shape of the third trench is rectangular, the corners of the sidewalls and bottom of the third trench are rounded to make the corners of the sidewalls and bottom of the third trench arc-shaped.

[0013] For example, forming a gate structure in a third trench in the first region and the second region includes: forming a gate dielectric layer at least a portion of the bottom and sidewalls of the third trench in the first region and the second region and on the surface of the substrate; forming a gate material layer that fills the third trench in the first region and the third trench in the second region; performing a second planarization process to remove the gate material layer on the substrate; and etching back the gate material layer such that the top of the gate material layer in the third trench is lower than the surface of the substrate, wherein the remaining gate material layer and the gate dielectric layer constitute the gate structure, wherein the gate material layer located on the remaining second isolation structure in the first region serves as a field plate.

[0014] This application, in another aspect, provides a semiconductor device comprising: a substrate including a first region and a second region, wherein a plurality of first isolation structures are formed in the substrates of the first region and the second region, and at least one second isolation structure is further formed in the substrate of the first region, wherein the plurality of first isolation structures and at least one second isolation structure are spaced apart in a first direction, the first direction being parallel to the surface of the substrate; a drift region and a well region, wherein the well region is located in the substrates of the first region and the second region, and the drift region is located in the substrate of the first region, the well region of the first region and the drift region are arranged adjacent to each other, and the second isolation structure is at least partially located within the drift region; a gate structure located in a third trench, wherein the gate structure of the first region is located in the third trench of the first region, and the gate structure of the second region is located in the third trench of the second region, wherein the third trench of the first region is located in the substrate of the first region, extends from the surface of the substrate to the interior of the second isolation structure and spans a portion of the drift region and a portion of the well region of the first region, and the third trench of the second region is located in the substrate of the second region, extends from the surface of the substrate to the interior of the well region of the second region and is located between adjacent first isolation structures of the second region, and the top of the gate structure is lower than the surface of the substrate.

[0015] For example, it further includes: a source and a drain, wherein the source and drain of the first region are located in the substrate on opposite sides of the gate structure of the first region, and the source and drain of the second region are located in the substrate on opposite sides of the gate structure of the second region; and a lightly doped drain region, wherein the lightly doped drain region of the first region is located in the substrate below the source and drain of the first region, and the lightly doped drain region of the second region is located in the substrate below the source and drain of the second region.

[0016] The semiconductor device and its fabrication method provided in this application form an embedded gate structure in the substrate of the first and second regions. The top of the gate structure is lower than the substrate surface. This eliminates the need to form sidewalls on the sidewalls of the gate to achieve effective isolation between the gate structure and the subsequently formed lightly doped drain region, source, and drain. This reduces process costs and complexity, improves device yield, and reduces the device area, which is beneficial for device miniaturization and high-density integration. Attached Figure Description

[0017] The following drawings, which are incorporated herein by reference as part of this invention, are provided for understanding the invention. The drawings illustrate embodiments of the invention and their descriptions, serving to explain the principles of the invention.

[0018] In the attached image: Figures 1A to 1DA schematic diagram of the semiconductor device obtained by sequentially implementing the semiconductor device fabrication method of the related technology of this application is shown; Figure 2 A flowchart illustrating a method for fabricating a semiconductor device according to a specific embodiment of this application is shown; Figures 3A to 3J This diagram illustrates a semiconductor device obtained by sequentially implementing a method for fabricating a semiconductor device according to a specific embodiment of this application. Detailed Implementation

[0019] The invention will now be described more fully with reference to the accompanying drawings, which illustrate embodiments of the invention. However, the invention can be embodied in various forms and should not be construed as limited to the embodiments set forth herein. Rather, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, for clarity, the dimensions and relative dimensions of layers and regions may be exaggerated. The same reference numerals denote the same elements throughout.

[0020] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this invention, the first element, component, area, layer, or portion discussed below may be referred to as the second element, component, area, layer, or portion.

[0021] Spatial relation terms such as “below,” “under,” “below,” “below,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0022] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0023] To fully understand this application, detailed steps and structures will be presented in the following description to illustrate the technical solutions proposed in this application. Preferred embodiments of this application are described in detail below; however, in addition to these detailed descriptions, this application may have other implementation methods.

[0024] In the field of semiconductor power devices, laterally diffused metal-oxide-semiconductor (LDMOS) devices, a type of DMOS device, are widely used in integrated circuits such as communication RF power amplifiers, power management, and automotive electronics due to their excellent breakdown voltage, good linearity, high switching speed, and outstanding power handling characteristics. The on-resistance and breakdown voltage of LDMOS devices are two core performance parameters, and there is an inherent mutual constraint between them: reducing the on-resistance usually requires shortening the drift region length or increasing the doping concentration, but this weakens the breakdown voltage; conversely, increasing the breakdown voltage often requires lengthening the drift region or introducing an electric field modulation structure, leading to an increase in on-resistance. To improve the breakdown voltage of LDMOS devices, related technologies typically employ a gate field plate structure 10, such as... Figure 1A-1D As shown, this structure modulates the surface electric field distribution by extending the gate to cover part of the drift region. The gate field plate structure 10 is typically a stepped oxide layer structure (e.g., Figure 1AAs shown), Local Oxidation of Silicon (LOCOS) structure (such as...) Figure 1B As shown), Shallow Trench Isolation (STI) structure (such as...) Figure 1C (as shown) and contact field plate (such as Figure 1D (As shown). However, the aforementioned gate field plate structure 10 is mostly constructed based on planar gate technology.

[0025] In related technologies, the gate 11 of DMOS devices mostly adopts a planar structure, and its core process has significant defects: On the one hand, the gate 11 of DMOS devices needs to be fabricated on the surface of a silicon substrate. In order to achieve the isolation between the gate 11 and the source and drain and the formation of the lightly doped drain region (LDD), sidewalls 12 must be formed on the sidewalls of the gate 11 first, which increases the process complexity and is also prone to substrate damage due to the etching of sidewalls 12, reducing the device yield. In addition, the presence of sidewalls 12 restricts the miniaturization of the device and makes it difficult to adapt to the development needs of high-density integration. On the other hand, LDD implantation and source-drain implantation usually require two separate photolithography and ion implantation processes, which leads to an increase in the number of masks and an increase in process cost.

[0026] Therefore, in view of the aforementioned technical problems, this application proposes a method for fabricating a semiconductor device, such as... Figure 2 As shown, it mainly includes the following steps: Step S1, providing a substrate, the substrate including a first region and a second region, a plurality of first isolation structures are formed in the substrates of the first region and the second region, and at least one second isolation structure is also formed in the substrate of the first region, wherein the plurality of first isolation structures and at least one second isolation structure are spaced apart in a first direction, the first direction being parallel to the surface of the substrate; Step S2: A well region is formed in the substrate of the first region and the second region. A drift region is also formed in the substrate of the first region. The drift region and the well region of the first region are arranged adjacent to each other. The second isolation structure is at least partially located in the drift region. Step S3: A third trench is formed in the substrate of the first region and the second region respectively. The third trench in the first region extends from the surface of the substrate to the interior of the second isolation structure and spans a portion of the drift region and a portion of the well region of the first region. The third trench in the second region extends from the surface of the substrate to the interior of the well region of the second region and is located between adjacent first isolation structures in the second region. Step S4: A gate structure is formed in the third trench of the first region and the second region, with the top of the gate structure being lower than the surface of the substrate.

[0027] The semiconductor device and its fabrication method in this application form an embedded gate structure in the substrate of the first and second regions. The top of the gate structure is lower than the substrate surface. This eliminates the need to form sidewalls on the sidewalls of the gate to achieve effective isolation between the gate structure and the subsequently formed lightly doped drain region, source, and drain. This reduces process costs and complexity, improves device yield, and reduces device area, which is beneficial for device miniaturization and high-density integration.

[0028] Example 1 Below, for reference Figure 2 as well as Figures 3A to 3J The method for fabricating the semiconductor device of this application is described in detail, wherein, Figure 2 A flowchart illustrating a method for fabricating a semiconductor device according to a specific embodiment of this application is shown. Figures 3A to 3J This diagram illustrates a semiconductor device obtained by sequentially implementing a method for fabricating a semiconductor device according to a specific embodiment of this application.

[0029] For example, the method for fabricating the semiconductor device of this application includes the following steps: First, step S1 is performed to provide a substrate, which includes a first region and a second region. A plurality of first isolation structures are formed in the substrates of the first and second regions, and at least one second isolation structure is also formed in the substrate of the first region. The plurality of first isolation structures and at least one second isolation structure are spaced apart in a first direction, which is parallel to the surface of the substrate.

[0030] In one example, such as Figure 3A As shown, a substrate 20 is provided, and the material of the substrate 20 includes, but is not limited to, at least one of the following materials: silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), silicon germanium carbon (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP), sapphire, or other III / V compound semiconductors; or silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator (S-SiGeOI), silicon-on-insulator (SiGeOI), and germanium-on-insulator (GeOI); or it may be a double-sided polished wafer (DSP), a ceramic substrate such as alumina, a quartz, or a glass substrate, etc. Although several examples of materials that can form the substrate have been described herein, any material that can serve as a substrate falls within the spirit and scope of the invention.

[0031] For example, the substrate 20 is divided into a first region 201 and a second region 202, the first region 201 being used to form a DMOS device and the second region 202 being used to form a CMOS device, so as to achieve monolithic integration of high-voltage power output and low-voltage logic control functions.

[0032] Exemplarily, a protective layer is also formed on the substrate 20, comprising a first buffer layer 203 on the substrate 20 and a silicon nitride layer 204 on the first buffer layer 203. The method for forming the first buffer layer 203 includes, but is not limited to, thermal oxidation; the material of the first buffer layer 203 includes, but is not limited to, silicon dioxide; and the method for forming the silicon nitride layer 204 includes, but is not limited to, chemical vapor deposition (CVD). The first buffer layer 203 is formed between the substrate 20 and the silicon nitride layer 204 to alleviate stress in subsequent processes and protect the substrate 20. In other examples, the protective layer may also be a single-layer structure, which is not specifically limited.

[0033] In one example, such as Figures 3A to 3C As shown, a plurality of first isolation structures 21 are formed in the substrate 20 of the first region 201 and the second region 202, and at least one second isolation structure 22 is also formed in the substrate 20 of the first region 201. The plurality of first isolation structures 21 and at least one second isolation structure 22 are spaced apart in a first direction. The steps of forming the first isolation structure 21 and the second isolation structure 22 include: like Figures 3A to 3CAs shown, when a protective layer is formed on the substrate 20, a patterned first mask layer is first formed on the surface of the silicon nitride layer 204, defining the position and shape of the first isolation structure 21. Next, the patterned first mask layer is used as a mask to etch the protective layer and the substrate 20 to form a plurality of first trenches 211 in the substrate 20 of the first region 201 and the second region 202. The first trenches 211 can be inverted trapezoidal structures that are wider at the top and narrower at the bottom, meaning the top opening width of the first trench 211 is greater than its bottom width. Then, a patterned second mask layer is formed on the patterned first mask layer, defining the position and shape of the second isolation structure 22. Afterwards, the patterned second mask layer is used as a mask to etch the protective layer and the substrate 20 to form at least one second trench 212 in the substrate 20 of the first region 201. The second trench 212 is located adjacent to the first trench in the first region 201. Between 211, the first trench 211 and the second trench 212 extend from the surface of the substrate 20 to the interior of the substrate 20. The second trench 212 has a larger dimension in the first direction than the first trench 211 in the first direction, and the depth of the second trench 212 is less than the depth of the first trench 211. The first direction is parallel to the surface of the substrate 20. For example, the width of the second trench 212 is 0.5um-20um, and the width of the first trench 211 is 0.5um-2um. The second trench 212 replaces the LOCOS in the prior art, avoids the bird beak effect, and reserves space for subsequent embedded gates. After etching, the second mask layer and the remaining first mask layer are removed. Finally, the first trench 211 and the second trench 212 are filled with isolation material to form a first isolation structure 21 and a second isolation structure 22. The dimension of the second isolation structure 22 in the first direction is larger than the dimension of the first isolation structure 21 in the first direction. The etching of the protective layer and the substrate 20 can be performed using dry etching, which can be conventional etching processes such as reactive ion etching (RIE), ion beam etching, or plasma etching. Alternatively, for certain specific applications, the protective layer can be omitted, and photolithography and etching processes can be performed directly on the substrate 20 to form the first isolation structure 21 and the second isolation structure 22; no specific limitations are imposed on this.

[0034] For example, after forming the second trench 212 and before filling it with insulating material, the corners of the sidewalls and bottom of the second trench 212 are rounded. For example, the corners are rounded by an etching process (e.g., using gases such as Ar, CF4, or SF6 for brief etching at a low bias voltage) so that the corners of the sidewalls and bottom of the second trench 212 are arc-shaped corners, for example, the arc of the arc-shaped corner is a quarter circle arc, thereby avoiding the problem of electric field concentration in right-angle structures.

[0035] For example, such as Figure 3CAs shown, the step of filling the first trench 211 and the second trench 212 with insulating material to form the first insulating structure 21 and the second insulating structure 22 includes: First, a liner layer (not shown) is filled in the first trench 211 and the second trench 212. The liner layer covers the bottom and sidewalls of the first trench 211 and the second trench 212 as well as the surface of the substrate 20. The liner layer can be formed by atomic layer deposition (ALD) or low pressure chemical vapor deposition (LPCVD). The liner layer can be an oxide, and its function is to improve the step coverage of the subsequent filling material and relieve stress.

[0036] Next, a first isolation material is formed on the pad layer. The first isolation material fills the first trench 211 and the second trench 212. The first isolation material can be formed by high-density plasma chemical vapor deposition (HDP-CVD) or other methods. The first isolation material includes, but is not limited to, silicon dioxide, which has both deposition and in-situ sputtering capabilities. It can effectively fill the first trench (narrow and deep) with a large depth-to-width ratio and the second trench (wide and shallow) with a large lateral dimension, ensuring that there are no voids or gaps inside the trenches and completely filling the first trench 211 and the second trench 212, while covering the surface of the substrate 20.

[0037] Finally, a first planarization process is performed, such as chemical mechanical polishing (CMP), to remove the padding layer and the first isolation material located above the surface of the substrate 20, leaving the remaining padding layer and the first isolation material only inside the first trench 211 and the second trench 212, thereby forming the first isolation structure 21 and the second isolation structure 22, respectively. Furthermore, when a protective layer (i.e., the first buffer layer 203 and the silicon nitride layer 204) is formed on the substrate 20, CMP stops at the silicon nitride layer 204, and then the protective layer is removed, resulting in the final isolation structure being higher than the surface of the substrate. This dual-layer isolation material filling strategy not only improves the filling quality of deep and narrow trenches but also takes into account the reflow and density of wide and shallow trenches, effectively avoiding the depressions or voids that may occur in traditional single-step filling, thus ensuring the electrical performance and reliability of subsequent devices.

[0038] Next, step S2 is performed to form a well region in the substrate of the first region and the second region, and a drift region is also formed in the substrate of the first region. The drift region and the well region of the first region are arranged adjacent to each other, and the second isolation structure is at least partially located in the drift region.

[0039] In one example Figure 3DAs shown, after the formation of the first isolation structure 21 and the second isolation structure 22 is completed, an ion implantation process is performed on the substrate 20 of the first region 201 and the second region 202 to form a well region 205 and a drift region 206 in the substrate 20 of the first region 201. Before performing the ion implantation process, a second buffer layer 23 can be formed on the substrate 20 by means including but not limited to thermal oxidation or low-pressure chemical vapor deposition. The main function of the second buffer layer 23 is to reduce lattice damage to the surface of the substrate 20 caused by ion implantation. The specific steps of the ion implantation process include: First, the implantation region of the well region 205 is defined using photolithography, and a second buffer layer 23 is used as a surface protection layer. Well regions 205 are formed in the substrates 20 of the first region 201 and the second region 202 respectively by ion implantation. The specific conductivity type depends on the device requirements. Next, the drift region 206 is further formed in the first region 201: the implantation region of the drift region 206 is defined using photolithography, and the doped region is extended to the outside and adjacent to the well region 205 of the first region 201 by ion implantation. The final drift region 206 has a depth in the substrate 20 greater than the depth of the well region 205, which is beneficial for expanding the depletion region and reducing the peak surface electric field. The second isolation structure 22 is at least partially located within the drift region 206 and can be rationally configured according to different device requirements. Its wide and shallow structure not only acts as a lateral field plate but also works in conjunction with the deeply buried drift region to modulate the electric field distribution, improving the breakdown voltage of the DMOS device, while avoiding the uncontrollable effective channel length problem caused by the bird's beak effect in traditional LOCOS.

[0040] It should be noted that after the ion implantation process, an annealing process is performed. The annealing process can activate the doped impurities to make them electrically active, repair the silicon lattice damage caused by implantation, precisely control the diffusion depth and distribution of impurities, and improve the substrate interface quality. This ensures that the well region and drift region have good electrical properties and structural integrity, laying the foundation for the device to achieve high breakdown voltage, low on-resistance and high reliability.

[0041] Continuing, step S3 is performed to form a third trench in the substrate of the first region and the second region. The third trench in the first region extends from the substrate surface into the interior of the second isolation structure and spans a portion of the drift region and a portion of the well region of the first region. The third trench in the second region extends from the substrate surface into the interior of the well region of the second region and is located between adjacent first isolation structures in the second region.

[0042] In one example, such as Figure 3EAs shown, after the formation of the well region 205 and the drift region 206 is completed, a third trench 24 is formed in the substrate 20 of the first region 201 and the second region 202. The specific steps for forming the third trench 24 include: when a second buffer layer 23 is formed on the substrate 20, a patterned photoresist layer is formed on the surface of the second buffer layer 23. The patterned photoresist layer defines the position and shape of the third trench 24 of the first region 201 and the second region 202. The second buffer layer 23 and the substrate 20 are etched using the patterned photoresist layer as a mask to form the third trench 24 in the substrate 20 of the first region 201 and the second region 202. In this design, the third trench 24 of the first region 201 extends from the surface of the substrate 20 into the interior of the substrate 20, spanning the junction between the drift region 206 and the well region 205 of the first region, and further extends into the interior of the second isolation structure 22. A portion of the second isolation structure 22 near the drain side of the subsequent first region 201 is retained after the formation of the third trench 24 in the first region 201, and the remaining second isolation structure 22 has an L-shaped cross-section. The third trench 24 in the second region 202 extends from the surface of the substrate 20 into the interior of the substrate 20, into the well region 205 of the second region 202, and is located between adjacent first isolation structures 21 in the second region 202, providing an active gate window for the CMOS device. The depth of the third trench 24 in the two regions is differentiated according to device requirements, laying the foundation for the subsequent formation of the embedded gate structure. Dry etching can be used for etching the second buffer layer and the substrate. Dry etching can be conventional etching processes such as reactive ion etching (RIE), ion beam etching, or plasma etching.

[0043] For example, the first region 201 is used to form a DMOS device, and the second region 202 is used to form a CMOS device. The drift region of the DMOS device can have a different conductivity type than its well region. For example, if the drift region has an N-type conductivity, then the well region has a P-type conductivity, or vice versa.

[0044] For example, the cross-sectional shape of the third trench 24 in the first region 201 and the second region 202 is rectangular or U-shaped. When the cross-sectional shape of the third trench 24 is rectangular, in order to avoid electric field concentration at sharp corners, after etching to form the third trench 24 and before depositing the gate dielectric layer, the corners of the sidewalls and bottom of the third trench 24 in the first region 201 and the second region 202 are rounded. For example, the corners are smoothed by etching process (e.g., using gases such as Ar, CF4 or SF6 for short-term etching under a low bias voltage) so that the corners of the sidewalls and bottom of the third trench 24 are arc corners, for example, the arc of the arc corner is a quarter circle arc, thereby avoiding the problem of electric field concentration in right-angle structures.

[0045] Next, step S4 is performed to form a gate structure in the third trench of the first region and the second region, with the top of the gate structure being lower than the surface of the substrate.

[0046] In one example, such as Figures 3F to 3H As shown, a gate structure 25 is formed in the third trench 24 of the first region 201 and the second region 202, including: firstly, forming a gate dielectric layer 241 on the bottom and sidewalls of the third trench 24 of the first region 201 and the second region 202 and on the surface of the substrate 20. When a second buffer layer 23 is formed on the substrate, the second buffer layer 23 needs to be removed first. The gate dielectric layer 241 is formed on the surface of the substrate 20 and can be formed using processes including but not limited to thermal oxidation or atomic layer deposition (ALD). The material of the gate dielectric layer 241 includes but is not limited to silicon dioxide, silicon oxynitride, or high dielectric constant materials, etc., to provide good interface characteristics and gate control capability. Since the third trench 24 of the first region 201 extends into the interior of the second isolation structure 22, and the second isolation structure 22 is made of insulating materials such as oxides, the gate dielectric layer can be formed only on the sidewalls and bottom of the third trench 24 that is not located on the surface of the second isolation structure 22. 241; Subsequently, a gate material layer 242 is formed on the gate dielectric layer 241. The gate material layer 242 can be formed using processes including but not limited to low-pressure chemical vapor deposition (LPCVD). The material of the gate material layer 242 includes at least one of polysilicon, titanium nitride, tantalum titanium alloy, titanium aluminum alloy, or tungsten. It completely fills the third trench 24 of the first region 201 and the second region 202 and covers the gate dielectric layer 241. Then, a second planarization process is performed, such as chemical mechanical polishing (CMP), to remove excess gate material layer 242 located above the surface of the substrate 20. Finally, the gate material layer 242 in the third trench 24 is etched back. The etching depth is controlled so that the top of the remaining gate material layer 242 in the third trench 24 is lower than the surface of the substrate 20. The remaining gate material layer 242 and the gate dielectric layer 241 constitute the gate structure 25, thereby forming an embedded gate structure 25. The gate structure 25 not only avoids the dependence of traditional planar gates on sidewalls, but also achieves self-alignment by utilizing trench sidewalls. When the subsequent metal silicide layer is formed, the source and drain can be isolated from the gate structure, reducing the parasitic capacitance of the source, drain and gate structures. In addition, in the first region, such as the DMOS region, the embedded gate structure 25 partially covers the second isolation structure 22, which also acts as a field plate and helps to improve the breakdown voltage.

[0047] In the first region 201, the gate material layer 242 located on the remaining second isolation structure 22 serves as a field plate. The gate material layer and the second isolation structure below it together constitute a field plate structure. By capacitively coupling, the electric field distribution on the surface of the drift region is modulated, which effectively alleviates the electric field concentration near the drain, thereby improving the breakdown voltage of the DMOS device.

[0048] In one example, such as Figure 3I As shown, after forming the gate structure 25, the method further includes forming a source 26 and a drain 27 in the substrate 20 on opposite sides of the gate structure 25 in the first region 201 and the gate structure 25 in the second region 202, and forming a lightly doped drain region 28 below the source 26 and drain 27. Specifically, a patterned photoresist layer is first formed on the substrate surface, which defines the implantation windows of the source 26 and drain 27 in the first region 201 and the second region 202; then, at least two ion implantations are performed sequentially using the patterned photoresist layer as a mask to form the source 26 and drain 27, and to form the lightly doped drain region 28 below the source 26 and drain 27. Since the gate structure 25 is embedded in the third trench 24 and its top is lower than the surface of the substrate 20, the gate dielectric layer on its sidewalls acts as a barrier similar to a sidewall, and the self-alignment of the lightly doped drain region with the source / drain can be achieved without additional deposition and etching to form sidewalls. This process not only simplifies the fabrication process and reduces the number of photomasks, lowering manufacturing costs, but also avoids the size limitations and substrate damage associated with sidewall processes. Furthermore, because the lightly doped drain region is located directly below the source / drain electrodes and does not need to extend laterally beyond the source / drain electrodes as in related technologies, the device area can be further reduced, facilitating device miniaturization and high-density integration. It should be noted that after the ion implantation process, an annealing step is included to fully activate the implanted dopant ions, repair lattice damage to the substrate caused by high-energy ion bombardment, and thus improve device performance.

[0049] Optionally, the top of the gate structure is lower than the bottom of the source and the drain, which can reduce the parasitic capacitance between the electrodes.

[0050] Optionally, the doping concentration of the source 26 and the drain 27 is higher than that of the lightly doped drain region 28. In the first region, the drift region 206, the source 26, the drain 27 and the lightly doped drain region 28 have the same conductivity type. In the second region, the source 26, the drain 27 and the lightly doped drain region 28 have the same doping type.

[0051] For example, the source 26 of the first region 201 is located in the well region 205 of the first region 201, and the drain 27 of the first region 201 is located in the drift region 206. Both the source 26 and the drain 27 of the second region 202 are located in the well region 205 of the second region 202. The aforementioned source, drain, and the lightly doped drain region below them are all defined by the same photomask and formed simultaneously using ion implantation and annealing processes. This ensures both the differentiated electrical design of DMOS and CMOS devices and achieves high compatibility and simplification of the manufacturing process.

[0052] In one example, such as Figure 3J As shown, a metal silicide layer 29 is formed on the surfaces of the source 26, drain 27, and gate structure 25. Specifically, after forming the source 26, drain 27, and lightly doped drain region 28, a metal silicide layer 29 is further formed on the surfaces of the source 26, drain 27, and gate structure 25 to reduce contact resistance and improve the overall electrical performance of the device. Specifically, a metal thin film is first deposited on the substrate surface. The metal can be selected from nickel, cobalt, titanium, or their alloys, and can be achieved by sputtering or chemical vapor deposition. Subsequently, an annealing process is performed to react the metal with the surfaces of the source 26, drain 27, and gate structure 25 to form the metal silicide layer 29. Unreacted metal is removed by wet etching. The final metal silicide layer 29 covers the surfaces of the source 26, drain 27, and gate structure 25, significantly reducing the contact resistance of subsequent metal interconnects and improving the overall speed and power efficiency of the device.

[0053] It is worth mentioning that the above steps are only examples, and the order of the steps can be adjusted without conflict.

[0054] Thus, the process steps of the semiconductor device fabrication method according to the embodiments of this application are completed. It is understood that the semiconductor device fabrication method of this embodiment includes not only the above steps, but may also include other necessary steps before, during or after the above steps, all of which are included within the scope of the fabrication method of this embodiment.

[0055] In summary, the semiconductor device fabrication method of this application forms an embedded gate structure in the substrate of the first and second regions. The top of the gate structure is lower than the substrate surface. This eliminates the need to form sidewalls on the sidewalls of the gate to achieve effective isolation between the gate structure and the subsequently formed lightly doped drain region, source, and drain. This reduces process costs and complexity, improves device yield, and reduces device area, which is beneficial for device miniaturization and high-density integration.

[0056] Example 2 This application also provides a semiconductor device, which can be prepared by the method of the aforementioned embodiment one, or by other suitable preparation methods.

[0057] The following reference Figures 3A to 3J The semiconductor devices in the embodiments of this application will be explained and described, wherein structures that are the same as those in the aforementioned Embodiment 1 will not be described in detail here.

[0058] Specifically, such as Figures 3A to 3J As shown, the semiconductor device of this application includes: a substrate 20, which includes a first region 201 and a second region 202. A plurality of first isolation structures 21 are formed in the substrate 20 of the first region 201 and the second region 202. At least one second isolation structure 22 is also formed in the substrate 20 of the first region 201. The plurality of first isolation structures 21 and at least one second isolation structure 22 are spaced apart in a first direction. The first isolation structures 21 and the second isolation structures 22 extend from the surface of the substrate 20 to the interior of the substrate 20. The dimension of the second isolation structure 22 in the first direction is larger than the dimension of the first isolation structure 21 in the first direction. The first direction is parallel to the surface of the substrate 20. A drift region 206 and a well region 205 are also included. The well region 205 is located in the substrate 20 of the first region 201 and the second region 202. The drift region 206 is located in the substrate 20 of the first region 201. The well region 205 and drift region 206 of 201 are arranged adjacently, and the second isolation structure 22 is located within the drift region 206; the gate structure 25 is located in the third trench 24, the gate structure 25 of the first region 201 is located in the third trench 24 of the first region 201, and the gate structure 25 of the second region 202 is located in the third trench 24 of the second region 202. The third trench 24 of the first region 201 is located in the substrate 20 of the first region 201, extends from the surface of the substrate 20 to the interior of the second isolation structure 22 and spans part of the drift region 206 and part of the well region 205. The third trench 24 of the second region 202 is located in the substrate 20 of the second region 202, extends from the surface of the substrate 20 to the interior of the well region 205 of the second region 202 and is located between the adjacent first isolation structures 21 of the second region 202. The top of the gate structure 25 is lower than the surface of the substrate 20.

[0059] In one example, the semiconductor device further includes: a source 26 and a drain 27, wherein the source 26 and drain 27 of the first region 201 are located in the substrate 20 on opposite sides of the gate structure 25 of the first region 201, and the source 26 and drain 27 of the second region 202 are located in the substrate 20 on opposite sides of the gate structure 25 of the second region 202; and a lightly doped drain region 28, wherein the lightly doped drain region 28 of the first region 201 is located in the substrate 20 below the source 26 and drain 27 of the first region 201, and the lightly doped drain region 28 of the second region 202 is located in the substrate 20 below the source 26 and drain 27 of the second region 202.

[0060] In one example, the top of the gate structure 25 is lower than the bottom of the source 26 and the drain 27.

[0061] In one example, the semiconductor device further includes a metal silicide layer 29 covering the surfaces of the source 26, drain 27, and gate structure 25. The metal silicide layer 29 is formed by reacting nickel, cobalt, titanium, or an alloy thereof with underlying silicon or polysilicon material via a self-aligned silicide process. This significantly reduces the contact resistance between the source / drain and the metal contacts, as well as the resistance from the gate structure, thereby improving the device's switching speed and power efficiency.

[0062] The semiconductor device of this application forms an embedded gate structure in the substrate of the first and second regions. The top of the gate structure is lower than the substrate surface. This eliminates the need to form sidewalls on the sidewalls of the gate to achieve effective isolation between the gate structure and the subsequently formed lightly doped drain region, source, and drain. This reduces process cost and complexity, improves device yield, and reduces device area, which is beneficial for device miniaturization and high-density integration.

[0063] Although several embodiments have been described herein, it should be understood that many other modifications and embodiments will be conceived by those skilled in the art, all of which will fall within the spirit and scope of the disclosed concept. More particularly, various modifications and changes can be made in terms of the arrangement and / or components of the subject matter within the scope of the disclosure, drawings, and appended claims. In addition to modifications and changes in components and / or arrangement, the use of alternative methods will also be obvious to those skilled in the art.

Claims

1. A method of manufacturing a semiconductor device, characterized by, The preparation method comprises: providing a substrate, the substrate comprising a first region and a second region, a plurality of first isolation structures being formed in the substrate of the first region and the second region, and at least one second isolation structure being formed in the substrate of the first region, wherein the plurality of first isolation structures and the at least one second isolation structure are arranged at intervals in a first direction, the first direction being parallel to the surface of the substrate; forming a well region in the substrate of the first region and the second region, and forming a drift region in the substrate of the first region, the drift region being arranged adjacent to the well region of the first region, and the second isolation structure being at least partially located in the drift region; forming a third trench in the substrate of the first region and the second region respectively, the third trench of the first region extending from the surface of the substrate to the inside of the second isolation structure and across part of the drift region and part of the well region of the first region, and the third trench of the second region extending from the surface of the substrate to the inside of the well region of the second region and being located between adjacent first isolation structures of the second region; forming a gate structure in the third trench of the first region and the second region, the top of the gate structure being lower than the surface of the substrate.

2. The production method according to claim 1, wherein After the gate structure is formed, further comprising: forming a source and a drain in the substrate on the opposite sides of the gate structure of the first region and the gate structure of the second region respectively, and forming a lightly doped drain region below the source and the drain, wherein the source, the drain and the lightly doped drain region are formed by ion implantation through the same mask plate; the source of the first region being located in the well region of the first region, the drain of the first region being located in the drift region, and the source and the drain of the second region being located in the well region of the second region.

3. The production method according to claim 2, wherein the top of the gate structure being lower than the bottom of the source and the drain.

4. The production method according to claim 1, wherein The steps of forming the first isolation structure and the second isolation structure comprise: forming a patterned first mask layer on the surface of the substrate; etching the substrate with the patterned first mask layer as a mask to form a plurality of first trenches in the substrate of the first region and the second region; forming a patterned second mask layer on the patterned first mask layer; etching the substrate with the patterned second mask layer as a mask to form at least one second trench in the substrate of the first region, the second trench being located between adjacent first trenches of the first region, and the first trench and the second trench extending from the surface of the substrate to the inside of the substrate; filling the first trench and the second trench with an isolation material to form the first isolation structure and the second isolation structure.

5. The production method according to claim 1, wherein The first region is used to form a DMOS device, and the second region is used to form a CMOS device.

6. The production method according to claim 4, wherein After the second trench is formed and before the isolation material is filled, further comprising rounding the corners of the sidewall and the bottom of the second trench to make the corners of the sidewall and the bottom of the second trench into arc-shaped corners.

7. The production method according to claim 2, wherein The second isolation structure near the drain side of the first region is reserved after forming the third trench of the first region, the cross-sectional shape of the reserved second isolation structure is L-shaped, the cross-sectional shape of the third trench of the first region and the third trench of the second region is rectangular or U-shaped, and when the cross-sectional shape of the third trench is rectangular, the corner of the sidewall and the bottom of the third trench is rounded to make the corner of the sidewall and the bottom of the third trench be an arc-shaped corner.

8. The production method according to claim 1, wherein The gate structure is formed in the third trench of the first region and the second region, including: A gate dielectric layer is formed on at least part of the bottom and sidewall of the third trench of the first region and the second region and the surface of the substrate; A gate material layer is formed, which fills the third trench of the first region and the third trench of the second region; A second planarization process is performed to remove the gate material layer on the substrate; The gate material layer is etched back so that the top of the gate material layer in the third trench is lower than the surface of the substrate, and the remaining gate material layer and the gate dielectric layer constitute the gate structure, wherein the gate material layer on the remaining second isolation structure in the first region serves as a field plate.

9. A semiconductor device, characterized by comprising: Including: A substrate including a first region and a second region, a plurality of first isolation structures are formed in the substrate of the first region and the second region, and at least one second isolation structure is further formed in the substrate of the first region, wherein the plurality of first isolation structures and the at least one second isolation structure are arranged at intervals in a first direction, and the first direction is parallel to the surface of the substrate; A drift region and a well region, the well region is located in the substrate of the first region and the second region, the drift region is located in the substrate of the first region, and the well region and the drift region of the first region are arranged adjacent to each other, and the second isolation structure is at least partially located in the drift region; A gate structure is located in a third trench, the gate structure of the first region is located in the third trench of the first region, and the gate structure of the second region is located in the third trench of the second region, wherein the third trench of the first region is located in the substrate of the first region, extends from the surface of the substrate to the inside of the second isolation structure and across part of the drift region and part of the well region of the first region, the third trench of the second region is located in the substrate of the second region, extends from the surface of the substrate to the inside of the well region of the second region and is located between the adjacent first isolation structures of the second region, and the top of the gate structure is lower than the surface of the substrate.

10. The semiconductor device of claim 9, wherein, Further including: A source and a drain, the source and the drain of the first region are located in the substrate on the opposite sides of the gate structure of the first region, and the source and the drain of the second region are located in the substrate on the opposite sides of the gate structure of the second region; a lightly doped drain region, the lightly doped drain region of the first region being in the substrate under the source and drain of the first region, the lightly doped drain region of the second region being in the substrate under the source and drain of the second region.

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