Semiconductor device

Abstract

A semiconductor device includes a substrate, a substrate insulating layer, a first isolation region, a gate electrode, a plurality of channel layers, a source / drain region, a backside contact plug, and a backside isolation region. The substrate includes a first region and a second region. The substrate insulating layer is arranged on the lower surface of the substrate. The first isolation region extends through the substrate and toward the substrate insulating layer. The gate electrode is disposed on an upper surface of the substrate. The plurality of channel layers are surrounded by the gate electrode. The source / drain regions are disposed on opposite sides of the gate electrode and are connected to the plurality of channel layers. The backside contact plug is connected to the source / drain region. The backside isolation region passes through the substrate and the substrate insulating layer, and the backside isolation region separates the substrate.

Description

TECHNICAL FIELD

[0001] The present inventive concepts relate to semiconductor devices, and more particularly, to semiconductor devices including an insulating layer. BACKGROUND

[0002] As the demand for high performance, high speed, and / or multi-functionality of semiconductor devices increases, the integration of semiconductor devices has been increasing. According to the trend of high integration of semiconductor devices, semiconductor devices having a backside power delivery network (BSPDN) structure in which a power rail is disposed on a back surface of a semiconductor wafer have been developed. To address limitations in operational performance due to a reduction in size of a planar metal oxide semiconductor FET (MOSFET), semiconductor devices having a three-dimensional channel in which a transistor is built vertically have been developed. SUMMARY

[0003] An aspect of the present inventive concepts provides a semiconductor device having improved electrical properties.

[0004] According to an aspect of the present inventive concepts, a semiconductor device including a substrate, a substrate insulating layer, a first isolation region, a gate electrode, a plurality of channel layers, a source / drain region, a backside contact plug, and a backside isolation region is provided. The substrate includes a first region and a second region spaced apart from each other along a first direction. The substrate includes an upper surface and a lower surface. The substrate insulating layer is disposed on the lower surface of the substrate. The first isolation region passes through the substrate between the first region and the second region, and the first isolation region extends toward the substrate insulating layer. The gate electrode is disposed on the upper surface of the substrate in the first region and the second region. The plurality of channel layers are spaced apart from each other along a second direction perpendicular to the upper surface of the substrate, and are surrounded by the gate electrode, wherein the plurality of channel layers are disposed on the first region and the second region. The source / drain region is disposed on opposite sides of the gate electrode, wherein the source / drain region is connected to the plurality of channel layers. The backside contact plug extends from a lower surface of the substrate insulating layer to at least one of the source / drain regions along the second direction, wherein the backside contact plug is connected to the at least one of the source / drain regions. The backside isolation region passes through the substrate and the substrate insulating layer, and the backside isolation region separates the substrate.

[0005] According to another aspect of the inventive concepts, a semiconductor device including a semiconductor substrate, a substrate insulating layer, gate electrodes, a plurality of channel layers, source / drain regions, and a backside contact plug is provided. The semiconductor substrate has an upper surface and a lower surface. The substrate insulating layer is disposed on the lower surface of the semiconductor substrate. The gate electrodes are disposed on the upper surface of the semiconductor substrate and extend along a first direction, and the gate electrodes are spaced apart from each other. The plurality of channel layers are spaced apart from each other along a second direction perpendicular to the upper surface of the semiconductor substrate, and the plurality of channel layers are disposed on the upper surface of the semiconductor substrate and are surrounded by the gate electrodes. The source / drain regions are disposed on opposite sides of the gate electrodes, and the source / drain regions include first and second source / drain regions spaced apart from each other. The backside contact plug extends from a lower surface of the substrate insulating layer along the second direction, and the backside contact plug is recessed into at least one of the first and second source / drain regions. A thickness of the semiconductor substrate is equal to or less than a thickness of the substrate insulating layer.

[0006] According to another aspect of the inventive concepts, a semiconductor device including a semiconductor substrate, a substrate insulating layer, gate electrodes, a plurality of channel layers, source / drain regions, and a backside contact plug is provided. The semiconductor substrate has an upper surface and a lower surface. The substrate insulating layer is disposed on the lower surface of the semiconductor substrate. The gate electrodes are disposed on the upper surface of the semiconductor substrate and extend along a first direction, and the gate electrodes are spaced apart from each other. The source / drain regions are disposed on opposite sides of the gate electrodes, and the source / drain regions include first and second source / drain regions spaced apart from each other. The upper insulating layer is disposed on the source / drain regions. The front contact plug passes through the upper insulating layer, and the front contact plug is connected to one of the first and second source / drain regions. The backside contact plug extends from a lower surface of the substrate insulating layer along a second direction perpendicular to the upper surface of the substrate, and the backside contact plug is connected to the other of the first and second source / drain regions. The backside power structure is connected to the backside contact plug and conveys power. The backside isolation region passes through the semiconductor substrate and the substrate insulating layer. The backside isolation region separates the semiconductor substrate. A lower surface of the backside isolation region, a lower surface of the backside contact plug, and a lower surface of the substrate insulating layer are coplanar with each other.

[0007] According to an aspect of the present inventive concept, there is provided a method of manufacturing a semiconductor device, including: providing a substrate; disposing a substrate insulating layer on the substrate; and forming a first isolation region, a gate electrode, a plurality of channel layers, a source / drain region, a backside contact plug, and a backside isolation region on the substrate. After partially and selectively etching the substrate, the substrate insulating layer is disposed on a lower surface of the substrate. Then, a thinning process is performed to planarize the surface. Accordingly, a lower surface of the substrate insulating layer becomes coplanar with a lower surface of the backside contact plug, a lower surface of the backside isolation region, a lower surface of the first isolation region, and a lower surface of the second isolation region. BRIEF DESCRIPTION OF DRAWINGS

[0008] The above and other aspects and features of the inventive concept will become clearer from the following detailed description taken in conjunction with the accompanying drawings, in which: Figure 1 is a plan view of a semiconductor device according to an example embodiment of the inventive concept; Figure 2 is a cross-sectional view of a semiconductor device according to an example embodiment of the inventive concept; Figure 3 , Figure 4 , Figure 5 and Figure 6 is a cross-sectional view of a semiconductor device according to an example embodiment of the inventive concept; Figure 7A , Figure 7B , Figure 7C , Figure 7D , Figure 7E , Figure 7F , Figure 7G , Figure 7H and Figure 7I are diagrams illustrating sequential processes in a method of manufacturing a semiconductor device according to an example embodiment of the inventive concept. DETAILED DESCRIPTION

[0009] Hereinafter, preferred example embodiments of the inventive concept will be described with reference to the accompanying drawings. As used herein, terms such as "upper", "upper portion", "upper surface", "above", "lower", "lower portion", "lower surface", "below", and "side surface" are based on the drawings, and can vary depending on the direction in which components are actually arranged.

[0010] Embodiments of the inventive concept relate to a semiconductor device including an insulating layer.

[0011] According to embodiments of the inventive concept, an insulating layer can be formed on a semiconductor substrate after the semiconductor substrate is partially etched.

[0012] According to embodiments of the inventive concepts, a thinning process can be performed to planarize the surface. Thus, the lower surface of the substrate insulating layer can be coplanar with the lower surfaces of other vertical structures in the semiconductor device, such as the backside contact plug, the backside isolation region, the first isolation region, and the second isolation region.

[0013] Existing methods include removing portions of the semiconductor substrate to make room for other components, such as backside contact structures. Such methods present challenges due to the difficulty of precisely etching silicon (Si) included in the semiconductor substrate to remove specific portions. When the etching process is inconsistent or imprecise, the resulting surface can be unsmooth or poorly controlled, making it difficult to place vertical structures on the semiconductor substrate. As a result, thin spots caused by improper etching can lead to wafer splitting defects, such as cracks or chipping, during subsequent wafer separation processes.

[0014] Existing methods also include removing the entire semiconductor substrate and forming an insulating layer. However, removing the semiconductor substrate can damage or destroy the source / drain regions, which are critical parts of the transistor. Furthermore, the insulating layer that replaces the semiconductor substrate can not provide the same level of thermal conductivity as the original semiconductor substrate, and heat dissipation problems can arise.

[0015] Embodiments of the inventive concepts can address the challenges by selectively etching a portion of the semiconductor substrate, depositing an insulating layer, and then planarizing the surface. Embodiments of the inventive concepts can avoid wafer splitting defects, damage to the source / drain regions, and address heat dissipation problems by leaving a portion of the semiconductor substrate intact for thermal management.

[0016] Figure 1 is a top view of a semiconductor device according to example embodiments of the inventive concepts.

[0017] Figure 2 is a cross-sectional view of a semiconductor device according to example embodiments of the inventive concepts. Figure 2 is Figure 1 is a cross-sectional view of the semiconductor device of

[0018] Referring to Figure 1 and Figure 2, the semiconductor device 100 can include a semiconductor substrate 101 including a first region R1 and a second region R2, a substrate insulating layer 190 disposed on a lower surface of the semiconductor substrate 101, gate structures 160 disposed on the semiconductor substrate 101 and extending along a third direction (Z direction), the gate structures 160 including gate electrodes 165, respectively, a channel structure 140 including a first channel layer 141, a second channel layer 142, and a third channel layer 143 disposed on the semiconductor substrate 101, first to fourth source / drain regions 150A, 150B, 150C, and 150D in contact with the channel structure 140, a front contact plug 170 that passes through a first interlayer insulating layer 192 and a second interlayer insulating layer 194, and a backside contact plug 180 that passes through the substrate insulating layer 190 and the semiconductor substrate 101. The first channel layer 141, the second channel layer 142, and the third channel layer 143 can be spaced apart from each other along a vertical direction. The front contact plug 170 can be connected to the first source / drain region 150A and the third source / drain region 150C. The backside contact plug 180 can be connected to the second source / drain region 150B and the fourth source / drain region 150D. The semiconductor device 100 can further include the first interlayer insulating layer 192, the second interlayer insulating layer 194, and a third interlayer insulating layer 198, and can further include a first isolation region IL1 and a second isolation region IL2 defining an active region 105 on the semiconductor substrate 101 and a backside isolation region BIL isolating the semiconductor substrate 101. For example, the backside isolation region BIL can be disposed between the semiconductor substrate 101 and can separate the semiconductor substrate 101 from an adjacent semiconductor substrate 101. The semiconductor device 100 can further include a backside power structure 185 connected to the backside contact plug 180. For example, the backside power structure 185 can be disposed under the backside contact plug 180.

[0019] The semiconductor substrate 101 can include the first region R1 and the second region R2. The first region R1 and the second region R2 can be disposed adjacent to each other or can be spaced apart from each other. The first source / drain region 150A and the second source / drain region 150B can be disposed in the first region R1, and the third source / drain region 150C and the fourth source / drain region 150D can be disposed in the second region R2. For example, the first region R1 can be an n-channel field effect transistor (nFET) region, and the second region R2 can be a p-channel field effect transistor (pFET) region. However, in some example embodiments of the inventive concept, the first region R1 and the second region R2 can be regions in which transistors of the same conductivity type and different electrical properties are disposed. The first region R1 and the second region R2 can be referred to as regions of the semiconductor device 100 rather than regions of the semiconductor substrate 101.

[0020] The semiconductor substrate 101 can include an upper surface extending in the X direction and the Y direction, and a lower surface disposed opposite the upper surface. The semiconductor substrate 101 can include silicon (Si), germanium (Ge), or silicon germanium (SiGe). The semiconductor substrate 101 can include a bulk wafer, an epitaxial layer, a silicon-on-insulator (SOI) layer, or a semiconductor-on-insulator (SeOI) layer.

[0021] A first thickness t1 of the semiconductor substrate 101 can be a length measured along the Z direction from the upper surface to the lower surface of the semiconductor substrate 101. A length d1 can be a length of the first isolation region IL1 measured along the Z direction. The first thickness t1 can be less than the length d1.

[0022] The substrate insulating layer 190 can be a layer disposed on the lower surface of the semiconductor substrate 101. The substrate insulating layer 190 can be formed after the semiconductor substrate 101 is partially removed during a manufacturing process. The substrate insulating layer 190 can be formed of an insulating material, and can include, for example, an oxide, a nitride, or a combination thereof. In some example embodiments of the inventive concept, the substrate insulating layer 190 can include a plurality of insulating layers, and can be disposed on the lower surface of the semiconductor substrate 101. A second thickness t2 can be a length of the substrate insulating layer 190 measured along the Z direction. The second thickness t2 of the substrate insulating layer 190 can be equal to or greater than the first thickness t1, and the second thickness t2 can satisfy a range of 1 times to 2 times the first thickness t1 of the semiconductor substrate 101. The second thickness t2 of the substrate insulating layer 190 can be in a range of about 1 times to about 1.2 times the first thickness t1, but the inventive concept is not necessarily limited thereto.

[0023] The substrate insulating layer 190 and the semiconductor substrate 101 can be collectively referred to as a substrate structure. The substrate structure can include the first region R1 and the second region R2 in the same manner as the semiconductor substrate 101.

[0024] In the substrate structure, the first region R1 and the second region R2 can be spaced apart from each other along the Y direction. The first isolation region IL1 can be disposed between the first region R1 and the second region R2 and can extend along the X direction. An upper surface of the first isolation region IL1 can be disposed at the same or similar height as an upper surface of the semiconductor substrate 101. A lower surface of the first isolation region IL1 can be disposed at the same or similar height as a lower surface of the substrate insulating layer 190. For example, the lower surface of the first isolation region IL1 can be coplanar with the lower surface of the substrate insulating layer 190. A width of the lower surface of the first isolation region IL1 can be less than a first width W1 that is a width of the upper surface of the first isolation region IL1. For example, the width of the first isolation region IL1 can gradually decrease along the Z direction from the upper surface to the lower surface. Thus, the first isolation region IL1 can have an inclined side surface. In the X-Y plane, the first width W1 can be greater than a second width W2 that is a length of the gate structure 160 measured along the X direction. The second width can be a width of the gate electrode 165.

[0025] In the first region R1 and the second region R2 of the substrate structure, the second isolation region IL2 can isolate the respective active regions 105 from each other. The second isolation region IL2 can include an upper surface having a third width W3 measured along the X direction. The third width W3 of the second isolation region IL2 can be less than the first width W1 of the first isolation region IL1. The upper surface of the second isolation region IL2 can be coplanar with the upper surface of the first isolation region IL1, and the lower surface of the second isolation region IL2 can be coplanar with the lower surface of the first isolation region IL1. The first isolation region IL1 and the second isolation region IL2 can have the same length d1 measured along the Z direction, and the length d1 is substantially equal to a sum of the first thickness t1 of the semiconductor substrate 101 and the second thickness t2 of the substrate insulating layer 190. The first isolation region IL1 and the second isolation region IL2 can include the same material 102. For example, the first isolation region IL1 and the second isolation region IL2 can include an insulating material 102, can include at least one of an oxide, a nitride, an oxynitride, and a carbon oxide, and can include one of a silicon oxide and a silicon nitride.

[0026] In each of the first region R1 and the second region R2, the gate structure 160 can be disposed on the upper surface of the semiconductor substrate 101 and can extend along a single direction. For example, the first region R1 and the second region R2 can extend along the Y direction. The gate structure 160 of the first region R1 and the second region R2 can be disposed in a cut state, not disposed on an upper portion of the first isolation region IL1 between the first region R1 and the second region R2. The gate structure 160 can extend along the Y direction and can cover an upper portion of the second isolation region IL2 in each of the first region R1 and the second region R2.

[0027] The channel region of the transistor can be disposed in the channel structure 140, thereby intersecting with the gate electrode 165 of the gate structure 160. The gate structures 160 can be spaced apart from each other along the X direction. Each gate structure 160 may include a gate dielectric layer 162, a gate spacer layer 164, and a gate electrode 165. In an example embodiment, each gate structure 160 may further include a capping layer 166 disposed on the upper surface of the gate electrode 165.

[0028] A gate dielectric layer 162 may be disposed between the active region 105 and the gate electrode 165, and between the channel structure 140 and the gate electrode 165. The gate dielectric layer 162 may partially cover a portion of the surface of the gate electrode 165. For example, the gate dielectric layer 162 may surround the surface of the gate electrode 145 (except for the uppermost surface). The gate dielectric layer 162 may be disposed in the space between the gate electrode 165 and the gate spacer layer 164, but the inventive concept is not limited thereto. The gate dielectric layer 162 may include, for example, oxides, nitrides, or high-k materials. High-k materials can refer to dielectric materials with a dielectric constant higher than that of silicon oxide (SiO2). High-k materials may include, for example, alumina (Al2O3), tantalum oxide (Ta2O3), titanium oxide (TiO2), yttrium oxide (Y2O3), zirconium oxide (ZrO2), and zirconium silicon oxide (ZrSi). x O y Hafnium oxide (HfO2) and hafnium silicon oxide (HfSi) x O y ), Lanthanum oxide (La₂O₃), Lanthanum aluminum oxide (LaAl) x O y ), lanthanum hafnium oxide (LaHf) x O y Hafnium aluminum oxide (HfAl) x O y It is one of praseodymium oxide (Pr₂O₃) and praseodymium oxide (Pr₂O₃). In some exemplary embodiments of the present invention, the gate dielectric layer 162 may be a multilayer structure.

[0029] The gate electrode 165 may include a conductive material, such as a metal nitride like a titanium nitride (TiN) film, a tantalum nitride (TaN) film, or a tungsten nitride (WN) film; and / or a metallic material such as aluminum (Al), tungsten (W), or molybdenum (Mo); or a semiconductor material such as doped polycrystalline silicon. In some exemplary embodiments of the inventive concept, the gate electrode 165 may be a multilayer structure. The gate electrode 165 may be connected to an upper contact plug disposed thereon.

[0030] The gate spacer layer 164 can be disposed on both side surfaces of the gate electrode 165 and can be disposed on the channel structure 140. The gate spacer layer 164 can insulate the first to fourth source / drain regions 150A to 150D from each other with the gate electrode 165. The gate spacer layer 164 can also be disposed on the side surfaces of the gate structure 160 cut on the first isolation region IL1. Accordingly, the upper surface of the first isolation region IL1 can be in direct contact with the lower surface of the gate spacer layer 164, but the inventive concept is not necessarily limited thereto. In some example embodiments of the inventive concept, the shape of the upper end of each gate spacer layer 164 can vary in various ways, and the gate spacer layer 164 can be a multi-layer structure. The gate spacer layer 164 can include at least one of an oxide, a nitride, and an oxynitride, and can be formed of, for example, a low-k film. The low-k material can refer to a dielectric material having a dielectric constant lower than that of a silicon oxide film (SiO2).

[0031] The channel structure 140 can be disposed on the semiconductor substrate 101 and can intersect the gate structure 160. Each channel structure 140 can include the first to third channel layers 141, 142, and 143 spaced apart from each other along the Z direction. The channel structure 140 can be connected to the first to fourth source / drain regions 150A to 150D. The channel structure 140 can include a width equal to or similar to the width of the gate structure 160 measured along the X direction. In a cross-sectional view along the Y direction, the width of a lower channel layer among the first to third channel layers 141, 142, and 143 can be equal to or greater than the width of an upper channel layer among the first to third channel layers 141, 142, and 143. For example, the width of the third channel layer 143 can be equal to or greater than the width of the first channel layer 141. In some example embodiments of the inventive concept, the width of the channel structure 140 can be smaller than the width of the gate structure 160.

[0032] The channel structure 140 can be formed of a semiconductor material and can include, for example, at least one of silicon (Si), silicon germanium (SiGe), and germanium (Ge). In some example embodiments of the inventive concept, the number and shape of the channel layers 141, 142, and 143 included in a single channel structure 140 can vary.

[0033] In the semiconductor device 100, the gate electrode 165 can be disposed between the first to third channel layers 141, 142, and 143 and can be disposed on the channel structure 140. Accordingly, the semiconductor device 100 can include a transistor having a multi-bridge channel field effect transistor (FET) structure, such as the MBCFET TM , which features a fully wrapped gate field effect transistor.

[0034] The first to fourth source / drain regions 150A, 150B, 150C, and 150D can be disposed at both sides of the gate structure 160 and can be in contact with the channel structure 140, respectively. For example, the first to fourth source / drain regions 150A, 150B, 150C, and 150D can be disposed between the gate structures 160. The first to fourth source / drain regions 150A, 150B, 150C, and 150D can cover a side surface of each of the first channel layer 141, the second channel layer 142, and the third channel layer 143 of the channel structure 140. The first source / drain region 150A and the third source / drain region 150C can be connected to the front contact plug 170 by an upper surface or an upper end thereof, respectively, and the second source / drain region 150B and the fourth source / drain region 150D can be connected to the backside contact plug 180 by a lower surface or a lower end thereof, respectively. For example, the front contact plug 170 can penetrate the first source / drain region and the third source / drain region, and the backside contact plug 180 can penetrate the second source / drain region 150B and the fourth source / drain region 150D. The first to fourth source / drain regions 150A, 150B, 150C, and 150D can have a recessed shape due to the front contact plug 170 and the backside contact plug 180. The upper surface of the first to fourth source / drain regions 150A, 150B, 150C, and 150D can be disposed at the same height or a higher height than a lower surface of the gate electrode 165 disposed on the channel structure 140. However, it is not necessarily limited thereto, and in an example embodiment of the inventive concept, the height can be changed in various ways.

[0035] Each of the first to fourth source / drain regions 150A, 150B, 150C, and 150D can include a first epitaxial layer 152 and a second epitaxial layer 154. The first epitaxial layer 152 can cover a side surface of each of the first channel layer 141, the second channel layer 142, and the third channel layer 143, and can cover a side surface of the channel structure 140 disposed below the gate structure 160. The first epitaxial layer 152 can cover an inner sidewall and a lower surface of a recessed region in which each of the first to fourth source / drain regions 150A, 150B, 150C, and 150D is disposed. The first epitaxial layer 152 can have an outer convex surface protruding toward the gate structure 160 disposed below each of the first channel layer 141, the second channel layer 142, and the third channel layer 143. Accordingly, the first epitaxial layer 152 can have an outer surface in a curved shape protruding outward in a circular manner. However, the shape of the outer surface of the first epitaxial layer 152 is not necessarily limited to Figure 2The first epitaxial layer 152 can be in contact with the backside contact plug 180 in the first source / drain region 150A and the second source / drain region 150B. The second epitaxial layer 154 can be in contact with the backside contact plug 180 in the third source / drain region 150C and the fourth source / drain region 150D.

[0036] The second epitaxial layer 154 can cover the first epitaxial layer 152 and can fill the recessed region. The second epitaxial layer 154 can be in contact with a portion of an upper portion of the backside contact plug 180 in the second source / drain region 150B and the fourth source / drain region 150D. A width of the second epitaxial layer 154 measured along the X direction can be greater than a thickness of the first epitaxial layer 152 disposed on one side surface of the channel structure 140. In some example embodiments of the inventive concepts, each of the first to fourth source / drain regions 150A, 150B, 150C, and 150D can further include a third epitaxial layer disposed on an upper surface of the second epitaxial layer 154.

[0037] The first to fourth source / drain regions 150A, 150B, 150C, and 150D can include a semiconductor material, such as at least one of silicon (Si) and germanium (Ge), and can further include an impurity. The first epitaxial layer 152 and the second epitaxial layer 154 can have different compositions. For example, a concentration of a non-silicon element of the second epitaxial layer 154 can be higher than a concentration of a non-silicon element of the first epitaxial layer 152. The non-silicon element can be, for example, germanium (Ge) and / or a doping element.

[0038] For example, when the first region R1 is an nFET region and the second region R2 is a pFET region, the third source / drain region 150C and the fourth source / drain region 150D can not include germanium (Ge), or can include germanium (Ge) at a lower concentration than a concentration of germanium (Ge) of the first source / drain region 150A and the second source / drain region 150B. For example, the first source / drain region 150A and the second source / drain region 150B can include silicon (Si). For example, the third source / drain region 150C and the fourth source / drain region 150D can include silicon germanium (SiGe), and a concentration of germanium (Ge) of the second epitaxial layer 154 can be greater than a concentration of germanium (Ge) of the first epitaxial layer 152.

[0039] The doping concentration of the doping element (i.e., impurity) of the second epitaxial layer 154 can be higher than the doping concentration of the doping element of the first epitaxial layer 152. Accordingly, the specific resistance of the second epitaxial layer 154 can be smaller than the specific resistance of the first epitaxial layer 152. For example, the impurities of the first and second source / drain regions 150A and 150B can include N-type impurities such as at least one of phosphorus (P), arsenic (As), and antimony (Sb), and the impurities of the third and fourth source / drain regions 150C and 150D can include P-type impurities such as at least one of boron (B), gallium (Ga), and indium (In). For example, the impurity concentration of the first epitaxial layer 152 can be in the range of about 1 x 1018 / cm3to about 6 x 1019 / cm3, and the impurity concentration of the second epitaxial layer 154 can be in the range of about 1 x 1018 / cm3to about 1 x 1019 / cm3, but the inventive concept is not necessarily limited thereto. 20 / cm 3 / cm 21 / cm 3 / cm 21 / cm 3 / cm 22 / cm 3 / cm

[0040] The front contact plug 170 can pass through the first and second interlayer insulating layers 192 and 194, can be connected to the first and third source / drain regions 150A and 150C, and can apply an electrical signal to the first and third source / drain regions 150A and 150C. The front contact plug 170 can have a gradually narrowing side surface that is narrower in the lower width than in the upper width according to an aspect ratio, but the inventive concept is not necessarily limited thereto. The upper surfaces of the first and third source / drain regions 150A and 150C can be recessed and can create a space for the front contact plug 170 to be disposed. For example, the front contact plug 170 can extend from the upper surfaces of the first and third source / drain regions 150A and 150C, thereby forming a downwardly recessed curvature in the top surfaces of the first and third source / drain regions 150A and 150C.

[0041] The front contact plug 170 can recess the first and third source / drain regions 150A and 150C by substantially the same depth. The front contact plug 170 can extend from the upper portion to a portion below the lower surface of the uppermost first channel layer 141 of the channel structure 140, but the inventive concept is not necessarily limited thereto. For example, the lower end of the front contact plug 170 can be disposed, for example, at a height between the upper surface of the first channel layer 141 and the upper surface of the second channel layer 142. For example, the lower end of the front contact plug 170 can be disposed at a height between the upper and lower surfaces of the second channel layer 142.

[0042] The front contact plug 170 can include a metallic material, for example, tungsten (W), molybdenum (Mo), or aluminum (Al). In some example embodiments of the inventive concept, the front contact plug 170 can include a barrier layer forming an outer surface. The barrier layer can include, for example, a metal nitride such as titanium nitride (TiN), tantalum nitride (TaN), or tungsten nitride (WN). In example embodiments of the inventive concept, the number and arrangement of conductive layers included in the front contact plug 170 can vary in various ways.

[0043] The backside contact plug 180 can be disposed under the second source / drain region 150B and the fourth source / drain region 150D. The backside contact plug 180 can pass through the semiconductor substrate 101 from the lower surface of the substrate insulating layer 190 and can be connected to the second source / drain region 150B and the fourth source / drain region 150D, respectively.

[0044] Each backside contact plug 180 can include a lower region having a lower surface coplanar with the lower surface of the substrate insulating layer 190. The lower region of the backside contact plug 180 can have a width decreasing upward as it passes through the substrate insulating layer 190. The backside contact plug 180 can include an intermediate region disposed on the lower region. The intermediate region can pass through the semiconductor substrate 101. The backside contact plug can include an upper region disposed on the intermediate region, the upper region being recessed from the second source / drain region 150B and the fourth source / drain region 150D. The lower region, the intermediate region, and the upper region can have a shape in which the width decreases upward along the Z direction. Each backside contact plug 180 has a slanted side surface connecting the upper surface and the lower surface. The side surface of the backside contact plug 180 can have a continuous inclination with respect to the lower region and the upper region, but the inventive concept is not necessarily limited thereto.

[0045] The backside contact plug 180 can be in contact with both the first epitaxial layer 152 and the second epitaxial layer 154. The backside contact plug 180 can be in contact with the first epitaxial layer 152 in the lower region of the second source / drain region 150B and the lower region of the fourth source / drain region 150D, and can be in contact with the second epitaxial layer 154 at an upper end thereof. The upper end of the backside contact plug 180 can be disposed at a higher height than the lower end of the second source / drain region 150B and the lower end of the fourth source / drain region 150D. For example, the backside contact plug 180 can further extend along the Z direction after passing into the second source / drain region 150B and the fourth source / drain region 150D. The upper end of each backside contact plug 180 can be at different heights from each other.

[0046] The backside contact plug 180 can overlap the entire first channel layer 141, the second channel layer 142, and the third channel layer 143 in the X direction. For example, the backside contact plug 180 can partially overlap the third channel layer 143 in the X direction. For example, the backside contact plug 180 can partially overlap the second channel layer 142 and the third channel layer 143 in the X direction.

[0047] The backside contact plug 180 can include the same material as that of the front contact plug 170, and can include a metallic material such as aluminum (Al), tungsten (W), or molybdenum (Mo). The backside contact plug 180 can further include a barrier layer around a surface thereof, and the barrier layer can include, for example, a metal nitride such as a titanium nitride (TiN) film, a tantalum nitride (TaN) film, or a tungsten nitride (WN) film.

[0048] The backside isolation regions BIL can be respectively disposed under the gate structures 160. The backside isolation regions BIL can have a linear shape and can overlap the gate structures 160 in the X-Y plane, and can extend in the Y direction. The backside isolation regions BIL can overlap a portion of the gate structures 160, and can be disposed in the form of a wall to physically and electrically separate the semiconductor substrate 101 disposed under one of the source / drain regions 150A to 150D from the adjacent semiconductor substrate 101.

[0049] Accordingly, the backside isolation regions BIL can overlap a portion of the gate structures 160 disposed on both sides of the source / drain regions 150A to 150D, but the inventive concept is not necessarily limited thereto. For example, the backside isolation regions BIL can be implemented in various ways, as long as the backside isolation regions BIL are structures that isolate the semiconductor substrate 101 disposed under the source / drain regions 150A to 150D from the semiconductor substrate 101 disposed under the adjacent source / drain regions 150A to 150D. However, when the backside contact plug 180 is disposed on the lower surface of the semiconductor substrate 101, the backside isolation regions BIL can preferably be disposed under the gate structures 160 to secure a sufficient separation distance from the backside contact plug 180.

[0050] The back-side isolation region (BIL) may include a lower region having a lower surface coplanar with the lower surface of the substrate insulating layer 190 and an upper region disposed on the lower region. The lower region may have a shape in which the width decreases upward along the Z direction. The upper region of the back-side isolation region BIL may extend through the semiconductor substrate 101. The upper surface of each back-side isolation region BIL (including the upper end of the upper region) may contact the lower surface of the lowermost gate dielectric layer 162 of the gate structure 160. The upper region of the back-side isolation region BIL may have a width smaller than that of the lower region and may have a shape in which the width narrows upward. Each back-side isolation region BIL may have a sloped side surface connecting the upper and lower surfaces. The side surface of the back-side isolation region BIL may have a continuous slope relative to the lower and upper regions, but is not necessarily limited to this.

[0051] When the back-side isolation region (BIL) divides the substrate structure into multiple active regions 105 with a line shape disposed below each gate structure 160, the back-side isolation region (BIL) can intersect with the first isolation region (IL1) in the XY direction and form a lattice shape.

[0052] The back-side isolation region (BIL) may also include an insulating material 196, such as at least one of oxides, nitrides, oxynitrides and carbon oxides, and such as silicon oxide or silicon nitride, but the inventive concept is not limited thereto.

[0053] The back-side isolation region BIL can be disposed in the intersection region where the back-side isolation region BIL intersects with the first isolation region IL1, and can have a shape in which the first isolation region IL1 is cut. However, when the back-side isolation region BIL and the first isolation region IL1 comprise the same material, the substrate structure can include lattice-shaped isolation regions defining the first source / drain regions 150A to the fourth source / drain regions 150D in the first region R1 and the second region R2, without boundaries. However, the inventive concept is not necessarily limited thereto.

[0054] When the back isolation region BIL overlaps with the gate structure 160 along the Z direction, the gate structure 160 may have a width measured along the X direction that is smaller than the second width W2, but the inventive concept is not limited thereto.

[0055] like Figure 2 As shown, the lower surface of the substrate insulating layer 190 can be coplanar with the lower surface of the back side isolation region BIL, the lower surface of the back side contact plug 180, the lower surface of the first isolation region IL1, and the lower surface of the second isolation region IL2.

[0056] The backside power structure 185 can be connected to a lower end or a lower surface of the backside contact plug 180. The backside power structure 185 together with the backside contact plug 180 can form a buried source / drain power network (BSPDN) for applying a power or a ground voltage, and can be referred to as a lower surface power rail or a buried power rail. For example, the backside power structure 185 can be a buried interconnection line extending in one direction (e.g., in a Y direction) under the backside contact plug 180, but the shape of the backside power structure 185 is not necessarily limited thereto. For example, in some example embodiments of the inventive concept, the backside power structure 185 can include a via region and / or a line region. The width of the backside power structure 185 can continuously increase downward, but the inventive concept is not necessarily limited thereto.

[0057] The backside power structure 185 can include an electrically conductive material, for example, at least one of tungsten (W), copper (Cu), aluminum (Al), cobalt (Co), ruthenium (Ru), titanium (Ti), and molybdenum (Mo).

[0058] The first interlayer insulating layer 192 can cover upper surfaces of the first to fourth source / drain regions 150A to 150D and an upper surface of the first isolation region IL1. The second interlayer insulating layer 194 can cover an upper surface of the first interlayer insulating layer 192 and an upper surface of the gate structure 160. The third interlayer insulating layer 198 can cover a lower surface of the substrate insulating layer 190 and can surround a side surface of the backside power structure 185.

[0059] The first, second, and third interlayer insulating layers 192, 194, and 198 can include at least one of an oxide, a nitride, and an oxynitride, and can include, for example, a low-k material. In some example embodiments of the inventive concept, each of the first, second, and third interlayer insulating layers 192, 194, and 198 can include a plurality of insulating layers.

[0060] The semiconductor device 100 can be packaged by vertically inverting Figure 2 the structure so that the backside power structure 185 is located thereon, but the package type of the semiconductor device 100 is not necessarily limited thereto. The source / drain regions 150 can be connected to the backside power structure 185 through the backside contact plug 180, thereby improving integration.

[0061] Hereinafter, a semiconductor device according to example embodiments of the inventive concept will be described with reference to Figures 3 to 6 wherein the same or similar components are designated by the same reference numerals as those described in connection with other figures. As for elements for which detailed descriptions have not been given, it can be assumed that they are at least similar to the corresponding elements already described in Figure 1 and Figure 2

[0062] Reference will now be made to Figure 3 ​In the semiconductor device 100a, the backside contact plug 180 can include a metal semiconductor compound layer 182 and a conductive layer 184. The metal semiconductor compound layer 182 can cover the outer surfaces of the middle region and the upper region of the backside contact plug 180. The metal semiconductor compound layer 182 can be disposed at a contact interface between the semiconductor substrate 101 and the second source / drain region 150B and the fourth source / drain region 150D.

[0063] The metal semiconductor compound layer 182 can be located on a portion of the upper surface and the side surface of the backside contact plug 180. The metal semiconductor compound layer 182 can be disposed in at least a region where the backside contact plug 180 contacts the second epitaxial layer 154. However, in example embodiments of the inventive concept, the extent of the metal semiconductor compound layer 182 need not be limited. The metal semiconductor compound layer 182 can be, for example, a metal silicide layer. The conductive layer 184 can fill a contact hole surrounded by the metal semiconductor compound layer 182. The conductive layer 184 can include a metal material, such as aluminum (Al), tungsten (W), or molybdenum (Mo). In example embodiments of the inventive concept, the number and arrangement of conductive layers included in the backside contact plug 180 can vary in various ways.

[0064] The conductive layer 184 can be in direct contact with the substrate insulating layer 190 in the lower region of the backside contact plug 180, and can be connected to the semiconductor substrate 101 and the second source / drain region 150B and the fourth source / drain region 150D through the metal semiconductor compound layer 182 in the middle region and the upper region of the backside contact plug 180.

[0065] The front contact plug 170 can also include a conductive layer 174 and a metal semiconductor compound layer 172. The metal semiconductor compound layer 172 can be disposed in a lower region of the front contact plug 170 that contacts the source / drain regions 150A and 150C, and the conductive layer 174 can extend vertically from an upper surface of the front contact plug 170 to the lower region of the front contact plug 170. The conductive layer 174 can be in direct contact with the first interlayer insulating layer 192 and the second interlayer insulating layer 194 disposed on the upper portions of the source / drain regions 150A and 150C. The metal semiconductor compound layer 172 can be, for example, a metal silicide layer. The conductive layer 174 can fill a contact hole surrounded by the metal semiconductor compound layer 172. The conductive layer 174 can include, for example, a metal material, such as aluminum (Al), tungsten (W), or molybdenum (Mo).

[0066] Reference Figure 4 , the semiconductor device 100b can be similar to the semiconductor device 100a except for the shape of each backside contact plug 180. Figure 2 and Figure 3The semiconductor device 100c can include the same elements as the semiconductor device 100a. As for elements that have not been described in detail, it can be assumed that the elements are at least similar to the corresponding elements already described in Figure 2 and Figure 3 .

[0067] The backside contact plug 180 can include a curved portion between the intermediate region 184b and the upper region 184a.

[0068] The curved portion of the backside contact plug 180 can have a shape in which the width of the lower end of the upper region 184a that contacts the source / drain regions 150B and 150D decreases more rapidly than the width of the upper end of the intermediate region 184b. For example, the lower portion of the upper region 184a is narrower than the upper portion of the intermediate region 184b, and the curved portion is formed at a point where the width changes rapidly between the two portions. Thus, the backside contact plug 180 can include a curved portion whose width decreases from its lower surface to its upper surface, which decreases discontinuously between the intermediate region 184b and the upper region 184a. As shown in Figure 3 When the metal-semiconductor compound layer 182 is included, the metal-semiconductor compound layer 182 can surround the curved portion.

[0069] Referring to Figure 5 , the semiconductor device 100c can further include a gate isolation region IL3.

[0070] The gate isolation region IL3 can be disposed in a region in which the gate structure 160 is disposed, on the X-Y plane. For example, the gate isolation region IL3 can have a linear shape extending along the Y direction to be parallel to the adjacent gate structure 160. The gate isolation region IL3 can be disposed between the adjacent gate structures 160.

[0071] The gate isolation region IL3 can extend from the gate structure 160 toward the substrate insulating layer 190 in a region in which the gate structure 160 is disposed. The gate isolation region IL3 can pass through the first interlayer insulating layer 192 and the substrate insulating layer 190. Thus, the gate isolation region IL3 can be a wall-shaped structure that passes through the semiconductor device 100c along the Z direction and extends in a linear shape in the Y direction. At least one gate isolation region IL3 can be disposed in the first region R1 or the second region R2. In the gate isolation region IL3, when the source and the drain of the adjacent transistors are electrically isolated from each other, the transistors can be configured such that the intermediate gate structure 160 is connected to the channel structure 140 and the semiconductor substrate 101 below, thereby forming the source / drain regions 150A to 150D, respectively. The adjacent transistors each having the gate structure 160 on both sides can be electrically isolated from each other by the gate isolation region IL3.

[0072] The gate isolation region IL3 can be disposed parallel to the backside isolation region BIL disposed under the gate structure 160 disposed on both sides thereof. However, a length of the gate isolation region IL3 measured along the Z direction can be greater than a length of the backside isolation region BIL measured along the Z direction.

[0073] An upper surface of the gate isolation region IL3 can be coplanar with an upper surface of the first interlayer insulating layer 192 and an upper surface of the gate structure 160, and a lower surface of the gate isolation region IL3 can be coplanar with a lower surface of the substrate insulating layer 190. Accordingly, the lower surface of the gate isolation region IL3 can be coplanar with a lower surface of the backside isolation region BIL and a lower surface of the backside contact plug 180. A width of the gate isolation region IL3 can gradually narrow from the upper surface to the lower surface, with a sloped side surface connecting the upper surface and the lower surface.

[0074] In an upper region of the gate isolation region IL3, the side surface can be in contact with the gate spacer layer 164, but the inventive concept is not necessarily limited thereto. The gate isolation region IL3 can include an insulating material, and can include at least one of an oxide, a nitride, an oxynitride, or a carbon oxide. For example, silicon oxide or silicon nitride can be included, but the inventive concept is not necessarily limited thereto.

[0075] The gate isolation region IL3 can include the same material as the first isolation region IL1 and the second isolation region IL2. A lower surface of the gate isolation region IL3 can be disposed at the same height as a lower surface of the first isolation region IL1 and a lower surface of the second isolation region IL2, and an upper surface of the gate isolation region IL3 can be disposed at the same height as or a higher height than an upper surface of the first isolation region IL1 and an upper surface of the second isolation region IL2. For example, a length of the gate isolation region IL3 measured along the Z direction can be greater than a length of the first isolation region IL1 measured along the Z direction and a length of the second isolation region IL2 measured along the Z direction.

[0076] Reference Figure 6 In the semiconductor device 100d, the front contact plug 170 can not be disposed, and the backside contact plug 180 can be disposed in the adjacent source / drain regions 150A to 150D, respectively.

[0077] The backside contact plugs 180 can be disposed in the first source / drain region 150A, the second source / drain region 150B, the third source / drain region 150C, and the fourth source / drain region 150D disposed at both sides of the gate structure 160, such that the backside contact plugs 180 for applying a signal to the first source / drain region 150A, the second source / drain region 150B, the third source / drain region 150C, and the fourth source / drain region 150D can be disposed in the same direction as the first source / drain region 150A to the fourth source / drain region 150D. As described, the backside contact plugs 180 can pass through the lower surface of the semiconductor device 100d. For example, the backside contact plugs 180 passing through the lower surface of the semiconductor device 100d can avoid electrical contact with the gate structure 160, thereby preventing shorting with the gate structure 160.

[0078] The plurality of backside contact plugs 180 formed in the first source / drain region 150A, the second source / drain region 150B, the third source / drain region 150C, and the fourth source / drain region 150D, respectively, can have the same shape, and the shape can be applied to one of the backside contact plugs 180. Figures 2 to 4 One of the two backside contact plugs 180 among the backside contact plugs 180 can be connected to the backside power structure 185.

[0079] Figures 7A to 7I FIGS. 1 to 6 are diagrams illustrating sequential processes in a method of manufacturing a semiconductor device according to an example embodiment of the inventive concept. In Figures 7A to 7I In Figure 1 and Figure 2 an example embodiment of the inventive concept of a method of manufacturing a semiconductor device will be described. Figures 7A to 7I respectively, cross-sectional views taken along lines I-I' and II-II' of Figure 1

[0080] Referring to Figure 7A The sacrificial layer 118 and the first channel layer 141, the second channel layer 142, and the third channel layer 143 can be alternately stacked on the semiconductor substrate 101. For example, the sacrificial layer 118 can be stacked between the first channel layer 141, the second channel layer 142, and the third channel layer 143.

[0081] The semiconductor substrate 101 can include silicon (Si), germanium (Ge), or silicon germanium (SiGe). The semiconductor substrate 101 can include a bulk wafer, an epitaxial layer, a silicon-on-insulator (SOI) layer, or a semiconductor-on-insulator (SeOI) layer.

[0082] The semiconductor substrate 101 can have a thickness greater than Figure 2 ​The first thickness t1 of the semiconductor substrate 101 is shown as an initial thickness ts. The initial thickness ts of the semiconductor substrate 101 can be greater than Figure 2 The sum of the first thickness t1 and the second thickness t2 of the substrate insulating layer 190 is shown.

[0083] The sacrificial layer 118 can be replaced with a gate dielectric layer 162 and a gate electrode 165 by a subsequent process, as shown. Figure 2 The sacrificial layer 118 can include a material having etching selectivity with respect to each of the first channel layer 141, the second channel layer 142, and the third channel layer 143. For example, the sacrificial layer 118 can be selectively etched without significantly affecting the first channel layer 141, the second channel layer 142, and the third channel layer 143. The first channel layer 141, the second channel layer 142, and the third channel layer 143 can include a different material from that of the sacrificial layer 118. The sacrificial layer 118 and the first channel layer 141, the second channel layer 142, and the third channel layer 143 can include different semiconductor materials including, for example, at least one of silicon (Si), silicon germanium (SiGe), and germanium (Ge), and can include impurities or can not include impurities. For example, the sacrificial layer 118 can include silicon germanium (SiGe), and the first channel layer 141, the second channel layer 142, and the third channel layer 143 can include silicon (Si).

[0084] The sacrificial layer 118 and the first channel layer 141, the second channel layer 142, and the third channel layer 143 can be formed by performing an epitaxial growth process from the semiconductor substrate 101. In some example embodiments of the inventive concept, the number of channel layers 141, 142, and 143 stacked alternately with the sacrificial layer 118 can vary in various ways. The first isolation region IL1 and the second isolation region IL2 can be formed within the first channel layer 141, extending to a predetermined depth in the semiconductor substrate 101.

[0085] The first isolation region IL1 and the second isolation region IL2 can be formed by etching a region of the semiconductor substrate 101 other than the active region 105 in which the first to fourth source / drain regions 150A to 150D and the channel structure 140 are disposed. Then, a trench having a predetermined depth is formed, and an insulating material can be stacked and can fill the trench. In this case, the trench can be formed such that the upper width of the first isolation region IL1 is greater than the upper width of the second isolation region IL2, and the depth of the trench can differ from each other depending on the upper width of the trench.

[0086] Compared to the trench corresponding to the first isolation region IL1, the trench corresponding to the second isolation region IL2 having a narrower upper width can have a shallower depth. The first isolation region IL1 and the second isolation region IL2 can be formed by applying an insulating material 102 that fills each trench.

[0087] Accordingly, an initial length ds of the first isolation region IL1 measured along the Z direction can be greater than an initial length dt of the second isolation region IL2 measured along the Z direction. The initial length ds of the first isolation region IL1 and the initial length dt of the second isolation region IL2 can be greater than a length d1 of each of the first isolation region IL1 and the second isolation region IL2 measured along the Z direction. Figure 2

[0088] The initial lengths ds and dt (i.e., lengths measured along the Z direction) of the first isolation region IL1 and the second isolation region IL2 can be greater than the length d1 of each of the first isolation region IL1 and the second isolation region IL2 as illustrated. Figure 2 In this case, the width of the first isolation region IL1 and the width of the second isolation region IL2 can narrow from the upper surface to the lower surface. The lower surface of the first isolation region IL1 and the lower surface of the second isolation region IL2 can be disposed at a height higher than the lower surface of the semiconductor substrate 101. Accordingly, the lower surface of the first isolation region IL1 and the lower surface of the second isolation region IL2 can not be exposed to the lower surface of the semiconductor substrate 101. A predetermined separation distance td can be maintained between the lower surface of the first isolation region IL1 having a greater length ts and the lower surface of the semiconductor substrate 101.

[0089] Referring to Figure 7B The first isolation region IL1 and the second isolation region IL2 can be etched to the height of the upper surface of the semiconductor substrate 101 such that the upper surface of the first isolation region IL1 and the upper surface of the second isolation region IL2 can be aligned with the upper surface of the semiconductor substrate 101. The initial lengths ds and dt of the first isolation region IL1 and the second isolation region IL2 can be reduced as illustrated, and can be referred to as reduced initial lengths ds' and dt'. Figure 7B

[0090] Subsequently, a portion of the sacrificial layer 118, a portion of the first channel layer 141, the second channel layer 142, and the third channel layer 143, and a portion of the substrate 101 can be removed, and an active structure can be formed. The sacrificial gate structure 200 and the gate spacer layer 164 can be formed on the active structure.

[0091] ​​The active structure can include the sacrificial layers 118 and the first, second, and third channel layers 141, 142, and 143 stacked alternately with each other, and can further include the active regions 105 which can protrude from the substrate 101 by removing a portion of the substrate 101. The active structure can be formed to have a linear shape extending in one direction (e.g., the X direction), and can be spaced apart from each other along the Y direction. The first and second isolation regions IL1 and IL2 can be exposed between two active structures and can be spaced apart from each other. The active regions 105 can include different impurities in the first and second regions R1 and R2. However, in some example embodiments of the inventive concept, the active regions 105 can not include impurities.

[0092] The sacrificial gate structure 200 can be a sacrificial structure formed in a region in which the gate dielectric layer 162 and the gate electrode 165 are disposed on the channel structure 140 by a subsequent process, as shown. Figure 2 The sacrificial gate structure 200 can have a linear shape extending along a single direction while intersecting the active structure. For example, the sacrificial gate structure 200 can extend along the Y direction and can cut the first isolation region IL1 between the first and second regions R1 and R2.

[0093] Each of the sacrificial gate structures 200 can include the first and second sacrificial gate layers 202 and 205 stacked sequentially, and a mask pattern layer 206. The first and second sacrificial gate layers 202 and 205 can be patterned using the mask pattern layer 206. The first and second sacrificial gate layers 202 and 205 can be an insulating layer and a conductive layer, respectively, but the inventive concept is not necessarily limited thereto, and the first and second sacrificial gate layers 202 and 205 can be formed as a single layer. For example, the first sacrificial gate layer 202 can include silicon oxide, and the second sacrificial gate layer 205 can include polysilicon. The mask pattern layer 206 can include silicon oxide and / or silicon nitride.

[0094] The gate spacer layer 164 can be formed on both sidewalls of the sacrificial gate structure 200. The gate spacer layer 164 can be formed of a low-k material, and can include at least one of SiO, SiN, SiCN, SiOC, SiON, and SiOCN. Accordingly, the gate spacer layer 164 can be disposed such that a lower surface thereof is in contact with the first isolation region IL1.

[0095] Referring to Figure 7C The recessed regions can be formed by partially removing the sacrificial layers 118 and the first, second, and third channel layers 141, 142, and 143 exposed by the sacrificial gate structure 200.

[0096] First, the exposed sacrificial layer 118 and portions of the first, second, and third channel layers 141, 142, and 143 can be removed using the sacrificial gate structures 200 and the gate spacer layer 164 as a mask, and a recessed region can be formed by partially removing the active region 105. Accordingly, the first, second, and third channel layers 141, 142, and 143 can form a channel structure 140 having a finite length along the X direction.

[0097] The active region 105 exposed through the recessed region can be further removed to form an extended recessed region, and first to fourth source / drain regions 150A, 150B, 150C, and 150D can be formed.

[0098] The first to fourth source / drain regions 150A, 150B, 150C, and 150D can be grown and formed from side surfaces of the channel structure 140 and side surfaces of the active region 105 using a selective epitaxy process. The first and second source / drain regions 150A and 150B and the third and fourth source / drain regions 150C and 150D can be formed using different processes and can have different compositions. The first to fourth source / drain regions 150A, 150B, 150C, and 150D can include impurities by in-situ doping. Each of the first to fourth source / drain regions 150A, 150B, 150C, and 150D can include a first epitaxial layer 152 and a second epitaxial layer 154. The first and second epitaxial layers 152 and 154 can include non-silicon elements having different concentrations.

[0099] Reference Figure 7D A first interlayer insulating layer 192 can be formed, and the sacrificial layer 118 and the sacrificial gate structures 200 can be removed.

[0100] The first interlayer insulating layer 192 can be formed by forming an insulating film covering the sacrificial gate structures 200, the first to fourth source / drain regions 150A, 150B, 150C, and 150D, and the first isolation region IL1 and performing a planarization process.

[0101] The sacrificial layer 118 and the sacrificial gate structures 200 can be selectively removed with respect to the gate spacer layer 164, the first interlayer insulating layer 192, the first to fourth source / drain regions 150A, 150B, 150C, and 150D, and the channel structure 140. First, the sacrificial gate structures 200 can be removed to form an upper gap region UR. Then, the sacrificial layer 118 exposed through the upper gap region UR can be removed to form a lower gap region LR. For example, when the sacrificial layer 118 includes silicon germanium (SiGe) and the channel structure 140 includes silicon (Si), the sacrificial layer 118 can be selectively removed by performing a wet etching process.

[0102] Referring to Figure 7E The gate dielectric layer 162 and the gate electrode 165 can be formed to form the gate structure 160, and the second interlayer insulating layer 194 and the front contact plug 170 can be formed.

[0103] The gate dielectric layer 162 and the gate electrode 165 can fill the upper gap region UR and the lower gap region LR. The gate dielectric layer 162 can conformally cover the inner surfaces of the upper gap region UR and the lower gap region LR. After the gate electrode 165 completely fills the upper gap region UR and the lower gap region LR, the gate electrode 165 can be removed together with the gate dielectric layer 162 and the gate spacer layer 164 in the upper gap region UR from the upper portion thereof to a predetermined depth, and the gate cap layer 166 can be formed.

[0104] The second interlayer insulating layer 194 can be formed on the gate structure 160. After the second interlayer insulating layer 194 is formed, the front contact plug 170 can be formed through the second interlayer insulating layer 194 and the first interlayer insulating layer 192.

[0105] Referring to Figure 7F The semiconductor substrate 101 can be partially removed.

[0106] First, in order to perform a process on the lower surface of the substrate 101, a carrier substrate SUB can be formed on the second interlayer insulating layer 194, and the entire structure can be inverted to perform the following processes.

[0107] The semiconductor substrate 101 can be thinned to have a first thickness t1 by performing dry etching from the lower surface of the semiconductor substrate 101. A first isolation region IL1 having a lower surface spaced apart from the lower surface of the semiconductor substrate 101 by a predetermined separation distance td and a second isolation region IL2 having a lower surface at a height higher than that of the lower surface of the first isolation region IL1 can remain unetched. The first isolation region IL1 and the second isolation region IL2 can remain to have initial lengths ds' and dt' reduced due to selective etching of the semiconductor substrate 101.

[0108] Accordingly, the lower surface of the first isolation region IL1 and the lower surface of the second isolation region IL2 can protrude upward from the lower surface of the thinned semiconductor substrate 101 during the process, and the protrusion lengths of the first isolation region IL1 and the second isolation region IL2 can be different from each other. By the selective dry etching of the semiconductor substrate 101, a residual portion can be formed between the side surfaces of the first isolation region IL1 and the second isolation region IL2 and the lower surface of the semiconductor substrate 101, but the inventive concept is not necessarily limited thereto.

[0109] Referring toFigure 7G A substrate insulating layer 190 can be formed on the exposed lower surface of the semiconductor substrate 101, and the substrate insulating layer 190 can be thinned to have a second thickness t2.

[0110] For example, the substrate insulating layer 190 can be deposited to have a sufficient thickness to cover the lower surfaces of the protruding first isolation regions IL1 and the protruding second isolation regions IL2. The substrate insulating layer 190 can be formed by stacking silicon nitride, but the inventive concept is not necessarily limited thereto. Subsequently, the substrate insulating layer 190 can be thinned to have a second thickness t2 by performing a planarization process, and the lengths of the first isolation regions IL1 and the lengths of the second isolation regions IL2 can also be reduced according to the etching. Accordingly, the lower surfaces of the first isolation regions IL1 and the lower surfaces of the second isolation regions IL2 can be exposed at the lower surface of the substrate insulating layer 190. Figure 2 The second thickness t2 is shown, and the lengths of the first isolation regions IL1 and the lengths of the second isolation regions IL2 can also be reduced according to the etching. Accordingly, the lower surfaces of the first isolation regions IL1 and the lower surfaces of the second isolation regions IL2 can be exposed at the lower surface of the substrate insulating layer 190.

[0111] In this case, the thinning can be performed using chemical mechanical polishing (CMP), and thus the first isolation regions IL1 and the second isolation regions IL2 can have a first length d1 from the upper surface of the semiconductor substrate 101. The first length d1 can be equal to or similar to the sum of the first thickness t1 of the semiconductor substrate 101 and the second thickness t2 of the substrate insulating layer 190.

[0112] Referring to FIG. 1A, Figure 7H A backside isolation region BIL can be formed.

[0113] First, a trench extending from the lower surface of the substrate insulating layer 190 to the lower surface of the channel structure 140 can be formed to be aligned with the gate structure 160, respectively. At least a portion of the trench can overlap the gate structure 160 along the Z direction, and can be formed in a linear shape. The trench for the backside isolation region BIL can cross the second isolation regions IL2 along the Y direction. An insulating material 196 can be over-deposited to fill the corresponding trench and cover the upper surface of the substrate insulating layer 190. The insulating material 196 can be silicon oxide or silicon nitride, but the inventive concept is not necessarily limited thereto.

[0114] Referring to FIG. 1A, Figure 7I A backside contact plug 180 can be formed.

[0115] The planarization can be used to remove the over-deposited insulating material 196 and expose the lower surface of the substrate insulating layer 190, thereby exposing the lower surface of the first isolation region IL1 and the lower surface of the second isolation region IL2 and the lower surface of the backside isolation region BIL. As described above, the contact holes reaching the second source / drain region 150B and the fourth source / drain region 150D can be formed while exposing the lower surface of the substrate insulating layer 190. When the contact holes are formed, the backside contact plug 180 can be formed by forming a conductive layer to fill the contact holes.

[0116] Subsequently, referring to Figure 2 the third interlayer insulating layer 198 can be formed, and a portion of the third interlayer insulating layer 198 can be removed to form the backside power structure 185 connected to the backside contact plug 180. Accordingly, the semiconductor device 100 of Figure 1 and Figure 2 can be manufactured.

[0117] According to the example embodiments of the inventive concept, when the backside contact plug 180 is formed according to the transistor property, a portion of the semiconductor substrate 101 can be preserved, and the lower insulating layer can be formed to optimize the process, thereby providing the semiconductor device 100 having improved electrical properties and increased process yield.

[0118] While example embodiments have been shown and described above, it will be clear to those of ordinary skill in the art that modifications and changes can be made without departing from the scope of the inventive concept as defined by the appended claims.

Claims

1. A semiconductor device, the semiconductor device comprising: A substrate, the substrate including a first region and a second region spaced apart from each other along a first direction, wherein the substrate includes an upper surface and a lower surface; A substrate insulating layer, the substrate insulating layer being disposed on the lower surface of the substrate; A first isolation region extends through the substrate between the first region and the second region, and the first isolation region extends toward the substrate insulating layer; A gate electrode is disposed in the first region and the second region, and is located on the upper surface of the substrate; A plurality of channel layers, the plurality of channel layers being spaced apart from each other along a second direction perpendicular to the upper surface of the substrate and surrounded by the gate electrode, wherein the plurality of channel layers are disposed on the first region and the second region; Source / drain regions are disposed on opposite sides of the gate electrode, wherein the source / drain regions are connected to the plurality of channel layers; A back-side contact plug extending from the lower surface of the substrate insulating layer along the second direction to at least one of the source / drain regions, wherein the back-side contact plug is connected to the at least one of the source / drain regions; and A back-side isolation region extends through the substrate and the substrate insulating layer, and the back-side isolation region separates the substrate.

2. The semiconductor device according to claim 1, wherein, The lower surface of the back-side isolation region, the lower surface of the back-side contact plug, and the lower surface of the substrate insulating layer are coplanar with each other.

3. The semiconductor device according to claim 1, wherein, The lower surface of the substrate insulating layer and the lower surface of the first isolation region are coplanar.

4. The semiconductor device according to claim 1, wherein, The substrate has a first thickness. The substrate insulating layer has a second thickness, and The second thickness is equal to or greater than the first thickness.

5. The semiconductor device according to claim 4, wherein, The second thickness is 1 to 1.2 times the first thickness.

6. The semiconductor device according to claim 4, wherein, The back-side isolation region has a vertical length greater than the first thickness of the substrate.

7. The semiconductor device according to claim 4, wherein, The first isolation region has a vertical length greater than the first thickness of the substrate.

8. The semiconductor device according to claim 1, wherein, The back contact plug has a vertical length that is greater than both the vertical length of the first isolation region and the vertical length of the back isolation region.

9. The semiconductor device according to claim 1, wherein, The back-side isolation region has a linear shape, and at least a portion of the back-side isolation region overlaps with the gate electrode along the second direction.

10. The semiconductor device according to claim 1, wherein, The width of the first isolation region in the first direction is greater than the length of the gate electrode measured along a third direction, and the third direction is perpendicular to both the first and second directions.

11. The semiconductor device according to claim 1, further comprising: A second isolation region is disposed in the first region and the second region, wherein the second isolation region extends between the source / drain regions along a third direction perpendicular to the first direction to separate the substrate.

12. The semiconductor device according to claim 11, wherein, The width of the second isolation region in the first direction is smaller than the width of the first isolation region in the first direction.

13. The semiconductor device according to claim 12, wherein, The length of the second isolation region in the second direction is equal to the length of the first isolation region in the second direction.

14. The semiconductor device according to claim 1, wherein, The source / drain region includes: A first epitaxial layer, the first epitaxial layer covering the side surfaces of the plurality of channel layers, and the first epitaxial layer having a first impurity concentration; and A second epitaxial layer is disposed on the first epitaxial layer, and the second epitaxial layer has a second impurity concentration that is higher than the first impurity concentration.

15. The semiconductor device according to claim 14, wherein, The back contact plug passes through the first epitaxial layer, and the back contact plug includes an upper end that contacts the second epitaxial layer.

16. The semiconductor device according to claim 1, wherein, The back-side contact plug includes: A conductive layer that penetrates the substrate insulating layer and the substrate, and extends into the source / drain region; and A metal-semiconductor compound layer is disposed between the conductive layer and the source / drain region and between the conductive layer and the substrate, and the metal-semiconductor compound layer is the upper end of the back contact plug.

17. The semiconductor device according to claim 1, wherein, The first region is an nFET region, and the second region is a pFET region.

18. A semiconductor device, the semiconductor device comprising: A semiconductor substrate having an upper surface and a lower surface; A substrate insulating layer is disposed on the lower surface of the semiconductor substrate; Gate electrodes, the gate electrodes being disposed on the upper surface of the semiconductor substrate and extending along a first direction, and the gate electrodes being spaced apart from each other; A plurality of channel layers, the plurality of channel layers being spaced apart from each other along a second direction perpendicular to the upper surface of the semiconductor substrate and disposed on the upper surface of the semiconductor substrate, the plurality of channel layers being surrounded by the gate electrode; The source / drain regions are disposed on opposite sides of the gate electrode, and the source / drain regions include a first source / drain region and a second source / drain region spaced apart from each other. as well as A back-side contact plug extending from the lower surface of the substrate insulating layer along the second direction, and the back-side contact plug being recessed into at least one of the first source / drain region and the second source / drain region. Wherein, the thickness of the semiconductor substrate is equal to or less than the thickness of the substrate insulating layer.

19. The semiconductor device of claim 18, further comprising: A back-side isolation region extends from the lower surface of the substrate insulating layer toward the upper surface of the semiconductor substrate and electrically isolates the semiconductor substrate. The lower surface of the back-side isolation area and the lower surface of the back-side contact plug are coplanar.

20. A semiconductor device, the semiconductor device comprising: A semiconductor substrate having an upper surface and a lower surface; A substrate insulating layer is disposed on the lower surface of the semiconductor substrate; Gate electrodes, the gate electrodes being disposed on the upper surface of the semiconductor substrate and extending along a first direction, and the gate electrodes being spaced apart from each other; The source / drain regions are disposed on opposite sides of the gate electrode, and the source / drain regions include a first source / drain region and a second source / drain region spaced apart from each other. An upper insulating layer is disposed on the source / drain region; A front contact plug that passes through the upper insulating layer and is connected to one of the first source / drain region and the second source / drain region; A back-side contact plug extends from the lower surface of the substrate insulating layer along a second direction perpendicular to the upper surface of the semiconductor substrate, and the back-side contact plug is connected to the other of the first source / drain region and the second source / drain region; A back-side power structure, which is connected to the back-side contact plug and configured to transmit power; as well as A back-side isolation region that extends through the semiconductor substrate and the substrate insulating layer. The back-side isolation region separates the semiconductor substrate, and The lower surface of the back-side isolation region, the lower surface of the back-side contact plug, and the lower surface of the substrate insulating layer are coplanar with each other.

Images