Method for preparing heterojunction cell by tubular PECVD (Plasma Enhanced Chemical Vapor Deposition) and heterojunction cell
The method of preparing heterojunction solar cells by tubular PECVD has solved the problems of equipment uniformity and high cost, and has achieved efficient silicon wafer surface passivation and low-cost production, thus promoting the industrialization of heterojunction solar cells.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-17
- Publication Date
- 2026-03-27
AI Technical Summary
Tubular PECVD equipment suffers from poor uniformity and difficulty in preparing intrinsic amorphous silicon thin films with high microstructure factors when fabricating heterojunction solar cells. In addition, the equipment cost is high, which limits the large-scale industrialization of heterojunction solar cells.
The method of preparing heterojunction cells using tubular PECVD involves preparing a dense silicon oxide protective film, a passivation layer, and a transparent conductive oxide film on the surface of a silicon wafer, followed by metallization using low-temperature silver paste printed on a screen, to form a planar or micro-textured heterojunction cell structure, thus replacing plate-type PECVD equipment.
It improves the microstructure factor of intrinsic amorphous silicon thin films, enhances the passivation effect of silicon wafers, reduces equipment costs, improves the open-circuit voltage and conversion efficiency of cells, and reduces the footprint and production costs.
Smart Images
Figure CN121751799A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The application belongs to the technical field of heterojunction solar cells, and particularly relates to a method for preparing a heterojunction cell by using a tubular PECVD and the heterojunction cell. BACKGROUND
[0002] The crystalline silicon / amorphous silicon heterojunction solar cell (HJT) has the advantages of high open-circuit voltage, high conversion efficiency, low preparation temperature, simple process flow, and high bifaciality, and these advantages make the crystalline silicon / amorphous silicon heterojunction solar cell gradually become one of the mainstreams of current mass production of high-efficiency cells.
[0003] The heterojunction cell route has been subject to the problem of excessively high cost, and has not realized large-scale expansion. In recent years, with the development and introduction of silicon wafer thinning, indium-free target material, 0BB and silver-coated copper paste and other technologies into mass production, the production cost of the heterojunction cell has been greatly reduced, and even in the process of continuously rising silver prices, it is expected to be lower than other technical routes.
[0004] The excessively high investment cost of production equipment is still a key factor restricting the development of the heterojunction cell. Although many domestic equipment manufacturers continue to make efforts to help reduce the cost of heterojunction equipment, compared with other cell technical routes, the cost of the production equipment of the heterojunction cell is still high, especially the plate-type PECVD equipment, the investment cost of which is more than 150 million yuan / GW, accounting for 50% of the total equipment investment cost. In addition to the high equipment cost, the plate-type PECVD also has other problems. It uses a tray to load silicon wafers for film plating, has small capacity, and uses a series mode for the film plating chamber, which occupies a large area. The tubular PECVD can well solve the above problems. The tubular PECVD has lower equipment cost, smaller area occupation, and larger capacity, and is more conducive to the large-scale industrialization development of the heterojunction cell. However, the tubular PECVD also has some shortcomings. It is difficult to prepare a uniform and high-microstructure-factor intrinsic amorphous silicon film (i-a-Si:H).
[0005] There are a large number of dangling bonds on the surface of the crystalline silicon substrate. These dangling bonds are easy to capture photo-generated carriers to cause serious surface recombination, resulting in a decrease in the minority carrier lifetime of the silicon wafer and a decrease in the efficiency of the cell wafer. Therefore, the heterojunction cell needs to first prepare an i0 layer (microstructure factor range 55%-70%) with a high microstructure factor on the surface of the textured silicon wafer in the CVD process. The i0 film layer structure with a high microstructure factor is relatively loose, which can inhibit the generation of an epitaxial layer along the silicon substrate lattice direction of the amorphous silicon film. Meanwhile, the i0 layer has a high hydrogen content, which can have a good passivation effect on the dangling bonds on the surface of the silicon substrate. Thus, the minority carrier lifetime of the silicon wafer is significantly improved, and the open-circuit voltage and conversion efficiency of the cell are improved.
[0006] Now generally adopted plate type PECVD to prepare intrinsic amorphous silicon thin film of heterojunction cell, its advantage lies in can quickly, simply prepare high power pure silane process.
[0007] In the preparation of intrinsic amorphous silicon thin film i0 layer, the main problem of tubular PECVD is:
[0008] 1, the uniformity of pure silane process is poor, the film coating effect of furnace mouth, furnace and furnace tail is very different;
[0009] 2, using intermittent discharge mode, the ignition time is much smaller than the off time, in the off process, the silicon atoms on the surface of the film relax, hydrogen atoms appear to escape phenomenon, the degree of lattice mismatch of the film gradually weakens, the film growth tends to a lower microstructure factor direction, it is difficult to generate epitaxial layer on the surface of silicon substrate, it is difficult to have good passivation effect on the dangling bond on the surface of silicon substrate.
[0010] It should be noted that the above information disclosed in the background art section of the present application is only used to understand the background art of the present application, and therefore, the above description is not considered to constitute information of the prior art. SUMMARY
[0011] The embodiments of the present disclosure at least provide a method for preparing a heterojunction cell by tubular PECVD, and a heterojunction cell.
[0012] In a first aspect, embodiments of this disclosure provide a method for fabricating heterojunction solar cells using tubular PECVD, comprising the following steps: S1, pre-cleaning an N-type monocrystalline silicon wafer for later use; S2, using a tubular diffusion furnace to getter the N-type monocrystalline silicon wafer until the sheet resistance of the wafer is 30-70 ohms; S3, using a tank cleaning agent to clean and texturize the texturized N-type monocrystalline silicon wafer until the base size of the textured pyramid is 2-5 μm; S4, using tubular PECVD to prepare silicon oxide on the front side of the texturized N-type monocrystalline silicon wafer to form a dense silicon oxide protective film; S5, performing alkaline solution polishing on the back side of the N-type monocrystalline silicon wafer in S4 to remove the tips of the textured pyramids; S6, performing acid washing on the oxide layer on the front side of the N-type monocrystalline silicon wafer in S5 to obtain a normally texturized front side of the silicon wafer and a back side of the silicon wafer with a planar or near-planar microtexture; S7, a passivation layer is deposited on the back side of the N-type monocrystalline silicon wafer in S6 using tubular PECVD to obtain a back passivation layer; S8, a passivation layer is deposited on the front side of the N-type monocrystalline silicon wafer in S7 using tubular PECVD to obtain a front passivation layer; S9, an N-type microcrystalline doped layer is deposited on the front passivation layer of the N-type monocrystalline silicon wafer in S8 using tubular PECVD; S10, an intrinsic microcrystalline layer, a functional layer, and a P-type microcrystalline doped layer are deposited on the back passivation layer of the N-type monocrystalline silicon wafer in S9 using tubular PECVD; S11, a transparent conductive layer is deposited on both the front and back sides of the N-type monocrystalline silicon wafer in S10 using PVD to obtain a transparent conductive oxide film; S12, low-temperature silver paste is screen-printed on both the front and back sides of the N-type monocrystalline silicon wafer in S11, and after drying and curing, the metallization of the microcrystalline silicon heterojunction solar cell is completed.
[0013] In one optional embodiment, the thickness of the silicon oxide protective film in S4 is 1 to 5 nm.
[0014] In one alternative implementation, after removing the pyramid tip in S5, the pyramid base size of the velvet surface is greater than 2 μm.
[0015] In one optional embodiment, the passivation power supply frequency in S7 is 500kHz to 13.56MHz; the passivation layer stack coating includes a first passivation layer on the back side, a second passivation layer on the back side, and a third passivation layer on the back side; the thickness of the first passivation layer on the back side is 2 to 6nm, the coating temperature is 100 to 250℃, the silane flow rate is 1000 to 8000 sccm, the argon to silane flow ratio is 1 to 20:1, the pressure is 0.3 to 2.5 torr, the power is 2500 to 8000W, and the duty cycle is 10:50 to 300; the thickness of the second passivation layer on the back side is 2 to 5nm. The coating temperature is 100–250℃, the silane flow rate is 1000–8000 sccm, the argon to silane flow rate ratio is 1–20:1, the pressure is 0.3–2.5 torr, the power is 2500–8000 W, and the duty cycle is 10:50–300; the thickness of the third passivation layer on the back side is 3–10 nm, the coating temperature is 100–250℃, the silane flow rate is 300–3000 sccm, the hydrogen to silane flow rate ratio is 8–20:1, the pressure is 1–3.5 torr, the power is 2500–8000 W, and the duty cycle is 10:50–300.
[0016] In one optional embodiment, the passivation power supply frequency in S8 is 500kHz to 13.56MHz; the passivation layer stack coating includes a first passivation layer, a second passivation layer, and a third passivation layer on the front side; the thickness of the first passivation layer on the front side is 1 to 4nm, the coating temperature is 100 to 250℃, the silane flow rate is 1000 to 8000 sccm, the pressure is 0.3 to 2.5 torr, the power is 2500 to 8000W, and the duty cycle is 10:50 to 300; the thickness of the second passivation layer on the front side is 1 to 3nm. The coating temperature is 100–250℃, the silane flow rate is 1000–8000 sccm, the pressure is 0.3–2.5 torr, the power is 2500–8000 W, and the duty cycle is 10:50–300; the thickness of the third passivation layer on the front side is 3–6 nm, the coating temperature is 100–250℃, the silane flow rate is 300–3000 sccm, the hydrogen to silane flow ratio is 10–30:1, the pressure is 1–3.5 torr, the power is 2500–8000 W, and the duty cycle is 10:50–300.
[0017] In one optional embodiment, the thickness of the N-type microcrystalline doped layer in S9 is 8–15 nm.
[0018] In one optional embodiment, the thickness of the intrinsic microcrystalline layer in S10 is 1-3 nm, the thickness of the functional layer is 2-5 nm, and the thickness of the P-type microcrystalline doped layer is 15-30 nm.
[0019] In one optional embodiment, the sheet resistance of the transparent conductive oxide film in S11 is 30 Ω / sq, and the mobility is 100 cm⁻¹. 2 / Vs, transmittance is 98%; the transparent conductive oxide film includes any one of ITO, IWO, ICO, and AZO.
[0020] In one optional embodiment, the grid lines of the low-temperature silver paste screen-printed in S12 are 9-13 μm high and 30-40 μm wide.
[0021] Secondly, embodiments of this disclosure also provide a heterojunction solar cell, prepared using the method described above, comprising: an N-type monocrystalline silicon wafer; the front side of the N-type monocrystalline silicon wafer, from bottom to top, includes a front passivation layer, an N-type microcrystalline doped layer, a transparent conductive oxide film, and a metal electrode; the back side of the N-type monocrystalline silicon wafer, from top to bottom, includes a back passivation layer, an intrinsic microcrystalline layer, a functional layer, a P-type microcrystalline doped layer, a transparent conductive oxide film, and a metal electrode; and the front side of the N-type monocrystalline silicon wafer adopts a normal textured surface with a pyramid base size of 2-5 μm, and the back side adopts a planar or near-planar microtexture.
[0022] The beneficial effects of this invention are that the method for preparing heterojunction solar cells by tubular PECVD reduces the coating area on the silicon substrate surface by using a planar structure or a microtexture with a small specific surface area, which is equivalent to increasing the coating rate of tubular PECVD without generating dust. This results in an improved microstructure factor of the prepared intrinsic amorphous silicon thin film and a better passivation effect on the silicon wafer surface. At the same time, by completely replacing plate PECVD with tubular PECVD, the equipment cost of heterojunction solar cells is significantly reduced.
[0023] Other features and advantages of the invention will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing the invention. The objects and other advantages of the invention are realized and obtained through the structures particularly pointed out in the description and the drawings.
[0024] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description
[0025] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.
[0026] Figure 1This is a schematic diagram of a heterojunction solar cell provided in an embodiment of the present disclosure;
[0027] In the picture:
[0028] 1. N-type single-crystal silicon wafer; 21. Front passivation layer; 22. Back passivation layer; 3. Intrinsic microcrystalline layer; 4. Functional layer; 51. N-type microcrystalline doped layer; 52. P-type microcrystalline doped layer; 6. Transparent conductive oxide thin film; 7. Metal electrode;
[0029] Figure 2 SEM images of the unpolished silicon wafer surface on the back side, provided for embodiments of this disclosure;
[0030] Figure 3 SEM images of the back-polished silicon wafer surface for 50 seconds provided in this embodiment of the present disclosure;
[0031] Figure 4 SEM images of the back-polished silicon wafer surface after 100 seconds, provided for embodiments of this disclosure;
[0032] Figure 5 SEM image of a silicon wafer surface polished 150s on the back side, provided for an embodiment of this disclosure. Detailed Implementation
[0033] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0034] As used herein, the phrases “in one embodiment,” “according to one embodiment,” “in some embodiments,” etc., generally refer to the fact that a particular feature, structure, or characteristic following the phrase can be included in at least one embodiment of this disclosure. Therefore, a particular feature, structure, or characteristic can be included in more than one embodiment of this disclosure, such that these phrases do not necessarily refer to the same embodiment. As used herein, the terms “example,” “exemplary,” etc., are used to “serve as an example, instance, or illustration.” Any implementation, aspect, or design described herein as “example” or “exemplary” is not necessarily to be construed as preferred or superior to other implementations, aspects, or designs. Rather, the use of the terms “example,” “exemplary,” etc., is intended to present concepts in a specific manner.
[0035] In this document, exemplary embodiments of the present disclosure will be described in more detail with reference to the accompanying drawings. As used herein, expressions such as “at least one of…” modify the entire list of elements when following a list of elements, rather than individual elements in the list. For example, the expression “at least one of a, b, and c” should be understood to include only a, only b, only c, both a and b, both a and c, both b and c, or all of a, b, and c.
[0036] The terminology used herein is for the purpose of describing specific exemplary configurations only and is not intended to be limiting. As used herein, the singular articles “a,” “an,” and “the” may also be intended to include plural forms unless otherwise clearly stated herein. The terms “comprising,” “including,” and “having” are inclusive and thus specify the presence of features, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, steps, operations, elements, components, and / or combinations thereof. The method steps, processes, and operations described herein should not be construed as requiring them to be performed in the specific order discussed or shown, unless specifically identified as such. Additional or alternative steps may be employed.
[0037] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.
[0038] The following detailed description of some embodiments of the present invention is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.
[0039] This disclosure provides a method for fabricating heterojunction solar cells using tubular PECVD, comprising the following steps: S1, pre-cleaning an N-type monocrystalline silicon wafer for later use; S2, using a tubular diffusion furnace to getter the N-type monocrystalline silicon wafer until the sheet resistance is 30-70 ohms; S3, using a tank cleaning agent to clean and texturize the texturized N-type monocrystalline silicon wafer until the base size of the textured pyramid is 2-5 μm; S4, using tubular PECVD to prepare silicon oxide on the front side of the texturized N-type monocrystalline silicon wafer, forming a dense silicon oxide protective film; S5, performing alkaline solution polishing on the back side of the N-type monocrystalline silicon wafer in S4 to remove the tips of the textured pyramids; S6, performing acid washing on the front oxide layer of the N-type monocrystalline silicon wafer in S5 to obtain a normally texturized front side and a back side with a planar or near-planar microtexture; S7, ... In step S6, a passivation layer is deposited on the back side of the N-type monocrystalline silicon wafer using tubular PECVD to obtain a back passivation layer. In step S8, a passivation layer is deposited on the front side of the N-type monocrystalline silicon wafer in step S7 using tubular PECVD to obtain a front passivation layer. In step S9, an N-type microcrystalline doped layer is deposited on the front passivation layer of the N-type monocrystalline silicon wafer in step S8 using tubular PECVD. In step S10, an intrinsic microcrystalline layer, a functional layer, and a P-type microcrystalline doped layer are deposited on the back passivation layer of the N-type monocrystalline silicon wafer in step S9 using tubular PECVD. In step S11, a transparent conductive layer is deposited on both the front and back sides of the N-type monocrystalline silicon wafer in step S10 using PVD to obtain a transparent conductive oxide film. In step S12, low-temperature silver paste is screen-printed on both the front and back sides of the N-type monocrystalline silicon wafer in step S11. After drying and curing, the metallization of the microcrystalline silicon heterojunction solar cell is completed.
[0040] In some embodiments, specifically, the thickness of the N-type single-crystal silicon wafer is 90–130 μm.
[0041] In some embodiments, specifically, the thickness of the silicon oxide protective film in S4 is 1 to 5 nm.
[0042] In some embodiments, specifically, after removing the pyramid apex in S5, the pyramid base size of the textured surface is greater than 2 μm; the remaining base size can be controlled by adjusting the alkaline solution concentration, reaction temperature, and reaction time. A longer reaction time results in a larger remaining base size on the silicon wafer surface, making the back surface of the silicon wafer closer to a plane, which can be matched using an intrinsic amorphous silicon layer with a smaller microstructure factor.
[0043] In some embodiments, specifically, the passivation power supply frequency in S7 is 500kHz to 13.56MHz; the passivation layer stack coating includes a first passivation layer on the back side, a second passivation layer on the back side, and a third passivation layer on the back side; the thickness of the first passivation layer on the back side is 2 to 6nm, the coating temperature is 100 to 250℃, the silane flow rate is 1000 to 8000 sccm, the argon to silane flow rate ratio is 1 to 20:1, the pressure is 0.3 to 2.5 torr, the power is 2500 to 8000 W, and the duty cycle is 10:50 to 300; the thickness of the second passivation layer on the back side is 2 to 5nm. The coating temperature is 100–250℃, the silane flow rate is 1000–8000 sccm, the argon to silane flow rate ratio is 1–20:1, the pressure is 0.3–2.5 torr, the power is 2500–8000 W, and the duty cycle is 10:50–300; the thickness of the third passivation layer on the back side is 3–10 nm, the coating temperature is 100–250℃, the silane flow rate is 300–3000 sccm, the hydrogen to silane flow rate ratio is 8–20:1, the pressure is 1–3.5 torr, the power is 2500–8000 W, and the duty cycle is 10:50–300.
[0044] In some embodiments, specifically, the passivation power supply frequency in S8 is 500kHz to 13.56MHz; the passivation layer stack coating includes a first passivation layer on the front side, a second passivation layer on the front side, and a third passivation layer on the front side; the thickness of the first passivation layer on the front side is 1 to 4nm, the coating temperature is 100 to 250℃, the silane flow rate is 1000 to 8000 sccm, the pressure is 0.3 to 2.5 torr, the power is 2500 to 8000W, and the duty cycle is 10:50 to 300; the thickness of the second passivation layer on the front side is 1 to 3nm. The coating temperature is 100–250℃, the silane flow rate is 1000–8000 sccm, the pressure is 0.3–2.5 torr, the power is 2500–8000 W, and the duty cycle is 10:50–300; the thickness of the third passivation layer on the front side is 3–6 nm, the coating temperature is 100–250℃, the silane flow rate is 300–3000 sccm, the hydrogen to silane flow ratio is 10–30:1, the pressure is 1–3.5 torr, the power is 2500–8000 W, and the duty cycle is 10:50–300.
[0045] Specifically, adding Ar to the process gas in the I0 layer can improve the dissociation rate of silane gas, enhance the gas flow inside the furnace tube, improve the uniformity of the gas field, and improve the uniformity of the coating.
[0046] Specifically, by increasing the power supply frequency of tubular PECVD, the plasma density generated by ionization is increased, thereby increasing the deposition rate of the film layer. At the same time, the proportion of high-energy plasma is reduced, thus reducing the bombardment of the film layer by high-energy plasma.
[0047] In some embodiments, specifically, the thickness of the N-type microcrystalline doped layer in S9 is 8–15 nm.
[0048] In some embodiments, specifically, the thickness of the intrinsic microcrystalline layer in S10 is 1-3 nm, the thickness of the functional layer is 2-5 nm, and the thickness of the P-type microcrystalline doped layer is 15-30 nm.
[0049] In some embodiments, specifically, the sheet resistance of the transparent conductive oxide film in S11 is 30 Ω / sq, and the mobility is 100 cm⁻¹. 2 / Vs, transmittance 98%; the transparent conductive oxide film includes any one of ITO (indium tin oxide), IWO (tungsten-doped indium oxide), ICO (cerium-doped indium oxide), and AZO (aluminum-doped zinc oxide).
[0050] In some embodiments, specifically, the grid lines of the low-temperature silver paste screen-printed in S12 are 9-13 μm high and 30-40 μm wide.
[0051] like Figure 1 As shown in the embodiments of this disclosure, a heterojunction solar cell is also provided, which is prepared by the method described above, including: an N-type monocrystalline silicon wafer; the front side of the N-type monocrystalline silicon wafer includes, from bottom to top, a front passivation layer, an N-type microcrystalline doped layer, a transparent conductive oxide film, and a metal electrode; the back side of the N-type monocrystalline silicon wafer includes, from top to bottom, a back passivation layer, an intrinsic microcrystalline layer, a functional layer, a P-type microcrystalline doped layer, a transparent conductive oxide film, and a metal electrode; and the front side of the N-type monocrystalline silicon wafer adopts a normal textured surface with a pyramid base size of 2-5 μm, and the back side adopts a planar or near-planar microtexture.
[0052] Specifically, the intrinsic microcrystalline layer can passivate the dangling bonds on the surface of the single-crystal silicon substrate, reduce surface defect states, and thus reduce carrier surface recombination.
[0053] Specifically, in this article, normal nap refers to a pyramid base size of 2–5 μm, small nap refers to a pyramid base size of 0.5–2 μm, and micro nap refers to a pyramid base size of <0.5 μm.
[0054] Example:
[0055] S1-S3: N-type single crystal silicon wafers are used. After texturing and cleaning, the thickness of the silicon wafer is 100um, and the base size of its textured pyramid is 2-4um.
[0056] S4-S6: A 2nm silicon oxide protective film was prepared on the front side of the silicon wafer using tubular PECVD. The back side of the silicon wafer was then polished with an alkaline solution for 50s, 100s, and 150s, respectively, to prepare three sets of silicon wafers with different back-side morphologies. The specific morphologies of the back side of the silicon wafers are shown above. Figure 3 , Figure 4 and Figure 5 As shown. The protective silicon oxide layer on the front side is then removed by acid washing;
[0057] S7: The back passivation layer is deposited by tubular PECVD. The thickness of the first back passivation layer is 2-6nm, the thickness of the second back passivation layer is 2-5nm, and the thickness of the third back passivation layer is 3-10nm.
[0058] S8: The front passivation layer is stacked and deposited using tubular PECVD. The thickness of the first passivation layer on the back is 1-4nm, the thickness of the second passivation layer on the back is 1-3nm, the thickness of the third passivation layer on the back is 3-6nm, and an N-type microcrystalline doped layer with a thickness of 8-15nm is deposited on top of the front passivation layer.
[0059] S9: An N-type microcrystalline doped layer with a thickness of 8-15nm is deposited on the front passivation layer using plate PECVD.
[0060] S10: An intrinsic microcrystalline layer with a thickness of 1-3nm, a functional layer with a thickness of 2-5nm, and a P-type microcrystalline doped layer with a thickness of 15-30nm are deposited on the back passivation layer using plate PECVD.
[0061] S11: PVD-deposited ITO thin film, sheet resistance 30Ω / □, mobility 100cm⁻¹ 2 / Vs, transmittance 98%;
[0062] S12: Low-temperature silver paste is screen-printed on the front and back of the silicon wafer, with grid lines 9-13µm high and 30-40µm wide. After drying and curing, the metallization of the microcrystalline silicon heterojunction cell is completed.
[0063] Control group:
[0064] S1-S3: N-type single-crystal silicon wafers are used. After texturing and cleaning, the wafer thickness is 100µm, and the base size of the textured pyramid is 2-4µm. The specific morphology of the back side of the silicon wafer is shown above. Figure 2 As shown;
[0065] S7: The back passivation layer is deposited by tubular PECVD. The thickness of the first back passivation layer is 2-6nm, the thickness of the second back passivation layer is 2-5nm, and the thickness of the third back passivation layer is 3-10nm.
[0066] S8: The front passivation layer is stacked and deposited using tubular PECVD. The thickness of the first passivation layer on the back is 1-4nm, the thickness of the second passivation layer on the back is 1-3nm, the thickness of the third passivation layer on the back is 3-6nm, and an N-type microcrystalline doped layer with a thickness of 8-15nm is deposited on top of the front passivation layer.
[0067] S9: An N-type microcrystalline doped layer with a thickness of 8-15nm is deposited on the front passivation layer using plate PECVD.
[0068] S10: An intrinsic microcrystalline layer with a thickness of 1-3nm, a functional layer with a thickness of 2-5nm, and a P-type microcrystalline doped layer with a thickness of 15-30nm are deposited on the back passivation layer using plate PECVD.
[0069] S11: PVD-deposited ITO thin film, sheet resistance 30Ω / sq, mobility 100cm⁻¹ 2 / Vs, transmittance 98%;
[0070] S12: Low-temperature silver paste is screen-printed on the front and back of the silicon wafer, with grid lines 9-13µm high and 30-40µm wide. After drying and curing, the metallization of the microcrystalline silicon heterojunction cell is completed.
[0071] like Figures 2-5 The following table shows SEM images of silicon wafers with different polishing times. The specific performance parameters are shown in Table 1 below.
[0072] Table 1
[0073]
[0074]
[0075] Three sets of examples and a control group were taken and operated according to the above process steps.
[0076] Comparison of data from the three sets of examples and the control group: The minority carrier lifetime was significantly improved after the CVD process, mainly due to the reduction in the specific surface area on the back of the silicon wafer, the increase in the microstructure factor of the amorphous silicon film deposited on the surface, the significant improvement in the anti-epitaxy effect, and the increase in film thickness, which significantly improved the passivation effect. Therefore, the open-circuit voltage increased by more than 3mV, the fill factor was also significantly improved, and the cell efficiency was improved by up to 1%.
[0077] Comparing different embodiments: Higher back-side flatness results in better passivation of the amorphous silicon film, leading to improved minority carrier lifetime after CVD. However, excessive amorphous silicon film thickness causes a significant decrease in the battery's flyback factor (FF) and overall battery efficiency. The back-side microtexture needs to be matched with the amorphous silicon film to achieve optimal battery efficiency. In this embodiment, 50 seconds of back-side polishing is the optimal process.
[0078] In summary, this method for fabricating heterojunction solar cells using tubular PECVD reduces the deposition area on the silicon substrate surface by employing a planar structure or a microtexture with a small specific surface area. This effectively increases the deposition rate of tubular PECVD without generating dust, thereby improving the microstructure factor of the prepared intrinsic amorphous silicon thin film and resulting in better passivation of the silicon wafer surface. At the same time, by completely replacing plate-type PECVD with tubular PECVD, the equipment cost of heterojunction solar cells is significantly reduced.
[0079] Based on the above-described preferred embodiments of the present invention, and through the foregoing description, those skilled in the art can make various changes and modifications without departing from the inventive concept. The technical scope of this invention is not limited to the contents of the specification, but must be determined according to the scope of the claims.
Claims
1. A method for fabricating heterojunction solar cells using tubular PECVD, characterized in that, Includes the following steps: S1, Pre-clean the N-type monocrystalline silicon wafer and set it aside; S2, N-type single crystal silicon wafers are gouged using a tube diffusion furnace until the sheet resistance of the silicon wafer is 30-70 ohms and then put into use. S3, using a tank cleaning agent to clean and texturize the N-type monocrystalline silicon wafer after gettering, until the base size of the textured pyramid is 2-5 μm; S4, using tubular PECVD to prepare silicon oxide on the front side of the texturized N-type single crystal silicon wafer to form a dense silicon oxide protective film; S5, the back side of the N-type single crystal silicon wafer in S4 is polished with an alkaline solution to remove the apex of the textured pyramid; S6, acid pickling is performed on the front oxide layer of the N-type monocrystalline silicon wafer in S5 to obtain a silicon wafer front with normal texture and a silicon wafer back with a planar or near-planar microtexture. S7, a passivation layer is deposited on the back side of the N-type single crystal silicon wafer in S6 using tubular PECVD to obtain the back passivation layer; S8 uses tubular PECVD to deposit a passivation layer on the front side of the N-type single crystal silicon wafer in S7 to obtain the front passivation layer. S9 uses tubular PECVD to deposit a film on the front passivation layer of the N-type single crystal silicon wafer in S8 to obtain an N-type microcrystalline doped layer. S10 uses tubular PECVD to deposit a film on the back passivation layer of the N-type single crystal silicon wafer in S9, thereby obtaining an intrinsic microcrystalline layer, a functional layer and a P-type microcrystalline doped layer in sequence. S11, using PVD to deposit a transparent conductive layer on both the front and back sides of the N-type single crystal silicon wafer in S10, to obtain a transparent conductive oxide film; S12 uses low-temperature silver paste screen printing on both the front and back sides of the N-type monocrystalline silicon wafer in S11. After drying and curing, the metallization of the microcrystalline silicon heterojunction cell is completed.
2. The method as described in claim 1, characterized in that, The thickness of the silicon oxide protective film in S4 is 1–5 nm.
3. The method as described in claim 1, characterized in that, After removing the pyramid tip in S5, the pyramid base size of the velvet surface is greater than 2μm.
4. The method as described in claim 1, characterized in that, The passivation power frequency in S7 is 500kHz to 13.56MHz; The passivation layer stack coating includes a first passivation layer on the back side, a second passivation layer on the back side, and a third passivation layer on the back side; The thickness of the first passivation layer on the back side is 2-6 nm, the coating temperature is 100-250 °C, the silane flow rate is 1000-8000 sccm, the argon to silane flow rate ratio is 1-20:1, the pressure is 0.3-2.5 torr, the power is 2500-8000 W, and the duty cycle is 10:50-300. The thickness of the second passivation layer on the back side is 2-5 nm, the coating temperature is 100-250 °C, the silane flow rate is 1000-8000 sccm, the argon to silane flow rate ratio is 1-20:1, the pressure is 0.3-2.5 torr, the power is 2500-8000 W, and the duty cycle is 10:50-300. The thickness of the third passivation layer on the back side is 3-10 nm, the coating temperature is 100-250 °C, the silane flow rate is 300-3000 sccm, the hydrogen to silane flow rate ratio is 8-20:1, the pressure is 1-3.5 torr, the power is 2500-8000 W, and the duty cycle is 10:50-300.
5. The method as described in claim 1, characterized in that, The passivation power supply frequency in S8 is 500kHz to 13.56MHz; The passivation layer stack coating includes a first passivation layer on the front side, a second passivation layer on the front side, and a third passivation layer on the front side; The thickness of the first passivation layer on the front side is 1-4 nm, the coating temperature is 100-250℃, the silane flow rate is 1000-8000 sccm, the pressure is 0.3-2.5 torr, the power is 2500-8000 W, and the duty cycle is 10:50-300. The thickness of the second passivation layer on the front side is 1-3 nm, the coating temperature is 100-250℃, the silane flow rate is 1000-8000 sccm, the pressure is 0.3-2.5 torr, the power is 2500-8000 W, and the duty cycle is 10:50-300. The thickness of the third passivation layer on the front side is 3-6 nm, the coating temperature is 100-250℃, the silane flow rate is 300-3000 sccm, the hydrogen to silane flow rate ratio is 10-30:1, the pressure is 1-3.5 torr, the power is 2500-8000 W, and the duty cycle is 10:50-300.
6. The method as described in claim 1, characterized in that, The thickness of the N-type microcrystalline doped layer in S9 is 8–15 nm.
7. The method as described in claim 1, characterized in that, The intrinsic microcrystalline layer in S10 has a thickness of 1–3 nm, the functional layer has a thickness of 2–5 nm, and the P-type microcrystalline doped layer has a thickness of 15–30 nm.
8. The method as described in claim 1, characterized in that, The transparent conductive oxide film in S11 has a sheet resistance of 30 Ω / sq and a mobility of 100 cm⁻¹. 2 / Vs, transmittance is 98%; The transparent conductive oxide film includes any one of ITO, IWO, ICO, and AZO.
9. The method as described in claim 1, characterized in that, The screen-printed low-temperature silver paste in S12 has a grid line height of 9-13 μm and a width of 30-40 μm.
10. A heterojunction battery, characterized in that, Prepared by the method according to any one of claims 1-9, comprising: N-type monocrystalline silicon wafers; The front side of the N-type single crystal silicon wafer, from bottom to top, includes a front passivation layer, an N-type microcrystalline doped layer, a transparent conductive oxide thin film, and a metal electrode. The back side of the N-type single crystal silicon wafer, from top to bottom, includes a back passivation layer, an intrinsic microcrystalline layer, a functional layer, a P-type microcrystalline doped layer, a transparent conductive oxide thin film, and a metal electrode. Furthermore, the front side of the N-type monocrystalline silicon wafer adopts a normal textured surface with a pyramid base size of 2 to 5 μm, and the back side adopts a planar or near-planar microtexture.