Display panel and electronic device including the same

Abstract

The invention relates to a display panel and an electronic device including the same. The display panel includes: a substrate; the pixel circuit comprises a first sub-pixel circuit, a second sub-pixel circuit and a third sub-pixel circuit; a first insulating layer disposed on the pixel circuit; a first conductive layer disposed on the first insulating layer and including a first data line, a second data line, and a third data line; a second insulating layer disposed on the first conductive layer; and a second conductive layer disposed on the second insulating layer and including a first pixel electrode, a second pixel electrode, a third pixel electrode, and a shielding pattern. The shield pattern includes a first portion overlapping the first data line, a second portion overlapping the second data line, and a first connection portion connecting the first portion and the second portion to each other.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2024-0132010, filed on September 27, 2024, and all benefits derived from that application, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0002] One or more embodiments relate to a display panel and an electronic device including the display panel. Background Technology

[0003] Recently, display panels have been used in electronic devices for various purposes. As display panels become more widely used, the demand for high-quality display panels has increased. To manufacture high-quality display panels, it is desirable to house various types of electronic components within a narrow area. Summary of the Invention

[0004] Because various electronic components are arranged in a narrow area, the quality of the image displayed by the display panel may be degraded due to the coupling between adjacent electronic components. However, such a technical problem is merely an example, and this disclosure is not limited thereto.

[0005] Other aspects will be set forth in part in the description which follows, and will be apparent in part from the description, or may be learned by practice of the embodiments presented in this disclosure.

[0006] According to one or more embodiments, a display panel includes: a substrate including a display area and a peripheral area outside the display area; a pixel circuit disposed in the display area and including a first sub-pixel circuit, a second sub-pixel circuit, and a third sub-pixel circuit adjacent to each other in a first direction; a first insulating layer disposed on the pixel circuit; a first conductive layer disposed on the first insulating layer and including a first data line connected to the first sub-pixel circuit, a second data line connected to the second sub-pixel circuit, and a third data line connected to the third sub-pixel circuit; a second insulating layer disposed on the first conductive layer; and a second conductive layer disposed on the second insulating layer and including a first pixel electrode connected to the first sub-pixel circuit, a second pixel electrode connected to the second sub-pixel circuit, a third pixel electrode connected to the third sub-pixel circuit, and a shielding pattern, wherein the shielding pattern includes a first portion overlapping the first data line in a plan view, a second portion overlapping the second data line in a plan view, and a first connecting portion connecting the first portion and the second portion to each other.

[0007] In this embodiment, the first part, the second part, and the first connecting part can be connected to each other as a whole.

[0008] In an embodiment, in a plan view, the first pixel electrode and the second pixel electrode may be disposed between the first data line and the second data line.

[0009] In one embodiment, the first data line and the second data line may be symmetrically arranged about a virtual line that passes between the first sub-pixel circuit and the second sub-pixel circuit and is parallel to a second direction that intersects the first direction.

[0010] In one embodiment, the first portion of the shielding pattern may include an extension that overlaps with the third data line, which is adjacent to the first data line.

[0011] In an embodiment, the first conductive layer may further include an auxiliary voltage line extending in a second direction intersecting the first direction, and the third data line and the auxiliary voltage line may be symmetrically arranged about a virtual line passing through the third sub-pixel circuit and parallel to the second direction.

[0012] In one embodiment, the shielding pattern can be connected to the auxiliary voltage line through contact holes passing through the second insulating layer.

[0013] In an embodiment, the first conductive layer may further include: a first driving voltage line disposed between the first data line and the second data line; and a second driving voltage line disposed between the auxiliary voltage line and the third data line.

[0014] In an embodiment, in a plan view, the first pixel electrode and the second pixel electrode may overlap with the first driving voltage line, and the third pixel electrode may overlap with the second driving voltage line.

[0015] In an embodiment, the shielding pattern may be provided as a plurality of shielding patterns, which may be separated from each other in a first direction, and the voltage transmitted to the first shielding pattern among the plurality of shielding patterns may be different from the voltage transmitted to the second shielding pattern among the plurality of shielding patterns.

[0016] In an embodiment, the voltages transmitted to the multiple shielding patterns may have values ​​in a preset order that repeats in a first direction.

[0017] In an embodiment, the shielding pattern may be provided as a plurality of shielding patterns, and the second conductive layer may further include a second connecting portion that connects the plurality of shielding patterns to each other.

[0018] In this embodiment, multiple shielding patterns and second connecting portions can be connected together to form a single unit.

[0019] In an embodiment, the second conductive layer may include a plurality of grid electrodes spaced apart from each other in a first direction, and each of the plurality of grid electrodes may include at least two of a plurality of shielding patterns and a second connection portion connecting the at least two shielding patterns.

[0020] In an embodiment, the voltages transmitted to the multiple grid electrodes may have values ​​in a preset order that repeats in a first direction.

[0021] According to one or more embodiments, an electronic device includes: a display panel; and a lower cover forming an appearance and defining an opening in the front surface of the lower cover to expose a portion of the display panel, wherein the display panel includes: a substrate including a display area and a peripheral area outside the display area; pixel circuitry disposed in the display area and including a first sub-pixel circuit, a second sub-pixel circuit, and a third sub-pixel circuit adjacent to each other in a first direction; a first insulating layer disposed on the pixel circuitry; a first conductive layer disposed on the first insulating layer and including a first data line connected to the first sub-pixel circuitry, a second data line connected to the second sub-pixel circuitry, and a third data line connected to the third sub-pixel circuitry; a second insulating layer disposed on the first conductive layer; and a second conductive layer disposed on the second insulating layer and including a first pixel electrode connected to the first sub-pixel circuitry, a second pixel electrode connected to the second sub-pixel circuitry, a third pixel electrode connected to the third sub-pixel circuitry, and a shielding pattern, wherein the shielding pattern includes a first portion overlapping the first data line in a plan view, a second portion overlapping the second data line in a plan view, and a first connecting portion connecting the first portion and the second portion to each other.

[0022] In an embodiment, the first part, the second part, and the first connecting part of the shielding pattern can be connected to each other as a whole.

[0023] In one embodiment, the first data line and the second data line may be symmetrically arranged about a virtual line that passes between the first sub-pixel circuit and the second sub-pixel circuit and is parallel to a second direction that intersects the first direction.

[0024] In one embodiment, the first portion of the shielding pattern may include an extension that overlaps with the third data line, which is adjacent to the first data line.

[0025] In one embodiment, the first conductive layer may further include an auxiliary voltage line extending in a second direction intersecting the first direction, and the shielding pattern may be connected to the auxiliary voltage line through contact holes passing through the second insulating layer.

[0026] In an embodiment, the first conductive layer may further include: a first driving voltage line disposed between the first data line and the second data line; and a second driving voltage line disposed between the second data line and the third data line, and the shielding pattern may be connected to the first driving voltage line or the second driving voltage line through contact holes passing through the second insulating layer.

[0027] In an embodiment, the shielding pattern may be provided as a plurality of shielding patterns, which may be separated from each other in a first direction, and the voltage transmitted to the first shielding pattern among the plurality of shielding patterns may be different from the voltage transmitted to the second shielding pattern among the plurality of shielding patterns.

[0028] In an embodiment, the shielding pattern may be provided as a plurality of shielding patterns, and the second conductive layer may further include a second connecting portion that connects the plurality of shielding patterns.

[0029] In this embodiment, multiple shielding patterns and a second connecting portion can be connected as one unit.

[0030] In an embodiment, the second conductive layer may include a plurality of grid electrodes spaced apart from each other in a first direction, and each of the plurality of grid electrodes may include at least two of a plurality of shielding patterns and a second connection portion connecting the at least two shielding patterns.

[0031] In an embodiment, the voltages transmitted to the multiple grid electrodes may have values ​​in a preset order that repeats in a first direction.

[0032] These and / or other aspects will become apparent and more readily understood from the following detailed description of the embodiments, the accompanying drawings, and the claims. Attached Figure Description

[0033] The above and other aspects, features and advantages of certain embodiments of the present disclosure will become more apparent from the following description taken in conjunction with the accompanying drawings, in which:

[0034] Figure 1 This is a perspective view of an electronic device according to an embodiment;

[0035] Figure 2 This is an exploded perspective view of an electronic device according to an embodiment;

[0036] Figure 3 This is a block diagram of an electronic device according to an embodiment;

[0037] Figure 4 This is a schematic plan view of the display panel according to an embodiment;

[0038] Figures 5A to 5C This is an equivalent circuit diagram of the light-emitting diodes and sub-pixel circuits of the display panel according to an embodiment;

[0039] Figure 6 This is a schematic plan view of the common voltage supply line and auxiliary common voltage line of the display panel according to an embodiment;

[0040] Figure 7 This is a schematic plan view of voltage lines with a grid structure according to an embodiment;

[0041] Figure 8 This is a schematic diagram of the construction of the voltage line according to an embodiment;

[0042] Figure 9A This is a plan view showing the selection of the first conductive layer of the display panel according to an embodiment. Figure 9B This is a plan view showing the selection of the second conductive layer of the display panel according to an embodiment, and Figure 9C This is a plan view of the overlapping first and second conductive layers of the display panel according to an embodiment;

[0043] Figure 10 This is a schematic plan view of the data line and shielding pattern according to an embodiment;

[0044] Figure 11 It is along Figure 9C The line II-II' intercepted Figure 9C A schematic cross-sectional view of the display panel;

[0045] Figure 12 It is along Figure 9C The line III-III' intercepted Figure 9C A schematic cross-sectional view of the display panel;

[0046] Figure 13 This is a schematic cross-sectional view of the display panel according to an embodiment;

[0047] Figure 14 This is a schematic plan view of the display panel according to an embodiment;

[0048] Figure 15 This is a schematic plan view of the grid electrode according to an embodiment;

[0049] Figure 16 This is a schematic plan view of the display panel according to an embodiment;

[0050] Figure 17 It is a schematic plan view of the shielding patterns separated from each other according to an embodiment; and

[0051] Figure 18 This is a schematic plan view of the grid electrodes separated from each other according to an embodiment. Detailed Implementation

[0052] Reference will now be made in detail to embodiments, examples of which are illustrated in the accompanying drawings, wherein the same reference numerals refer to the same elements throughout. In this respect, present embodiments may take different forms and should not be construed as limited to the description set forth herein. Accordingly, embodiments are described below only by reference to the accompanying drawings to explain aspects of the present description. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. Throughout this disclosure, the expression “at least one of a, b, and c” indicates only a, only b, only c, both a and b, both a and c, both b and c, all of a, b, and c, or variations thereof.

[0053] Because this disclosure allows for various modifications and numerous embodiments, certain embodiments will be illustrated in the accompanying drawings and described in the written description. The effects and features of this disclosure, as well as methods of implementing them, will be elucidated with reference to the embodiments described in detail below with reference to the accompanying drawings. However, this disclosure is not limited to the embodiments described below and can be embodied in various forms.

[0054] In the following description, embodiments will be referenced to the accompanying drawings, wherein the same reference numerals refer to the same elements throughout, and repeated descriptions of the same elements are omitted.

[0055] Although terms such as "first" and "second" can be used to describe various components, these components are not limited to these terms. The terms above are used to distinguish one component from another.

[0056] As used herein, unless the context clearly indicates otherwise, the singular forms “a” and “the (said)” are intended to include the plural forms as well.

[0057] It will be understood that the terms “comprising” and / or “including” as used herein indicate the presence of a stated feature or component, but do not preclude the addition of one or more other features or components.

[0058] It will be further understood that when a layer, area, or component is referred to as being "on" another layer, area, or component, that layer, area, or component may be directly or indirectly on that other layer, area, or component. That is, for example, there may be intermediate layers, areas, or components.

[0059] It will be understood that when a layer, area, or component is referred to as being "connected" to another layer, area, or component, that layer, area, or component may be "directly connected" to that other layer, area, or component, or may be "indirectly connected" to that other layer, area, or component, while another layer, area, or component lies between that layer, area, or component and that other layer, area, or component. For example, it will be understood that when a layer, area, or element is referred to as being "electrically connected" to another layer, area, or element, that layer, area, or element may be "directly electrically connected" to that other layer, area, or element, or may be "indirectly electrically connected" to that other layer, area, or component, while another layer, area, or element lies between that layer, area, or element and that other layer, area, or component.

[0060] In this specification, "A and / or B" means A or B or A and B. In this specification, "at least one of A and B" means A or B or A and B.

[0061] In this specification, the x, y, and z directions are not limited to directions corresponding to the three axes of a Cartesian coordinate system, and can be interpreted in a broader sense. For example, the x, y, and z directions can be perpendicular to each other, or they can represent different orientations that are not perpendicular to each other.

[0062] In this specification, the terms "plane" or "plan view" mean when the target portion is viewed from above (e.g., when viewed in a direction perpendicular to the upper surface of the substrate (z direction)), and the term "section" means when the target portion is viewed from the side in a vertically cut section.

[0063] In this specification, when the first element overlaps with the second element, it means that the first element is located above or below the second element, and at least a portion of the first element and the second element overlap each other in a plan view.

[0064] Where certain embodiments can be implemented differently, a particular process sequence may be performed in an order different from the order described. As an example, two processes described consecutively may be performed substantially simultaneously, or in reverse order.

[0065] For ease of explanation, the dimensions of the elements in the accompanying drawings may be exaggerated or reduced. As an example, for ease of description, the dimensions and thicknesses of each element shown in the drawings are arbitrarily represented, and therefore, this disclosure is not necessarily limited thereto.

[0066] Figure 1 This is a perspective view of electronic device 1 according to an embodiment, and Figure 2 This is an exploded perspective view of electronic device 1 according to an embodiment.

[0067] refer to Figure 1 and Figure 2Electronic device 1 may include means for displaying moving or still images, and can be used as a display screen for various products including televisions, laptop computers, monitors, billboards, Internet of Things (IoT) devices, and portable electronic devices including mobile phones, smartphones, tablet PCs, mobile communication terminals, electronic notebooks, e-books, portable multimedia players (PMPs), navigators, and ultra-mobile personal computers (UMPCs). Electronic device 1 according to embodiments can be used in wearable devices including smartwatches, watch phones, glasses displays, and head-mounted displays (HMDs). Electronic device 1 according to embodiments can be used as a display in a car's dashboard, a central information display (CID) on the car's central dashboard or instrument panel, an interior mirror display replacing a car's rearview mirror, and a display for an entertainment system for rear-seat passengers of a car, arranged on the back of the front seats.

[0068] For ease of description, Figure 1 and Figure 2 An electronic device 1 according to an embodiment is shown as a smartphone. The electronic device 1 according to the embodiment may include a cover window 70, a display panel 10, a data driver 1430, a display circuit board 30, a component 40, a bracket 60, a main circuit board 50, a battery 80, and a lower cover 90.

[0069] In the plan view of this specification, "left," "right," "up," and "down" indicate the directions when viewing the display panel 10 in a direction perpendicular to the display panel 10. As an example, "left" represents the -x direction, "right" represents the +x direction, "up" represents the +y direction, and "down" represents the -y direction.

[0070] Electronic device 1 can have a rectangular shape in a plan view. For example, as shown... Figure 1 As shown, the electronic device 1 in the plan view can have a quadrilateral shape, which has a shorter side in the x-direction and a longer side in the y-direction. The corner where the shorter side in the x-direction intersects the longer side in the y-direction can be arc-shaped with a predetermined curvature, or it can be formed as a right angle. The planar shape of the electronic device 1 is not limited to a rectangular shape, but can be other polygonal shapes, elliptical shapes, or irregular shapes.

[0071] A cover window 70 can be disposed on the display panel 10 to cover the upper surface of the display panel 10. Accordingly, the cover window 70 can protect the upper surface of the display panel 10.

[0072] The cover window 70 may include a transmissive cover portion DA 70 and a light-shielding cover portion NDA 70, wherein the transmissive cover portion DA 70 corresponds to the display panel 10, and the light-shielding cover portion NDA 70 surrounds the transmissive cover portion DA 70. The light-shielding cover portion NDA 70 may include an opaque material (e.g., a colored opaque material) that blocks light. The light-shielding cover portion NDA 70 may include a pattern that can be seen by the user when no image is displayed.

[0073] The display panel 10 can be positioned below the cover window 70. In a plan view, the display panel 10 can overlap with the transmissive cover portion DA70 of the cover window 70.

[0074] The display panel 10 may include a display area DA. The display area DA is the area in which an image is displayed, and may include an area (or component area) that transmits light emitted from a component 40 disposed below the display panel 10. The component 40 may include external modules (such as sensors and cameras) that use visible light, infrared light, and sound.

[0075] Display panel 10 may be a light-emitting display panel including light-emitting diodes (LEDs). The LEDs may include organic light-emitting diodes (OLEDs) containing an organic emitting layer. In an embodiment, the LED may be an inorganic LED comprising inorganic materials. An inorganic LED may include a PN junction diode comprising inorganic semiconductor materials. When a forward voltage is applied to the PN junction diode, holes and electrons are injected, and the energy generated by the recombination of holes and electrons is converted into light energy, thus emitting light of a predetermined color. Inorganic LEDs may have a width ranging from a few micrometers to several hundred micrometers. In an embodiment, the inorganic LED may be represented by a micro LED.

[0076] The display panel 10 can be a rigid display panel that is rigid and therefore not easily bent, or a flexible display panel that is flexible and therefore easily bendable, foldable, or rollable. As examples, the display panel 10 may include a foldable display panel that can be folded and unfolded, a curved display panel that has a curved display surface, a curved display panel in which areas other than the display surface are bent, a rollable display panel that can be rolled up and flattened, and a stretchable display panel.

[0077] The display panel 10 can be made transparent and is a transparent display panel, so that objects or backgrounds disposed below the display panel 10 can be seen from the upper surface of the display panel 10. Alternatively, the display panel 10 can be a reflective display panel that can reflect objects or backgrounds above the upper surface of the display panel 10.

[0078] The data driver 1430 may be disposed on the display panel 10 in the form of an integrated circuit (IC). In another embodiment, the data driver 1430 may be disposed on the display circuit board 30.

[0079] The display circuit board 30 can be attached to one side of the display panel 10. The display circuit board 30 can be a flexible printed circuit board (FPCB) that can be bent, a rigid printed circuit board (PCB) that is strong and not easily bent, or a composite printed circuit board that includes both rigid and flexible printed circuit boards.

[0080] In this embodiment, the touch sensor driver may be disposed on the display circuit board 30. The touch sensor driver may include an integrated circuit. The touch sensor driver may be attached to the display circuit board 30. The touch sensor driver may be electrically connected to the touch electrodes of the touch screen layer of the display panel 10 via the display circuit board 30.

[0081] The touchscreen layer of the display panel 10 can sense user touch input using at least one of various touch methods, such as resistive and capacitive methods. As an example, when the touchscreen layer of the display panel 10 senses user touch input using a capacitive method, the touch sensor driver can determine whether the user has touched the touchscreen layer by applying a drive signal to the drive electrode in the touch electrodes and sensing the voltage charged in the mutual capacitance between the drive electrode and the sensing electrode through the sensing electrode in the touch electrodes. User touches can include contact touches and proximity touches. A contact touch indicates that an object, such as a user's finger or pen, directly contacts the overlay window 70 arranged on the touchscreen layer. A proximity touch, such as a hover touch, indicates that an object, such as a user's finger or pen, is located above or near the overlay window 70 and moves away from it. The touch sensor driver can be configured to transmit sensor data to a main processor based on the sensed voltage, and the main processor can calculate the touch coordinates of the touch input by analyzing the sensor data.

[0082] An auxiliary processor may be disposed on the display circuit board 30, wherein the auxiliary processor is configured to supply driving voltage for driving the pixel, scan driver and data driver 1430 of the display panel 10.

[0083] A bracket 60 for supporting the display panel 10 may be disposed below the display panel 10. The bracket 60 may include plastic, metal, or both plastic and metal. A first camera hole CMH1 in which a camera module 1710 is embedded, a battery hole BH in which a battery 80 is disposed, and a cable hole CAH through which cables connected to the display circuit board 30 pass may be defined in the bracket 60. A component hole CPH overlapping with the display panel 10 may be provided in the bracket 60. The component hole CPH may overlap with a component 40 of the main circuit board 50 in the third direction (z-direction). In one embodiment, the display area DA of the display panel 10 may overlap with a component 40 of the main circuit board 50 in the third direction (z-direction). In another embodiment, the component hole CPH may not be defined in the bracket 60.

[0084] In an embodiment, component 40 may include first to fourth components 41, 42, 43, and 44, each overlapping the display panel 10 in a plan view. The first to fourth components 41, 42, 43, and 44 may include a proximity sensor, an illuminance sensor, an iris sensor, a facial recognition sensor, and a camera (or image sensor). The proximity sensor, using infrared light, can detect objects positioned near the upper surface of the electronic device 1, and the illuminance sensor can detect the brightness of light incident on the upper surface of the electronic device 1. Additionally, the iris sensor can capture the iris of a person positioned above the upper surface of the electronic device 1, and the camera can capture objects positioned on the upper surface of the electronic device 1. Component 40 is not limited to proximity sensors, illuminance sensors, iris sensors, facial recognition sensors, and cameras. Various modules described below may be configured.

[0085] The main circuit board 50 and the battery 80 can be disposed below the bracket 60. The main circuit board 50 can be a rigid printed circuit board or a flexible printed circuit board.

[0086] The main circuit board 50 may include a main processor 1110, a camera module 1710, a main connector 55, and a component 40. The main processor 1110 may include an integrated circuit. The camera module 1710 may be disposed on both the upper and lower surfaces of the main circuit board 50, and the main processor 1110 and the main connector 55 may each be disposed on one of the upper and lower surfaces of the main circuit board 50.

[0087] Camera module 1710 processes image frames, such as still images or moving images, acquired by an image sensor in camera mode, and outputs the image frames to main processor 1110. Camera module 1710 may include at least one of a camera sensor (e.g., a charge-coupled device (CCD) and complementary metal-oxide-semiconductor (CMOS), a photoelectric sensor (or image sensor), and a laser sensor. Camera module 1710 may be connected to the image sensor in component 40 overlapping with display area DA, and can process images input to the image sensor.

[0088] A cable passing through the cable hole CAH of the bracket 60 can be connected to the main connector 55, and thus the main circuit board 50 can be electrically connected to the display circuit board 30.

[0089] The lower cover 90 can form the appearance of the electronic device 1 and can define an opening in the front surface of the lower cover 90 that exposes a portion of the display panel 10. The lower cover 90 has an opening shape corresponding to the display panel 10 and can be assembled to the display panel 10. The lower cover 90 can be located on the opposite side (i.e., the rear side) of the cover window 70, with the display panel 10 between the lower cover 90 and the cover window 70. The lower cover 90 can be disposed below the main circuit board 50 and the battery 80. The lower cover 90 can be fastened and fixed to the bracket 60. The lower cover 90 can form the lower appearance of the electronic device 1. The lower cover 90 can include plastic, metal, or both plastic and metal.

[0090] A second camera aperture CMH2, exposing the lower surface of the camera module 1710, can be defined in the lower cover 90. The positions of the camera module 1710 and the corresponding first camera aperture CMH1 and second camera aperture CMH2 are not limited to... Figure 1 and Figure 2 The embodiments shown are not applicable and can be modified in various ways.

[0091] Figure 3 This is a block diagram of electronic device 1 according to an embodiment.

[0092] refer to Figure 3 Electronic device 1 may include a processor 1100, a memory 1200, an input module 1300, a display module 1400, a power module 1500, a built-in module 1600, and an external module 1700. According to an embodiment, in electronic device 1, at least one of the components may be omitted, or one or more other components may be added. According to an embodiment, some of the components (e.g., built-in module 1600) may be integrated into another component (e.g., display module 1400).

[0093] Processor 1100 can control at least one other element (e.g., hardware or software element) connected to electronic device 1 by executing software, and perform various data processing or operations. According to an embodiment, as at least some of the data processing or operations, processor 1100 can store commands or data received from another element (e.g., input module 1300, sensor module 1610, or communication module 1730) in volatile memory 1210, process the commands or data stored in volatile memory 1210, and store the result data in non-volatile memory 1220.

[0094] Processor 1100 may include a main processor 1110 and an auxiliary processor 1120. Main processor 1110 may include at least one of a central processing unit (CPU) 1111 and an application processor (AP). Main processor 1110 may further include at least one of a graphics processing unit (GPU) 1112, a communication processor (CP), and an image signal processor (ISP). Main processor 1110 may further include a neural processing unit (NPU) 1113. NPU 1113 is a processor specifically designed to process artificial intelligence models, and these models can be created through machine learning. The artificial intelligence model may include multiple layers of artificial neural networks. The artificial neural networks may be one of deep neural networks (DNN), convolutional neural networks (CNN), recurrent neural networks (RNN), restricted Boltzmann machines (RBM), deep belief networks (DBN), bidirectional recurrent deep neural networks (BRDNN), deep Q-networks, and combinations of two or more of the above artificial neural networks, but are not limited to the examples described above. Additionally or alternatively, in addition to hardware architecture, the artificial intelligence model may include software architecture. At least two of the processing units and the processor can be implemented as an integrated structure (e.g., a single chip) or can be implemented as separate structures (e.g., multiple chips).

[0095] The auxiliary processor 1120 may include a controller 1121. The controller 1121 may include interface conversion circuitry and timing control circuitry. The controller 1121 receives image signals from the main processor 1110, converts the data format of the image signals to match the interface specifications of the display module 1400, and outputs the image data. The controller 1121 can output various types of control signals for driving the display module 1400.

[0096] The auxiliary processor 1120 may further include data processing circuitry such as a data conversion circuit 1122, a gamma correction circuit 1123, and a rendering circuit 1124. The data conversion circuit 1122 may receive image data from the controller 1121, correct the image data to display an image at a desired brightness according to the characteristics of the electronic device 1 or user settings, or convert the image data to reduce power consumption or compensate for image retention. The gamma correction circuit 1123 may convert image data or a gamma reference voltage, etc., so that the image displayed by the electronic device 1 has desired gamma characteristics. The rendering circuit 1124 may receive image data from the controller 1121 and render the image data by taking into account the pixel configuration applied to the display panel 10 of the electronic device 1. At least one of the data conversion circuit 1122, the gamma correction circuit 1123, and the rendering circuit 1124 may be integrated into another component (e.g., the main processor 1110 or the controller 1121). In an embodiment, the auxiliary processor 1120 may be integrated into the data driver 1430.

[0097] The memory 1200 can store various types of data, as well as input or output data for data-related commands, wherein the various types of data are used by at least one element of the electronic device 1 (e.g., processor 1100 or sensor module 1610). The memory 1200 may include at least one of volatile memory 1210 and non-volatile memory 1220.

[0098] The input module 1300 can receive commands or data from outside the electronic device 1 (e.g., a user or external electronic device 2000), wherein the commands or data will be used by components of the electronic device 1 (e.g., processor 1100, sensor module 1610, or sound output module 1630).

[0099] The input module 1300 may include a first input module 1310 to which commands or data from the user are input and a second input module 1320 to which commands or data from an external electronic device 2000 are input.

[0100] The first input module 1310 may include a microphone, mouse, keyboard, or pen (e.g., a passive or active pen). The first input module 1310 may include a mechanical input tool such as a button, dome switch, chuck wheel, and chuck switch, or a touch input tool located on the lower or side surface of the electronic device 1. The touch input tool may include the touchscreen layer of the display panel 10.

[0101] The second input module 1320 can be connected via wiring or wirelessly to various types of external electronic devices 2000 connected to the electronic device 1. In embodiments, the second input module 1320 may include a High Definition Multimedia Interface (HDMI), a Universal Serial Bus (USB) interface, a Secure Digital Card (SD) card interface, or an audio interface. The second input module 1320 may include a connector that can physically connect the electronic device 1 to the external electronic device 2000, wherein the connector includes an HDMI connector, a USB connector, an SD card connector, or an audio connector (e.g., a headphone connector). The electronic device 1 can perform appropriate controls related to the connected external electronic device 2000 in response to the connection of the external electronic device 2000 to the second input module 1320.

[0102] Display module 1400 provides visual information to the user. Display module 1400 may include display panel 10, scan driver 1420, and data driver 1430.

[0103] Display panel 10 displays (outputs) information processed by electronic device 1. Display panel 10 may display execution screen information of an application driven in electronic device 1, or user interface (UI) information (e.g., graphical user interface (GUI) information) corresponding to the execution screen information.

[0104] The scan driver 1420 can be mounted as a driver chip on the display panel 10. Alternatively, the scan driver 1420 can be directly disposed on the display panel 10. As an example, the scan driver 1420 may include an amorphous silicon thin-film transistor (TFT) gate (ASG) driving circuit, a low-temperature polycrystalline silicon (LTPS) TFT gate driving circuit, or an oxide semiconductor TFT gate (OSG) driving circuit embedded in the display panel 10. The scan driver 1420 receives control signals from the controller 1121 and outputs scan signals to the display panel 10 in response to the control signals.

[0105] The display panel 10 may further include a transmission control driver. The transmission control driver outputs a transmission control signal to the display panel 10 in response to a control signal received from the controller 1121. The transmission control driver may be formed separately from the scan driver 1420 or integrated into the scan driver 1420.

[0106] The data driver 1430 receives a control signal from the controller 1121, converts the image data into a data signal in the form of an analog voltage in response to the control signal, and outputs the data signal to the display panel 10.

[0107] The data driver 1430 can be integrated into some components of the auxiliary processor 1120. As an example, the data driver 1430 can be provided in a timing controller embedded driver IC that includes the controller 1121.

[0108] Power module 1500 supplies power to the components of electronic device 1. Power module 1500 may include a battery 80 charged with a power supply voltage. Additionally, power module 1500 has a connection port, which may be included in a second input module 1320 to which an external charger supplying power to charge battery 80 is connected. Alternatively, power module 1500 may include wireless power transmission / reception components for wirelessly charging battery 80. The wireless power transmission / reception components may include multiple coil-type antenna radiators. Power module 1500 may include a power management integrated circuit (PMIC). The PMIC supplies optimized power to each component of electronic device 1.

[0109] The electronic device 1 may further include a built-in module 1600 and an external module 1700. The built-in module 1600 may include a sensor module 1610, an antenna module 1620, and a sound output module 1630. The external module 1700 may include a camera module 1710, an optical module 1720, and a communication module 1730.

[0110] Sensor module 1610 may include touch electrodes and touch sensor drivers for the touchscreen layer of display panel 10. Sensor module 1610 can sense input caused by a user's body or by a pen, and generate electrical signals or data values ​​corresponding to the input. Sensor module 1610 may include at least one of fingerprint sensor 1611, input sensor 1612, and digitizer 1613.

[0111] The fingerprint sensor 1611 can generate data values ​​corresponding to a user's fingerprint. The fingerprint sensor 1611 may include one of an optical fingerprint sensor and a capacitive fingerprint sensor.

[0112] The input sensor 1612 can generate data values ​​corresponding to the coordinate information of input caused by the user's body or by a pen. The input sensor 1612 generates the amount of capacitance change caused by the input as a data value. The input sensor 1612 can sense input caused by a passive pen, or transmit data to / receive data from an active pen.

[0113] The input sensor 1612 can also measure biosignals related to biological information such as blood pressure, water content, or body fat. As an example, if a user touches a part of their body to the sensor layer or sensing panel and does not move it for a preset time, the input sensor 1612 can sense the biosignal based on the change in the electric field caused by that part of the user's body and output the information desired by the user to the display module 1400.

[0114] The digitizer 1613 can generate data values ​​corresponding to the coordinate information of the input caused by the pen. The digitizer 1613 generates the amount of electromagnetic change caused by the input as a data value. The digitizer 1613 can sense the input caused by a passive pen, or transmit data to / receive data from an active pen.

[0115] In an embodiment, at least one of the fingerprint sensor 1611, the input sensor 1612, and the digitizer 1613 may be integrated into the display panel 10. As an example, at least one of the fingerprint sensor 1611, the input sensor 1612, and the digitizer 1613 may be formed during a process following the formation of the pixel circuitry and light-emitting diodes of the display panel 10. Accordingly, the display panel 10 may function as one of the input modules 1300 providing an input interface between the electronic device 1 and the user, and may also function as a display module 1400 providing an output interface between the electronic device 1 and the user.

[0116] In another embodiment, at least two of the fingerprint sensor 1611, input sensor 1612, and digitizer 1613 may be formed into an integrated sensing panel using the same process. Although the sensing panel may be disposed between the display panel 10 and the overlay window 70 disposed on the display panel 10, this disclosure is not limited thereto.

[0117] Antenna module 1620 may include at least one antenna for transmitting or receiving signals or power to or from an external source. In an embodiment, antenna module 1620 may transmit or receive signals to or from external electronic device 2000 via an antenna suitable for a communication method. The antenna pattern of antenna module 1620 may be integrated into a component of display module 1400 (e.g., display panel 10) or input sensor 1612.

[0118] The sound output module 1630 is a device for outputting sound signals to the outside of the electronic device 1, and can output sound data received from the communication module 1730 or sound data stored in the memory 1200 during call signal reception, communication mode, recording mode, voice recognition mode, and broadcast reception mode. The sound output module 1630 can output sound signals related to the functions performed by the electronic device 1 (e.g., call signal reception tone and message reception tone). The sound output module 1630 may include a receiver and a speaker. At least one of the receiver and speaker may be a sound generator attached to the display panel 10 and vibrating the display panel 10 to output sound. The sound generator may be a piezoelectric element or piezoelectric actuator that contacts and expands according to an electrical signal, or it may be an exciter that generates magnetic force by using a voice coil to vibrate the display panel 10.

[0119] Camera module 1710 can capture still images and moving images. In embodiments, camera module 1710 may include at least one lens, image sensor, or image signal processor. Camera module 1710 may further include an infrared camera capable of measuring the presence of a user, the user's position, and the user's gaze, etc.

[0120] The light module 1720 can use light from a light source to output a signal to notify of an event, or it can provide light to obtain an image. Examples of events include message reception, call signal reception, missed calls, alarms, calendar reminders, receiving emails, and being notified of battery charging information. The light module 1720 may include a light-emitting diode or a xenon lamp. The light module 1720 can emit monochromatic or multicolor light to the front or back of the electronic device 1. The light module 1720 can operate in conjunction with the camera module 1710 or independently.

[0121] Communication module 1730 can establish a wired or wireless communication channel between electronic device 1 and external electronic device 2000, and perform communication through the established communication channel. Communication module 1730 may include one or both of the following: a wireless communication module such as a cellular communication module, a short-range wireless communication module, or a Global Navigation Satellite System (GNSS) communication module; and a wired communication module such as a Local Area Network (LAN) communication module or a power line communication module. Communication module 1730 can transmit and receive wireless signals via the Internet using at least one of Wireless LAN (WLAN), Wi-Fi, Wi-Fi Direct, and Digital Living Network Alliance (DLNA) technologies. Additionally, communication module 1730 can support the use of... The communication module 1730 can be implemented in a single chip or as a separate chip. It supports short-range communication using at least one of the following technologies: RFID (Radio Frequency Identification), Infrared Data Association (IrDA), Ultra-Wideband (UWB), ZigBee, Near Field Communication (NFC), Wi-Fi, Wi-Fi Direct, and Wireless USB.

[0122] Additionally, the electronic device 1 may further include a component 40 that generates electrical signals or data values ​​corresponding to the internal or external states of the electronic device 1. Component 40 may include, for example, a proximity sensor, a brightness sensor, an acceleration sensor, a magnetic sensor, a gravity sensor, a gyroscope sensor, a motion sensor, an RGB sensor, an infrared sensor, a fingerprint scanning sensor, an ultrasonic sensor, an optical sensor, an environmental sensor (e.g., a barometer, a hygrometer, a thermometer, a radiation detection sensor, a thermal detection sensor, and a gas detection sensor), and a chemical sensor (e.g., an electronic nose, a medical sensor, and a biosensor).

[0123] Electronic device 1 outputs various information through display module 1400 within the operating system. When processor 1100 executes an application stored in memory 1200, display module 1400 provides application information to the user through display panel 10.

[0124] Based on input data received from input module 1300 or sensor module 1610, processor 1100 outputs commands or data to display module 1400, sound output module 1630, camera module 1710, or optical module 1720. As an example, processor 1100 can generate image data corresponding to the input data and output the image data to display module 1400, or generate command data corresponding to the input data and output the command data to camera module 1710 or optical module 1720. When no input data is received from input module 1300 within a preset time, processor 1100 switches the operating mode of electronic device 1 to low-power mode or sleep mode to reduce the power consumed by electronic device 1.

[0125] Processor 1100 receives external input via input module 1300 or sensor module 1610 and executes an application corresponding to the external input. For example, if a user selects a camera icon displayed on display panel 10, processor 1100 receives user input via input sensor 1612 and activates camera module 1710. Processor 1100 transmits image data corresponding to the captured image obtained by camera module 1710 to display module 1400. Display module 1400 can display the image corresponding to the captured image via display panel 10.

[0126] As another example, when the display module 1400 performs personal information authentication, the fingerprint sensor 1611 acquires the input fingerprint information as input data. The processor 1100 compares the input data acquired by the fingerprint sensor 1611 with the authentication data stored in the memory 1200, and executes the application based on the comparison result. The display module 1400 can display the information executed according to the application logic via the display panel 10.

[0127] As another example, when a music stream icon displayed on display module 1400 is selected, processor 1100 obtains user input via input sensor 1612 and launches a music stream application stored in memory 1200. When a music execution command is entered in the music stream application, processor 1100 activates sound output module 1630 and provides the user with sound information matching the music execution command.

[0128] Some of the components can be connected to each other via communication methods between peripherals, such as buses, general purpose input / output (GPIO), serial peripheral interfaces (SPI), mobile industrial processor interfaces (MIPI), or ultrapath interconnect (UPI) links, to exchange signals (e.g., commands or data). In an embodiment, the main processor 1110 can transmit image signals to the auxiliary processor 1120 via MIPI.

[0129] Figure 4 This is a schematic plan view of the display panel 10 according to an embodiment.

[0130] refer to Figure 4 The display panel 10 may include a display area DA and a peripheral area PA outside the display area DA. The display area DA is the area in which an image is displayed and can be configured with multiple pixels. The display area DA can have various shapes, such as a circular shape, an elliptical shape, a polygonal shape, or a shape of a specific graphic. As an example, in Figure 4 The display area DA shown has an approximate rectangular shape with rounded corners.

[0131] A peripheral region PA can be disposed outside the display area DA. The peripheral region PA may include a first peripheral region PA1 and a second peripheral region PA2, wherein the first peripheral region PA1 is configured to surround at least a portion of the display area DA, and the second peripheral region PA2 is adjacent to one side of the display area DA and extends in a second direction (e.g., the y-direction). The width of the second peripheral region PA2 in the first direction (e.g., the x-direction) may be smaller than the width of the display area DA in the first direction (e.g., the x-direction). At least a portion of the second peripheral region PA2 can be easily bent using this structure. In an embodiment, the display panel 10 can be bent about a bending axis intersecting the second peripheral region PA2.

[0132] Figure 4 The planar shape of the display panel 10 shown may be substantially the same as the shape of the substrate 100 included in the display panel 10. When the display panel 10 includes a display area DA and a peripheral area PA outside the display area DA, it can be said that the substrate 100 includes the display area DA and the peripheral area PA outside the display area DA. In the following description, for convenience, it is based on the assumption that the substrate 100 includes the display area DA and the peripheral area PA.

[0133] Substrate 100 may comprise glass, metal, or polymer resin. Substrate 100 may comprise polymer resins such as polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, or cellulose acetate propionate. Substrate 100 may have a multilayer structure comprising two layers containing the aforementioned polymer resin and an inorganic material layer disposed between the two layers.

[0134] Pixels can be disposed in a display area DA, and the display area DA can display an image using light emitted from the pixels. Each pixel can include multiple subpixels. As an example, a pixel can include a red subpixel, a green subpixel, and a blue subpixel. Each subpixel can include a light-emitting diode (LED), and the LED can be electrically connected to subpixel circuitry PCs. The subpixel circuitry PCs and the LEDs can be disposed in the display area DA.

[0135] The scan driver 1420, data driver 1430, pad section 14, drive voltage supply line 15, and common voltage supply line 16 can be located in the peripheral area PA.

[0136] Scan driver 1420 can be configured to provide scan signals to sub-pixel circuits PCs via scan lines SL. Scan lines SL can be gate lines connected to the gates of switching transistors included in the sub-pixel circuits PCs. Scan signals can be gate signals that turn the switching transistors included in the sub-pixel circuits PCs on or off. Scan drivers 1420 can be disposed on opposite sides of the peripheral region PA, with the display region DA located between scan drivers 1420. Some of the sub-pixel circuits PCs disposed in the display region DA can be electrically connected to the scan driver 1420 disposed on the left (-x direction), and the remaining sub-pixel circuits PCs can be electrically connected to the scan driver 1420 disposed on the right (+x direction). In another embodiment, scan drivers 1420 can be disposed only on one side of the peripheral region PA.

[0137] The pad portion 14 may be disposed in the second peripheral region PA2 of the substrate 100. The pad portion 14 may include a plurality of pads electrically connected to the display circuit board 30 and exposed by an insulating layer without being covered by an insulating layer. The pads 34 of the display circuit board 30 may be electrically connected to the pad portion 14 of the display panel 10.

[0138] The display circuit board 30 transmits signals from the auxiliary processor 1120 to the display panel 10. Control signals generated by the auxiliary processor 1120 can be transmitted through the display circuit board 30 to the scan driver 1420 and the data driver 1430. In an embodiment, the display circuit board 30 may include a power management IC (not shown). The power management IC can provide a drive voltage ELVDD (see FIG. 5) and a common voltage ELVSS (see FIG. 5) to the drive voltage supply line 15 and the common voltage supply line 16, respectively. The drive voltage ELVDD can be provided to the sub-pixel circuits PCs through the drive voltage line PL connected to the drive voltage supply line 15, and the common voltage ELVSS can be provided to the counter electrode of the light-emitting diodes (LEDs) connected to the common voltage supply line 16. The drive voltage supply line 15 may extend in a first direction (e.g., the x-direction). The common voltage supply line 16 may have a ring shape with an open side and partially surround the display area DA.

[0139] Data signals can be transmitted to sub-pixel circuits PCs via the input line IL and the data line DL, which is electrically connected to the input line IL.

[0140] Figures 5A to 5C This is an equivalent circuit diagram of the light-emitting diodes (LEDs) and sub-pixel circuits (PCs) of the display panel 10 according to an embodiment.

[0141] refer to Figure 5A Subpixel circuits (PCs) can be connected to light-emitting diodes (LEDs) to enable subpixel illumination. LEDs can emit red, green, blue, or white light. The subpixel circuits (PCs) may include a storage capacitor (Cst), a first transistor (T1) that is a driving transistor, and a second transistor (T2) that is a switching transistor. The second transistor (T2) can be connected to a gate line (GL) and a data line (DL), and is configured to transmit a data signal (Dm) to the first transistor (T1) according to a gate signal, wherein the data signal (Dm) is input through the data line (DL) and the gate signal is input through the gate line (GL).

[0142] The storage capacitor Cst can be connected to the gate of the first transistor T1 and the drive voltage line PL, and is configured to store the voltage corresponding to the difference between the voltage delivered from the second transistor T2 and the drive voltage ELVDD supplied to the drive voltage line PL.

[0143] The first transistor T1 can be connected to the drive voltage line PL and the storage capacitor Cst, and is configured to control the drive current Id according to the voltage stored in the storage capacitor Cst. The drive current Id flows from the drive voltage line PL to the light-emitting diode (LED). The LED can be configured to emit light at a preset brightness based on the drive current Id.

[0144] refer to Figure 5B The sub-pixel circuits PCs may include first to seventh transistors T1, T2, T3, T4, T5, T6, and T7, and a storage capacitor Cst. Depending on the transistor type (P-type or N-type) and / or operating conditions, the first terminal of each of the first to seventh transistors T1, T2, T3, T4, T5, T6, and T7 may be a source or a drain, and the second terminal may be a terminal different from the first terminal. As an example, if the first terminal is a source, the second terminal may be a drain. The first transistor T1 may be a drive transistor in which the magnitude of its source-drain current is determined according to its gate-source voltage, and the second to seventh transistors T2, T3, T4, T5, T6, and T7 may be switching transistors that are turned on / off according to the gate-source voltage or the gate voltage.

[0145] The sub-pixel circuits PCs can be connected to a first gate line GWL, a second gate line GIL, a third gate line GBL, an emit control line EML, a data line DL, a drive voltage line PL, and a first initialization voltage line VIL. The first gate line GWL is configured to transmit a first scan signal (first gate signal) GW, the second gate line GIL is configured to transmit a second scan signal (second gate signal) GI, the third gate line GBL is configured to transmit a third scan signal (third gate signal) GB, the emit control line EML is configured to transmit an emit control signal EM, the data line DL is configured to transmit a data signal Dm, the drive voltage line PL is configured to transmit a drive voltage ELVDD, and the first initialization voltage line VIL is configured to transmit a first initialization voltage VINT.

[0146] The first transistor T1 may include a gate, a first terminal, and a second terminal, wherein the gate is connected to a second node N2, the first terminal is connected to a first node N1, and the second terminal is connected to a third node N3. The first transistor T1 receives a data signal Dm according to the switching operation of the second transistor T2 and is configured to supply a drive current Id to a light-emitting diode (LED). The LED may be an organic light-emitting diode (OLED).

[0147] The second transistor T2 may include a gate, a first terminal, and a second terminal, wherein the gate is connected to a first gate line GWL, the first terminal is connected to a data line DL, and the second terminal is connected to a first node N1. The second transistor T2 can be turned on according to a first gate signal GW transmitted through the first gate line GWL, and can perform a switching operation to transmit a data signal Dm to the first node N1, wherein the data signal Dm is transmitted through the data line DL.

[0148] The third transistor T3 may include a gate, a first terminal, and a second terminal, wherein the gate is connected to a first gate line GWL, the first terminal is connected to a second node N2, and the second terminal is connected to a third node N3. The third transistor T3 can be turned on according to a first gate signal GW to connect the first transistor T1 diode, wherein the first gate signal GW is transmitted through the first gate line GWL.

[0149] The fourth transistor T4 may include a gate, a first terminal, and a second terminal, wherein the gate is connected to a second gate line GIL, the first terminal is connected to a first initialization voltage line VIL, and the second terminal is connected to a second node N2. The fourth transistor T4 may be turned on according to a second gate signal GI to initialize the gate voltage of the first transistor T1 by transmitting the first initialization voltage VINT to the gate of the first transistor T1, wherein the second gate signal GI is transmitted through the second gate line GIL.

[0150] The fifth transistor T5 may include a gate, a first terminal, and a second terminal, wherein the gate is connected to the emitter control line EML, the first terminal is connected to the drive voltage line PL, and the second terminal is connected to the first node N1. The sixth transistor T6 may include a gate, a first terminal, and a second terminal, wherein the gate is connected to the emitter control line EML, the first terminal is connected to the third node N3, and the second terminal is connected to the pixel electrode of the light-emitting diode (LED). The fifth transistor T5 and the sixth transistor T6 are simultaneously turned on according to the emitter control signal EM, and a drive current Id flows through the LED, wherein the emitter control signal EM is transmitted through the emitter control line EML.

[0151] The seventh transistor T7 may include a gate, a first terminal, and a second terminal. The gate is connected to a third gate line GBL, the first terminal is connected to the second terminal of the sixth transistor T6 and the pixel electrode of the light-emitting diode (LED), and the second terminal is connected to a first initialization voltage line VIL. The seventh transistor T7 can be turned on according to the third gate signal GB to initialize the pixel electrode of the LED by transmitting the first initialization voltage VINT to the pixel electrode of the LED, wherein the third gate signal GB is transmitted through the third gate line GBL. The seventh transistor T7 may be omitted.

[0152] The storage capacitor Cst may include a first capacitor electrode and a second capacitor electrode, wherein the first capacitor electrode is connected to a second node N2 and the second capacitor electrode is connected to a drive voltage line PL.

[0153] A light-emitting diode (LED) may include a pixel electrode (e.g., an anode) and a common electrode (e.g., a cathode or counter electrode) facing the pixel electrode, wherein the common electrode may be configured to receive a common voltage ELVSS. The LED can display an image by receiving a drive current Id from a first transistor T1 and emitting light of a preset color.

[0154] refer to Figure 5C The sub-pixel circuits PCs may include first to eighth transistors T1, T2, T3, T4, T5, T6, T7, and T8, and a storage capacitor Cst. The first transistor T1 may be a driving transistor in which the magnitude of its source-drain current is determined according to its gate-source voltage, and the second to eighth transistors T2, T3, T4, T5, T6, T7, and T8 may be switching transistors for transmitting signals.

[0155] The sub-pixel circuits PCs can be connected to a first gate line GWL, a second gate line GIL, a third gate line GBL, a fourth gate line GCL, an emit control line EML, a data line DL, a drive voltage line PL, a first initialization voltage line VIL, a second initialization voltage line VAIL, and a bias voltage line VOBL. Specifically, the first gate line GWL is configured to transmit a first scan signal (first gate signal) GW; the second gate line GIL is configured to transmit a second scan signal (second gate signal) GI; the third gate line GBL is configured to transmit a third scan signal (third gate signal) GB; the fourth gate line GCL is configured to transmit a fourth gate signal GC; the emit control line EML is configured to transmit an emit control signal EM; the data line DL is configured to transmit a data signal Dm; the drive voltage line PL is configured to transmit a drive voltage ELVDD; the first initialization voltage line VIL is configured to transmit a first initialization voltage VINT; the second initialization voltage line VAIL is configured to transmit a second initialization voltage VAINT; and the bias voltage line VOBL is configured to transmit a bias voltage VOBS.

[0156] The first transistor T1 may include a gate, a first terminal, and a second terminal, wherein the gate is connected to a second node N2, the first terminal is connected to a first node N1, and the second terminal is connected to a third node N3. The first transistor T1 receives a data signal Dm according to the switching operation of the second transistor T2 and is configured to supply a drive current Id to a light-emitting diode (LED).

[0157] The second transistor T2 may include a gate, a first terminal, and a second terminal, wherein the gate is connected to a first gate line GWL, the first terminal is connected to a data line DL, and the second terminal is connected to a first node N1. The second transistor T2 can be turned on according to a first gate signal GW transmitted through the first gate line GWL, and can perform a switching operation to transmit a data signal Dm to the first node N1, wherein the data signal Dm is transmitted through the data line DL.

[0158] The third transistor T3 may include a gate, a first terminal, and a second terminal, wherein the gate is connected to a fourth gate line GCL, the first terminal is connected to a second node N2, and the second terminal is connected to a third node N3. The third transistor T3 can be turned on according to a fourth gate signal GC to connect the first transistor T1 diode, wherein the fourth gate signal GC is transmitted through the fourth gate line GCL.

[0159] The fourth transistor T4 may include a gate, a first terminal, and a second terminal, wherein the gate is connected to a second gate line GIL, the first terminal is connected to a first initialization voltage line VIL, and the second terminal is connected to a second node N2. The fourth transistor T4 may be turned on according to a second gate signal GI to initialize the gate voltage of the first transistor T1 by transmitting the first initialization voltage VINT to the gate of the first transistor T1, wherein the second gate signal GI is transmitted through the second gate line GIL.

[0160] The fifth transistor T5 may include a gate, a first terminal, and a second terminal, wherein the gate is connected to the emitter control line EML, the first terminal is connected to the drive voltage line PL, and the second terminal is connected to the first node N1. The sixth transistor T6 may include a gate, a first terminal, and a second terminal, wherein the gate is connected to the emitter control line EML, the first terminal is connected to the third node N3, and the second terminal is connected to the pixel electrode of the light-emitting diode (LED). The fifth transistor T5 and the sixth transistor T6 are simultaneously turned on according to the emitter control signal EM, and a drive current Id flows through the LED, wherein the emitter control signal EM is transmitted through the emitter control line EML.

[0161] The seventh transistor T7 may include a gate, a first terminal, and a second terminal. The gate is connected to a third gate line GBL, the first terminal is connected to the second terminal of the sixth transistor T6 and the pixel electrode of the light-emitting diode (LED), and the second terminal is connected to a second initialization voltage line VAIL. The seventh transistor T7 can be turned on according to the third gate signal GB to initialize the pixel electrode of the LED by transmitting the second initialization voltage VAINT to the pixel electrode of the LED. The third gate signal GB is transmitted through the third gate line GBL, and the second initialization voltage VAINT is transmitted from the second initialization voltage line VAIL.

[0162] The eighth transistor T8 includes a gate, a first terminal, and a second terminal, wherein the gate is connected to a third gate line GBL, the first terminal is connected to a first node N1, and the second terminal is connected to a bias voltage line VOBL. The eighth transistor T8 can be turned on according to a third gate signal GB transmitted through the third gate line GBL, and is configured to transmit a bias voltage VOBS to the first node N1, wherein the bias voltage VOBS is transmitted from the bias voltage line VOBL.

[0163] The storage capacitor Cst may include a first capacitor electrode CE1 and a second capacitor electrode CE2, wherein the first capacitor electrode CE1 is connected to the second node N2 and the second capacitor electrode CE2 is connected to the drive voltage line PL.

[0164] A light-emitting diode (LED) may include a pixel electrode (e.g., an anode) and a common electrode (e.g., a cathode) facing the pixel electrode, wherein the common electrode may be configured to receive a common voltage ELVSS. The LED can display an image by receiving a drive current Id from a first transistor T1 and emitting light of a preset color.

[0165] Despite Figure 5A and Figure 5B The transistors in the sub-pixel circuits PCs shown are P-type transistors, but the embodiments are not limited to this. As another example, the transistors in the sub-pixel circuits PCs can be N-type transistors, or as shown in the diagram. Figure 5C As shown, some transistors can be P-type transistors and others can be N-type transistors. As an example, the third transistor T3 and the fourth transistor T4 can be N-type transistors, and the rest can be P-type transistors. Figures 5A to 5C Subpixel circuits PCs are provided as examples, and the design of subpixel circuits PCs according to this disclosure can be modified in various ways.

[0166] Figure 6 This is a schematic plan view of the common voltage supply line 16 and the auxiliary common voltage line VSSLa of the display panel 10 according to an embodiment.

[0167] refer to Figure 6 The display panel 10 may include a display area DA and a peripheral area PA outside the display area DA. A pad portion 14 may be disposed on one side of the substrate 100. The pad portion 14 may be electrically connected to the display circuit board 30.

[0168] A common voltage supply line 16 can be located in the peripheral area PA. The common voltage supply line 16 can have a ring shape with an open side and partially surround the display area DA. The common voltage supply line 16 can be electrically connected to the power management integrated circuit of the display board 30 via pad portion 14 to receive the common voltage ELVSS.

[0169] In an embodiment, the display panel 10 may include auxiliary common voltage lines VSSLa disposed in the display area DA. The auxiliary common voltage lines VSSLa may each extend in a second direction (e.g., the y-direction) and be separated from each other in a first direction (e.g., the x-direction). The auxiliary common voltage lines VSSLa may each be electrically connected to a common voltage supply line 16 on the upper (+y-direction) and / or lower (-y-direction) side of the peripheral area PA to receive the common voltage ELVSS. In an embodiment, the auxiliary common voltage lines VSSLa may each be electrically connected to the counter electrode of the light-emitting diode (LED) via auxiliary electrodes (not shown) in the display area DA. The display panel 10 can reduce the voltage drop of the common voltage ELVSS due to the resistance of the counter electrode by using the auxiliary common voltage lines VSSLa. Accordingly, the display panel 10 can display high-quality images by preventing or reducing brightness degradation due to the voltage drop of the common voltage ELVSS.

[0170] Figure 7 This is a schematic plan view of voltage lines with a grid structure according to an embodiment.

[0171] refer to Figure 7 The display panel 10 may include a display area DA and a peripheral area PA outside the display area DA. A pad portion 14 may be disposed on one side of the substrate 100. The pad portion 14 may be electrically connected to the display circuit board 30.

[0172] A voltage supply line VLo can be disposed within the peripheral region PA. In one embodiment, the voltage supply line VLo can have a ring shape with an open side and partially surround the display region DA. In another embodiment, the voltage supply line VLo can be disposed on two opposite sides of the peripheral region PA, with the display region DA between the voltage supply lines VLo. The voltage supply line VLo can be electrically connected to the power management integrated circuit of the display board 30 via pad portion 14 to receive a direct current (DC) voltage.

[0173] The display panel 10 may include horizontal voltage lines VLh and vertical voltage lines VLv disposed in the display area DA. The horizontal voltage lines VLh may each extend in a first direction (e.g., the x-direction) and be separated from each other in a second direction (e.g., the y-direction). The horizontal voltage lines VLh may each be electrically connected to a voltage supply line VLo located to the left (-x direction) and / or right (+x direction) of the peripheral area PA to receive DC voltage. The horizontal voltage lines VLh may each be electrically connected to sub-pixel circuits PCs disposed in the same row to transmit DC voltage to the sub-pixel circuits PCs.

[0174] Vertical voltage lines VLv may each extend in a second direction (e.g., the y-direction) and be separated from each other in a first direction (e.g., the x-direction). Vertical voltage lines VLv may be disposed on different layers from horizontal voltage lines VLh. Vertical voltage lines VLv may each be electrically connected to horizontal voltage lines VLh through contact holes disposed in the display area DA to form a mesh structure. In an embodiment, vertical voltage lines VLv may each be electrically connected to voltage supply lines VLo on the upper (+y-direction) and / or lower (-y-direction) sides of the peripheral area PA.

[0175] The DC voltage can be one of the voltages supplied to the sub-pixel circuits (PCs). As an example, the DC voltage can be a first initialization voltage VINT, a second initialization voltage VAINT, or a bias voltage VOBS. When the DC voltage is the first initialization voltage VINT, the horizontal voltage line VLh can be the first initialization voltage line VIL, and the vertical voltage line VLv can be the first auxiliary initialization voltage line. When the DC voltage is the second initialization voltage VAINT, the horizontal voltage line VLh can be the second initialization voltage line VAIL, and the vertical voltage line VLv can be the second auxiliary initialization voltage line. When the DC voltage is the bias voltage VOBS, the horizontal voltage line VLh can be the bias voltage line VOBL, and the vertical voltage line VLv can be an auxiliary bias voltage line. The mesh structure can reduce the brightness deviation at each location of each sub-pixel by reducing the DC voltage drop.

[0176] Figure 8 This is a schematic diagram of the construction of the voltage line according to an embodiment.

[0177] refer to Figure 8 The first initialization voltage line VIL, the second-1 initialization voltage line VAIL1 and the second-2 initialization voltage line VAIL2 extending in the first direction (e.g., the x direction) and the auxiliary voltage line VLa extending in the second direction (e.g., the y direction) can be disposed in the display area DA of the display panel 10.

[0178] Each of the first initialization voltage lines VIL can transmit a first initialization voltage VINT to a sub-pixel circuit PCs arranged in the same row. In an embodiment, the second initialization voltage VAINT transmitted to the sub-pixel circuit PCs may vary depending on the color of the light emitted by the light-emitting diodes (LEDs) electrically connected to the sub-pixel circuit PCs. The second-1 initialization voltage line VAIL1 and the second-2 initialization voltage line VAIL2 may each correspond to a reference. Figure 5C The second initialization voltage line VAIL is described. As an example, the second-1 initialization voltage line VAIL1 can be electrically connected to the red sub-pixel circuits PCs arranged in the same row to transmit the second-1 initialization voltage. The second-2 initialization voltage line VAIL2 can be electrically connected to the blue and green sub-pixel circuits PCs arranged in the same row to transmit the second-2 initialization voltage.

[0179] Auxiliary voltage lines VLa can be arranged separately from each other in a first direction (e.g., the x-direction), and the voltages transmitted by each auxiliary voltage line VLa can have values ​​in a preset order repeated in the first direction (e.g., the x-direction). In an embodiment, the first auxiliary voltage line VLa can be the first auxiliary initialization voltage line VILa that transmits the first initialization voltage VINT. The third auxiliary voltage line VLa can be the second-1 auxiliary initialization voltage line VAIL1a that transmits the second-1 initialization voltage. The fifth auxiliary voltage line VLa can be the second-2 auxiliary initialization voltage line VAIL2a that transmits the second-2 initialization voltage. Each of the second, fourth, and sixth auxiliary voltage lines VLa can be an auxiliary common voltage line VSSLa that transmits the common voltage ELVSS. The six auxiliary voltage lines VLa arranged sequentially in the first direction (e.g., the x-direction) can be defined as an auxiliary voltage line group GR. The auxiliary voltage line group GR can be repeatedly arranged in the first direction (e.g., the x-direction) in the display area DA.

[0180] The first auxiliary initialization voltage line VILa can be electrically connected to the first initialization voltage line VIL in the display area DA through the first contact hole CNTv1. The first initialization voltage line VIL and the first auxiliary initialization voltage line VILa can form a grid structure for transmitting the first initialization voltage VINT.

[0181] The second-1 initialization voltage line VAIL1 can be electrically connected to the second-1 auxiliary initialization voltage line VAIL1a in the display area DA through the second contact hole CNTv2. The second-1 initialization voltage line VAIL1 and the second-1 auxiliary initialization voltage line VAIL1a can form a grid structure for transmitting the second-1 initialization voltage.

[0182] The second-2 initialization voltage line VAIL2 can be electrically connected to the second-2 auxiliary initialization voltage line VAIL2a in the display area DA through the third contact hole CNTv3. The second-2 initialization voltage line VAIL2 and the second-2 auxiliary initialization voltage line VAIL2a can form a grid structure for transmitting the second-2 initialization voltage.

[0183] The auxiliary common voltage line VSSLa may not be electrically connected to other voltage lines located below it in the display area DA. The auxiliary common voltage line VSSLa may be electrically connected to the common voltage supply line 16 in the peripheral area PA to transmit the common voltage ELVSS.

[0184] Despite Figure 8 The diagram shows an auxiliary voltage line group GR comprising six auxiliary voltage lines VLa, but this disclosure is not limited thereto. In another embodiment, the auxiliary voltage line group GR may include fewer or more auxiliary voltage lines VLa. As an example, the auxiliary voltage line group GR may further include auxiliary bias voltage lines, and these auxiliary bias voltage lines may be electrically connected to the bias voltage line VOBL in the display area DA to form a grid structure for transmitting the bias voltage VOBS. The design of the order in which the voltages transmitted by the auxiliary voltage lines VLa included in the auxiliary voltage line group GR can be varied.

[0185] Figure 9A This is a plan view of the selection of the first conductive layer 500 of the display panel 10 according to an embodiment. Figure 9B This is a plan view of the selected second conductive layer 600 of the display panel 10 according to an embodiment, and Figure 9C This is a plan view of the overlapping first conductive layer 500 and second conductive layer 600 of the display panel 10 according to an embodiment. Figure 10 This is a schematic plan view of the data line and shielding pattern according to an embodiment. Figure 11 It is along Figure 9C The line II-II' intercepted Figure 9C A schematic cross-sectional view of the display panel 10, and Figure 12 It is along Figure 9C The line III-III' intercepted Figure 9C A schematic cross-sectional view of the display panel 10. Additionally, Figures 9A to 9C It can correspond to Figure 4 The part "I" in the text.

[0186] refer to Figures 9A to 9C and Figure 11 The display panel 10 may include a substrate 100, a pixel circuit PC disposed on the substrate 100, and light-emitting diodes LED2 and LED3 disposed on the pixel circuit PC.

[0187] A pixel circuit layer PCL, including pixel circuits PC, can be disposed on the substrate 100. The pixel circuits PC can be disposed in a pixel circuit region PCA, and can include a first sub-pixel circuit PCs1, a second sub-pixel circuit PCs2, and a third sub-pixel circuit PCs3. The first sub-pixel circuits PCs1, the second sub-pixel circuits PCs2, and the third sub-pixel circuit PCs3 can be disposed adjacent to each other in a first direction (e.g., the x-direction). The first sub-pixel circuit PCs1 can be disposed in a first sub-region SA1, the second sub-pixel circuit PCs2 can be disposed in a second sub-region SA2, and the third sub-pixel circuit PCs3 can be disposed in a third sub-region SA3.

[0188] Each of the first sub-pixel circuit PCs1, the second sub-pixel circuit PCs2, and the third sub-pixel circuit PCs3 may include a storage capacitor Cst and at least one transistor TR. The transistor TR may include a semiconductor layer Act, a gate electrode GE, a source electrode SE, and a drain electrode DE, wherein the gate electrode GE overlaps with the channel region of the semiconductor layer Act in a planar view, the source electrode SE is electrically connected to the source region of the semiconductor layer Act, and the drain electrode DE is electrically connected to the drain region of the semiconductor layer Act. In embodiments, at least one of the source electrode SE and the drain electrode DE of the transistor TR may be omitted, and the drain region or source region of the transistor TR may be connected to the source region or drain region of an adjacent transistor.

[0189] In this embodiment, the semiconductor layer Act may comprise a silicon-based semiconductor material or an oxide-based semiconductor material. Silicon-based semiconductor materials may include amorphous silicon and polycrystalline silicon (e.g., low-temperature polycrystalline silicon (LTPS)). Oxide-based semiconductor materials may comprise at least one selected from indium (In), gallium (Ga), tin (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), aluminum (Al), cesium (Cs), cerium (Ce), and zinc (Zn). As an example, oxide-based semiconductor materials may include InSnZnO (ITZO) or InGaZnO (IGZO).

[0190] The storage capacitor Cst may include a first capacitor electrode CE1 and a second capacitor electrode CE2 that overlaps with the first capacitor electrode CE1 in a plan view. In an embodiment, the first capacitor electrode CE1 may be integrally connected to the gate electrode GE of the transistor TR.

[0191] At least one insulating layer may be disposed between the semiconductor layer Act of transistor TR and the gate electrode GE, between the first capacitor electrode CE1 and the second capacitor electrode CE2, and between the second capacitor electrode CE2 and the source electrode SE and the drain electrode DE.

[0192] The first insulating layer 110 may be disposed on the pixel circuit layer PCL. The first insulating layer 110 may include an organic insulating material such as acrylic acid, benzocyclobutene (BCB), polyimide, or hexamethyldisiloxane (HMDSO).

[0193] The first conductive layer 500 may be disposed on the first insulating layer 110. The first conductive layer 500 may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and / or copper (Cu), and may include a single layer or multiple layers comprising the above materials. In an embodiment, the first conductive layer 500 may have a three-layer structure of titanium layer / aluminum layer / titanium layer.

[0194] The first conductive layer 500 may include a first data line DL1, a second data line DL2, a third data line DL3, a first driving voltage line PL1, a second driving voltage line PL2, and an auxiliary voltage line VLa. The first conductive layer 500 may include a first connecting electrode CM1, a second connecting electrode CM2, and a third connecting electrode CM3. The first data line DL1, the second data line DL2, the third data line DL3, the first driving voltage line PL1, the second driving voltage line PL2, and the auxiliary voltage line VLa may extend generally in a second direction (e.g., the y-direction). Here, extending generally in a second direction (e.g., the y-direction) means that some portions of the wiring may be bent and extended in a first direction (e.g., the x-direction), etc.

[0195] The first data line DL1, the second data line DL2, and the third data line DL3 can be connected to the first sub-pixel circuit PCs1, the second sub-pixel circuit PCs2, and the third sub-pixel circuit PCs3, respectively, to transmit the data signal Dm. The first data line DL1 can be located to the left (in the -x direction) of the first sub-region SA1, and the second data line DL2 can be located to the right (in the +x direction) of the second sub-region SA2. In an embodiment, the first data line DL1 and the second data line DL2 can be symmetrically arranged about a virtual line RL1 that passes between the first sub-pixel circuit PCs1 and the second sub-pixel circuit PCs2 and is parallel to the second direction (e.g., the y-direction).

[0196] The first driving voltage line PL1 and the second driving voltage line PL2 can transmit the driving voltage ELVDD to the first sub-pixel circuit PCs1, the second sub-pixel circuit PCs2, and the third sub-pixel circuit PCs3. The first driving voltage line PL1 can be located in the first sub-region SA1 and the second sub-region SA2, and the second driving voltage line PL2 can be located in the third sub-region SA3. In a planar view, the first driving voltage line PL1 can be located between the first data line DL1 and the second data line DL2, and can overlap with the first sub-pixel circuit PCs1 and the second sub-pixel circuit PCs2. In a planar view, the second driving voltage line PL2 can be located between the second data line DL2 and the third data line DL3, and can overlap with the third sub-pixel circuit PCs3.

[0197] The auxiliary voltage line VLa can be wiring that transmits DC voltage. As an example, the auxiliary voltage line VLa can be a first auxiliary initialization voltage line VILa, a second-1 auxiliary initialization voltage line VAIL1a, a second-2 auxiliary initialization voltage line VAIL2a, or an auxiliary common voltage line VSSLa. In an embodiment, in a plan view, the auxiliary voltage line VLa can be positioned between the second data line DL2 and the second drive voltage line PL2. The third data line DL3 and the auxiliary voltage line VLa can be symmetrically positioned about a virtual line RL2 that passes through and is parallel to a second direction (e.g., the y-direction) across the third sub-pixel circuit PCs3.

[0198] In each pixel circuit region PCA, the first data line DL1, the first driving voltage line PL1, the second data line DL2, the auxiliary voltage line VLa, the second driving voltage line PL2, and the third data line DL3 can be sequentially arranged in a first direction (e.g., the x direction).

[0199] The second insulating layer 120 may be disposed on the first conductive layer 500. The second insulating layer 120 may comprise an organic insulating material such as acrylic acid, benzocyclobutene (BCB), polyimide, or hexamethyldisiloxane (HMDSO).

[0200] The second conductive layer 600 may be disposed on the second insulating layer 120. The second conductive layer 600 may include a first pixel electrode 511, a second pixel electrode 512, a third pixel electrode 513, and a mesh electrode 520. The second conductive layer 600 may include a conductive oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), or aluminum zinc oxide (AZO). The second conductive layer 600 may include a reflective layer comprising silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), or mixtures thereof. In another embodiment, the second conductive layer 600 may further include a layer on / below the reflective layer comprising ITO, IZO, ZnO, AZO, or In2O3.

[0201] The first pixel electrode 511 can be electrically connected to the first sub-pixel circuit PCs1 via the first connecting electrode CM1. The second pixel electrode 512 can be electrically connected to the second sub-pixel circuit PCs2 via the second connecting electrode CM2. The third pixel electrode 513 can be electrically connected to the third sub-pixel circuit PCs3 via the third connecting electrode CM3.

[0202] Each of the first pixel electrode 511 and the second pixel electrode 512 can be disposed across the first sub-region SA1 and the second sub-region SA2. In a plan view, the first pixel electrode 511 and the second pixel electrode 512 can be disposed between the first data line DL1 and the second data line DL2. In a plan view, each of the first data line DL1 and the second data line DL2 can be separated from the first pixel electrode 511 and the second pixel electrode 512. Accordingly, because the first data line DL1, the second data line DL2, the first pixel electrode 511, and the second pixel electrode 512 have sufficient distance, the coupling between the data lines DL1 and DL2 and the pixel electrodes 511 and 512 can be reduced.

[0203] In the plan view, the first pixel electrode 511 and the second pixel electrode 512 may overlap with the first driving voltage line PL1. That is, the first driving voltage line PL1 may be disposed between the first sub-pixel circuit PCs1 and the first pixel electrode 511, and between the second sub-pixel circuit PCs2 and the second pixel electrode 512. Accordingly, the first driving voltage line PL1 can reduce the coupling between the first sub-pixel circuit PCs1 and the first pixel electrode 511, and between the second sub-pixel circuit PCs2 and the second pixel electrode 512.

[0204] The third pixel electrode 513 can be disposed in the third sub-region SA3. In a plan view, the third pixel electrode 513 can be disposed between the auxiliary voltage line VLa and the third data line DL3. In a plan view, the third pixel electrode 513 can overlap with the third data line DL3 and the auxiliary voltage line VLa. Because the third data line DL3 and the auxiliary voltage line VLa are symmetrically arranged about the virtual line RL2 that passes through the third sub-pixel circuit PCs3, the bending of the third pixel electrode 513 due to the lower structure can be symmetrical about the virtual line RL2. Accordingly, the brightness deviation of the third light-emitting diode LED3 due to the user's viewing angle can be reduced.

[0205] Furthermore, in the planar view, the third pixel electrode 513 can overlap with the second driving voltage line PL2. The second driving voltage line PL2 can effectively reduce the coupling between the third sub-pixel circuit PCs3 and the third pixel electrode 513.

[0206] The grid electrode 520 may include a second connection portion 527 connecting a plurality of shielding patterns SHP to a plurality of adjacent shielding patterns SHP. Each of the shielding patterns SHP may include a first portion 521 overlapping a first data line DL1, a second portion 523 overlapping a second data line DL2, and a first connection portion 525 connecting the first portion 521 to the second portion 523. The first portion 521 and the second portion 523 may extend generally in a second direction (e.g., the y-direction), and the first connection portion 525 may extend across a first drive voltage line PL1 in a first direction (e.g., the x-direction).

[0207] In an embodiment, the shielding pattern SHP may define an opening 523op adjacent to the third pixel electrode 513 to prevent contact with the third pixel electrode 513. Due to the opening 523op, the second portion 523 of the shielding pattern SHP may be divided into multiple portions.

[0208] Adjacent shielding patterns SHP in a first direction (e.g., the x-direction) can be connected to each other via a second connection portion 527. The second connection portion 527 can extend across the second drive voltage line PL2 in the first direction (e.g., the x-direction). The first portion 521, the second portion 523, the first connection portion 525, and the second connection portion 527 can be connected to each other integrally to form a grid electrode 520.

[0209] refer to Figure 10The first data line DL1 may have a first width w1 in a first direction (e.g., the x-direction). The first portion 521 of the shielding pattern SHP, overlapping the first data line DL1 in a plan view, may have a second width w2 in the first direction (e.g., the x-direction), and the second width w2 may be greater than the first width w1. In an embodiment, the first portion 521 of the shielding pattern SHP may have sufficient width to cover all bends in the first data line DL1. Similarly, the second data line DL2 may have a first width w1 in the first direction (e.g., the x-direction), and the second portion 523 of the shielding pattern SHP, overlapping the second data line DL2 in a plan view, may have a second width w2 in the first direction (e.g., the x-direction) greater than the first width w1. In a cross-sectional view, the first portion 521 of the shielding pattern SHP may be disposed between the first data line DL1 and the counter electrode 540, and in a cross-sectional view, the second portion 523 may be disposed between the second data line DL2 and the counter electrode 540. Accordingly, the shielding pattern SHP can effectively reduce the coupling between the first data line DL1, the second data line DL2 and the counter electrode 540.

[0210] The first data line DL1 may be disposed adjacent to the third data line DL3, which is electrically connected to the third sub-pixel circuit PCs3 disposed in the preceding column. The first portion 521 of the shielding pattern SHP may have an extension 521a protruding a third width w3 in a fourth direction (e.g., the -x direction). In a plan view, the extension 521a may overlap with the portion of the third data line DL3 adjacent to the first portion 521. In a cross-sectional view, the extension 521a of the shielding pattern SHP may be disposed between the third data line DL3 and the counter electrode 540.

[0211] Because the third data line DL3 is configured to partially overlap with or be very close to the third pixel electrode 513, it is difficult to form a pattern that masks the third data line DL3. Accordingly, the coupling between the third data line DL3 and the counter electrode 540 can be reduced by covering at least a portion of the third data line DL3 with an extension 521a protruding from the first portion 521 of the shielding pattern SHP.

[0212] A dam layer BNL can be disposed on the second conductive layer 600. The dam layer BNL can cover the outer portion of each of the first pixel electrode 511, the second pixel electrode 512, and the third pixel electrode 513. The inner portions of the first pixel electrode 511, the second pixel electrode 512, and the third pixel electrode 513 can overlap with the intermediate layer through a first opening, a second opening OP2, and a third opening OP3 respectively defined in the dam layer BNL in a plan view.

[0213] The dam layer BNL can include organic insulating materials such as polyamide, acrylic resin, benzocyclobutene and hexamethyldisiloxane (HMDSO), and can be formed by spin coating or the like.

[0214] An intermediate layer may be disposed on the embankment layer BNL. The intermediate layer may include a first emitter layer overlapping with the first pixel electrode 511, a second emitter layer 532 overlapping with the second pixel electrode 512, and a third emitter layer 533 overlapping with the third pixel electrode 513 in a planar view. The intermediate layer may include a first functional layer 535 disposed between the pixel electrode and the emitter layer and / or a second functional layer 536 disposed between the emitter layer and the counter electrode 540. Each of the first functional layer 535 and the second functional layer 536 may include a hole transport layer (HTL), a hole injection layer (HIL), an electron transport layer (ETL), and / or an electron injection layer (EIL). Each of the first functional layer 535 and the second functional layer 536 may extend to overlap with multiple pixel electrodes in a planar view.

[0215] In an embodiment, the intermediate layer may include a first stack comprising an emission layer and a functional layer, a second stack comprising an emission layer and a functional layer, and a charge generation layer between the first stack and the second stack. The charge generation layer may include a negative charge generation layer and a positive charge generation layer. The luminous efficiency of a series-connected light-emitting diode (LED) comprising multiple emission layers can be further improved by using the negative and positive charge generation layers.

[0216] The negative charge generation layer can be an N-type charge generation layer. The negative charge generation layer can be configured to supply electrons. The negative charge generation layer can include a host material and a dopant. The host material can include an organic material. The dopant material can include a metallic material. The positive charge generation layer can be a P-type charge generation layer. The positive charge generation layer can be configured to supply holes. The positive charge generation layer can include a host material and a dopant. The host material can include an organic material. The dopant material can include a metallic material.

[0217] Counter electrode 540 may be disposed on an intermediate layer. Counter electrode 540 may comprise a conductive material having a relatively low work function. As an example, counter electrode 540 may comprise a (semi-)transparent layer comprising silver (Ag), magnesium (Mg), aluminum (Al), nickel (Ni), chromium (Cr), lithium (Li), calcium (Ca), or alloys thereof. Alternatively, counter electrode 540 may further comprise a layer on the (semi-)transparent layer comprising ITO, IZO, ZnO, or In2O3. In embodiments, counter electrode 540 may comprise silver (Ag) and magnesium (Mg). Counter electrode 540 may be configured to correspond to a plurality of light-emitting diodes. In other words, counter electrode 540 may extend to overlap with a plurality of pixel electrodes in a planar view.

[0218] The stacked structure of the first pixel electrode 511, the intermediate layer and the counter electrode 540 can correspond to the first light-emitting diode, the stacked structure of the second pixel electrode 512, the intermediate layer and the counter electrode 540 can correspond to the second light-emitting diode LED2, and the stacked structure of the third pixel electrode 513, the intermediate layer and the counter electrode 540 can correspond to the third light-emitting diode LED3.

[0219] refer to Figure 9C and Figure 12 The shielding pattern SHP can be electrically connected to the auxiliary voltage line VLa in the lower part through the contact hole CNT passing through the second insulating layer 120 to receive DC voltage. In an embodiment, the auxiliary voltage line VLa can be a first auxiliary initialization voltage line VILa, a second-1 auxiliary initialization voltage line VAIL1a, a second-2 auxiliary initialization voltage line VAIL2a, or an auxiliary common voltage line VSSLa.

[0220] In an embodiment, when the auxiliary voltage line VLa is the first auxiliary initialization voltage line VILa, the first initialization voltage VINT can be transmitted to the shielding pattern SHP. Adjacent shielding patterns SHP can be connected to each other via the second connection portion 527 to form a grid electrode 520. The display panel 10 may have a dual-connection structure of the first initialization voltage line VIL, the first auxiliary initialization voltage line VILa, and the grid electrode 520. Accordingly, the display panel 10 can prevent or reduce the voltage drop of the first initialization voltage VINT due to the resistance of the first initialization voltage line VIL and the first auxiliary initialization voltage line VILa.

[0221] When the auxiliary voltage line VLa is the auxiliary common voltage line VSSLa, the common voltage ELVSS can be transmitted to the shielding pattern SHP. Due to the dual connection structure of the grid electrode 520 and the auxiliary common voltage line VSSLa, the display panel 10 can prevent or reduce the voltage drop of the common voltage ELVSS in the display area DA in the first direction (e.g., the x direction).

[0222] Figure 13 This is a schematic cross-sectional view of the display panel 10 according to an embodiment. (See reference) Figure 13 The shielding pattern SHP can be electrically connected to the second drive voltage line PL2 through contact holes CNTs passing through the second insulating layer 120. In another embodiment, the shielding pattern SHP can be electrically connected to the first drive voltage line PL1 through contact holes passing through the second insulating layer 120. The drive voltage ELVDD can be transmitted to the shielding pattern SHP.

[0223] In another embodiment, the shielding pattern SHP may not be electrically connected to the voltage lines in the lower part of the display area DA. In the display area DA, the shielding pattern SHP and the voltage lines below it can be electrically separated from each other by the second insulating layer 120. The shielding pattern SHP may extend to the peripheral area PA and be electrically connected to the drive voltage supply line 15, the common voltage supply line 16, or the voltage supply line VLo.

[0224] Figure 14 This is a schematic plan view of the display panel 10 according to an embodiment.

[0225] refer to Figure 14 The grid electrode 520 may include a second connection portion 527 connecting the shielding pattern SHP to an adjacent shielding pattern SHP. Each of the shielding patterns SHP may include a first portion 521 overlapping the first data line DL1, a second portion 523 overlapping the second data line DL2, and a first connection portion 525 connecting the first portion 521 to the second portion 523.

[0226] The shielding pattern SHP may include a curved portion 523b that bypasses the third pixel electrode 513, thereby fully separating the second portion 523 from the third pixel electrode 513. Although in Figure 14 The diagram shows the curved portion 523b completely covering the second data line DL2, but this disclosure is not limited thereto. In another embodiment, the curved portion 523b may be partially offset from the second data line DL2 in a plan view to bypass the third pixel electrode 513. Because the second portion 523 is connected through the curved portion 523b and is not separated, the resistance of the shielding pattern SHP can be reduced.

[0227] Figure 15 This is a schematic plan view of the grid electrode 520 according to an embodiment.

[0228] refer to Figure 15 The display panel 10 may include a first conductive layer 500 and a second conductive layer 600 disposed on the first conductive layer 500. The first conductive layer 500 may include a first data line DL1, a second data line DL2, a third data line DL3, a first driving voltage line PL1, a second driving voltage line PL2, and an auxiliary voltage line VLa extending in a second direction (e.g., the y-direction). The second conductive layer 600 may include a first pixel electrode 511, a second pixel electrode 512, a third pixel electrode 513, and a grid electrode 520.

[0229] The grid electrode 520 may include a second connection portion 527 connecting a shielding pattern SHP to an adjacent shielding pattern SHP. Each of the shielding patterns SHP may include a first portion 521 overlapping a first data line DL1, a second portion 523 overlapping a second data line DL2, and a first connection portion 525 connecting the first portion 521 to the second portion 523. The first portion 521, the second portion 523, the first connection portion 525, and the second connection portion 527 included in a grid electrode 520 may be connected to each other integrally. In an embodiment, the grid electrode 520 may be disposed across the entire surface of the display area DA. That is, the shielding patterns SHP and the second connection portions 527 disposed in the display area DA may all be connected integrally.

[0230] For reference Figure 8 The voltage transmitted by each of the auxiliary voltage lines VLa can have values ​​that repeat in a preset order in a first direction (e.g., the x-direction). As an example, the auxiliary voltage lines VLa can be repeatedly arranged in the first direction (e.g., the x-direction) in the order of first auxiliary initialization voltage line VILa, auxiliary common voltage line VSSLa, second-1 auxiliary initialization voltage line VAIL1a, auxiliary common voltage line VSSLa, second-2 auxiliary initialization voltage line VAIL2a, and auxiliary common voltage line VSSLa. The grid electrode 520 can be electrically connected to the auxiliary voltage lines VLa that transmit the same voltage via contact holes CNT. As an example, such as... Figure 15 As shown, the grid electrode 520 can be electrically connected only to the auxiliary common voltage line VSSLa through the contact hole CNT. The grid electrode 520 and other auxiliary voltage lines VLa, such as the first auxiliary initialization voltage line VILa, the second-1 auxiliary initialization voltage line VAIL1a, and the second-2 auxiliary initialization voltage line VAIL2a, can be electrically separated from each other through the second insulating layer 120.

[0231] In another embodiment, the grid electrode 520 can be electrically connected via the contact hole CNT to one of the following voltage lines: the first auxiliary initialization voltage line VILa, the second-1 auxiliary initialization voltage line VAIL1a, and the second-2 auxiliary initialization voltage line VAIL2a. In another embodiment, the grid electrode 520 can be electrically connected via the contact hole CNT to the first driving voltage line PL1 and / or the second driving voltage line PL2.

[0232] Figure 16 This is a schematic plan view of the display panel 10 according to an embodiment.

[0233] refer to Figure 16The display panel 10 may include a first conductive layer 500 and a second conductive layer 600 disposed on the first conductive layer 500. The first conductive layer 500 may include a first data line DL1, a second data line DL2, a third data line DL3, a first driving voltage line PL1, a second driving voltage line PL2, and an auxiliary voltage line VLa extending in a second direction (e.g., the y-direction). The auxiliary voltage line VLa may include an auxiliary common voltage line VSSLa. The first conductive layer 500 may include a first connecting electrode CM1, a second connecting electrode CM2, and a third connecting electrode CM3. The second conductive layer 600 may include a first pixel electrode 511 electrically connected to the first connecting electrode CM1, a second pixel electrode 512 electrically connected to the second connecting electrode CM2, a third pixel electrode 513 electrically connected to the third connecting electrode CM3, and a shielding pattern SHP.

[0234] Each of the shielding patterns SHP may include a first portion 521 overlapping a first data line DL1, a second portion 523 overlapping a second data line DL2, and a first connection portion 525 connecting the first portion 521 to the second portion 523. The first portion 521 and the second portion 523 may extend generally in a second direction (e.g., the y-direction), and the first connection portion 525 may extend across the first drive voltage line PL1 in a first direction (e.g., the x-direction).

[0235] The first portion 521 of the shielding pattern SHP may have an extension 521a that protrudes a third width w3 in a fourth direction (e.g., the -x direction). In a plan view, the extension 521a may overlap with a portion of the third data line DL3 adjacent to the first portion 521. In an embodiment, the shielding pattern SHP may define an opening 523op adjacent to the third pixel electrode 513 to avoid contact with the third pixel electrode 513. Due to the opening 523op, the second portion 523 of the shielding pattern SHP may be divided into multiple portions. In another embodiment, the shielding pattern SHP may include a curved portion 523b that bypasses the third pixel electrode 513 to avoid contact with the third pixel electrode 513.

[0236] In this embodiment, the shielding pattern SHP can be electrically connected to the auxiliary voltage line VLa in the lower part through the contact hole CNT passing through the second insulating layer 120 to receive a DC voltage. Here, the DC voltage can be one of the voltages supplied to the sub-pixel circuits PCs and the light-emitting diodes LEDs. As an example, the DC voltage can be a first initialization voltage VINT, a second-1 initialization voltage, a second-2 initialization voltage, or a common voltage ELVSS.

[0237] In another embodiment, the shielding pattern SHP can be electrically connected to the first drive voltage line PL1 or the second drive voltage line PL2 in the lower part through contact holes passing through the second insulating layer 120 to receive the drive voltage ELVDD.

[0238] Adjacent shielding patterns SHP can be separated from each other in a first direction (e.g., the x-direction). In an embodiment, the shielding patterns SHP can be separated from each other in a planar view, with the third pixel electrode 513 located between the shielding patterns SHP. The DC voltages delivered to the separated shielding patterns SHP can be different from each other. As an example, a first initialization voltage VINT can be delivered to one of the shielding patterns SHP, and a common voltage ELVSS can be delivered to the other shielding pattern SHP.

[0239] Figure 17 This is a schematic plan view of the shielding patterns SHP that are separated from each other according to an embodiment.

[0240] refer to Figure 17 The display panel 10 may include a first conductive layer 500 and a second conductive layer 600 disposed on the first conductive layer 500. The first conductive layer 500 may include a first data line DL1, a second data line DL2, a third data line DL3, a first driving voltage line PL1, a second driving voltage line PL2, and an auxiliary voltage line VLa extending in a second direction (e.g., the y-direction). The second conductive layer 600 may include a first pixel electrode 511, a second pixel electrode 512, a third pixel electrode 513, and a shielding pattern SHP separated from each other in a first direction (e.g., the x-direction).

[0241] Each of the shielding patterns SHP may include a first portion 521 overlapping the first data line DL1, a second portion 523 overlapping the second data line DL2, and a first connecting portion 525 connecting the first portion 521 to the second portion 523. The first portion 521, the second portion 523, and the first connecting portion 525 may be connected to each other as a single unit. Adjacent shielding patterns SHP may be separated from each other, while the third pixel electrode 513 is located between adjacent shielding patterns SHP.

[0242] For reference Figure 8 The voltage transmitted by each of the auxiliary voltage lines VLa can have values ​​that repeat in a preset order in a first direction (e.g., the x-direction). As an example, the auxiliary voltage lines VLa can be repeatedly set in the first direction (e.g., the x-direction) in the order of first auxiliary initialization voltage line VILa, auxiliary common voltage line VSSLa, second-1 auxiliary initialization voltage line VAIL1a, auxiliary common voltage line VSSLa, second-2 auxiliary initialization voltage line VAIL2a, and auxiliary common voltage line VSSLa.

[0243] Each of the shielding patterns SHP can be electrically connected to an adjacent auxiliary voltage line VLa via a contact hole. For example, the first shielding pattern SHP1 can be electrically connected to the first auxiliary initialization voltage line VILa via a contact hole, the third shielding pattern SHP3 can be electrically connected to the second-1 auxiliary initialization voltage line VAIL1a via a contact hole, and the fifth shielding pattern SHP5 can be electrically connected to the second-2 auxiliary initialization voltage line VAIL2a via a contact hole. Each of the second shielding pattern SHP2, the fourth shielding pattern SHP4, and the sixth shielding pattern SHP6 can be electrically connected to an adjacent auxiliary common voltage line VSSLa via a contact hole. That is, the DC voltage transmitted to each of the multiple shielding patterns SHP can have values ​​in a preset order that repeats in a first direction. The design of the DC voltage transmitted to each of the shielding patterns SHP can be modified differently.

[0244] Figure 18 This is a schematic plan view of the grid electrodes 520 separated from each other according to an embodiment.

[0245] refer to Figure 18 The display panel 10 may include a first conductive layer 500 and a second conductive layer 600 disposed on the first conductive layer 500. The first conductive layer 500 may include a first data line DL1, a second data line DL2, a third data line DL3, a first driving voltage line PL1, a second driving voltage line PL2, and an auxiliary voltage line VLa extending in a second direction (e.g., the y-direction). The second conductive layer 600 may include a first pixel electrode 511, a second pixel electrode 512, a third pixel electrode 513, a first grid electrode 551, a second grid electrode 552, and a third grid electrode 553.

[0246] The first grid electrode 551, the second grid electrode 552, and the third grid electrode 553 may be disposed separately from each other in a first direction (e.g., the x-direction). Each of the first grid electrode 551, the second grid electrode 552, and the third grid electrode 553 may include at least two shielding patterns SHP and a second connection portion 527 connecting the shielding patterns SHP. As an example, the first grid electrode 551 may include a first shielding pattern SHP1, a second shielding pattern SHP2, and a second connection portion 527 connecting the first shielding pattern SHP1 to the second shielding pattern SHP2. The second grid electrode 552 may include a third shielding pattern SHP3, a fourth shielding pattern SHP4, and a second connection portion 527 connecting the third shielding pattern SHP3 to the fourth shielding pattern SHP4. The third grid electrode 553 may include a fifth shielding pattern SHP5, a sixth shielding pattern SHP6, and a second connection portion 527 connecting the fifth shielding pattern SHP5 to the sixth shielding pattern SHP6. Although in Figure 18The diagram shows that each of the first grid electrode 551, the second grid electrode 552, and the third grid electrode 553 includes two shielding patterns SHP, but this disclosure is not limited thereto. In another embodiment, the number of shielding patterns SHP included in the grid electrodes 551, 552, and 553 may differ from each other.

[0247] Each of the shielding patterns SHP may include a first portion 521 overlapping the first data line DL1, a second portion 523 overlapping the second data line DL2, and a first connecting portion 525 connecting the first portion 521 to the second portion 523. The first portion 521, the second portion 523, the first connecting portion 525, and the second connecting portion 527 included in a grid electrode 551, 552, or 553 may be connected to each other as a single unit.

[0248] The voltage transmitted by each of the auxiliary voltage lines VLa can have values ​​that repeat in a preset order in a first direction (e.g., the x-direction). As an example, the auxiliary voltage lines VLa can be repeatedly set in the first direction (e.g., the x-direction) in the order of first auxiliary initialization voltage line VILa, auxiliary common voltage line VSSLa, second-1 auxiliary initialization voltage line VAIL1a, auxiliary common voltage line VSSLa, second-2 auxiliary initialization voltage line VAIL2a, and auxiliary common voltage line VSSLa.

[0249] Each of the first grid electrode 551, the second grid electrode 552, and the third grid electrode 553 can be electrically connected to an adjacent auxiliary voltage line VLa via a contact hole. As an example, such as... Figure 18 As shown, the first grid electrode 551 can be electrically connected to the first auxiliary initialization voltage line VILa through a contact hole, the second grid electrode 552 can be electrically connected to the second-1 auxiliary initialization voltage line VAIL1a, and the third grid electrode 553 can be electrically connected to the second-2 auxiliary initialization voltage line VAIL2a.

[0250] The DC voltages supplied to grid electrodes 551, 552, and 553 may have values ​​that repeat in a predetermined order in a first direction (e.g., the x-direction). As an example, the DC voltages supplied to grid electrodes 551, 552, and 553 may repeat in the order of a first initialization voltage VINT, a second-1 initialization voltage, and a second-2 initialization voltage. The design of the DC voltages supplied to grid electrodes 551, 552, and 553 can be varied. In an embodiment, the first grid electrode 551 may be electrically connected to an auxiliary common voltage line VSSLa instead of a first auxiliary initialization voltage line VILa. Each of grid electrodes 551, 552, and 553 may be electrically connected to a voltage line susceptible to voltage drop.

[0251] According to an embodiment, the display panel 10 can reduce the coupling between data lines DL1, DL2, and DL3 and the counter electrode 540 by including a shielding pattern SHP that transmits DC voltage. Additionally, the display panel 10 can use a dual-connection structure of the shielding pattern SHP and the auxiliary voltage line VLa to reduce the drop in DC voltage.

[0252] According to embodiments, a display panel configured to display high-quality images by reducing coupling between electronic components, and an electronic device including the display panel, can be realized. However, the scope of this disclosure is not limited to this effect.

[0253] It should be understood that the embodiments described herein are to be considered in a descriptive sense only and not for limiting purposes. The description of features or aspects within each embodiment should generally be considered applicable to other similar features or aspects in other embodiments. Although one or more embodiments have been described with reference to the accompanying drawings, those skilled in the art will understand that various changes in form and detail may be made in the embodiments without departing from the spirit and scope defined by the claims.

Claims

1. A display panel, comprising: The substrate includes a display area and a peripheral area outside the display area; A pixel circuit is disposed in the display area and includes a first sub-pixel circuit, a second sub-pixel circuit, and a third sub-pixel circuit that are adjacent to each other in a first direction; A first insulating layer is disposed on the pixel circuit; A first conductive layer is disposed on the first insulating layer and includes a first data line connected to the first sub-pixel circuit, a second data line connected to the second sub-pixel circuit, and a third data line connected to the third sub-pixel circuit. A second insulating layer is disposed on the first conductive layer; as well as A second conductive layer is disposed on the second insulating layer and includes a first pixel electrode connected to the first sub-pixel circuit, a second pixel electrode connected to the second sub-pixel circuit, a third pixel electrode connected to the third sub-pixel circuit, and a shielding pattern. The shielding pattern includes a first portion that overlaps with the first data line in a plan view, a second portion that overlaps with the second data line in the plan view, and a first connecting portion that connects the first portion and the second portion to each other.

2. The display panel according to claim 1, wherein, The first part, the second part, and the first connecting part are connected to each other as one unit.

3. The display panel according to claim 1, wherein, In the plan view, the first pixel electrode and the second pixel electrode are disposed between the first data line and the second data line.

4. The display panel according to claim 1, wherein, The first data line and the second data line are symmetrically arranged about a virtual line that passes between the first sub-pixel circuit and the second sub-pixel circuit and is parallel to a second direction that intersects the first direction.

5. The display panel according to claim 1, wherein, The first portion of the shielding pattern includes an extension that overlaps with the third data line, which is adjacent to the first data line.

6. The display panel according to claim 1, wherein, The first conductive layer further includes an auxiliary voltage line extending in a second direction intersecting the first direction, and The third data line and the auxiliary voltage line are symmetrically arranged about a virtual line that passes through the third sub-pixel circuit and is parallel to the second direction.

7. The display panel according to claim 6, wherein, The shielding pattern is connected to the auxiliary voltage line through contact holes passing through the second insulating layer.

8. The display panel according to claim 6, wherein, The first conductive layer further includes: A first driving voltage line is disposed between the first data line and the second data line; and The second driving voltage line is disposed between the auxiliary voltage line and the third data line.

9. The display panel according to claim 8, wherein, In the plan view, the first pixel electrode and the second pixel electrode overlap with the first driving voltage line, and the third pixel electrode overlaps with the second driving voltage line.

10. The display panel according to claim 8, wherein, The shielding pattern is connected to the first driving voltage line or the second driving voltage line through contact holes passing through the second insulating layer.

11. The display panel according to claim 1, wherein, The shielding pattern is provided as multiple shielding patterns. The plurality of shielding patterns are separated from each other in the first direction, and The voltage transmitted to the first shielding pattern among the plurality of shielding patterns is different from the voltage transmitted to the second shielding pattern among the plurality of shielding patterns.

12. The display panel according to claim 11, wherein, The voltages transmitted to the plurality of shielding patterns have values ​​that repeat in a preset order in the first direction.

13. The display panel according to claim 1, wherein, The shielding pattern is provided as a plurality of shielding patterns, and the second conductive layer further includes a second connecting portion that connects the plurality of shielding patterns to each other.

14. The display panel according to claim 13, wherein, The plurality of shielding patterns and the second connecting portion are connected to each other as a whole.

15. The display panel according to claim 13, wherein, The second conductive layer includes a plurality of grid electrodes spaced apart from each other in the first direction, and Each of the plurality of grid electrodes includes at least two of the plurality of shielding patterns and a second connection portion connecting the at least two shielding patterns.

16. The display panel according to claim 15, wherein, The voltages transmitted to the plurality of grid electrodes have values ​​that repeat in a preset order in the first direction.

17. An electronic device comprising: Display panel according to any one of claims 1 to 16; as well as The lower cover forms the appearance and defines an opening in the front surface of the lower cover that exposes a portion of the display panel.

Images