Ion implantation method for regulating and controlling channel effect and power device manufacturing method

Abstract

The invention provides an ion implantation method for regulating and controlling a channel effect. The ion implantation method comprises the following steps: providing a semiconductor substrate; controllable injection is carried out on the semiconductor substrate, and controllable lattice damage is formed in the semiconductor substrate by controlling the dosage of the controllable injection, so that the channel effect degree of subsequent injection is actively regulated and controlled; performing multi-channel element injection on the semiconductor substrate; and performing adjustment injection on the semiconductor substrate. By controlling the controllable injection dosage, the lattice damage can be controlled, a unified and controlled lattice initial state is provided for the subsequent injection process of all chips, and the required breakdown voltage can be accurately predicted and set; and random fluctuation of the channel effect caused by intrinsic parameter differential between different production devices is eliminated.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor devices, in particular, to an ion implantation method for regulating channeling effect and a power device manufacturing method. BACKGROUND

[0002] In the manufacturing of semiconductor power devices, ion implantation is a key process for forming the doping profile of well regions, source and drain regions, etc. A typical implantation flow includes element implantation (e.g. boron, phosphorus ions) for forming conductive channels, and conditioning implantation (e.g. BF2 ions) for adjusting the resistance and capacitance of specific regions.

[0003] Since the semiconductor substrate is a crystalline material, its atomic arrangement has regular directionality. When the trajectory of the implanted ions aligns with the specific direction of the crystal lattice gap, the ions will travel a much longer distance with significantly lower energy loss, which is known as channeling effect. In the manufacturing of power devices, especially when high-energy ion implantation is performed to form deep junctions, channeling effect is particularly significant. This effect can cause the actual distribution depth and concentration of the dopant atoms to deviate significantly from the design expectation, thereby causing uncontrollable fluctuations in the key electrical parameters, especially the breakdown voltage (BVDSS). More importantly, subtle mechanical and alignment differences between different production equipment can amplify such fluctuations, leading to exceptionally prominent inter-equipment differences in the BVDSS of the final devices, which severely affects product yield and reliability.

[0004] To address the above problems, the main means adopted by the prior art is to perform complete pre-amorphization. This technique typically uses heavy ions or high-dose implantation of germanium (Ge), silicon (Si), etc. before element implantation to completely disrupt the crystal structure of the substrate surface and convert it into an amorphous state. This amorphous layer acts as a buffer zone, effectively eliminating channeling effect and ensuring that subsequent implanted ions stop in a disordered lattice environment, thereby obtaining a more controllable and repeatable doping profile. However, this complete pre-amorphization completely eliminates channeling effect, causing the BVDSS of the final device to be locked at a fixed level determined by the degree of amorphization. If fine-tuning of the BVDSS is desired, it will become extremely difficult, and typically requires redesigning the longitudinal structure (e.g. well depth, junction depth) or lateral size of the entire device, which greatly limits the ability to optimize product performance for different application scenarios. SUMMARY

[0005] In view of the above problems in the prior art for eliminating channeling effect, the present application provides an ion implantation method for regulating channeling effect and a device manufacturing method, which actively and accurately regulates channeling effect to achieve an ion implantation method for quickly setting the breakdown voltage of power devices and optimizing performance.

[0006] To achieve the above object and other related objects, the present application provides a method for regulating channeling effect of ion implantation, which comprises: providing a semiconductor substrate; performing a controllable implantation on the semiconductor substrate, and forming controllable lattice damage in the semiconductor substrate by controlling the dose of the controllable implantation to actively regulate the degree of channeling effect of subsequent implantation; performing multiple element implantations on the semiconductor substrate; performing an adjustment implantation on the semiconductor substrate.

[0007] Optionally, the controllable implantation on the semiconductor substrate comprises that the controllable implantation is the same as the element of the adjustment implantation.

[0008] Optionally, the controllable implantation on the semiconductor substrate comprises that the dose of the controllable implantation is a part of the total dose of the adjustment implantation which is performed in advance.

[0009] Optionally, the dose of the controllable implantation accounts for 2% to 15% of the total dose of the adjustment implantation.

[0010] Optionally, the controllable implantation on the semiconductor substrate comprises that the controllable implantation is a neutral element implantation.

[0011] Optionally, the neutral element is selected from group IV or group 0 inert element.

[0012] Optionally, the implantation dose of the neutral element ranges from 5e13 atoms / cm 2 to 2e14 atoms / cm 2 .

[0013] The present application also provides a method for manufacturing a power device, which comprises: providing a semiconductor substrate; selecting a suitable controllable implantation dose according to the relationship between the breakdown voltage value of the power device and the dose of the controllable implantation, and combining the target breakdown voltage value; forming a doped region in the substrate by using the method for regulating channeling effect of ion implantation as described in any one of the above descriptions; forming controllable lattice damage in the semiconductor substrate by controlling the dose of the controllable implantation in a specific dose window of the controllable lattice damage; performing multiple element implantations on the semiconductor substrate; performing an adjustment implantation on the semiconductor substrate Optionally, the relationship between the breakdown voltage value of the power device and the dose of the controllable implantation comprises: Linear region: the breakdown voltage value of the power device is negatively correlated with the controllable injected dose in a linear relationship; Saturation stable region: the breakdown voltage value of the power device does not change significantly with the increase of the controllable injected dose.

[0014] As described above, the ion implantation method for regulating channel effect and the manufacturing method of power device provided by the present application have at least the following beneficial technical effects: the ion implantation method for regulating channel effect provided by the present application fundamentally converts the effect of channel effect from a harmful phenomenon that must be completely eliminated into a controllable lever that can be used to accurately regulate the performance of a device; by controlling the controllable injected dose, the lattice damage can be controlled, that is, without re-designing the device architecture and without changing the entire set of ion implantation energy and dose, a uniform and controlled initial state of the lattice is provided for the subsequent implantation process of all chips, the required breakdown voltage can be accurately predicted and set, and the randomness of channel effect is fundamentally inhibited, so that the random fluctuation of channel effect caused by the inherent parameter difference between different production equipment is effectively eliminated, the difference between equipment for BVDSS is significantly reduced, and the product yield, reliability and mass production stability are greatly improved. BRIEF DESCRIPTION OF DRAWINGS

[0015] Figure 1 A flow chart of the ion implantation method for regulating channel effect provided by the embodiment one of the present application is shown.

[0016] Figure 2 A schematic diagram of the relationship between the controllable injected dose and the BVDSS of the MOSFET device provided by the embodiment one is shown.

[0017] Figure 3 A comparative schematic diagram of the breakdown voltage on different ion implantation equipment is shown.

[0018] Figure 4 A flow chart of the manufacturing method of power device of the embodiment two system is shown. DETAILED DESCRIPTION

[0019] The embodiments of the present application are described below through specific and concrete examples, and those skilled in the art can easily understand other advantages and effects of the present application from the disclosure of the present specification. The present application can also be implemented or applied through other different specific embodiments, and each detail in the present specification can be modified or changed based on different viewpoints and applications without departing from the spirit of the present application.

[0020] It should be noted that the diagrams provided in the embodiments only schematically illustrate the basic concepts of the present application, and although only the components related to the present application are shown in the diagrams, the diagrams are not drawn according to the number, shape and size of the components in actual implementation, and the shape, number, positional relationship and proportion of each component in actual implementation can be changed at will under the premise of realizing the technical solutions of the present application, and the component layout form can also be more complex.

[0021] Embodiment one The present embodiment provides an ion implantation method for regulating channel effect, as shown in the flowchart of the ion implantation method for regulating channel effect provided by the present embodiment; the ion implantation method for regulating channel effect specifically includes the following steps: Figure 1 S11: providing a semiconductor substrate; S12: performing a controllable implantation on the semiconductor substrate, forming controllable lattice damage in the semiconductor substrate by controlling the dose of the controllable implantation; S13: performing an element implantation on the semiconductor substrate; S14: performing an adjustment implantation on the semiconductor substrate. S11: providing a semiconductor substrate; S12: performing a controllable implantation on the semiconductor substrate, forming controllable lattice damage in the semiconductor substrate by controlling the dose of the controllable implantation; S13: performing an element implantation on the semiconductor substrate; S14: performing an adjustment implantation on the semiconductor substrate.

[0022] Specifically, step S11: providing a semiconductor substrate. Generally, the semiconductor substrate is a silicon, silicon carbide, gallium nitride, gallium arsenide, etc. substrate, which is used to manufacture power MOSFET, IGBT, etc. power devices. The ion implantation method of the present application is particularly suitable for manufacturing power devices with precise requirements for breakdown voltage (BVDSS), including power MOSFET, insulated gate bipolar transistor (IGBT), and super junction power device.

[0023] Specifically, step S12: performing a controllable implantation on the semiconductor substrate, forming controllable lattice damage in the semiconductor substrate by controlling the dose of the controllable implantation.

[0024] Specifically, step S13: performing a plurality of element implantations on the semiconductor substrate; step S14: performing an adjustment implantation on the semiconductor substrate.

[0025] Specifically, the controllable implantation includes two technical paths, the first technical path is to advance part of the total dose of the subsequent adjustment implantation to the present step, and the controllable implantation and the adjustment implantation are the same element; the second technical path is to implant a neutral element in the present step, and control the implantation dose of the neutral element.

[0026] Generally, the purpose of element implantation is to form a conductive channel, and the P-type doping concentration and the N-type drift region doping concentration are precisely designed so that the number of carriers (holes) provided by the P region and the number of carriers (electrons) provided by the N region are substantially equal, and under the action of an electric field, the two regions are completely depleted to form a charge-neutral high-resistance depletion region, achieving the effect of withstanding higher breakdown voltage. Generally, the element implantation process includes multiple B element implantations, which are used for resistance-capacitance adjustment of the conductive channel, and the implantation depth is from deep to shallow. Among the multiple element implantations, the first element implantation is a high-energy B element implantation, which is more likely to cause channeling effect.

[0027] Generally, the main purpose of adjusting implantation is to optimize the contact resistance and adjust the doping concentration of a specific region: before preparing a metal electrode on the semiconductor, the contact region is heavily doped to form an ohmic contact, which can significantly reduce the contact resistance between the metal and the semiconductor, thereby affecting the resistance and capacitance of the region, and ultimately optimizing the switching speed, on-resistance and other performances of the device. Generally, the adjusting implantation element depends on the type of semiconductor substrate. For a P-type substrate, the adjusting implantation elements include B, BF2 + , etc.; for an N-type substrate, the adjusting implantation elements include P, As, etc.

[0028] Further, the proportion of the controllable implantation dose to the total dose is 2%、 The strategy for the first technical route is to borrow part of the dose of the above-mentioned adjusting implantation in advance, and control the dose of the controllable implantation borrowed in advance. Generally, the proportion of the controllable implantation dose to the total dose is between 2% and 15%, that is, the ratio of the controllable implantation dose to the adjusting implantation dose is between 1:49 and 3:17. 4%, 6%, 8%, 10%, 15%.

[0029] Specifically, in this example, a MOSFET device is prepared as an example, a semiconductor substrate is provided, and a gate structure is formed on the semiconductor substrate; a controllable implantation is performed on the semiconductor substrate, and the controllable implantation element is BF2 + ; then a plurality of element implantations are performed, and the element implantation element is a B element; finally, adjusting implantation is performed, and the adjusting implantation element is BF2 + . Specifically, it is assumed that the total dose of BF2 + implantation is A, a dose of a is divided from the total dose A and borrowed to controllable implantation; then element implantation is performed; finally, the remaining A-a dose of BF2 + implantation is implanted into the semiconductor substrate.

[0030] As Figure 2 shown, a schematic diagram showing the relationship between the controllable implantation dose provided by this embodiment and the BVDSS of the MOSFET device is shown; as Figure 2As shown, for comparison, two independent wafers are provided in this embodiment, and different doses of controllable implantation are performed in different regions by means of splitting experiments, and the relationship between BVDSS of MOSFET devices under different doses of controllable implantation is observed. As shown in Table 1, the controllable implantation dose table provided in this embodiment is shown as follows:

[0031] Specifically, the total dose of BF2 + implantation is 1E15 atoms / cm 2 ; three B element implantations are performed on the semiconductor substrate, and the implantation dose is 2E12 atoms / cm 2 ; specifically, a group of control groups is also set, that is, the controllable implantation dose of BF2 + is 0%; six groups of different doses of controllable implantation are set, and the controllable implantation doses are 2E13 atoms / cm 2 , 4E13 atoms / cm 2 , 6E13 atoms / cm 2 , 8E13 atoms / cm 2 , 10E13 atoms / cm 2 , and 15E13 atoms / cm 2 , respectively. Correspondingly, the adjustment implantation doses are 9.8E14 atoms / cm 2 , 9.6E14 atoms / cm 2 , 9.4E14 atoms / cm 2 , 9.2E14 atoms / cm 2 , 8E14 atoms / cm 2 , and 8.5E14 atoms / cm 2 , respectively.

[0032] Specifically, as Figure 2As shown, the ratio of the controllable implant dose a to the total implant dose A includes: 4%, 6%, 8%, 10%, 15%. As can be clearly seen from the figure: for the first wafer: the average BVDSS of the control group is 46.7; the average BVDSS of the ratio of the controllable implant dose a to the total implant dose A being 4% is 47.99; the average BVDSS of the ratio of the controllable implant dose a to the total implant dose A being 6% is 47.74; the average BVDSS of the ratio of the controllable implant dose a to the total implant dose A being 8% is 47.74; the average BVDSS of the ratio of the controllable implant dose a to the total implant dose A being 10% is 46.63; the average BVDSS of the ratio of the controllable implant dose a to the total implant dose A being 10% is 46.81; the average BVDSS of the ratio of the controllable implant dose a to the total implant dose A being 15% is 44.66; for the second wafer: the average BVDSS of the control group is 46.15; the average BVDSS of the ratio of the controllable implant dose a to the total implant dose A being 4% is 47.52; the average BVDSS of the ratio of the controllable implant dose a to the total implant dose A being 6% is 47.36; the average BVDSS of the ratio of the controllable implant dose a to the total implant dose A being 8% is 46.41; the average BVDSS of the ratio of the controllable implant dose a to the total implant dose A being 10% is 46.63; the average BVDSS of the ratio of the controllable implant dose a to the total implant dose A being 10% is 45.77; the average BVDSS of the ratio of the controllable implant dose a to the total implant dose A being 15% is 44.63.

[0033] Observation Figure 2 As shown by the results and data, it can be seen that as the ratio of the controllable implant dose a to the total implant dose A increases, the average BVDSS presents a clear downward trend; specifically, when the controllable implant dose ratio is in the range of 4% to 10%, the BVDSS changes most gently and controllably. Specifically, within this range, the adjustment of BVDSS has extremely high linearity and predictability (such as the first wafer, the BVDSS is stable above 47 V when the controllable implant dose ratio is 4% to 8%, and then starts to gently decrease). Therefore, as a preferred embodiment, the ratio of the controllable implant dose to the total dose is further limited to between 4% and 10%. This range can achieve flexible regulation while ensuring the stability of device performance and process. Specifically, when the controllable implant dose is 1.5E14 atoms / cm 2 , the breakdown voltage remains at a constant level.

[0034] Therefore, there is a two-stage correspondence between the breakdown voltage of the power device and the dose of the controlled injection (i.e., the controlled injection). In the first stage, the linear region: when the proportion of the controlled injection dose a in the total dose A of the regulated injection is in the range of about 4% to 10%, the breakdown voltage and the controlled injection dose present a highly linear and predictable negative correlation. In this range, with the increase of the proportion of the controlled injection dose, the BVDSS value decreases gently and linearly; in the second stage, the saturation and stability region: when the controlled injection dose exceeds a certain threshold, the downward trend of BVDSS stops. BVDSS no longer changes significantly with the increase of the injection dose, but enters a stable plateau period and maintains at a constant level. This phenomenon shows that at this dose, an amorphous layer has been formed on the substrate surface to completely suppress the channel effect. After that, BVDSS will be determined by the completely amorphous state.

[0035] As shown in Figure 3 , a comparative schematic diagram of the breakdown voltage on different ion implantation equipment is shown; specifically, the BVDSS values of the devices in different equipment at the same controlled injection dose. The present application also takes two wafers as an example to illustrate the breakdown voltage (BVDSS) of the devices on different ion implantation equipment. The STD Sequence is a device made by the conventional technical solution, and the Sequence change is a device improved by the technical solution provided by the present application. For example, different low-beam ion implanters, medium-beam ion implanters, and high-beam ion implanters are used to make devices with the same doping concentration. For example, the present application tests the BVDSS of the devices improved by the present application and the conventional devices in BSL equipment and Qual equipment, respectively. Specifically, based on the linear relationship between BVDSS and dose ratio, the present embodiment selects 8% as the fixed process condition, which is in the proportion value, to test the BVDSS distribution of the prepared devices.

[0036] As can be seen from Figure 3 , the difference between the BVDSS of the two devices of the present application measured in the BSL equipment is 0.39 and 0.36, respectively; the difference between the BVDSS measured in the Qual equipment is 0.30 and 0.35, respectively; and the difference between the BVDSS of the two devices of the conventional technical means measured in the BSL equipment is 0.55 and 0.59, respectively; the difference between the BVDSS measured in the Qual equipment is 0.44 and 0.52, respectively.

[0037] As can be seen, on the same equipment, the BVDSS difference between two wafers under the present invention is significantly smaller than that under the conventional method. The present invention provides a unified and standardized process starting point for different production lines (machines), thereby significantly reducing the differences between equipment. The fundamental reason why the present invention can achieve the above effect is that, through the lattice damage control implantation step, a unified and controlled initial lattice state is provided for the subsequent implantation process of all chips. This step standardizes the process starting point, fundamentally eliminating the random fluctuations of the channel effect caused by the inherent slight differences in parameters of different equipment, thereby transforming the originally uncontrollable equipment difference factor into a predictable and repeatable process result.

[0038] For the second technical approach: a controlled implantation is performed on the semiconductor substrate, specifically a neutral element implantation. Generally, the intermediate atoms are selected from Group IV elements or Group 0 inert elements, including Group IV germanium (Ge) and silicon (Si), or Group 0 argon (Ar). These elements are electrically inert in the silicon substrate and do not act as donor or acceptor impurities, thus not interfering with the original electrical doping design of the device. By controlling the implantation dose, the degree of lattice damage can be precisely controlled. Typically, the implantation dose of the neutral element is in the range of 5E13 atoms / cm². 2 Up to 2E14 atoms / cm 2 Therefore, since the neutral element does not participate in the electrical properties, it avoids any potential impact on the doping profile, and it is easy to expect to achieve the same BVDSS linear control and uniformity improvement effect as the first path.

[0039] Example 2 This embodiment provides a method for manufacturing a power device, such as... Figure 4 The diagram shows a flowchart of a method for fabricating a power device according to the system of this embodiment; including: S21: providing a semiconductor substrate; S22: selecting a suitable controllable implantation dose based on the linear relationship between the breakdown voltage of the power device and the controllable implantation dose, combined with the target breakdown voltage; S23: forming a doped region in the substrate using an ion implantation method for controlling the channel effect as described in any of the embodiments; S24: forming controllable lattice damage in the semiconductor substrate by controlling the controllable implantation dose, within a specific dose window of the controllable lattice damage; S25: performing multi-channel element implantation on the semiconductor substrate; S26: performing a single-channel controlled implantation on the semiconductor substrate.

[0040] Specifically, S21: Provide a semiconductor substrate. A silicon substrate is provided, and front-end processes have been completed, such as forming a gate oxide layer and a polysilicon gate structure on the substrate.

[0041] S22: According to the linear relationship between the breakdown voltage value of the power device and the controllable injection dose, the appropriate controllable injection dose is selected in combination with the target breakdown voltage value; specifically, based on the linear relationship between the breakdown voltage and the lattice damage control injection dose established in advance through experiments, the required controllable injection dose is determined according to the target BVDSS value. Alternatively, depending on the different production of power devices and different doping elements, the relationship between the breakdown voltage and the lattice damage control injection dose needs to be established in advance through experiments.

[0042] Specifically: when the target BVDSS value is in the linear region, the breakdown voltage value of the power device is negatively correlated with the controllable injection dose in a linear relationship, so the required dose is accurately calculated according to the linear relationship. This embodiment takes the data provided in Embodiment One as an example: if the target BVDSS is 47.5V, according to the linear relationship curve of Figure 2 , it can be determined that the BF2 + ion with a dose of 6E13 atoms / cm 2 should be used.

[0043] When the target BVDSS value is in the saturation and stability region, the breakdown voltage value of the power device does not change significantly with the increase of the controllable injection dose, and the minimum effective dose corresponding to the saturation region is selected. When the controllable injection dose reaches the starting point of the saturation region, the dose ratio exceeds 10% or the dose exceeds 1.5E14 atoms / cm 2 , as described in Embodiment One, which means that an amorphous layer has been formed on the surface of the silicon substrate to completely suppress the channel effect.

[0044] S23: Perform ion implantation in the semiconductor substrate by controlling the dose of controllable injection to form controllable lattice damage.

[0045] The ion implantation method described in Embodiment One is adopted to form the required doping region (such as P-body, contact injection region, etc.) in the substrate. Specifically, taking the first path described in Embodiment One as an example: perform lattice damage control injection: use the same element as the subsequent adjustment injection, use BF2 + ions, and implant the dose determined in step S22 (such as 6E13 atoms / cm 2 ). This step is not for electrical doping, and its core function is to create a controlled and uniform lattice damage layer on the substrate surface using ion bombardment. Provide a unified initial lattice state for all subsequent ion implantation, thereby actively regulating and locking the degree of channel effect.

[0046] S24: Perform multi-element injection on the semiconductor substrate; S25: Perform one adjustment injection on the semiconductor substrate.

[0047] Performing multi-pass element implantation: performing multi-pass boron (B + ) ion implantation with different energies in the original process sequence. Performing conditioning implantation: performing the remaining dose of BF2 + ion implantation (e.g. total dose 1E15 atoms / cm 2 , then step S23 in this embodiment implants 9.4E14 atoms / cm 2 ).

[0048] Performing subsequent device processes. After the ion implantation is completed, standard semiconductor manufacturing subsequent processes are performed, including but not limited to: rapid thermal annealing to activate the dopant atoms, forming side walls on both sides of the gate, performing source-drain deep doping, depositing interlayer dielectric layers, forming contact holes, performing metallization to make electrodes, etc., finally completing the entire power MOSFET device manufacturing.

[0049] A variety of power devices can be manufactured by this method, including but not limited to: power MOSFET, insulated gate bipolar transistor (IGBT), super-junction (Super-Junction) power device, power diode, radio frequency power device. The power devices manufactured by this method have a breakdown voltage that can accurately hit the design target, and show high consistency between different production batches and equipment. This verifies that using lattice damage control implantation as a core process lever, combined with its quantitative relationship with breakdown voltage for manufacturing, is an efficient and reliable power device manufacturing scheme.

[0050] The above embodiments only exemplarily illustrate the principles and effects of the present application, and are not intended to limit the present application. Any person skilled in the art can modify or change the above embodiments without departing from the spirit and scope of the present application. Therefore, all equivalent modifications or changes made by those skilled in the art without departing from the spirit and technical idea disclosed by the present application should be covered by the claims of the present application.

Claims

1. An ion implantation method for controlling the channeling effect, characterized in that, include: Provide a semiconductor substrate; A controllable implantation is performed on the semiconductor substrate. By controlling the dosage of the controllable implantation, controllable lattice damage is formed in the semiconductor substrate to actively regulate the degree of channel effect in subsequent implantations. Multi-channel element implantation is performed on the semiconductor substrate; A conditioning implantation is performed on the semiconductor substrate.

2. The ion implantation method for controlling the channeling effect according to claim 1, characterized in that, A controlled implantation of the semiconductor substrate includes the following: the controlled implantation is the same as the adjustable implantation element.

3. The ion implantation method for controlling the channeling effect according to claim 2, characterized in that, A controlled implantation of the semiconductor substrate includes: the controlled implantation dose being a portion of the total implantation dose that is pre-executed.

4. The ion implantation method for controlling the channeling effect according to claim 3, characterized in that, The controlled injection dose accounts for 2% to 15% of the total regulated injection dose.

5. The ion implantation method for controlling the channeling effect according to claim 1, characterized in that, A controlled implantation process on the semiconductor substrate includes: the controlled implantation is neutral element implantation.

6. The ion implantation method for controlling the channeling effect according to claim 5, characterized in that, The neutral element is selected from group IV elements or group 0 elements.

7. The ion implantation method for controlling the channeling effect according to claim 4, characterized in that, The injection dose of the neutral element is in the range of 5e13 atoms / cm². 2 ~2e14 atoms / cm 2 .

8. A method for manufacturing a power device, characterized in that, include: Provide a semiconductor substrate; Based on the relationship between the breakdown voltage of the power device and the controllable injection dose, a suitable controllable injection dose is selected in conjunction with the target breakdown voltage. The ion implantation method for controlling the channel effect as described in any one of claims 1 to 7 is used to perform ion implantation in a semiconductor substrate by controlling the dose of controllable implantation, thereby forming controllable lattice damage. Multi-channel element implantation is performed on the semiconductor substrate; A conditioning implantation is performed on the semiconductor substrate.

9. The method for manufacturing a power device according to claim 8, characterized in that, The relationship between the breakdown voltage of the power device and the controlled injected dose includes: Linear region: The breakdown voltage of the power device is negatively correlated with the controlled injected dose in a linear relationship; Saturation stability region; the breakdown voltage of the power device does not change significantly with the increase of the controllable injection dose.

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