Package and electronic device

Abstract

The invention relates to the technical field of semiconductors, and discloses a packaging body and electronic equipment, the packaging body comprises a bearing part, a first chip, a second chip, a first clamping piece and an interconnection structure, and the bearing part comprises a base island and a plurality of pins; the first chip is mounted on the base island and is provided with a first surface and a second surface, and the first chip comprises a first electrode formed on the first surface and a second electrode formed on the second surface; the second chip is stacked on one side, away from the bearing part, of the first chip and is provided with a third surface and a fourth surface, and the second chip comprises a third electrode on the third surface and a fourth electrode on the fourth surface; the second electrode and the third electrode are electrically connected with the first pin in the plurality of pins at the same time through the first clamping piece; and the interconnection structure is electrically connected with the first electrode through a first conductive channel arranged on the first chip and is electrically connected with the fourth electrode through a second conductive channel arranged on the second chip, so that electric connection between the first electrode and the fourth electrode is realized.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor technology, and in particular to a package and an electronic device. BACKGROUND

[0002] Insulated Gate Bipolar Transistor (IGBT) plays an important role in modern power systems, which has the advantages of low conduction loss, can withstand high voltage, can work stably for a long time in high temperature environment, and can quickly respond to signal changes in the circuit, thereby realizing efficient power conversion, reducing energy loss, and improving the efficiency of the entire power system. In order to ensure the stable operation of IGBT single tube and prolong its service life, it is usually necessary to be used in parallel with a diode such as a fast recovery diode FRD or a Schottky diode SBD. The main purpose of the diode is to protect the IGBT from reverse voltage. When the IGBT is turned off, due to the inductance in the circuit, a reverse voltage will be generated, and if there is no diode, this reverse voltage can cause the IGBT to be damaged. The anti-parallel diode can quickly conduct to release the reverse voltage through the diode, avoiding damage to the IGBT due to excessive voltage.

[0003] The present application relates to the technical field of semiconductor technology, and in particular to a package and an electronic device. SUMMARY

[0004] The present application provides a package and an electronic device, which can reduce the size of the package and improve the integration of the package.

[0005] In a first aspect, an embodiment of the present application provides a package, which comprises: a bearing portion comprising a base island and a plurality of pins arranged at the periphery of the base island; a first chip mounted on the base island, the first chip comprising a first surface facing the base island and a second surface facing away from the base island, the first chip comprising a first electrode arranged on the first surface and a second electrode arranged on the second surface; a second chip stacked on the second surface of the first chip, the second chip comprising a third surface facing the first chip and a fourth surface facing away from the first chip, the second chip comprising a third electrode arranged on the third surface and a fourth electrode arranged on the fourth surface; a first clamping piece clamped between the first chip and the second chip, the first clamping piece being configured to connect the second electrode and the third electrode to a first pin of the plurality of pins; an interconnection structure disposed between the first chip and the second chip, the interconnection structure being electrically connected to the first electrode through a first conductive channel penetrating the second surface of the first chip and communicating with the first electrode; the interconnection structure being electrically connected to the fourth electrode through a second conductive channel penetrating the third surface of the second chip and communicating with the fourth electrode.

[0006] In some embodiments, the first electrode of the first chip is electrically connected to the base island, and the first pin is electrically insulated from the base island. The plurality of pins further includes a second pin electrically connected to the base island and a third pin disposed to be electrically insulated from the base island. The first chip further includes a fifth electrode disposed on the second surface, the fifth electrode being electrically connected to the third pin.

[0007] In some embodiments, the fifth electrode and the third pin are electrically connected through a second interconnection structure: The second interconnection structure includes any one of the following: a second clamping piece at least partially located on the second surface of the first chip, the second clamping piece being connected between the fifth electrode and the third pin; or a wire at least partially located on the second surface of the first chip, the wire being connected between the fifth electrode and the third pin by bonding.

[0008] In some embodiments, the first conductive channel includes a blind hole-shaped first recess recessed downward from the second surface of the first chip, the bottom of the first recess being exposed or connected to the first electrode. The interconnection structure is at least partially embedded in the first recess to be electrically connected to the first electrode.

[0009] In some embodiments, a first dielectric layer and a first metal layer are sequentially stacked on the wall of the first recess.

[0010] In some embodiments, the first conductive channel includes a plurality of vias formed on the second surface of the first chip and communicating with the first electrode, each of the vias being filled with conductive material, and the interconnection structure being electrically connected to the first electrode through the conductive material.

[0011] In some embodiments, the second conductive channel comprises a blind hole-shaped second groove recessed downward from a fourth surface of the second chip, a bottom of the second groove being exposed or connected to the fourth electrode. The interconnection structure is at least partially embedded in the second groove to be electrically connected with the fourth electrode.

[0012] In some embodiments, the first clamping piece is provided with a barbed fastening part which is buckled on the first pin.

[0013] In some embodiments, the first clamping piece is provided with a plurality of through holes, including at least one first type of through hole and at least one second type of through hole, the first type of through hole corresponding to the first pin in position, and the second type of through hole corresponding to the first chip in position.

[0014] In a second aspect, the embodiments of the present application provide an electronic device comprising the package body of any one of the first aspect.

[0015] The embodiments of the present application have the following beneficial effects: The present application opens a first conductive channel on the first chip and a second conductive channel on the second chip, so that the interconnection structure located between the first chip and the second chip can be electrically connected with the first electrode through the first conductive channel and electrically connected with the fourth electrode through the second conductive channel, that is, the first electrode and the fourth electrode are electrically connected through the interconnection structure, so that the first chip and the second chip can be connected in parallel in a stacked manner, the size of the base island can be reduced, the package body can select more package outlines, the integration degree can be improved, and the dual requirements of miniaturization and high performance can be realized. BRIEF DESCRIPTION OF DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiment description. Obviously, the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings can also be obtained without creative labor based on these drawings, wherein: Figure 1 Fig. 1 shows a first structural schematic diagram of a package body of an embodiment of the present application; Figure 2 Fig. 2 shows a partial structural schematic diagram of a package body of an embodiment of the present application; Figure 3 Fig. 3 shows a structural schematic diagram of a bearing part of an embodiment of the present application; Figure 4 Fig. 4 shows a structural schematic diagram of a bearing part and a first chip of an embodiment of the present application; Figure 5A structure schematic diagram of the bearing part, the first chip, the first clamping piece and the second clamping piece of the embodiment of the present application is shown. Figure 6 A first structure schematic diagram of the first chip of the embodiment of the present application is shown. Figure 7 A first cross-sectional structure schematic diagram of the first chip of the embodiment of the present application is shown. Figure 8 A second structure schematic diagram of the package of the embodiment of the present application is shown. Figure 9 A second structure schematic diagram of the first chip of the embodiment of the present application is shown. Figure 10 A second cross-sectional structure schematic diagram of the first chip of the embodiment of the present application is shown. Figure 11 A structure schematic diagram of the second chip of the embodiment of the present application is shown. Figure 12 A structure schematic diagram of the second chip and the first interconnection structure of the embodiment of the present application is shown. Figure 13 A structure schematic diagram of the first clamping piece and the second clamping piece of the embodiment of the present application is shown. Figure 14 A third structure schematic diagram of the package of the embodiment of the present application is shown. Figure 15 A top view structure schematic diagram of the package of the embodiment of the present application is shown.

[0017] Main element mark explanation: 100: package; 102: second surface; 103: third surface; 104: fourth surface; 110: bearing part; 111: base island; 112: pin; 112a: first pin; 112b: second pin; 112c: third pin; 120: first chip; 1201: first recess; 1202: via hole; 1203: second recess; 1204: through hole; 121: first electrode; 122: second electrode; 123: fifth electrode; 130: second chip; 131: third electrode; 132: fourth electrode; 140: first clamping piece; 141: first barb fastening part; 150: second clamping piece; 151: second barb fastening part; 160: interconnection structure; 170: lead wire; 180: plastic package. DETAILED DESCRIPTION The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all the embodiments.

[0018] The components of the application embodiments described and illustrated herein can be arranged and designed in a wide variety of different configurations. Therefore, the following detailed description of the application, read with reference to the accompanying drawings, is not intended to limit the scope of the application as claimed, but is merely representative of selected embodiments of the application. The resulting connection of all embodiments of the application encompasses all alternatives, modifications and equivalents.

[0019] Hereinafter, the terms "include", "have", and their conjugates, used in the various embodiments of the present application, merely indicate the presence of the features, numbers, steps, operations, elements, components, or combinations thereof, and do not exclude the possibility of the presence or addition of one or more other features, numbers, steps, operations, elements, components, or combinations thereof. Also, the terms "first", "second", "third", and the like, are used only to distinguish the description, and cannot be understood as designating or implying a relative importance.

[0020] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which various embodiments of the present application belong. The terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is identical to the contextual meaning in the relevant field of art and should not be interpreted in an idealized or overly formal sense unless clearly defined in various embodiments of the present application.

[0021] Some embodiments of the present application will be described below in detail with reference to the accompanying drawings. The following embodiments and features of the embodiments can be combined with each other without conflict.

[0022] Referring to Figure 1 and Figure 2 In an embodiment of the present application, the package 100 includes a carrier 110, a first chip 120, a second chip 130, a first clip 140, a second clip 150, and an interconnection structure 160. Meanwhile, referring to Figures 3 to 5 In the manufacturing process, the first chip 120 is first mounted on the carrier 110, then the first clip 140 and the second clip 150 are mounted, and finally the second chip 130 is mounted.

[0023] The carrier 110 plays a role of bearing in the package 100, and includes a base island 111 and a plurality of pins 112 disposed outside the base island 111. The number, position, and layout of the pins 112 can be flexibly designed according to specific application requirements.

[0024] As Figure 6As shown, the first chip 120 is mounted on the base island 111 and has a first surface facing the support portion 110 and a second surface 102 away from the support portion 110. The first chip 120 includes a first electrode 121 formed on the first surface and a second electrode 122 formed on the second surface 102, that is, the first electrode 121 and the second electrode 122 are formed on two surfaces of the first chip 120 that are opposite to each other.

[0025] The second chip 130 is stacked on the side of the first chip 120 away from the support portion 110, such as Figure 11 As shown, the second chip 130 has a third surface 103 facing the carrier portion 110 and a fourth surface 104 away from the carrier portion 110. The second chip 130 includes a third electrode 131 formed on the third surface 103 and a fourth electrode 132 formed on the fourth surface 104. That is, the third electrode 131 and the fourth electrode 132 are formed on two surfaces of the second chip 130 that are opposite to each other.

[0026] The first clip 140 is disposed between the first chip 120 and the second chip 130, electrically connecting the second electrode 122 and the third electrode 131 to the first pin 112a of the plurality of pins 112. Specifically, the first chip 120, the first clip 140, and the second chip 130 are arranged sequentially in the direction away from the support portion 110. At the same time, the second electrode 122 and the third electrode 131 are both electrically connected to the first clip 140, and the first clip 140 is electrically connected to the first pin 112a, thereby electrically connecting the second electrode 122 and the third electrode 131 to the first pin 112a.

[0027] An interconnection structure 160 is disposed between the first chip 120 and the second chip 130, and is electrically connected to the first electrode 121 via a first conductive channel provided in the first chip 120 and to the fourth electrode 132 via a second conductive channel provided in the second chip 130, thereby realizing the electrical connection between the first electrode 121 and the fourth electrode 132.

[0028] Specifically, since the first electrode 121 is disposed on the first surface of the first chip 120 facing the carrier portion 110, and the fourth electrode 132 is disposed on the fourth surface 104 of the second chip 130 away from the carrier portion 110, the first electrode 121 and the fourth electrode 132 are separated by the first chip 120 and the second chip 130. In the prior art, when it is necessary to achieve electrical connection between the first electrode 121 and the fourth electrode 132, and electrical connection between the second electrode 122 and the third electrode 131, the first chip 120 and the second chip 130 can only be laid flat so that the first electrode 121 and the fourth electrode 132 are on the same side, and the second electrode 122 and the third electrode 131 are on the same side, so that the first electrode 121 and the fourth electrode 132 are electrically connected through leads on the same side, and the second electrode 122 and the third electrode 131 are electrically connected through leads on the same side.

[0029] In this embodiment, a first conductive channel is formed on the first chip 120 and a second conductive channel is formed on the second chip 130. This allows the interconnect structure 160 located between the first chip 120 and the second chip 130 to be electrically connected to the first electrode 121 via the first conductive channel and to the fourth electrode 132 via the second conductive channel. That is, the first electrode 121 and the fourth electrode 132 are electrically connected through the interconnect structure 160, thereby enabling the first chip 120 and the second chip 130 to be connected in parallel in a stacked manner. This reduces the size of the base island 111, allowing the package 100 to choose more package shapes, improve integration, and achieve the dual requirements of miniaturization and high performance.

[0030] Meanwhile, the introduction of the first clip 140 replaces the traditional multiple bonding wires, which not only significantly increases the effective cross-sectional area for current flow, but also significantly reduces on-resistance and stray inductance, improving device switching speed and power efficiency. Furthermore, the large-area contact improves the heat dissipation path on the front of the chip, achieving bidirectional heat dissipation and enhancing overall thermal management capabilities. In addition, the first clip 140 possesses good mechanical strength, enhancing the package structure's resistance to vibration and thermal fatigue, and improving board-level reliability; it can also integrate through-holes for quality inspection of the underlying bonding layer.

[0031] Continue reading Figures 1 to 5 The first electrode 121 of the first chip 120 is electrically connected to the base island 111, and the first pin 112a is insulated from the base island 111. The plurality of pins 112 further include a second pin 112b electrically connected to the base island 111 and a third pin 112c insulated from the base island 111. The first chip 120 further includes a fifth electrode 123 formed on the second surface 102, and the fifth electrode 123 is electrically connected to the third pin 112c.

[0032] Specifically, in this embodiment, the number of pins 112 is at least three, including a first pin 112a, a second pin 112b, and a third pin 112c. The first pin 112a and the third pin 112c are spaced apart from the base island 111, and the second pin 112b is electrically connected to the base island 111. For example, the second pin 112b can be integrally formed with the base island 111. The first pin 112a, the second pin 112b, and the third pin 112c can be arranged sequentially along a straight line. It should be noted that this application does not limit the number or arrangement of pins 112.

[0033] Simultaneously, the first electrode 121 is electrically connected to the base island 111, thereby connecting the first electrode 121, the base island 111, and the second pin 112b. The fifth electrode 123 is also electrically connected to the third pin 112c. In this embodiment, the first electrode 121 is electrically connected to the second pin 112b via the base island 111. Since the interconnect structure 160 connects the first electrode 121 to the fourth electrode 132, both the first electrode 121 and the fourth electrode 132 are electrically connected to the second pin 112b. Meanwhile, the second electrode 122 and the third electrode 131 are electrically connected to the first pin 112a via the first clip 140, and the fifth electrode 123 is electrically connected to the third pin 112c.

[0034] In a specific application scenario, the first chip 120 is an Insulated Gate Bipolar Transistor (IGBT), wherein the first electrode 121 can be the drain, the second electrode 122 can be the source, and the fifth electrode 123 can be the gate. The second chip 130 is a diode, which can be a fast recovery diode or a Schottky diode. One of the third electrode 131 and the fourth electrode 132 is the anode and the other is the cathode. For example, the third electrode 131 is the anode and the fourth electrode 132 is the cathode. Of course, the third electrode 131 can also be the cathode and the fourth electrode 132 is the anode. For ease of explanation, the following description will use the third electrode 131 as the anode and the fourth electrode 132 as the cathode. In this application scenario, under the action of the interconnect structure 160, the drain of the first chip 120 and the cathode of the second chip 130 are both electrically connected to the second pin 112b, the source of the first chip 120 and the anode of the second chip 130 are both electrically connected to the first pin 112a through the first clip 140, and the gate of the first chip 120 is electrically connected to the third pin 112c.

[0035] See Figure 1 as well as Figure 5The second clip 150 is located on the side of the first chip 120 opposite to the carrier portion 110, and the second clip 150 electrically connects the fifth electrode 123 and the third pin 112c. Specifically, in this embodiment, the second clip 150 is used to electrically connect the fifth electrode 123 and the third pin 112c of the first chip 120. The arrangement of the first clip 140 and the second clip 150 can achieve lower on-resistance and lower thermal effects, and can be completed in one step, greatly improving packaging production efficiency compared to the traditional multi-bonding wire method.

[0036] The first clip 140 and the second clip 150 can be made of the same material. For example, the first clip 140 and the second clip 150 can both be copper clips. Of course, the materials of the first clip 140 and the second clip 150 can also be different.

[0037] See Figure 14 as well as Figure 15 In another embodiment, the package 100 further includes a lead 170 located on the side of the first chip 120 opposite to the carrier portion 110, and the lead 170 is electrically connected to the fifth electrode 123 and the third pin 112c. Specifically, with Figure 1 The implementation method differs in that the fifth electrode 123 is electrically connected to the third pin 112c using conventional bonding wires.

[0038] Continue reading Figure 14 as well as Figure 15 In one embodiment, there are multiple first pins 112a, and the first clip 140 is electrically connected to multiple first pins 112a simultaneously.

[0039] In one embodiment, see Figure 6 as well as Figure 7 The first conductive channel includes a first groove 1201 formed on the second surface 102 and communicating with the first electrode 121, and the interconnect structure 160 is at least partially embedded in the first groove 1201 to be electrically connected to the first electrode 121.

[0040] Specifically, a first groove 1201 is formed on the second surface 102 of the first chip 120 to expose the first electrode 121 on the first surface, and an interconnect structure 160 is at least partially embedded in the first groove 1201 and electrically connected to the first electrode 121. The number of first grooves 1201 can be one or more, and each first groove 1201 corresponds one-to-one with an interconnect structure 160, with the interconnect structure 160 embedded in its corresponding first groove 1201. The first grooves 1201 can be formed on the first chip 120 by wafer-level etching.

[0041] In one embodiment, a first dielectric layer and a first metal layer are sequentially stacked on the wall of the first groove 1201. The first dielectric layer is made of at least one of silicon dioxide and silicon nitride, and can be formed on the wall of the first groove 1201 by chemical vapor deposition. Then, a first metal layer is formed on the wall of the first groove 1201 to enhance mechanical support. After the interconnect structure 160 is placed into the first groove 1201 through a self-aligning process, its bottom surface can form an ohmic contact with the first electrode 121, and its side surface can form a low-impedance interconnect with the first metal layer. The first metal layer can also be electrically connected to the first electrode 121. The first metal layer can be a titanium-copper-nickel composite structure.

[0042] It is understood that by setting the first groove 1201, the first electrode 121, the second electrode 122 and the fifth electrode 123 of the first chip 120 can be integrated on the same surface. When the first chip 120 is an insulated gate bipolar transistor, the source, drain and gate can be integrated on the same surface.

[0043] See Figure 8 , Figure 9 as well as Figure 10 In another embodiment, the first conductive channel includes a plurality of vias 1202 formed on the second surface 102 and communicating with the first electrode 121. The vias 1202 are filled with a conductive material electrically connected to the first electrode 121, and the interconnect structure 160 is electrically connected to the first electrode 121 through the conductive material. Specifically, with Figure 6 The implementation method differs in that it extends the first electrode 121 to the same side as the second electrode 122 using through-silicon via (TSV) technology, enabling the first electrode 121, the second electrode 122, and the fifth electrode 123 of the first chip 120 to be integrated on the same plane. When the first chip 120 is an insulated-gate bipolar transistor, the source, drain, and gate can be integrated on the same plane. See also... Figure 9 Furthermore, a first electrode 121 electrically connected to the via 1202 can be formed on the second surface 102.

[0044] In one embodiment, the first chip 120 can be bonded to the base island 111 by solder paste, wherein the thickness of the first chip 120 is in the range of 60um to 120um, and the thickness of the solder paste can be 45um to 55um, for example, the thickness of the solder paste is 50um.

[0045] See Figure 11 as well as Figure 12The second conductive channel includes a second groove 1203 formed on the third surface 103 and communicating with the fourth electrode 132. The interconnect structure 160 is at least partially embedded in the second groove 1203 to be electrically connected to the fourth electrode 132. The second groove 1203 allows for the co-integration of the third electrode 131 and the fourth electrode 132 of the second chip 130. The second groove 1203 can be formed on the second chip 130 by wafer-level etching.

[0046] Similar to the first groove 1201 described above, a second dielectric layer and a second metal layer can be sequentially formed on the wall of the second groove 1203. The material of the second dielectric layer includes at least one of silicon dioxide and silicon nitride. The second dielectric layer can be formed on the wall of the second groove 1203 by chemical vapor deposition. Then, a second metal layer is formed on the wall of the second groove 1203 to enhance mechanical support. After the interconnect structure 160 falls into the second groove 1203 through a self-aligning process, its bottom surface can form an ohmic contact with the fourth electrode 132, and its side surface can form a low-impedance interconnect with the second metal layer. The second metal layer can also be electrically connected to the fourth electrode 132. The second metal layer can be a titanium-copper-nickel composite structure.

[0047] In another embodiment, the fourth electrode 132 can also be extended to the same side as the third electrode 131 using through-silicon via (TSV) technology.

[0048] The interconnect structure 160 can specifically be a solder ball. It should be noted that this application does not impose specific restrictions on the interconnect structure 160, as long as it is conductive.

[0049] See Figure 13 The first clip 140 is provided with a first barb fastening part 141, which is fastened to the first pin 112a.

[0050] In one embodiment, see Figure 13 The second clip 150 is provided with a second barb fastening part 151, which is fastened to the third pin 112c.

[0051] Each barb fastening part is located at a preset position on the edge of each clip, and can be fastened to its corresponding pin 112 during installation. The first barb fastening part 141 of the first clip 140 fastens to the first pin 112a, and the second barb fastening part 151 of the second clip 150 fastens to the third pin 112c, achieving physical limiting and pre-fixing. The barb fastening parts not only improve the stability during assembly, but also effectively suppress the thermal drift of the clips at high temperatures, preventing short circuits caused by contact between the clips and other electrodes, and ensuring electrical connection accuracy and packaging yield. In addition, the barb structure can achieve self-alignment and locking functions without additional components, simplifying the automated placement process and improving production efficiency.

[0052] The first clip 140 can be bonded to the first chip 120 and the first pin 112a using solder paste. To facilitate the detection of solder paste distribution during packaging, the first clip 140 is provided with multiple through holes 1204, including at least one first-type through hole and at least one second-type through hole. The position of the first-type through hole corresponds to the first pin 112a, and the position of the second-type through hole corresponds to the first chip 120. During the packaging process, when solder paste overflows from the through hole 1204, it can be determined that there is too much solder paste; when there is no solder paste in the through hole 1204, it can be determined that there is insufficient solder paste. Similarly, the second clip 150 is provided with a through hole 1204 corresponding to the third pin 112c.

[0053] The thickness of the first clamping piece 140 and the second clamping piece 150 ranges from 200µm to 300µm. For example, the thickness of the first clamping piece 140 and the second clamping piece 150 can be 200µm, 250µm, or 300µm, etc., and can be selected and set according to actual needs. Furthermore, the thicknesses of the first clamping piece 140 and the second clamping piece 150 can be equal or unequal.

[0054] Continue reading Figure 1 The package 100 may also include a molding compound 180 for molding the first chip 120, the second chip 130, etc., wherein at least a portion of the pins 112 are exposed outside the molding compound 180 to form an electrical connection with an external circuit.

[0055] In one embodiment, a plating layer is also formed on the exposed surfaces of pin 112 and base island 111. The plating material is pure tin, which complies with RoHS standards and avoids lead contamination. The main purpose of tin plating is to protect the conductor from the risk of open circuit caused by oxidation and corrosion. As a conductive medium, the tin layer can reduce contact resistance, improve signal transmission efficiency, and fuse quickly with solder during subsequent component installation, reducing soldering defects such as cold solder joints and poor solder joints.

[0056] This application also provides an electronic device, exemplary of which includes the package 100 of any of the above embodiments. Specifically, the electronic device can be any type of electronic device, such as a motor driver, a photovoltaic inverter, an electric vehicle electronic control system, or a switching power supply.

[0057] In summary, by stacking the first chip 120 and the second chip 130, this application can reduce the size requirements of the carrier portion 110, reduce the size of the base island 111, and allow the package 100 to select more package shapes such as TO263 and other smaller surface mount devices, thereby improving integration and meeting the dual requirements of device miniaturization and high performance.

[0058] Meanwhile, the first clip 140 and the second clip 150 improve the current carrying capacity of the device, reduce the on-resistance or thermal resistance of the device, and improve the board-level reliability of the device.

[0059] In addition, when the second chip 130 is a diode, the above-mentioned second groove 1203 can also minimize the parasitic inductance and capacitive coupling effects, ensuring the stable operation of the IGBT single tube and extending its service life.

[0060] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application.

Claims

1. A package, characterized in that, The package includes: The carrier includes a base island and multiple pins disposed around the base island; A first chip is mounted on the base island. The first chip includes a first surface facing the base island and a second surface facing away from the base island. The first chip includes a first electrode disposed on the first surface and a second electrode disposed on the second surface. The second chip is stacked on the second surface of the first chip. The second chip includes a third surface facing the first chip and a fourth surface away from the first chip. The second chip includes a third electrode disposed on the third surface and a fourth electrode disposed on the fourth surface. A first clip is clamped between the first chip and the second chip. The first clip is used to connect the second electrode and the third electrode together to the first pin among the plurality of pins. An interconnect structure is disposed between the first chip and the second chip, and the interconnect structure is electrically connected to the first electrode through a first conductive channel that penetrates the second surface of the first chip and connects to the first electrode. The interconnect structure is electrically connected to the fourth electrode through a second conductive channel that penetrates the third surface of the second chip and connects to the fourth electrode.

2. The package according to claim 1, characterized in that, The first electrode of the first chip is electrically connected to the base island, and the first pin is electrically insulated from the base island; The plurality of pins also include a second pin electrically connected to the base island and a third pin electrically insulated from the base island; The first chip also includes a fifth electrode disposed on the second surface, the fifth electrode being electrically connected to the third pin.

3. The package according to claim 2, characterized in that, The fifth electrode and the third pin are electrically connected through a second interconnection structure: The second interconnection structure includes any one of the following: A second clip, at least partially located on a second surface of the first chip, is connected between the fifth electrode and the third pin; or A lead, at least partially located on the second surface of the first chip, is bonded between the fifth electrode and the third pin.

4. The package according to claim 1, characterized in that, The first conductive channel includes a blind hole-shaped first groove formed by recessing downward from the second surface of the first chip, the bottom of the first groove being exposed or connected to the first electrode; The interconnect structure is at least partially embedded in the first groove to be electrically connected to the first electrode.

5. The package according to claim 4, characterized in that, The first groove has a first dielectric layer and a first metal layer stacked sequentially on its groove wall.

6. The package according to claim 1, characterized in that, The first conductive channel includes a plurality of vias formed on the second surface of the first chip and communicating with the first electrode. Each via is filled with a conductive material, and the interconnect structure is electrically connected to the first electrode through the conductive material.

7. The package according to claim 1, characterized in that, The second conductive channel includes a blind-hole-shaped second groove formed by recessing downward from the fourth surface of the second chip, the bottom of the second groove being exposed or connected to the fourth electrode; The interconnect structure is at least partially embedded in the second groove for electrical connection with the fourth electrode.

8. The package according to claim 1, characterized in that, The first clip is provided with a barb fastening part, which is fastened to the first pin.

9. The package according to claim 1, characterized in that, The first clip has multiple through holes, including at least one first type of through hole and at least one second type of through hole. The position of the first type of through hole corresponds to the first pin, and the position of the second type of through hole corresponds to the first chip.

10. An electronic device, characterized in that, Includes the package as described in any one of claims 1 to 9.

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