Chip packaging structure and preparation method

Abstract

The invention discloses a chip packaging structure and a preparation method thereof, and relates to the technical field of chip packaging, and the method comprises the steps: providing an adapter plate with a first surface and a second surface, and the adapter plate further comprises an adapter circuit; the first surface comprises a first bonding pad and a second bonding pad; the first bonding pad is electrically connected with the switching circuit; temporarily bonding and fixing the second surface and the carrier plate; fixing a chip on the first surface, wherein the chip is electrically connected with the first bonding pad; forming a plastic package layer surrounding the chip on the first surface; a through hole exposing the second bonding pad is formed in the surface of the side, away from the adapter plate, of the plastic packaging layer, a metal layer is formed, and the metal layer covers the surface of the through hole and the top face of the chip and makes contact with the top face of the chip and the second bonding pad; fixing a heat dissipation plate with a micro-channel on the surface of the metal layer, wherein the heat dissipation plate is in thermal contact with the bottom of the through hole and the metal layer on the surface of the chip; and removing the carrier plate. According to the chip packaging structure, the micro-channel is integrated in the chip packaging structure, so that the heat dissipation capability of the chip packaging structure is improved.

Description

Technical Field

[0001] This application relates to the field of chip packaging technology, and in particular to a chip packaging structure and its fabrication method. Background Technology

[0002] In current high-density packaging technologies, integrating silicon interposers with molded chips has become a key technological approach to improve system integration. However, this structure faces significant challenges in heat dissipation.

[0003] Current common heat dissipation designs mainly rely on the back of the chip or through an adapter board to dissipate heat to distant locations. In this heat dissipation path, heat must pass through multiple material interfaces, including the molding compound, adhesive layer, and substrate. This process not only results in a long heat dissipation path and high cumulative thermal resistance, but also easily leads to excessively high chip junction temperatures and localized hot spot accumulation. This not only severely limits the full potential of the chip's performance but also poses a direct threat to the long-term reliability of the device. Summary of the Invention

[0004] In view of the above problems, this application provides a chip packaging structure and fabrication method, which improves the heat dissipation capacity of the chip packaging structure by integrating microchannels in the chip packaging structure. The specific solution is as follows:

[0005] On one hand, this application provides a chip packaging method, including:

[0006] An adapter board is provided, having a first surface and a second surface disposed opposite to each other; the adapter board includes an adapter circuit; the first surface includes a first pad and a second pad; the first pad is electrically connected to the adapter circuit;

[0007] Temporarily bond and fix the second surface to the carrier plate;

[0008] The chip is fixed on the first surface and electrically connected to the first pad.

[0009] A molding compound is formed around the chip on the first surface, with the side of the molding compound facing away from the adapter plate flush with the top of the chip;

[0010] A through-hole is formed on the side of the molding layer away from the adapter plate to expose the second solder pad;

[0011] A metal layer is formed on the side of the molding layer facing away from the adapter board. The metal layer covers the surface of the via and the top surface of the chip, and contacts the top surface of the chip and the second pad.

[0012] A heat sink with microchannels is fixed on the surface of a metal layer, and the heat sink is in thermal contact with the bottom of the via and the metal layer on the chip surface.

[0013] Remove the carrier plate.

[0014] This application provides a first pad on the first surface of the adapter board for soldering and fixing the chip, and a second pad for forming thermal contact with the microchannel above, so as to facilitate the rapid transfer of heat from the adapter board to the microchannel.

[0015] The microchannels dissipate heat from the chip by making thermal contact with the metal layer on the top surface of the chip. They can also transfer heat from the bottom of the chip to the adapter board through the second pad and the metal layer connected to it to the microchannels, thereby improving the heat dissipation effect in the adapter board below the chip, thus improving the chip's heat dissipation effect and further improving the chip's operational reliability.

[0016] In some embodiments, the method of fixing the heat sink includes:

[0017] After applying thermally conductive adhesive to the area of ​​the metal layer corresponding to the chip, the heat sink and the metal layer are soldered and fixed in the area of ​​the corresponding through hole using solder.

[0018] The heat sink is welded and fixed to the metal layer, and the through holes are filled with solder.

[0019] In some embodiments, the second surface includes solder balls for connecting external circuitry;

[0020] Temporarily bonding and fixing the second surface to the carrier plate includes:

[0021] A bonding adhesive layer covering solder balls is used to temporarily bond and fix the second surface to the carrier plate.

[0022] In some embodiments, a method for fixing a chip on a first surface includes:

[0023] The chip is soldered and fixed on the first pad, with a gap between the bottom surface of the chip and the first surface;

[0024] The gap is filled with insulating colloid, which contains thermally conductive particles that are uniformly mixed in.

[0025] In some embodiments, a chip bonding region is included on the first surface, and a first pad is located within the chip bonding region;

[0026] Multiple second pads are evenly distributed around the chip bonding area.

[0027] In some embodiments, at the bottom of the via, there is a gap between the sidewall of the via and the second pad.

[0028] In some embodiments, the chip packaging method further includes:

[0029] Before forming the metal layer, the surface of the molding compound layer facing away from the adapter plate is thinned so that this surface is flush with the top surface of the chip. On the other hand, this application also provides a chip packaging structure that can be formed using the chip packaging method described in any of the above embodiments, including:

[0030] An adapter board has a first surface and a second surface disposed opposite to each other; the adapter board includes an adapter circuit; the first surface includes a first pad and a second pad; the first pad is electrically connected to the adapter circuit;

[0031] A chip, which is fixed to a first surface and electrically connected to a first pad;

[0032] A molding compound is disposed around the chip on a first surface, and the side of the molding compound facing away from the adapter plate is flush with the top of the chip; the side of the molding compound facing away from the adapter plate has a through hole exposing the second pad.

[0033] The metal layer is located on the side of the molding layer facing away from the adapter board. The metal layer covers the surface of the via and the top surface of the chip, and contacts the top surface of the chip and the second pad.

[0034] The heat sink is fixed on the surface of the metal layer and has microchannels inside. The heat sink is in thermal contact with the metal layer at the bottom of the through hole and on the surface of the chip.

[0035] In some embodiments, the heat sink and the metal layer are fixed to the through-hole by solder welding, and the solder fills the through-hole.

[0036] In some embodiments, the area of ​​the metal layer outside the through-hole is bonded to the heat sink with thermally conductive adhesive.

[0037] In some embodiments, the coefficient of thermal expansion of the adapter plate and the heat sink are matched.

[0038] In some embodiments, the number of microchannels in the heat sink is at least one. Attached Figure Description

[0039] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, the drawings used in the description of the embodiments or prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0040] The structures, proportions, sizes, etc., shown in the accompanying drawings are only for the purpose of assisting those skilled in the art in understanding and reading the content disclosed in the specification, and are not intended to limit the implementation conditions of this application. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in the proportions, or adjustments to the size, without affecting the effects and purposes that this application can produce, should still fall within the scope of the technical content disclosed in this application.

[0041] Figure 1 This is a flowchart of a chip packaging method provided in an embodiment of this application;

[0042] Figures 2-10 The chip packaging structure diagrams for the chip packaging method provided in the embodiments of this application at different process stages are shown.

[0043] Figure label:

[0044] 11-Adapter board; 1101-Adapter circuit; 12-First pad; 13-Second pad; 14-Carrier board; 15-Chip; 16-Encapsulation layer; 17-Metal layer; 18-Heat sink; 19-Microchannel; 20-Bonding adhesive layer; 21-Thermal conductive adhesive; 22-Solder; 23-Solder ball; 24-Insulating colloid; P1-First surface; P2-Second surface; T-Through hole. Detailed Implementation

[0045] The embodiments of this application will now be clearly and completely described with reference to the accompanying drawings. Those skilled in the art will recognize that, with technological advancements and the emergence of new scenarios, the technical solutions provided in the embodiments of this application are equally applicable to similar technical problems.

[0046] Currently, high-power molded devices commonly employ laser-grooved designs on the molded body followed by metal filling or metal heat sink attachment for heat dissipation. This approach has significant bottlenecks: First, the depth and precision of laser grooving are limited, resulting in high vertical thermal resistance in the formed thermal paths. Second, there is an inherent interfacial thermal resistance between the subsequently filled or attached metal and the molded substrate, and the mismatch in the thermal expansion coefficients of the two materials easily leads to interfacial delamination under temperature cycling, causing thermal performance degradation and reduced structural reliability. Furthermore, traditional microchannels are often fabricated separately from silicon, glass, or metal, and then integrated with the chip carrier board via thermally conductive adhesive or brazing. The adhesive itself has poor thermal conductivity, and the high-temperature process required for brazing poses a risk of thermal damage to the integrated molded device and its internal sensitive chip.

[0047] Furthermore, regarding warpage control, there is a significant mismatch in the coefficients of thermal expansion between the silicon interposer, molding compound, and chip. Under the temperature differences during the packaging process and the power cycling during operation, enormous thermal stress is generated, causing the entire package to warp. This warpage not only reduces the yield of subsequent processes but may also lead to fatal failures such as microbump cracking or interface delamination.

[0048] This application provides a chip packaging method, including:

[0049] An adapter board is provided, having a first surface and a second surface disposed opposite to each other; the adapter board includes an adapter circuit; the first surface includes a first pad and a second pad; the first pad is electrically connected to the adapter circuit;

[0050] Temporarily bond and fix the second surface to the carrier plate;

[0051] The chip is fixed on the first surface and electrically connected to the first pad.

[0052] A molding compound is formed around the chip on the first surface, with the side of the molding compound facing away from the adapter plate flush with the top of the chip;

[0053] A through-hole is formed on the side of the molding layer away from the adapter plate to expose the second solder pad;

[0054] A metal layer is formed on the side of the molding layer facing away from the adapter board. The metal layer covers the surface of the via and the top surface of the chip, and contacts the top surface of the chip and the second pad.

[0055] A heat sink with microchannels is fixed on the surface of a metal layer, and the heat sink is in thermal contact with the bottom of the via and the metal layer on the chip surface.

[0056] Remove the carrier plate.

[0057] In this application, the microchannels achieve heat dissipation by making thermal contact with the top surface of the chip through a metal layer. They can also transfer heat from the bottom of the chip to the adapter board through the second pad and the metal layer connected to it to the microchannels, thereby improving the heat dissipation effect in the adapter board below the chip, thus improving the chip's heat dissipation effect and further enhancing the chip's operational reliability.

[0058] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0059] This application provides a chip packaging method, such as... Figure 1 As shown, Figure 1 This is a flowchart of a chip packaging method provided in an embodiment of this application. Figures 2-10 The chip packaging structure diagrams are provided for each step of the chip packaging process in the embodiments of this application.

[0060] like Figure 1 As shown, the chip packaging method includes the following steps S10 to S80:

[0061] Step S10: As Figure 2 As shown, an adapter board 11 is provided, the adapter board 11 having a first surface P1 and a second surface P2 disposed opposite to each other; the adapter board 11 includes an adapter circuit 1101; the first surface P1 includes a first pad 12 and a second pad 13; the first pad 12 is electrically connected to the adapter circuit 1101.

[0062] For example, refer to Figure 2 The adapter board 11 integrates an adapter circuit 1101. The adapter circuit 1101 typically consists of a multi-layer interconnect structure and vias, used for high-density electrical interconnection and signal redistribution between the first surface P1 and the second surface P2, as well as in the horizontal direction. The first pad 12 is electrically connected to the adapter circuit 1101 inside the adapter board 11. The first pad 12 can serve as a signal, power, or ground pad, transmitting signals input through the first pad 12 to the second surface P2 or other locations on the adapter board 11 via the adapter circuit 1101. The second pad 13 can connect to subsequently formed heat dissipation pathways.

[0063] Step S20: As Figure 3 As shown, the second surface P2 is temporarily bonded and fixed to the carrier plate 14;

[0064] For example, refer to Figure 3 The adapter board 11 is typically thin and prone to warping and breakage. Using the bonding adhesive layer 20 to temporarily bond the adapter board 11 to the thicker carrier board 14 provides a stable and rigid foundation for subsequent chip mounting and encapsulation processes on the first surface P1 of the adapter board 11, preventing deformation or breakage. Furthermore, before the front-side processing is completed, the carrier board 14 can protect the existing structure on the second surface P2 of the adapter board 11 from contamination or damage.

[0065] Step S30: As Figure 4 As shown, chip 15 is fixed on the first surface P1, and chip 15 is electrically connected to the first pad 12.

[0066] For example, refer to Figure 4 Before fixing the chip 15 on the first surface P1, the active surface bumps of the chip 15 have been fabricated. Then, during the chip mounting process, a certain pressure and heat are applied to the chip 15 to form a metallurgical bond between the bumps and the first pad 12, so that the chip 15 is fixed on the first surface P1 and electrically connected to the first pad 12.

[0067] Step S40: As Figure 5As shown, a molding compound 16 is formed on the first surface P1 surrounding the chip 15, and the side surface of the molding compound 16 facing away from the adapter plate 11 is flush with the top of the chip 15.

[0068] For example, refer to Figure 5 Epoxy molding compound (EMC) can be used, and a transfer molding process can be employed to form a molding layer 16. This allows the molding compound to completely encapsulate the chip 15, which is already fixed on the adapter board 11, providing mechanical support and protecting the chip 15 and its bump interconnects from environmental stresses such as moisture, contaminants, and mechanical impact. Through molding and subsequent planarization, a continuous and flat polymer surface is formed on the top of the chip 15, which is beneficial for the subsequent integration of a microfluidic substrate on top of the chip.

[0069] Step S50: As Figure 6 As shown, a through hole is formed on the side surface of the molding layer 16 away from the adapter plate 11, exposing the second pad 13.

[0070] For example, refer to Figure 6 The via pattern can be defined on the planarized molding layer 16 using photolithography, and then the molding layer material can be selectively removed using dry etching to form the via T and expose the metal surface of the second pad 13.

[0071] Step S60: As Figure 7 As shown, a metal layer 17 is formed on the side of the molding layer 16 facing away from the adapter plate 11. The metal layer 17 covers the surface of the through hole T and the top surface of the chip 15, and contacts the top surface of the chip 15 and the second pad 13.

[0072] For example, refer to Figure 7 A low thermal resistance, high reliability metal layer 17 can be formed using an electroplating process to serve as a heat dissipation substrate. The metal layer 17 simultaneously covers the surface of the via T, the top surface of the chip 15, and the surface of the molding compound 16 facing away from the adapter plate 11, achieving heat diffusion; and it contacts the top surface of the chip 15 and the second pad 13, forming good thermal contact. Utilizing the high thermal conductivity of the metal, the concentrated heat generated when the chip 15 is working is quickly diffused to the entire surface of the metal layer 17, improving heat conduction and heat dissipation.

[0073] Step S70: As Figure 8 and Figure 9 As shown, a heat sink 18 with microchannels 19 is fixed on the surface of the metal layer 17, and the heat sink 18 is in thermal contact with the bottom of the through hole T and the metal layer 17 on the surface of the chip 15.

[0074] For example, refer to Figure 8 and Figure 9The microchannel 19 contains a circulating liquid coolant. Through bonding and bonding processes, a heat sink 18 with microchannel 19 is fixed on the surface of the metal layer 17, so that the heat sink 18 forms a tight and stable thermal contact with the metal layer 17 corresponding to the bottom of the through hole T and the metal layer 17 covering the top surface of the chip 15. With the help of the circulating liquid coolant in the microchannel 19, the heat conducted from the chip 15 to the metal layer 17 is quickly dissipated, achieving efficient heat dissipation.

[0075] Step S80: As Figure 10 As shown, remove carrier plate 14.

[0076] For example, refer to Figure 10 The carrier board 14 can be removed by mechanical peeling, and the residual bonding adhesive layer 20 can be removed to ensure that the encapsulation structure is clean and does not affect the subsequent electrical connection and reliability.

[0077] This application provides a first pad 12 on the first surface P1 of the adapter plate 11 to solder and fix the chip 15, and a second pad 13 on the second surface P2 to form thermal contact with the microchannel 19 above, so as to facilitate the rapid transfer of heat in the adapter plate 11 to the microchannel 19.

[0078] The microchannel 19 heats the chip 15 by making thermal contact with the metal layer 17 on the top surface of the chip 15. It can also transfer the heat from the bottom of the chip 15 to the adapter plate 11 through the second pad 13 and the metal layer 17 connected to it to the microchannel 19, thereby improving the heat dissipation effect in the adapter plate 11 below the chip 15, thus improving the heat dissipation effect of the chip 15 and further improving the working reliability of the chip 15.

[0079] In some embodiments, such as Figure 8 and Figure 9 As shown, the method for fixing the heat sink 18 includes:

[0080] After applying thermally conductive adhesive 21 to the area of ​​metal layer 17 corresponding to chip 15, heat sink 18 and metal layer 17 are soldered and fixed in the area of ​​corresponding through hole T using solder.

[0081] In this process, after the heat sink 18 is welded and fixed to the metal layer 17, the through hole T is filled with solder.

[0082] Specifically, solder 22 can be provided in the area corresponding to the through hole T on the heat sink 18. Solder 22 can be pre-planted solder balls. In this embodiment, solder 22 is a low melting point tin-silver alloy.

[0083] After applying thermally conductive adhesive 21 to the area of ​​the metal layer 17 corresponding to the chip 15, the heat sink 18 and the metal layer 17 can be welded and fixed to the corresponding via T area using a tin-silver alloy at low temperature. During the welding bonding of the heat sink 18 and the metal layer 17, the molten tin-silver alloy solder, under pressure, completely fills the interior of the via T, forming a dense, void-free solder filler 22. This allows the heat sink 18 to contact the top surface metal layer 17 of the chip 15, facilitating heat dissipation from the top surface of the chip 15. Simultaneously, it achieves thermal contact between the heat sink 18 and the bottom metal layer 17 of the via T, enabling rapid heat conduction from the adapter board 11 to the heat sink 18. By completing the welding at low temperature using tin-silver alloy solder, thermal damage to the chip packaging structure caused by high-temperature processes can be avoided.

[0084] In some embodiments, such as Figure 9 The chip package structure shown includes a second surface P2 with solder balls 23 for connecting external circuits; the second surface P2 is temporarily bonded and fixed to the carrier board 14, which includes using a bonding adhesive layer 20 covering the solder balls 23 to temporarily bond and fix the second surface P2 to the carrier board 14.

[0085] For details, please refer to Figure 9 The second surface P2 of the adapter board 11 is prepared with solder balls 23 for connecting the chip packaging structure to the external circuit. Epoxy resin bonding adhesive can be coated on the surface of the carrier board 14 using a spin coating process, and then bonded to the second surface P2 of the adapter board 11. This allows the bonding adhesive layer 20 to cover the solder balls 23 and temporarily bond and fix the second surface P2 to the carrier board 14. The bonding adhesive layer 20 covers the solder balls 23, isolating them from the external environment and avoiding physical damage and chemical contamination of the solder balls 23 in subsequent processes.

[0086] In some embodiments, reference Figure 4 The chip packaging structure shown includes a method for fixing chip 15 on the first surface P1, comprising:

[0087] A chip 15 is soldered and fixed on the first pad 12, and there is a gap between the bottom surface of the chip 15 and the first surface P1; the gap is filled with insulating colloid 24, and thermally conductive particles are uniformly mixed in the insulating colloid 24.

[0088] Specifically, the chip 15 is aligned with the first pad 12 of the first surface P1 of the adapter board 11 via the bumps on its bottom surface (active surface), and then fixed by reflow soldering or thermoforming. A gap is formed between the bottom surface of the chip 15 and the first surface P1 of the adapter board 11 due to the height of the bumps. A capillary underfill process can be used, employing an epoxy resin-based insulating colloid 24 as the matrix material. The epoxy resin-based insulating colloid possesses excellent insulation, flowability, and post-curing adhesive strength, preventing short circuits between the chip 15 and the adapter board 11. Simultaneously, thermally conductive particles are uniformly mixed into the insulating colloid 24. These particles can be high thermal conductivity and high insulation ceramic particles such as aluminum nitride (AlN), boron nitride (BN), or alumina (Al2O3).

[0089] The cured thermally conductive insulating colloid 24 has a mechanical reinforcement effect, which can disperse the stress of the solder bumps of the chip 15, avoid bump breakage caused by vibration, and improve the reliability of the connection between the chip 15 and the adapter board 11. In addition, the thermally conductive particles in the insulating colloid 24 can conduct some of the heat generated by the chip 15 during operation to the adapter board 11, further improving the heat dissipation effect.

[0090] The existing packaging structure generally uses colloid to fix the heat sink 18 on the top of the chip 15. The chip 15 mainly relies on the heat sink 18 on the top for heat dissipation. The colloid at the bottom of the chip 15 is mainly used to fix the chip 15 and buffer bonding stress, and there is no need for downward heat conduction.

[0091] In this application, because the heat sink 18 is in thermal contact with the second pad 13 located at the bottom of the via through the metal layer 17, heat in the adapter plate 11 can be conducted upwards to the heat sink 18. Based on this, there is a capability for heat conducted downwards from the bottom of the chip 15 to the adapter plate 11 to be transferred back to the heat sink 18 through this channel. Therefore, there is a need to use an insulating colloid 24 with better thermal conductivity at the bottom of the chip 15 to improve the heat conduction performance of the heat dissipation channel at the bottom of the chip 15.

[0092] In some embodiments, the first surface P1 includes a chip bonding region, and the first pad 12 is located within the chip bonding region; a plurality of second pads 13 are evenly distributed around the chip bonding region.

[0093] Specifically, within the chip bonding area, the first pad 12 is generally a signal pad used to transmit high-speed data signals, and a power and ground pad to provide power and ground.

[0094] Multiple second pads 13 are evenly distributed around the chip bonding area. The second pads 13 are thermally connected to the metal layer 17 covering the top surface of the chip. The metal layer 17 forms a thermal contact with the heat sink 18, which conducts the heat from the adapter plate 11 and the chip 15 to the first surface P1 and improves the uniformity of heat dissipation efficiency.

[0095] In some embodiments, at the bottom of the via T, there is a gap between the sidewall of the via T and the second pad 13.

[0096] Specifically, at the bottom of the via T, there is a gap between the sidewall of the via T and the second pad 13, so that the subsequently deposited metal layer 17 not only covers the top surface of the second pad 13, but also wraps around the sidewalls of the second pad 13, significantly increasing the contact area between the metal layer 17 and the second pad 13. The larger contact area results in a lower interfacial thermal resistance between the metal layer 17 and the second pad 13 and improves the adhesion stability of the metal layer 17 at the bottom of the via T.

[0097] In some embodiments, the chip packaging method further includes:

[0098] Before forming the metal layer 17, the surface of the molding layer 16 facing away from the adapter plate 11 is thinned so that the surface of the molding layer 16 facing away from the adapter plate 11 is flush with the top surface of the chip 15.

[0099] Specifically, chemical mechanical polishing (CMP) can be used to thin the surface of the molding compound 16 facing away from the adapter plate 11. Making the surface of the molding compound 16 facing away from the adapter plate 11 flush with the top surface of the chip 15 eliminates the height difference between the molding compound 16 and the top surface of the chip 15, ensuring a uniform thickness of the subsequent electroplated metal layer 17, thereby guaranteeing the uniformity of heat diffusion and the reliability of electrical interconnection. In addition, the flat surface reduces stress concentration points in the metal layer 17, lowering the risk of warping and peeling of the subsequent metal layer 17 due to uneven thickness, and improving the long-term stability of the packaging structure.

[0100] This application also provides a chip packaging structure 10, as shown in the following embodiments. Figure 10 The chip packaging structure 10 can be formed using the chip packaging method described in any of the above embodiments, including: an adapter board 11, a chip 15, a molding layer 16, a metal layer 17, and a heat sink 18.

[0101] The adapter board 11 has a first surface P1 and a second surface P2 disposed opposite to each other; the adapter board 11 includes an adapter circuit 1101; the first surface P1 includes a first pad 12 and a second pad 13; the first pad 12 is electrically connected to the adapter circuit 1101.

[0102] The adapter board 11 can be made of silicon-based material. The adapter board 11 integrates a complete adapter circuit 1101, including metal wiring, insulating layer and conductive vias. The conductive vias penetrate the first surface P1 and the second surface P2, and are filled with copper metal to form a conductive path, ensuring signal transmission integrity and heat dissipation efficiency.

[0103] The first pad 12 and the second pad 13 can be made of copper. The first pad 12 is directly electrically connected to the adapter circuit 1101 inside the adapter board 11, serving as an interconnection node between the chip 15 and the adapter circuit 1101. The second pad 13 can serve as an auxiliary heat dissipation function.

[0104] Chip 15 is fixed to the first surface P1 and electrically connected to the first pad 12;

[0105] Chip 15 can be at least one logic chip or arithmetic chip. The bottom surface of chip 15, i.e. the active surface, is pre-fabricated with an array of bumps, which are fixed to the first surface P1 of the adapter board 11 by a low-temperature reflow soldering bonding process. The bumps and the first pad 12 form a metallurgical bond, realizing the electrical connection between chip 15 and adapter circuit 1101.

[0106] The molding compound 16 is disposed around the chip 15 on the first surface P1, and the side surface of the molding compound 16 facing away from the adapter plate 11 is flush with the top of the chip 15; the side surface of the molding compound 16 facing away from the adapter plate 11 has a through hole T exposing the second pad 13.

[0107] The molding layer 16 can be made of epoxy molding compound (EMC). The molding layer 16 covers the side of the chip 15, the exposed area of ​​the first surface P1, and the bump interconnect structure, with only the top surface of the chip 15 exposed, thus providing mechanical protection, environmental isolation, and structural support.

[0108] The surface of the molding compound 16 facing away from the adapter board 11 is treated with chemical mechanical polishing (CMP) to achieve coplanarity with the top surface of the chip 15, providing a flat substrate for subsequent deposition of the metal layer 17. A through-hole T penetrating the thickness of the molding compound 16 is formed in the corresponding area of ​​the second pad 13 of the molding compound 16.

[0109] The metal layer 17 is located on the side surface of the molding layer 16 opposite to the adapter plate 11. The metal layer 17 covers the surface of the through hole T and the top surface of the chip 15, and contacts the top surface of the chip 15 and the second pad 13.

[0110] The metal layer 17 is made of copper and aluminum with high thermal conductivity and high electrical conductivity, and is formed by electroplating. The metal layer 17 is continuous and uninterrupted. The metal layer 17 covers the surface of the molding layer 16 away from the adapter plate 11, the surface of the through hole T, and the top surface of the chip 15.

[0111] The metal layer 17 forms a tight thermal contact with the top surface of the chip 15, and at the same time, it forms a thermal contact with the second pad 13 through the bottom of the through hole T.

[0112] The heat sink 18 is fixed on the surface of the metal layer 17 and a microchannel 19 is provided inside the heat sink 18. The heat sink 18 is in thermal contact with the bottom of the through hole T and the metal layer 17 on the surface of the chip 15.

[0113] For example, the heat sink 18 has microchannels 19 inside, which are filled with coolant for coolant circulation. The bottom of the heat sink 18 is in thermal contact with the metal layer 17 corresponding to the top of the chip 15 and the bottom of the through hole T. The coolant flows within the microchannels 19 to cool the heat from the chip 15 and the adapter plate 11.

[0114] In some embodiments, reference Figure 9 The heat sink and the metal layer are fixed to each other by soldering at the position of the through hole, and the solder fills the through hole. Specifically, the solder 22 can be a low melting point tin-silver alloy. The through hole T is filled with solder 22, and the filled solder 22 forms a metallurgical bond with the metal layer 17 on the inner wall of the through hole T and the second pad 13 at the bottom of the through hole T, thereby achieving thermal contact between the solder 22 and the metal layer 17 and the heat sink 18.

[0115] The heat from the adapter board 11 can be quickly conducted to the solder 22 through the second pad 13. At the same time, the heat from the top surface of the chip 15 can be diffused to the via T area through the metal layer 17 and then further conducted to the heat sink 18 through the solder 22.

[0116] In some embodiments, reference Figure 9 The metal layer 17 located outside the through hole T is bonded and fixed to the heat sink 18 by thermally conductive adhesive 21.

[0117] For example, the thermally conductive adhesive 21 can be a curable colloid. The flexibility of the thermally conductive adhesive 21 can reduce the stress of the heat sink 18 on the chip 15. In addition, the thermally conductive adhesive layer coated on the top area of ​​the chip 15 is itself a lateral heat diffusion layer, which helps to conduct the heat generated by the chip 15 to the heat sink 18 more evenly and improve the heat dissipation efficiency.

[0118] In some embodiments, the coefficient of thermal expansion of the adapter plate 11 is matched with that of the heat sink 18.

[0119] Specifically, when the difference in the coefficients of thermal expansion between the adapter plate 11 and the heat sink 18 is within a small range, the deformation of the adapter plate 11 and the heat sink 18 tends to be consistent when the temperature changes, which can reduce the thermal stress at the interface and improve the structural reliability.

[0120] In some embodiments, the number of microchannels 19 within the heat sink 18 is at least one.

[0121] Specifically, at least one microchannel 19 is formed in the heat sink 18 through an etching process, and the microchannel 19 is filled with coolant to improve the heat dissipation effect of the heat sink 18. Furthermore, the heat dissipation efficiency can be further improved by increasing the number of microchannels 19, for example, by setting multiple microchannels 19 in parallel, thereby expanding the contact area between the coolant in the microchannel and the heat sink 18.

[0122] The various embodiments in this application are described in a progressive, parallel, or combined manner. Each embodiment focuses on its differences from other embodiments, and similar or identical parts between embodiments can be referred to interchangeably. The embodiments provided in this application can be combined with each other without contradiction.

[0123] It should be noted that, in the description of this application, the accompanying drawings and embodiments are illustrative rather than restrictive. The same reference numerals throughout the embodiments identify the same structures. Additionally, for understanding and ease of description, the thicknesses of some layers, films, panels, regions, etc., may be exaggerated in the drawings. It is also understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, the element may be directly on the other element or there may be intermediate elements. Furthermore, "on" means positioning an element on or below another element, but does not inherently mean positioning it above another element according to the direction of gravity.

[0124] The terms "upper," "lower," "top," "bottom," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. When a component is considered to be "connected" to another component, it can be directly connected to the other component or there may be a component positioned centrally in the middle.

[0125] It should also be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that an article or apparatus comprising a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such an article or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the article or apparatus that includes the aforementioned element.

[0126] The above description of the disclosed embodiments enables those skilled in the art to make or use this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A chip packaging method, characterized in that, include: An adapter board is provided, the adapter board having a first surface and a second surface disposed opposite to each other; the adapter board includes an adapter circuit; The first surface includes a first pad and a second pad; the first pad is electrically connected to the adapter circuit. Temporarily bond and fix the second surface to the carrier plate; A chip is fixed on the first surface, and the chip is electrically connected to the first pad. A molding compound is formed on the first surface surrounding the chip, wherein the side of the molding compound facing away from the adapter plate is flush with the top of the chip; A through-hole is formed on the surface of the molding layer opposite to the adapter plate to expose the second pad; A metal layer is formed on the side of the molding layer facing away from the adapter plate. The metal layer covers the surface of the via and the top surface of the chip, and contacts the top surface of the chip and the second pad. A heat sink with microchannels is fixed on the surface of the metal layer, and the heat sink is in thermal contact with the bottom of the through hole and the metal layer on the chip surface. Remove the carrier plate.

2. The chip packaging method according to claim 1, characterized in that, The method for fixing the heat sink includes: After applying thermally conductive adhesive to the area of ​​the metal layer corresponding to the chip, the heat sink is soldered to the metal layer in the area corresponding to the through hole using solder. The heat sink is welded and fixed to the metal layer, and the solder fills the through hole.

3. The chip packaging method according to claim 1, characterized in that, The second surface includes solder balls for connecting external circuitry; Temporarily bonding and fixing the second surface to the carrier plate includes: The second surface is temporarily bonded and fixed to the carrier plate by using a bonding adhesive layer covering the solder balls.

4. The chip packaging method according to claim 1, characterized in that, The method for fixing the chip on the first surface includes: The chip is soldered and fixed on the first pad, and there is a gap between the bottom surface of the chip and the first surface; The gap is filled with an insulating colloid, which contains thermally conductive particles uniformly mixed in.

5. The chip packaging method according to claim 1, characterized in that, The first surface includes a chip bonding area, and the first pad is located within the chip bonding area; The chip bonding area has multiple second pads evenly distributed around it.

6. The chip packaging method according to claim 1, characterized in that, At the bottom of the through hole, there is a gap between the sidewall of the through hole and the second pad.

7. The chip packaging method according to any one of claims 1-6, characterized in that, Also includes: Before forming the metal layer, the surface of the molding compound facing away from the adapter plate is thinned so that the surface of the molding compound facing away from the adapter plate is flush with the top surface of the chip.

8. A chip packaging structure, characterized in that, The chip is formed using the chip packaging method described in any one of claims 1 to 7, comprising: An adapter board has a first surface and a second surface disposed opposite to each other; the adapter board includes an adapter circuit; the first surface includes a first pad and a second pad; the first pad is electrically connected to the adapter circuit; A chip, which is fixed to the first surface and electrically connected to the first pad; A molding compound is disposed around the chip on the first surface, and the side of the molding compound facing away from the adapter plate is flush with the top of the chip; the side of the molding compound facing away from the adapter plate has through holes exposing the second pads. A metal layer is located on the side surface of the molding compound facing away from the adapter board. The metal layer covers the surface of the via and the top surface of the chip, and contacts the top surface of the chip and the second pad. A heat sink is fixed to the surface of the metal layer and has microchannels inside it. The heat sink is in thermal contact with the bottom of the through hole and the metal layer on the surface of the chip.

9. The chip packaging structure according to claim 8, characterized in that, The heat sink and the metal layer are fixed to each other by soldering at the location of the through hole, and the solder fills the through hole.

10. The chip packaging structure according to claim 8, characterized in that, The metal layer located outside the through hole is bonded and fixed to the heat sink with thermally conductive adhesive.

11. The chip packaging structure according to claim 8, characterized in that, The adapter plate has a coefficient of thermal expansion that matches that of the heat sink.

12. The chip packaging structure according to claim 8, characterized in that, The heat sink contains at least one microchannel.

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