Semiconductor device

Abstract

A semiconductor device is provided herein. The semiconductor device includes: a wafer extending in a plane in a first direction and a second direction; the first insulating layer, the second insulating layer and the third insulating layer are sequentially stacked in the third direction above the surface of the wafer; a plurality of lower standard patterns disposed in the first insulating layer and the second insulating layer; and a plurality of dummy patterns disposed in the third insulating layer.

Description

TECHNICAL FIELD

[0001] Various embodiments of the present disclosure generally relate to a semiconductor device, and more particularly to a semiconductor device including a scribe line region and a chip region. BACKGROUND

[0002] A semiconductor device includes a multi-layer pattern forming an integrated circuit. The alignment between the multi-layer patterns can be measured by inspecting an overlay mark.

[0003] The overlay mark is formed in a scribe line region of a wafer. In the scribe line region, various patterns that do not participate in the operation of the integrated circuit can be provided in addition to the overlay mark.

[0004] As semiconductor devices become more highly integrated, the patterns forming the integrated circuit become more complex, resulting in an increase in the patterns provided in the scribe line region. SUMMARY

[0005] An embodiment of the present disclosure can provide a semiconductor device. The device can include a wafer including a chip region and a scribe line region surrounding the chip region, a surface of the wafer extending in a plane in a first direction and a second direction; a first insulating layer, a second insulating layer, and a third insulating layer stacked in a third direction over the surface of the wafer; a first overlay mark including a plurality of downstream marker patterns provided in the first insulating layer and the second insulating layer and overlapping the scribe line region of the wafer in a perpendicular direction; and a plurality of dummy patterns provided in the third insulating layer and overlapping the scribe line region of the wafer in the third direction. Each of the plurality of dummy patterns is formed with a first area measured in the first direction and the second direction, and each of the plurality of downstream marker patterns is formed with a second area measured in the first direction and the second direction. The first area of each of the plurality of dummy patterns is smaller than the second area of each of the plurality of downstream marker patterns.

[0006] An embodiment of the present disclosure can provide a semiconductor device. The device can include a wafer including a chip region and a scribe line region surrounding the chip region, a surface of the wafer extending in a plane in a first direction and a second direction; a first insulating layer, a second insulating layer, a third insulating layer, a fourth insulating layer, and a fifth insulating layer stacked in a third direction over the surface of the wafer; a plurality of dummy patterns provided in the third insulating layer and overlapping the scribe line region in the third direction; and an overlay mark overlapping the scribe line region of the wafer in the third direction. The overlay mark can not be provided in an area overlapping the plurality of dummy patterns in the third direction within each of the fourth insulating layer and the fifth insulating layer. The overlay mark can include a plurality of downstream marker patterns provided in the first insulating layer and the second insulating layer.

[0007] An embodiment of the present disclosure can provide a semiconductor device. The device can include: a wafer including a chip region and a scribe lane region surrounding the chip region, a surface of the wafer extending in a plane of a first direction and a second direction; a first insulating layer, a second insulating layer, and a third insulating layer stacked in a third direction over the surface of the wafer in order; an overlap mark including a plurality of downstream bar patterns provided in the first insulating layer and the second insulating layer and overlapping the scribe lane region of the wafer in the third direction; and a disc-shaped defect suppression structure including a plurality of dummy patterns provided in the third insulating layer, the plurality of dummy patterns overlapping the scribe lane region of the wafer in the third direction. The plurality of dummy patterns can overlap the plurality of downstream bar patterns in the third direction. BRIEF DESCRIPTION OF DRAWINGS

[0008] Figure 1 is a plan view illustrating a wafer according to an embodiment of the present disclosure.

[0009] Figure 2 is a cross-sectional view of a semiconductor device according to an embodiment of the present disclosure taken along the chip region.

[0010] Figure 3 is a plan view illustrating an overlap mark and a plurality of dummy patterns provided in a scribe lane region of a semiconductor device according to an embodiment of the present disclosure.

[0011] Figure 4A , Figure 4B and Figure 4C are cross-sectional views of a semiconductor device according to an embodiment of the present disclosure taken along Figure 3 lines A1-A1’, B1-B1’, and C1-C1’ shown in FIG. 1.

[0012] Figure 5A and Figure 5B are cross-sectional views of a semiconductor device according to an embodiment of the present disclosure taken along

[0013] Figure 6 is a plan view illustrating an overlap mark and a plurality of dummy patterns provided in a scribe lane region of a semiconductor device according to an embodiment of the present disclosure.

[0014] Figure 7A , Figure 7B and Figure 7C are cross-sectional views of a semiconductor device according to an embodiment of the present disclosure taken along Figure 6 lines A2-A2’, B2-B2’, and C2-C2’ shown in FIG. 2.

[0015] Figure 8is a cross-sectional view illustrating an overlapping mark and a multi-layer dummy pattern provided in a scribe lane region of a semiconductor device according to an embodiment of the present disclosure.

[0016] Figure 9A and Figure 9B is a plan view illustrating a first overlapping mark according to an embodiment of the present disclosure.

[0017] Figure 10A , Figure 10B and Figure 10C is a plan view illustrating a plurality of dummy patterns and a second overlapping mark according to an embodiment of the present disclosure.

[0018] Figure 11 is a plan view illustrating a first overlapping mark and a plurality of dummy patterns according to an embodiment of the present disclosure.

[0019] Figure 12 is a plan view illustrating an insulating layer above a plurality of dummy patterns according to an embodiment of the present disclosure.

[0020] Figure 13A and Figure 13B is a plan view illustrating a multi-layer dummy pattern according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0021] The specific configurations or functional descriptions disclosed herein are merely illustrative of embodiments according to the concept of the present disclosure. Embodiments according to the concept of the present disclosure can be implemented in various forms, and should not be construed as being limited to the specific embodiments set forth herein.

[0022] Terms such as "first" and "second" are used to distinguish various elements, and do not imply the size, order, priority, number, or importance of the elements. For example, in one example, a first element can be named as a second element, and in another example, a second element can be named as a first element. Terms such as "vertical", "above", "lower", "upper", and other terms implying relative spatial relationships or orientations are used only for the purpose of facilitating description or reference to the drawings, and are not otherwise limiting. It will be understood that when an element or layer is referred to as being "on" another element or layer, "connected to" or "coupled to" another element or layer, it can be directly on, directly connected or coupled to, or can have intervening elements or layers. In contrast, when an element is referred to as being "directly on" another element or layer, "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers. Cross-hatching illustrating correspondence or similarity between the drawings throughout the drawings, rather than indicating materials associated with the regions.

[0023] Various embodiments of the present disclosure relate to a semiconductor device capable of increasing the pattern integration of a scribe lane region while securing the stability of a manufacturing process.

[0024] Figure 1 is a plan view illustrating a wafer according to an embodiment of the present disclosure.

[0025] Referring to Figure 1 In the plan view, the wafer 101 can include a plurality of chip regions CR and a scribe lane region SR. The wafer 101 can include a semiconductor substrate. In an embodiment, the wafer 101 can include silicon, germanium, or a mixture thereof. The wafer 101 can extend in a plane in a first direction and a second direction.

[0026] An integrated circuit of a semiconductor device can be disposed in each chip region CR. The integrated circuit can form a semiconductor chip for a memory device such as a DRAM (Dynamic Random Access Memory), an SRAM (Static Random Access Memory), a flash memory, an MRAM (Magnetic Random Access Memory), an FRAM (Ferroelectric Random Access Memory), a ReRAM (Resistive Random Access Memory), or a PRAM (Phase-Change Random Access Memory). In an embodiment, the integrated circuit can be a memory circuit forming a cell array of the memory device, a logic circuit including a peripheral circuit controlling the operation of the cell array, or a combination of the memory circuit and the logic circuit.

[0027] In the plan view, the scribe lane region SR can surround the chip regions CR. In the scribe lane region SR, a pattern formed by the same or similar process as a pattern formed in each chip region CR can be disposed. The pattern disposed in the scribe lane region SR can include a monitor pattern for inspecting characteristics and alignment of the pattern formed in the chip region CR and a dummy pattern for the stability of a manufacturing process. In an embodiment, the monitor pattern can include an overlay mark for inspecting alignment, and some of the dummy pattern can form a disc-shaped defect suppression structure. The scribe lane region SR can include a separation region. After the integrated circuit is formed in the chip region CR, a process such as dicing or sawing can be performed along the separation region. Through the process such as dicing or sawing, the wafer 101 can be divided into a plurality of semiconductor chips.

[0028] A semiconductor device according to an embodiment of the present disclosure can include various patterns formed in a plurality of chip regions CR and a scribe lane region SR of a wafer 101.

[0029] Figure 2 is a cross-sectional view taken along a chip region of a semiconductor device according to an embodiment of the present disclosure.

[0030] Referring to Figure 2The semiconductor device can include a first insulating layer 111, a second insulating layer 121, a third insulating layer 131, a fourth insulating layer 141, and a fifth insulating layer 151 stacked over a chip region CR of a wafer 101. The wafer 101 has a surface extending in a planar surface in a first direction DR1 and a second direction DR2. The first insulating layer 111, the second insulating layer 121, the third insulating layer 131, the fourth insulating layer 141, and the fifth insulating layer 151 can be sequentially stacked over the wafer in a third direction DR3. In an embodiment, the first insulating layer 111, the second insulating layer 121, the third insulating layer 131, the fourth insulating layer 141, and the fifth insulating layer 151 are sequentially stacked in a vertical direction perpendicular to the surface of the wafer 101.

[0031] The semiconductor device can include a plurality of contact plugs and a plurality of wires vertically overlapping in the chip region CR of the wafer 101. In an embodiment, the plurality of contact plugs can include a first contact plug 113C disposed in the first insulating layer 111, a second contact plug 133C disposed in the third insulating layer 131, and a third contact plug 153C disposed in the fifth insulating layer 151, and the plurality of wires can include a first wire 123L disposed in the second insulating layer 121 and a second wire 143L disposed in the fourth insulating layer 141. The plurality of contact plugs and the plurality of wires can form a portion of an integrated circuit, and can be formed of various conductive materials. In an embodiment, the first contact plug 113C, the first wire 123L, the second contact plug 133C, the second wire 143L, and the third contact plug 153C can be electrically connected to each other and form an interconnection structure.

[0032] The alignment of the plurality of contact plugs and the plurality of wires can be determined by measuring an overlap mark formed substantially simultaneously with the contact plugs and the wires over the scribe lane region. Each of the contact plugs and the wires can be formed by filling an interior of a recessed region with a conductive material. The recessed region can be formed by etching an insulating layer in a layer in which each of the contact plugs and the plurality of wires is located. In a process of filling the interior of the recessed region with the conductive material, the conductive material can be left only in the recessed region by a planarization process such as chemical mechanical polishing (CMP). When the planarization process is performed, a dishing defect that causes a step between the conductive material and the insulating layer that is planarized can occur. To suppress the dishing defect, in an embodiment, a plurality of dummy patterns can be disposed in a region of the insulating layer of each layer that overlaps the scribe lane region. The words "simultaneously" and "simultaneously" as used herein in relation to events mean that the events occur over an overlapping time interval. For example, if a first event occurs within a first time interval and a second event occurs simultaneously within a second time interval, the first interval and the second interval at least partially overlap each other such that there is a time during which both the first event and the second event occur.

[0033] Figure 3 is a plan view illustrating an overlap mark and a plurality of dummy patterns provided in a scribe lane region of a semiconductor device according to an embodiment of the present disclosure.

[0034] Referring to Figure 3 , the overlap mark OV can include a plurality of first vernier patterns V1 and a plurality of second vernier patterns V2.

[0035] In the plan view, the plurality of first vernier patterns V1 can be arranged to be spaced apart from each other in the first direction DR1 or the second direction DR2, and can be formed in a bar type extending in the first direction DR1 or the second direction DR2. The bar type can have a length defined along a long axis in one of the first direction DR1 and the second direction DR2, and a width defined along a short axis in the other direction. For example, the plurality of first vernier patterns V1 arranged to be spaced apart from each other in the first direction DR1 can be formed in a bar type having a length extending in the second direction DR2, and the plurality of first vernier patterns V1 arranged to be spaced apart from each other in the second direction DR2 can be formed in a bar type having a length extending in the first direction DR1. The first direction DR1 and the second direction DR2 are defined as directions of two axes intersecting in the plan view.

[0036] The plurality of second vernier patterns V2 can be arranged to not overlap the plurality of first vernier patterns V1 in a perpendicular direction. Hereinafter, the perpendicular direction is referred to as a third direction DR3. Similar to the plurality of first vernier patterns V1, in the plan view, the plurality of second vernier patterns V2 can be arranged to be spaced apart from each other in the first direction DR1 or the second direction DR2, and can be formed in a bar type extending in the first direction DR1 or the second direction DR2.

[0037] By measuring the alignment between the plurality of first vernier patterns V1 and the plurality of second vernier patterns V2, the alignment between patterns formed in the chip region can be determined. The plurality of first vernier patterns V1 and the plurality of second vernier patterns V2 can overlap the plurality of dummy patterns 133D in the third direction DR3.

[0038] Figure 4A 、 Figure 4B and Figure 4C is a cross-sectional view taken along the line A1-A1', the line B1-B1', and the line C1-C1' of the semiconductor device according to the embodiment of the present disclosure. Figure 3

[0039] Referring to Figure 3 、 4A 、 Figure 4B and Figure 4C ​The plurality of first vernier patterns V1 can be divided into a plurality of first lower vernier patterns 113V1 of the first overlay mark OV1 and a plurality of first upper vernier patterns 143V1 of the second overlay mark OV2. The plurality of second vernier patterns V2 can be divided into a plurality of second lower vernier patterns 123V2 of the first overlay mark OV1 and a plurality of second upper vernier patterns 153V2 of the second overlay mark OV2.

[0040] The plurality of dummy patterns 133D is arranged at the height between the first overlap mark OV1 and the second overlap mark OV2. At this time, the plurality of dummy patterns 133D can be formed with a smaller area than the plurality of first downstream mark patterns 113V1 and the plurality of second downstream mark patterns 123V2 of the first overlap mark OV1, and can overlap them in the third direction DR3. In an embodiment, each of the plurality of dummy patterns 133D is formed with an area smaller than an area of each of the plurality of downstream mark patterns (i.e., 113V1 and 123V2) overlapping in the third direction DR3. For example, each of the plurality of dummy patterns 133D has a first area, and each of the plurality of first downstream mark patterns 113V1 has a second area greater than the first area. For example, each of the plurality of dummy patterns 133D has a first area, and each of the plurality of second downstream mark patterns 123V2 has a third area greater than the first area. In an embodiment, the area of the dummy pattern 133D (i.e., the first area) can be an area measured along the first direction DR1 and the second direction DR2. In an embodiment, the area of the first downstream mark pattern 113V1 (i.e., the second area) can be an area measured along the first direction DR1 and the second direction DR2. In an embodiment, the area of the second downstream mark pattern 123V2 (i.e., the third area) can be an area measured along the first direction DR1 and the second direction DR2. In an embodiment, the second area of the first downstream mark pattern 113V1 can have the same area as the third area of the second downstream mark pattern 123V2. The plurality of first upstream mark patterns 143V1 and the plurality of second upstream mark patterns 153V2 of the second overlap mark OV2 can be formed with a larger area than the plurality of dummy patterns 133D, and can overlap them in the third direction DR3. In an embodiment, each of the plurality of dummy patterns 133D is formed with an area smaller than an area of each of the plurality of upstream mark patterns (i.e., 143V1 and 153V2) overlapping in the third direction DR3. For example, each of the plurality of dummy patterns 133D has a first area, and each of the plurality of first upstream mark patterns 143V1 has a fourth area greater than the first area. For example, each of the plurality of dummy patterns 133D has a first area, and each of the plurality of second upstream mark patterns 153V2 has a fifth area greater than the first area. In an embodiment, the area of the dummy pattern 133D (i.e., the first area) can be an area measured along the first direction DR1 and the second direction DR2. In an embodiment, the area of the first upstream mark pattern 143V1 (i.e., the fourth area) can be an area measured along the first direction DR1 and the second direction DR2. In an embodiment, the area of the second upstream mark pattern 153V2 (i.e., the fifth area) can be an area measured along the first direction DR1 and the second direction DR2.In embodiments, the fourth area of the first upstream marker pattern 143V1 can have the same area as the fifth area of the second upstream marker pattern 153V2.

[0041] The first insulating layer 111, the second insulating layer 121, the third insulating layer 131, the fourth insulating layer 141, and the fifth insulating layer 151 can extend to overlap with the scribe line region SR of the wafer 101. The plurality of first downstream marker patterns 113V1 can overlap with the scribe line region SR of the wafer 101 in the third direction DR3 and can be disposed in the first insulating layer 111. The plurality of second downstream marker patterns 123V2 can overlap with the scribe line region SR of the wafer 101 in the third direction DR3 and can be disposed in the second insulating layer 121. The plurality of dummy patterns 133D can overlap with the scribe line region SR of the wafer 101 in the third direction DR3 and can be disposed in the third insulating layer 131. The plurality of first upstream marker patterns 143V1 can overlap with the scribe line region SR of the wafer 101 in the third direction DR3 and can be disposed in the fourth insulating layer 141. The plurality of second upstream marker patterns 153V2 can overlap with the scribe line region SR of the wafer 101 in the third direction DR3 and can be disposed in the fifth insulating layer 151.

[0042] Referring to Figure 2 , Figure 4A , Figure 4B and Figure 4C , the plurality of first downstream marker patterns 113V1 can be formed using a process of forming the first contact plug 113C and can include the same conductive material as the first contact plug 113C. The plurality of second downstream marker patterns 123V2 can be formed using a process of forming the first conductive line 123L and can include the same conductive material as the first conductive line 123L. In the third direction DR3, the plurality of second downstream marker patterns 123V2 can not overlap with the plurality of first downstream marker patterns 113V1 but can overlap with the first insulating layer 111. Accordingly, in embodiments, positions of the plurality of first downstream marker patterns 113V1 and the plurality of second downstream marker patterns 123V2 can be optically detected. In embodiments, based on the detection signal, alignment between the plurality of first downstream marker patterns 113V1 and the plurality of second downstream marker patterns 123V2 can be measured, and alignment between the first contact plug 113C and the first conductive line 123L can be determined.

[0043] The plurality of dummy patterns 133D can be formed using a process of forming the second contact plug 133C and can include the same conductive material as the second contact plug 133C. In embodiments, the plurality of dummy patterns 133D can function as a dish defect prevention structure while performing a planarization process such that the third insulating layer 131 is exposed.

[0044] The plurality of first upstream vernier patterns 143V1 can be formed using a process of forming the second conductive lines 143L, and can include the same conductive material as the second conductive lines 143L. The plurality of second upstream vernier patterns 153V2 can be formed using a process of forming the third contact plugs 153C, and can include the same conductive material as the third contact plugs 153C. In the third direction DR3, the plurality of second upstream vernier patterns 153V2 can not overlap the plurality of first upstream vernier patterns 143V1, but can overlap the fourth insulating layer 141. Accordingly, in embodiments, positions of the plurality of first upstream vernier patterns 143V1 and the plurality of second upstream vernier patterns 153V2 can be optically detected. In embodiments, based on the detection signal, alignment between the plurality of first upstream vernier patterns 143V1 and the plurality of second upstream vernier patterns 153V2 can be measured, and alignment between the third contact plugs 153C and the second conductive lines 143L can be determined.

[0045] The plurality of first upstream vernier patterns 143V1 and the plurality of second upstream vernier patterns 153V2 can overlap the plurality of dummy patterns 133D in the vertical direction, and each of the plurality of first upstream vernier patterns 143V1 and the plurality of second upstream vernier patterns 153V2 can be formed to have a larger area than each of the plurality of dummy patterns 133D. Accordingly, in embodiments, because interference of the detection signal caused by the plurality of dummy patterns 133D can be reduced in measuring alignment between the plurality of first upstream vernier patterns 143V1 and the plurality of second upstream vernier patterns 153V2, stability of a manufacturing process of the semiconductor device can be ensured.

[0046] In embodiments, to further reduce interference of the detection signal, the plurality of first upstream vernier patterns 143V1 can overlap the plurality of first downstream vernier patterns 113V1 in the third direction DR3, and the plurality of second upstream vernier patterns 153V2 can overlap the plurality of second downstream vernier patterns 123V2 in the third direction DR3. Each of the plurality of first upstream vernier patterns 143V1 and the plurality of second upstream vernier patterns 153V2 can be formed to have substantially the same area as each of the plurality of first downstream vernier patterns 113V1 and the plurality of second downstream vernier patterns 123V2, or can be formed to have a larger area than each of the plurality of first downstream vernier patterns 113V1 and the plurality of second downstream vernier patterns 123V2.

[0047] In embodiments, the plurality of dummy patterns 133D can overlap the first overlap mark OV1 and can function as a dish defect prevention structure, thereby reducing an area of the scribe lane region SR allocated to the dish defect prevention structure. In embodiments, the second overlap mark OV2 can overlap the first overlap mark OV1 and the plurality of dummy patterns 133D, thereby reducing an area of the scribe lane region SR allocated to the vernier patterns.

[0048] Figure 5A and Figure 5B is a cross-sectional view illustrating a chip region and a scribe lane region of a semiconductor device according to an embodiment of the present disclosure.

[0049] Referring to Figure 5A , a chip region CR of a wafer 101 can include a cell array region CAR and a peripheral circuit region PER. In an embodiment, DRAM elements can be formed on the cell array region CAR and the peripheral circuit region PER of the wafer 101. Hereinafter, one example of the DRAM elements formed on the chip region CR of the wafer 101 will be described.

[0050] The wafer 101 can be divided into a plurality of active regions ACT1 and ACT2 by an isolation layer ISO. The plurality of active regions ACT1 and ACT2 can include a first active region ACT1 disposed in the cell array region CAR and a second active region ACT2 disposed in the peripheral circuit region PER.

[0051] Memory cell transistors coupled to the word line WL and the bit line BL and a capacitor coupled to the memory cell transistors can be formed in the cell array region CAR of the wafer 101.

[0052] The word line WL can be embedded in the wafer 101. A cell gate insulating layer GIl is interposed between the word line WL and the wafer 101. A cap pattern CAP can be disposed above the word line WL. The word line WL can function as a gate of the memory cell transistor. The cap pattern CAP can include an insulating material such as silicon nitride. A first impurity implantation region II can be disposed on one side of the word line WL in the first active region ACT1. Although not shown in the drawing, a separate impurity implantation region can be disposed in a portion of the first active region ACT1 facing the first impurity implantation region II, with the word line WL interposed therebetween. The above-described first impurity implantation region II and the separate impurity implantation region can function as a source region and a drain region of the memory cell transistor.

[0053] The bit line BL can be electrically connected to the first impurity implantation region II of the first active region ACT1 through a bit line contact plug DC. The bit line BL can be spaced apart from the first active region ACT1 with a first interlayer insulating layer of a first lower insulating structure 103 interposed therebetween. The bit line contact plug DC can penetrate the first interlayer insulating layer of the first lower insulating structure 103 to directly contact the first impurity implantation region II. The bit line BL can be embedded in a second interlayer insulating layer of the first lower insulating structure 103. The second interlayer insulating layer can be disposed above the first interlayer insulating layer.

[0054] The bit line BL can be covered with a second lower insulating structure 105. The bit line BL can be spaced apart from the landing pad LP by the second lower insulating structure 105. The landing pad LP can be embedded in a third lower insulating structure 107 above the second lower insulating structure 105. Although not shown in the figure, the landing pad LP can be coupled to a separate impurity- implanted region of the first active region ACT1 via a lower contact plug. Thus, a source region of the memory cell transistor can be electrically connected to the bit line BL via the bit line contact plug DC, and a drain region of the memory cell transistor can be electrically connected to the bottom electrode BE of the capacitor via the landing pad LP and the lower contact plug.

[0055] The word line WL, the bit line BL, the bit line contact plug DC, and the landing pad LP can be formed of various conductive materials.

[0056] The capacitor coupled to the landing pad LP can include the bottom electrode BE, the dielectric layer DL, and the upper electrode UE.

[0057] The bottom electrode BE can be formed of various conductive materials. The bottom electrode BE can be coupled to the landing pad LP in various shapes. In an embodiment, the bottom electrode BE can be formed in a column shape. Although not shown in the figure, in an embodiment, the bottom electrode BE can be formed in a cylindrical shape. The first support pattern SP1 and the second support pattern SP2 can be disposed on one side of the bottom electrode BE. The first support pattern SP1 and the second support pattern SP2 can be disposed at different distances from the wafer 101 and spaced apart from each other. The bottom electrode BE can be spaced apart from another bottom electrode BE by the first support pattern SP1 and the second support pattern SP2. The first support pattern SP1 and the second support pattern SP2 can include an insulating material such as silicon oxide.

[0058] The dielectric layer DL can extend along a surface of each of the first support pattern SP1 and the second support pattern SP2 and a surface of the bottom electrode BE that does not contact the first support pattern SP1 and the second support pattern SP2. The dielectric layer DL can include an oxide, a nitride, an oxynitride, or a silicon oxynitride. The dielectric layer DL can include a metal such as hafnium, aluminum, zirconium, or lanthanum.

[0059] The upper electrode UE can include a first conductive layer L1 and a second conductive layer L2. The first conductive layer L1 can be a metal nitride layer such as a titanium nitride layer. The second conductive layer L2 can include a doped semiconductor layer such as a doped silicon layer or a metal layer such as tungsten.

[0060] The transistor TR forming the peripheral circuit can be formed in the peripheral circuit region PER of the wafer 101. The transistor TR includes a gate insulating layer GI2, a gate electrode GE, and a second impurity implantation region I2. The gate insulating layer GI2 and the gate electrode GE are layered over the second active region ACT2. The gate insulating layer GI2 and the gate electrode GE can be embedded in the first lower insulating structure 103. The second impurity implantation region I2 can be provided in the second active region ACT2 on one side and the other side of the gate electrode GE, and can function as a source region and a drain region.

[0061] The second lower insulating structure 105 and the third lower insulating structure 107 can extend onto the peripheral circuit region PER of the wafer 101 to cover the transistor TR and the first lower insulating structure 103. The transistor TR can be coupled to a conductive pattern of the lower interconnection structure IC that penetrates one or more of the first lower insulating structure 103, the second lower insulating structure 105, and the third lower insulating structure 107.

[0062] The upper electrode UE and the lower interconnection structure IC can be covered with a first insulating layer 111. A second insulating layer 121, a third insulating layer 131, a fourth insulating layer 141, and a fifth insulating layer 151 can be layered over the first insulating layer 111.

[0063] First contact plugs 113C1 and 113C2 can be provided in the first insulating layer 111. The first contact plugs 113C1 and 113C2 can include a first cell contact plug 113C1 electrically connected to the upper electrode UE and a first peripheral contact plug 113C2 electrically connected to the lower interconnection structure IC.

[0064] First conductive lines 123L and a first conductive pad 123P can be provided in the second insulating layer 121. The first conductive lines 123L can be coupled to the first cell contact plug 113C1, and the first conductive pad 123P can be coupled to the first peripheral contact plug 113C2.

[0065] Second contact plugs 133C1 and 133C2 can be provided in the third insulating layer 131. The second contact plugs 133C1 and 133C2 can include a second cell contact plug 133C1 electrically connected to the first conductive lines 123L and a second peripheral contact plug 133C2 electrically connected to the first conductive pad 123P.

[0066] Second conductive lines 143L and a second conductive pad 143P can be provided in the fourth insulating layer 141. The second conductive lines 143L can be coupled to the second cell contact plug 133C1, and the second conductive pad 143P can be coupled to the second peripheral contact plug 133C2.

[0067] The third contact plugs 153C1 and 153C2 can be disposed in the fifth insulating layer 151. The third contact plugs 153C1 and 153C2 can include a third cell contact plug 153C1 electrically connected to the second conductive line 143L and a third peripheral contact plug 153C2 electrically connected to the second conductive pad 143P.

[0068] The alignment of the first contact plugs 113C1 and 113C2, the first conductive line 123L, the first conductive pad 123P, the second contact plugs 133C1 and 133C2, the second conductive line 143L, the second conductive pad 143P, and the third contact plugs 153C1 and 153C2 described above can be determined by measuring Figure 5B the overlay marks OV1 or OV2 shown above the scribe lane region SR of the wafer 101.

[0069] Referring to Figure 5B , the layout of each of the first overlay mark OV1 and the second overlay mark OV2 can be substantially the same as the layout of the overlay mark OV shown in Figure 3 . Figure 5B Cross-sectional views of the first overlay mark OV1 and the second overlay mark OV2 taken along lines C1-C1’ are shown. Figure 3

[0070] Each of the first overlay mark OV1 and the second overlay mark OV2 can be provided with a plurality of dummy patterns 133D interposed therebetween. The layout of the plurality of dummy patterns 133D can be substantially the same as the layout of the plurality of dummy patterns shown in Figure 3 .

[0071] Figure 5A The first lower insulating structure 103, the second lower insulating structure 105, the third lower insulating structure 107, the first insulating layer 111, the second insulating layer 121, the third insulating layer 131, the fourth insulating layer 141, and the fifth insulating layer 151 shown in

[0072] The plurality of first downstream marker patterns 113V1 of the first overlay mark OV1 can overlap the scribe lane region SR of the wafer 101 in the third direction DR3 and can be disposed in the first insulating layer 111. The plurality of first downstream marker patterns 113V1 can be disposed above the third lower insulating structure 107. The plurality of second downstream marker patterns 123V2 of the first overlay mark OV1 can overlap the scribe lane region SR in the third direction DR3 and can be disposed in the second insulating layer 121.

[0073] The plurality of dummy patterns 133D can overlap the scribe lane region SR of the wafer 101 in the third direction DR3 and can be disposed in the third insulating layer 131. ​

[0074] The plurality of first upstream vernier patterns 143V1 of the second overlay mark OV2 can overlap the scribe line region SR of the wafer 101 in the third direction DR3, and can be disposed in the fourth insulating layer 141. The plurality of second upstream vernier patterns 153V2 of the second overlay mark OV2 can overlap the scribe line region SR of the wafer 101 in the third direction DR3, and can be disposed in the fifth insulating layer 151.

[0075] Referring to Figure 5A and Figure 5B The plurality of first downstream vernier patterns 113V1 can be formed using a process of forming the first contact plugs 113C1 and 113C2, and can include the same conductive material as the first contact plugs 113C1 and 113C2. The plurality of second downstream vernier patterns 123V2 can be formed using a process of forming the first conductive lines 123L and the first conductive pads 123P, and can include the same conductive material as the first conductive lines 123L and the first conductive pads 123P. In the third direction DR3, the plurality of second downstream vernier patterns 123V2 can not overlap the plurality of first downstream vernier patterns 113V1, but can overlap the first insulating layer 111.

[0076] The plurality of dummy patterns 133D can be formed using a process of forming the second contact plugs 133C1 and 133C2, and can include the same conductive material as the second contact plugs 133C1 and 133C2. In an embodiment, the plurality of dummy patterns 133D can function as a dish defect prevention structure while a planarization process is performed so that the third insulating layer 131 is exposed.

[0077] The plurality of first upstream vernier patterns 143V1 can be formed using a process of forming the second conductive lines 143L and the second conductive pads 143P, and can include the same conductive material as the second conductive lines 143L and the second conductive pads 143P. The plurality of second upstream vernier patterns 153V2 can be formed using a process of forming the third contact plugs 153C1 and 153C2, and can include the same conductive material as the third contact plugs 153C1 and 153C2. In the third direction DR3, the plurality of second upstream vernier patterns 153V2 can not overlap the plurality of first upstream vernier patterns 143V1, but can overlap the fourth insulating layer 141.

[0078] Figure 6 is a plan view illustrating an overlay mark and a plurality of dummy patterns disposed in a scribe line region of a semiconductor device according to an embodiment of the disclosure.

[0079] Referring to Figure 6 As described with reference to Figure 3 , the overlay mark OV can include a plurality of first vernier patterns V1 and a plurality of second vernier patterns V2.

[0080] In a plan view, the plurality of dummy patterns 133D' can be arranged to be spaced apart from each other in the first direction DR1 and the second direction DR2. In the third direction DR3, a portion of each of the dummy patterns 133D' can overlap the overlap mark OV, and another portion can not overlap the overlap mark OV.

[0081] Figure 7A 、 Figure 7B and Figure 7C is a cross-sectional view taken along line A2-A2', line B2-B2', and line C2-C2' shown in Figure 6 of the semiconductor device according to the embodiment of the present disclosure.

[0082] Referring to Figure 6 、 Figure 7A 、 Figure 7B and Figure 7C , the overlap mark OV can be a first overlap mark OV1 disposed below the plurality of dummy patterns 133D'. The plurality of first vernier patterns V1 can be a plurality of first lower vernier patterns 113V1 of the first overlap mark OV1, and the plurality of second vernier patterns V2 can be a plurality of second lower vernier patterns 123V2 of the first overlap mark OV1.

[0083] The first insulating layer 111, the second insulating layer 121, the third insulating layer 131, the fourth insulating layer 141, and the fifth insulating layer 151 can extend to overlap the scribe line region SR of the wafer 101.

[0084] As described with reference to Figure 4A 、 Figure 4B and Figure 4C , the plurality of first lower vernier patterns 113V1 can be disposed in the first insulating layer 111 and can include the same conductive material as the first contact plug 113C shown in Figure 2 . As described with reference to Figure 4A 、 Figure 4B and Figure 4C , the plurality of second lower vernier patterns 123V2 can be disposed in the second insulating layer 121 and can include the same conductive material as the first wire 123L shown in Figure 2 . As described with reference to Figure 4A 、 Figure 4B and Figure 4C , the alignment between the plurality of first lower vernier patterns 113V1 and the plurality of second lower vernier patterns 123V2 can be measured based on detection signals for the plurality of first lower vernier patterns 113V1 and the plurality of second lower vernier patterns 123V2, and the alignment between the first contact plug 113C and the first wire 123L shown in Figure 2 can be determined.

[0085] The plurality of dummy patterns 133D' can overlap the scribe lane region SR in the third direction DR3, and can be provided in the third insulating layer 131. The plurality of dummy patterns 133D' can include the same conductive material as the second contact plug 133C illustrated. Figure 2 In a plan view, each dummy pattern 133D' can be formed with a wider width than each first downstream mark pattern 113V1 or each second downstream mark pattern 123V2. In this case, a separate overlap mark can not be superimposed on the dummy pattern 133D', and the overlap mark corresponding to the second wire 143L and the third contact plug 153C illustrated can be provided in a separate region (not illustrated) that does not overlap the region of the first overlap mark OV1 and the dummy pattern 133D'. Thus, in embodiments, because it is possible to prevent or mitigate distortion of a detection signal for the overlap mark corresponding to the second wire 143L and the third contact plug 153C due to the dummy pattern 133D', it is possible to ensure stability of the manufacturing process of the semiconductor device. Figure 2

[0086] In embodiments, the plurality of dummy patterns 133D' can overlap the first overlap mark OV1 and function as a dish defect suppression structure, thereby reducing the area of the scribe lane region SR allocated to the dish defect suppression structure. In embodiments, because no other overlap mark is disposed on the dummy pattern 133D', the plurality of dummy patterns 133D' can be covered with the fourth insulating layer 141 and the fifth insulating layer 151. For example, the top surface of the plurality of dummy patterns 133D' is not blocked by other overlap marks and overlaps each of the fourth insulating layer 141 and the fifth insulating layer 151 in the third direction DR3. In embodiments, the top surface of the plurality of dummy patterns 133D' can be completely covered with each of the fourth insulating layer 141 and the fifth insulating layer 151.

[0087] Figure 8 is a cross-sectional view illustrating an overlap mark and a plurality of dummy patterns provided in a scribe lane region of a semiconductor device according to embodiments of the present disclosure. Figure 8 is a cross-sectional view of a semiconductor device taken along Figure 6 the line C2-C2' illustrated.

[0088] Referring to Figure 6 and Figure 8 as described above with reference to Figure 7A , Figure 7B and Figure 7C ​The first insulating layer 111, the second insulating layer 121, the third insulating layer 131, the fourth insulating layer 141, and the fifth insulating layer 151 can overlap with the scribe line region SR of the wafer 101, and a first downstream mark pattern 113V1 of the first overlap mark OV1 can be provided in the first insulating layer 111, and a second downstream mark pattern 123V2 of the first overlap mark OV1 can be provided in the second insulating layer 121, and a dummy pattern 133D' can be provided in the third insulating layer 131.

[0089] The semiconductor device can include a plurality of first upper dummy patterns 143D' or a plurality of second upper dummy patterns 153D', or can include both a plurality of first upper dummy patterns 143D' and a plurality of second upper dummy patterns 153D'. In an embodiment, the plurality of first upper dummy patterns 143D' can function as a dish-shaped defect suppression structure, and can be provided in the fourth insulating layer 141. The plurality of second upper dummy patterns 153D' can function as another dish-shaped defect suppression structure, and can be provided in the fifth insulating layer 151.

[0090] In an embodiment, by arranging dummy patterns in a plurality of layers as described above, a planar area of a scribe line region allocated to a dish-shaped defect suppression structure can be reduced during manufacturing of a semiconductor device.

[0091] Hereinafter, a manufacturing process performed in a scribe line region of a semiconductor device according to an embodiment of the disclosure will be described.

[0092] Figure 9A and Figure 9B is a plan view illustrating a first overlap mark according to an embodiment of the disclosure.

[0093] Referring to Figure 9A The first insulating layer 111 can be formed over a substructure including the wafer. Subsequently, a portion of the first insulating layer 111 can be etched to form a plurality of first recessed regions. Thereafter, the plurality of first recessed regions can be filled with a conductive material, and the conductive material can be separated into a plurality of first downstream mark patterns 113V1 by a planarization process.

[0094] Referring to Figure 9B The second insulating layer 121 can be formed to cover the plurality of first downstream mark patterns 113V1. Thereafter, a portion of the second insulating layer 121 can be etched to form a plurality of second recessed regions. Subsequently, the plurality of second recessed regions can be filled with a conductive material, and the conductive material can be separated into a plurality of second downstream mark patterns 123V2 by a planarization process.

[0095] Thereafter, the alignment between the plurality of first downstream marker patterns 113V1 and the plurality of second downstream marker patterns 123V2 can be measured using the first overlay mark OV1 including the first downstream marker pattern 113V1 and the second downstream marker pattern 123V2.

[0096] Figure 10A , Figure 10B and Figure 10C are plan views illustrating a plurality of dummy patterns and a second overlay mark according to an embodiment of the disclosure.

[0097] Referring to Figure 10A , the third insulating layer 131 can be formed to cover the first overlay mark OV1 described with reference to Figure 9B Subsequently, a portion of the third insulating layer 131 can be etched to form a plurality of third recessed regions. The plurality of third recessed regions can respectively overlap the plurality of first downstream marker patterns 113V1 and the plurality of second downstream marker patterns 123V2, and each third recessed region can be formed to have a smaller area than each first downstream marker pattern 113V1 or each second downstream marker pattern 123V2. Thereafter, the plurality of third recessed regions can be filled with a conductive material, and the conductive material can be separated into a plurality of dummy patterns 133D through a planarization process.

[0098] In an embodiment, the plurality of dummy patterns 133D can function as a dish-shaped defect suppression pattern. In an embodiment, because the plurality of dummy patterns 133D are formed after the measurement process using the first overlay mark OV1, the dummy patterns 133D do not affect the measurement process using the first overlay mark OV1.

[0099] Referring to Figure 10B , the fourth insulating layer 141 can be formed to cover the plurality of dummy patterns 133D. Subsequently, a portion of the fourth insulating layer 141 can be etched to form a plurality of fourth recessed regions. The plurality of fourth recessed regions can overlap some of the plurality of dummy patterns 133D and the plurality of first downstream marker patterns 113V1 as illustrated in FIG. 13B. Each fourth recessed region can be formed to have a larger area than each dummy pattern 133D. Each fourth recessed region can be formed to have substantially the same area as the first downstream marker pattern 113V1 as illustrated in FIG. 13B, or can be formed to have a larger area than the first downstream marker pattern 113V1 as illustrated in FIG. 13B. Subsequently, the plurality of fourth recessed regions can be filled with a conductive material, and the conductive material can be separated into a plurality of first upstream marker patterns 143V1 through a planarization process. Figure 10A Figure 10A Figure 10A

[0100] Referring to Figure 10C ​​​The fifth insulating layer 151 can be formed to cover a plurality of first swashplate patterns 143V1. Subsequently, a portion of the fifth insulating layer 151 can be etched to form a plurality of fifth recessed regions. The plurality of fifth recessed regions can then be filled with a conductive material, and the conductive material can be separated into a plurality of second swashplate patterns 153V2 by a planarization process.

[0101] Subsequently, a second overlapping mark OV2, comprising a first upstream marker pattern 143V1 and a second upstream marker pattern 153V2, can be used to measure the alignment between the plurality of first upstream marker patterns 143V1 and the plurality of second upstream marker patterns 153V2.

[0102] References can be used Figures 10A to 10C The process described is used to set up Figure 3 , Figure 4A , Figure 4B and Figure 4C The semiconductor device shown or Figure 5A and Figure 5B The semiconductor device shown.

[0103] Figure 11 This is a plan view illustrating a first overlapping mark and a plurality of dummy patterns according to an embodiment of the present disclosure.

[0104] Reference Figure 11 The third insulating layer 131 can be formed to cover the reference. Figure 9B The first overlapping mark OV1 is described. Subsequently, a portion of the third insulating layer 131 can be etched to form a plurality of third recessed regions. The plurality of third recessed regions may overlap with a plurality of first downstream marker patterns 113V1 and a plurality of second downstream marker patterns 123V2, respectively. Each third recessed region may have a width wider than the width of each first downstream marker pattern 113V1 or each second downstream marker pattern 123V2. In an embodiment, each of the first downstream marker pattern 113V1 and the second downstream marker pattern 123V2 may be formed as a rectangle, and the third recessed region may be formed as a square having a width wider than the shorter side of the rectangle. However, embodiments of this disclosure are not limited thereto. Subsequently, the plurality of third recessed regions may be filled with a conductive material, and the conductive material may be separated into a plurality of dummy patterns 133D' by a planarization process.

[0105] In this embodiment, the plurality of dummy patterns 133D' can be used as disc-shaped defect suppression patterns. In this embodiment, since the plurality of dummy patterns 133D' are formed after the measurement process using the first overlap mark OV1, the dummy patterns 133D' do not affect the measurement process using the first overlap mark OV1.

[0106] Figure 12is a plan view illustrating an insulating layer over a plurality of dummy patterns according to an embodiment of the present disclosure.

[0107] Referring to Figure 12 , the insulating layer can be laminated to cover Figure 11 the plurality of dummy patterns 133D'. The insulating layer can include Figures 7A to 7C a fourth insulating layer 141 and a fifth insulating layer 151 as illustrated. As described with reference to Figures 7A to 7C , each of the fourth insulating layer 141 and the fifth insulating layer 151 can be formed to cover the plurality of dummy patterns 133D'. In an embodiment, a top surface of the plurality of dummy patterns 133D' can be completely covered with each of the fourth insulating layer 141 and the fifth insulating layer 151.

[0108] Figure 13A and Figure 13B is a plan view illustrating a multilayer dummy pattern according to an embodiment of the present disclosure.

[0109] Referring to Figure 13A , the fourth insulating layer 141 can be formed to cover Figure 11 the plurality of dummy patterns 133D'. Thereafter, a portion of the fourth insulating layer 141 can be etched to form a plurality of fourth recessed areas. The plurality of fourth recessed areas can overlap the plurality of dummy patterns 133D' and can be formed in a shape different from the plurality of dummy patterns 133D'. Subsequently, the plurality of fourth recessed areas can be filled with a conductive material, and the conductive material can be separated into a plurality of first upper dummy patterns 143D' through a planarization process. In an embodiment, the plurality of first upper dummy patterns 143D' can function as a dish-shaped defect inhibition pattern.

[0110] Referring to Figure 13B , the fifth insulating layer 151 can be formed to cover the plurality of first upper dummy patterns 143D'. Thereafter, a portion of the fifth insulating layer 151 can be etched to form a plurality of fifth recessed areas. The plurality of fifth recessed areas can overlap the plurality of first upper dummy patterns 143D' and can be formed in a shape different from the plurality of first upper dummy patterns 143D'. Subsequently, the plurality of fifth recessed areas can be filled with a conductive material, and the conductive material can be separated into a plurality of second upper dummy patterns 153D' through a planarization process. In an embodiment, the plurality of second upper dummy patterns 153D' can function as a dish-shaped defect inhibition pattern.

[0111] The semiconductor device illustrated in Figure 13A and Figure 13B can be provided using the processes described with reference to Figure 8 .

[0112] According to embodiments of the disclosure, because the alignment between the patterns in the chip region is determined using the overlay marks including the plurality of downstream marker patterns and then the plurality of dummy patterns is formed, the measurement signal from the downstream marker patterns can avoid interference from the plurality of dummy patterns. Accordingly, in embodiments, the accuracy of the alignment monitoring can be enhanced, and the stability of the manufacturing process of the semiconductor device can be ensured.

[0113] According to embodiments of the disclosure, because the plurality of dummy patterns overlap with the plurality of downstream marker patterns, the arrangement efficiency of the patterns disposed in the scribe lane region can be improved, and the integration of the patterns disposed in the scribe lane region can be increased.

[0114] According to embodiments of the disclosure, because the plurality of dummy patterns can function as a donut defect prevention structure and overlap with the plurality of downstream marker patterns, the planar area occupied by the patterns disposed in the scribe lane region can be reduced while ensuring the stability of the manufacturing process.

[0115] CROSS-REFERENCE TO RELATED APPLICATIONS

[0116] This application claims priority to Korean Patent Application No. 10-2024-0129099, filed on September 24, 2024, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.

Claims

1. A semiconductor device comprising: a wafer including a chip region and a scribe lane region surrounding the chip region, a surface of the wafer extending in a plane of a first direction and a second direction; a first insulating layer, a second insulating layer, and a third insulating layer stacked in a third direction over the surface of the wafer in order; a first overlay mark including a plurality of downstream bar patterns provided in the first insulating layer and the second insulating layer and overlapping the scribe lane region of the wafer in the third direction; and a plurality of dummy patterns provided in the third insulating layer and overlapping the scribe lane region of the wafer in the third direction, wherein each of the plurality of dummy patterns is formed with a first area measured in the first direction and the second direction, wherein each of the plurality of downstream bar patterns is formed with a second area measured in the first direction and the second direction, and wherein the first area of each of the plurality of dummy patterns is smaller than the second area of each of the plurality of downstream bar patterns. the plurality of downstream bar patterns includes:

2. The semiconductor device according to claim 1, wherein a plurality of first downstream bar patterns provided in the first insulating layer; and a plurality of second downstream bar patterns provided in the second insulating layer and in a region within the second insulating layer that does not overlap the plurality of first downstream bar patterns in the third direction.

3. The semiconductor device according to claim 2, further comprising: a first contact plug provided in the first insulating layer and overlapping the chip region of the wafer in the third direction; a wire provided in the second insulating layer and overlapping the chip region of the wafer in the third direction; and a second contact plug provided in the third insulating layer and overlapping the chip region of the wafer in the third direction, wherein the plurality of first downstream bar patterns include substantially the same conductive material as the first contact plug, wherein the plurality of second downstream bar patterns include substantially the same conductive material as the wire, and wherein the plurality of dummy patterns include substantially the same conductive material as the second contact plug. the plurality of dummy patterns overlap the plurality of first downstream bar patterns and the plurality of second downstream bar patterns in the third direction.

5. The semiconductor device according to claim 1, further comprising:

4. The semiconductor device according to claim 2, wherein a fourth insulating layer and a fifth insulating layer stacked in the third direction over the third insulating layer in order; and a fourth contact plug provided in the fourth insulating layer and overlapping the chip region of the wafer in the third direction. ​ ​ a second overlay mark including a plurality of upstream mark patterns provided in the fourth insulating layer and the fifth insulating layer and overlapping the scribe line region of the wafer in the third direction, wherein each of the plurality of upstream mark patterns is formed with a third area measured in the first direction and the second direction, and wherein the first area of each of the plurality of dummy patterns is smaller than the third area of each of the plurality of upstream mark patterns.

6. The semiconductor device according to claim 5, wherein The plurality of upstream mark patterns overlaps the plurality of downstream mark patterns in the third direction.

7. The semiconductor device according to claim 5, wherein The plurality of upstream mark patterns includes: a plurality of first upstream mark patterns provided in the fourth insulating layer; and a plurality of second upstream mark patterns provided in the fourth insulating layer and in a region within the fourth insulating layer that does not overlap the plurality of first upstream mark patterns in the third direction.

8. The semiconductor device according to claim 7, further comprising: a wire provided in the fourth insulating layer and overlapping the chip region of the wafer in the third direction; and a contact plug provided in the fifth insulating layer and overlapping the chip region in the third direction, wherein the plurality of first upstream mark patterns include substantially the same conductive material as the wire, and wherein the plurality of second upstream mark patterns include substantially the same conductive material as the contact plug.

9. The semiconductor device according to claim 7, wherein The plurality of first upstream mark patterns and the plurality of second upstream mark patterns overlap the plurality of dummy patterns in the third direction.

10. The semiconductor device according to claim 1, wherein The plurality of dummy patterns form a dish-shaped defect suppression structure.

11. A semiconductor device comprising: a wafer including a chip region and a scribe line region surrounding the chip region, a surface of the wafer extending in a plane of a first direction and a second direction; a first insulating layer, a second insulating layer, a third insulating layer, a fourth insulating layer, and a fifth insulating layer stacked in a third direction in order over the surface of the wafer; a plurality of dummy patterns provided in the third insulating layer and overlapping the scribe line region in the third direction; and an overlay mark overlapping the scribe line region of the wafer in the third direction, wherein the overlay mark is not provided in a region within each of the fourth insulating layer and the fifth insulating layer that overlaps the plurality of dummy patterns in the third direction, and wherein the overlay mark includes a plurality of downstream mark patterns provided in the first insulating layer and the second insulating layer.

12. The semiconductor device according to claim 11, wherein The plurality of downstream mark patterns includes: a plurality of first downstream mark patterns provided in the first insulating layer; and a plurality of second downstream mark patterns provided in the second insulating layer and in a region within the second insulating layer that does not overlap the plurality of first downstream mark patterns in the third direction. a plurality of second downstream marker patterns disposed in the second insulating layer and in regions of the second insulating layer that do not overlap the plurality of first downstream marker patterns in the third direction.

13. The semiconductor device of claim 12, further comprising: a first contact plug disposed in the first insulating layer and overlapping the chip region of the wafer in the third direction; a wire disposed in the second insulating layer and overlapping the chip region of the wafer in the third direction; and a second contact plug disposed in the third insulating layer and overlapping the chip region of the wafer in the third direction, wherein the plurality of first downstream marker patterns comprise substantially the same conductive material as the first contact plug, wherein the plurality of second downstream marker patterns comprise substantially the same conductive material as the wire, and wherein the plurality of dummy patterns comprise substantially the same conductive material as the second contact plug.

14. The semiconductor device according to claim 12, wherein The plurality of dummy patterns overlap the plurality of first downstream marker patterns and the plurality of second downstream marker patterns in the third direction.

15. The semiconductor device according to claim 11, wherein The plurality of dummy patterns are covered with the fourth insulating layer and the fifth insulating layer.

16. The semiconductor device of claim 11, further comprising: a wire disposed in the fourth insulating layer and overlapping the chip region of the wafer in the third direction; and a contact plug disposed in the fifth insulating layer and overlapping the chip region of the wafer in the third direction.

17. The semiconductor device of claim 16, further comprising: a plurality of first upper dummy patterns disposed in a region of the fourth insulating layer that overlaps the overlap marker in the third direction and comprising substantially the same conductive material as the wire.

18. The semiconductor device of claim 16, further comprising: a plurality of second upper dummy patterns disposed in a region of the fifth insulating layer that overlaps the overlap marker in the third direction and comprising substantially the same conductive material as the contact plug.

19. The semiconductor device according to claim 11, wherein The plurality of dummy patterns form a dish defect suppression structure.

20. A semiconductor device, comprising: a wafer comprising a chip region and a scribe lane region surrounding the chip region, a surface of the wafer extending in a plane of a first direction and a second direction; a first insulating layer, a second insulating layer, and a third insulating layer stacked in a third direction over the surface of the wafer in order; an overlap marker comprising a plurality of downstream marker patterns disposed in the first insulating layer and the second insulating layer and overlapping the scribe lane region of the wafer in the third direction; and a plurality of dummy patterns disposed in the third insulating layer and overlapping the chip region of the wafer in the third direction. A disc-shaped defect suppression structure includes a plurality of dummy patterns provided in the third insulating layer, the dummy patterns overlapping the scribe lane region of the wafer in the third direction, wherein the plurality of dummy patterns overlap the plurality of downstream mark patterns in the third direction.

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