Configuring memory cells

Abstract

An apparatus may include a first inverter, a second inverter, a first access transistor, and a second access transistor. The first and second inverters may be cross-coupled between a first node and a second node to store signal states represented by voltage values at the first and second nodes. The first inverter and the second inverter may be configured to reliably operate at a higher voltage condition than a positive supply voltage of the apparatus. The first access transistor may selectively couple the first node to a bit line and allow direct control of the first node during an access operation. The second access transistor may selectively couple the second node to the bit line and allow direct control of the second node during an access operation. Respective positive supply inputs of the first inverter and the second inverter may be coupled to a voltage supply associated with a higher voltage level than a positive supply voltage of the device.

Description

[0001] Cross-reference to related applications

[0002] This application claims the benefit of U.S. Provisional Patent Application Serial No. 63 / 580,339, filed September 1, 2023, pursuant to 35 USC §119(e), the disclosure of which is incorporated herein by reference in its entirety. Background Technology

[0003] Storage elements (e.g., volatile storage elements, but not limited thereto) are used in a variety of operating environments. Attached Figure Description

[0004] To facilitate the identification of any particular element or action in the discussion, the most important number in the figure labels refers to the figure number of the element when it was first introduced.

[0005] Figure 1 It is a schematic diagram depicting the layout of a memory cell designed to be unaffected by SEU when operating in the high voltage (HV) domain, according to one or more examples.

[0006] Figure 2 This is a schematic diagram of a memory cell that provides SEU immunity when operating in the high voltage (HV) domain, based on one or more examples.

[0007] Figure 3 This is a schematic diagram of a memory cell that provides SEU immunity when operating in the high voltage (HV) domain, based on one or more examples.

[0008] Figure 4 It is a block diagram depicting a memory system including memory cells and their associated driver circuitry.

[0009] Figure 5 It describes the configuration of a memory cell or system based on one or more examples (such as...) Figure 1 memory cells, Figure 2 memory cells, Figure 3 memory cells or Figure 4 The voltage bias and status table of the operating state of the memory system.

[0010] Figure 6 An exemplary procedure for a two-stage write logic low value (“0”) operation to the exemplary memory cell discussed herein is illustrated according to one or more examples.

[0011] Figure 7 An exemplary procedure for a two-stage write logic high value (“1”) operation to an exemplary memory cell discussed herein is illustrated according to one or more examples.

[0012] Figure 8 It is a block diagram of a circuit that can be used in some examples to implement the various functions, operations, actions, processes or methods disclosed herein. Detailed Implementation

[0013] In the following detailed description, reference is made to the accompanying drawings, which form part of this disclosure, and specific examples of embodiments in which this disclosure may be practiced are shown by way of example. These embodiments have been described in sufficient detail to enable those skilled in the art to practice this disclosure. However, other embodiments may be utilized, and changes in structure, materials, and processes may be made without departing from the scope of this disclosure.

[0014] The illustrations presented herein are not intended to be actual views of any particular method, system, device, or structure, but are merely idealized representations used to describe embodiments of this disclosure. The figures presented herein are not necessarily drawn to scale. For the reader's convenience, similar structures or components in the figures may retain the same or similar designations; however, similar designations do not imply that the structure or component must be identical in size, composition, configuration, or any other attribute.

[0015] The following description may include examples to assist those skilled in the art in practicing the embodiments disclosed herein. The use of the terms “exemplary,” “by example,” and “for example” indicates that the related descriptions are illustrative, and while the scope of this disclosure is intended to cover examples and legal equivalents, the use of such terms is not intended to limit the embodiments or the scope of this disclosure to the specified parts, steps, features, or functions, etc.

[0016] It should be readily understood that the components of the embodiments generally described herein and illustrated in the accompanying drawings can be arranged and designed in a variety of different configurations. Therefore, the following description of various embodiments is not intended to limit the scope of this disclosure, but rather to represent various embodiments only. While various aspects of the embodiments may be presented in the accompanying drawings, the drawings are not necessarily drawn to scale unless specifically indicated otherwise.

[0017] Furthermore, the specific embodiments shown and described are merely examples and should not be construed as the only way to implement this disclosure unless otherwise indicated herein. Components, circuits, and functions may be shown in block diagram form so as not to obscure this disclosure with unnecessary detail. Rather, the specific embodiments shown and described are merely exemplary and should not be construed as the only way to implement this disclosure unless otherwise indicated herein. Additionally, block definitions and logical partitioning between blocks are examples of specific embodiments. It will be apparent to those skilled in the art that this disclosure can be practiced with many other partitioning solutions. In most cases, details regarding timing considerations, etc., have been omitted, as such details are not necessary for obtaining a full understanding of this disclosure and are within the capabilities of those skilled in the art.

[0018] Those skilled in the art will understand that information and signals can be represented using any of a variety of different techniques and methods. For clarity of presentation and description, some figures may illustrate a signal as a single signal. It should be understood by those skilled in the art that a signal may represent a signal bus, wherein the bus may have multiple bit widths, and this disclosure can be implemented on any number of data signals, including a single data signal.

[0019] The various exemplary logic blocks, modules, and circuits described in connection with the embodiments disclosed herein may be implemented or executed using a general-purpose processor, a special-purpose processor, a digital signal processor (DSP), an integrated circuit (IC), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic components, discrete hardware components, or any combination thereof designed to implement the functions described herein. A general-purpose processor (which may also be referred to herein as a host processor or simply host) may be a microprocessor, but in alternative embodiments, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration. When a general-purpose computer including a processor executes computational instructions (e.g., software code) related to the embodiments of this disclosure, the general-purpose computer is considered a special-purpose computer.

[0020] The implementation scheme can be described based on a process depicted as a flowchart, schematic diagram, structural diagram, or block diagram. While a flowchart can describe operable actions as a continuous process, many of these actions can be performed in another sequence, in parallel, or substantially simultaneously. Furthermore, the order of actions can be rearranged. A process can correspond to a method, thread, function, procedure, subroutine, or subroutine, but is not limited thereto. Furthermore, the methods disclosed herein can be implemented in hardware, software, or both. If implemented in software, functions can be stored or transmitted as one or more instructions or code onto a computer-readable medium. Computer-readable media includes both computer storage media and communication media, including any medium that facilitates the transfer of a computer program from one location to another.

[0021] Any reference to elements in this document using names such as “first”, “second”, etc., does not limit the number or order of those elements unless such limitation is explicitly stated. Rather, these names may be used herein as a convenient way to distinguish between two or more elements or instances of elements. Thus, referring to a first element and a second element does not imply that only two elements can be used there, or that the first element must somehow precede the second element. Furthermore, unless otherwise stated, a group of elements may include one or more elements.

[0022] As used herein, the term “substantially” means, and includes, the degree to which a given parameter, attribute, or condition is satisfied with a small degree of variance, such as, for example, within acceptable manufacturing tolerances, as would be understood by one of ordinary skill in the art. By way of example, depending on the particular parameter, attribute, or condition that is substantially satisfied, the parameter, attribute, or condition may be satisfied at least 90%, at least 95%, or even at least 99%.

[0023] As used herein, any relational terms (such as "above", "below", "on", "under", "upper", "lower", etc., but not limited thereto) are used for clarity and convenience in understanding this disclosure and the accompanying drawings, and such relational terms do not imply or depend on any particular preference, orientation or order unless the context clearly indicates otherwise.

[0024] In this description, the term "coupled" and its derivatives may be used to indicate that two elements cooperate or interact with each other. When an element is described as "coupled" to another element, then the element may be in direct physical or electrical contact, or there may be an intermediary element or layer. In contrast, when an element is described as "directly coupled" to another element, then there is no intermediary element or layer. The term "connection" is used interchangeably with the term "coupled" in this specification and has the same meaning unless otherwise expressly indicated or the context will otherwise indicate to a person skilled in the art.

[0025] A "volatile memory cell" is a data storage device that requires continuous power to maintain the information stored within it. A volatile memory cell represents information through its state (e.g., charged or not charged, high voltage or low voltage, but not limited to these), and requires continuous power to maintain its state. If the power supply to the cell is interrupted or turned off, the volatile memory cell loses its state and the information stored in it is lost.

[0026] Examples of volatile memory cells include, but are not limited to, latch circuits, flip-flop circuits, and circuits including cross-coupled inverters. Some field-programmable gate arrays (FPGAs) include configuration memory cells that include volatile memory cells. Additionally, static random access memory (SRAM) cells include volatile memory cells.

[0027] The terms "memory cell" and "volatile memory cell" are used interchangeably herein to refer to "volatile memory cell". When used in FPGAs, the example memory cell discussed herein may be referred to as a "configuration memory cell" or simply as a "configuration cell".

[0028] Due to stress limitations and the specific internal connections of transistors, traditional configuration memory cells used in FPGAs cannot be written to or read from when powered on in a high-voltage domain (a voltage condition higher than the positive supply voltage). In some cases, the traditional configuration memory cell powered by the high-voltage supply is powered off, powered on with a lower voltage supply, various access operations are performed, the configuration memory cell is powered off again, and then powered on again with a higher voltage supply. Power-off and power-on consume power and degrade performance. Here, "positive supply voltage" refers to the standard positive supply voltage (e.g., VDD, but not limited to) used to represent a standard logic high level (logic "1") for low-voltage components. Non-limiting examples of voltage levels for VDD include 1.2V logic, 1.8V logic, 2.5V logic, 3.3V logic, and 5V logic.

[0029] As a non-limiting example, an FPGA can use 1.2V VDD for the standard logic level of low-voltage components and 9V positive high voltage (VPHV) for programming or configuration operations.

[0030] One or more examples generally involve a configuration unit and a field-programmable gate array (FPGA) that includes the configuration unit. The configuration unit is designed to withstand a single-event switching (SEU) in a high-voltage (HV) environment. Such a configuration unit can be used in a field-programmable gate array (FPGA) where SEUs can cause significant reliability issues.

[0031] In one or more examples, the access point of the configuration cell is modified and additional word lines (WL) are included, compared to the traditional configuration cell used in FPGAs, so that the configuration cell can be written to and read from at high voltages without exposing any individual device to excessive stress that could lead to a SEU.

[0032] In one or more examples, such memory cells of a memory device or system or FPGA can be directly accessed for a constant amount of time without having to access other memory cells.

[0033] Figure 1 It is a schematic diagram depicting the layout of a memory cell 100 designed to be unaffected by SEU when operating in the high voltage (HV) domain, according to one or more examples.

[0034] The memory cell 100 includes PMOS transistors and NMOS transistors arranged in a configuration that defines the cell state.

[0035] Specifically, memory cell 100 includes a pair of cross-coupled inverters (first inverter 102 and second inverter 104), wherein the corresponding output of each inverter is coupled (e.g., electrically coupled, but not limited to) to the corresponding input of the other inverter. Notably, when the signal state of memory cell 100 is configuration data (e.g., data whose values ​​determine the behavior of logic elements in an FPGA, but not limited to), the signal on output OUT can carry the configuration data stored in memory cell 100. Memory cell 100 has two stable states, here logic low "0" and logic high "1". The cross-coupled inverters are state-holding elements of memory cell 100. The cross-coupled inverters form a configuration that allows memory cell 100 to define and maintain a stable state during operation. This configuration enables the memory cell to hold logic "0" or logic "1" according to the input signal.

[0036] The state of memory cell 100 is stored at storage nodes S1 and S2, which use voltage values ​​corresponding to VPHV and VSS to store the signal state of memory cell 100. The cross-coupled configuration of the first inverter 102 and the second inverter 104 strengthens the voltage levels at nodes S1 and S2 to ensure that the cell maintains a stable state.

[0037] The corresponding positive voltage power supply inputs of the two inverters are coupled to a first voltage power supply VPHV, and the corresponding ground inputs of the two inverters are coupled to a second voltage power supply VSS. VPHV is used to represent a logic high signal state (logic "1") within memory cell 100, and VSS is used to represent a logic low signal state (logic "0") within memory cell 100.

[0038] The corresponding input for receiving the first power supply voltage VPHV is operable to be coupled only to the first voltage power supply. In one or more examples, the corresponding input for receiving the first power supply voltage VPHV is directly coupled to the voltage power supply without any intermediate element that could switch the power supply to a lower voltage level.

[0039] The output of the inverter is connected to corresponding access devices in the first access device 106 and the second access device 108, which are controlled by word lines WL and WLB, respectively. These access devices selectively transmit signal states (or their complements) between memory nodes S1 and S2 of memory cell 100 and the bit line (BL). During a write operation, the access devices allow the transmission of the signal state and its complement from the bit line to the appropriate memory node of memory cell 100. During a read operation, the access devices allow the transmission of the signal state and its complement from the appropriate memory node of memory cell 100 to the bit line.

[0040] The terms "single event flip" and "SEU" refer to a state change at the source or drain node of a transistor caused by one or more ionized particles affecting the transistor. For example, the source or drain node of a transistor may be bombarded by heavy ions, which can cause an influx of electron-hole pairs that can drive the voltage at the source or drain node to be higher or lower. The higher or lower voltage at the source or drain node of the transistor can cause a state change in the transistor (e.g., "on" to "off" or "off" to "on"). The term "SEU" can be applied to a transistor to indicate that the transistor has changed state based on an SEU. The term "SEU" can also be applied to a device (e.g., a volatile memory element, but not limited to this) to indicate that the device has changed state based on an SEU; for example, data bits stored by a volatile memory element can be changed due to an SEU.

[0041] The terms "Single Event Flip-In Tolerance" and "SEU Tolerance" can refer to a state that is more resistant to SEU than another system, circuit, or device. In particular, an SEU-resistant system, circuit, or device may include one or more elements that allow the SEU-resistant system, circuit, or device to be less likely to experience SEU than a system, circuit, or device that does not include the one or more elements.

[0042] SEU resistors can improve a system, circuit, or device by enhancing its ability to maintain a stable latched state even when subjected to disturbances. For example, SEU tolerance can improve how a system, circuit, or device responds to events that unintentionally enable a word line for a short period of time. Examples of events that can enable a word line for a short period of time include, but are not limited to, user errors or malfunctions in the control system that drives the word line.

[0043] Volatile memory cells are particularly susceptible to SEUs. As a non-limiting example, an SEU can cause the transistor nodes in the inverters of a pair of cross-coupled inverters in a volatile memory element to change their state, thereby potentially altering the stored data bits.

[0044] Memory cell 100 includes impedance elements (RC) in the circuitry, particularly in paths that include components susceptible to SEUs (Sequentially Energetic U-turns). For example, adding an impedance element in a loop between cross-coupled inverters increases the circuit's time constant (e.g., RC time). This increased time constant makes the circuit less susceptible to SEUs, which are typically short-duration events. SEUs can cause rapid voltage changes that can alter (e.g., flip) the state of a cross-coupled inverter. The impedance element RC resists rapid voltage changes across the transistor, thus helping the inverter maintain or recover to its pre-SEU state before fully establishing an incorrect state. Impedance elements are characterized by their appropriate resistance to the charge flow that can alter the state of the volatile memory device and may include, but are not limited to, components such as resistive random access memory (ReRAM), antifuse, or vertical resistors.

[0045] Figure 1 The memory cell layout is depicted, but the additional word lines or modifications to the aforementioned access devices are not explicitly described.

[0046] Figure 2 This is a schematic diagram of a memory cell 200 that provides SEU immunity when operating in the high voltage (HV) domain, according to one or more examples. Memory cell 200 is a non-limiting example of memory cell 100.

[0047] As discussed below, memory cell 200 supports two-stage write operations and two-stage read operations, which respectively allow memory cell 100 to change state in a manner that ensures no single device within the cell is exposed to excessive voltage stress, thereby limiting sensitivity to SEU.

[0048] The memory cell 200 includes a first inverter 202, a second inverter 204, a first access transistor 206, and a second access transistor 208. The first inverter 202 and the second inverter 204 are cross-coupled to form the state retention element of the memory cell 100 as described above.

[0049] The first inverter 202 includes two PMOS transistors P1A and P1B connected in series, and two NMOS transistors N1A and N1B connected in series. Similarly, the second inverter 204 includes two PMOS transistors P2A and P2B connected in series, and two NMOS transistors N2A and N2B connected in series. The NMOS transistors N1A and N1B of the first inverter 202 and N2A and N2B of the second inverter 204 are used as pull-up networks, and the PMOS transistors P1A and P1B of the first inverter 202 and P2A and P2B of the second inverter 204 are used as pull-down networks.

[0050] In the first inverter 202 and the second inverter 204, the sources of N1A and N2A are connected to the voltage power supply line VSS associated with a logic low level (0V), and the drains of N1A and N2A are connected to the sources of NMOS transistors N1B and N2B. The drains of N1B and N2B are connected to nodes S1 and S2, respectively.

[0051] In the first inverter 202 and the second inverter 204, the sources of P1A and P2A are connected to the first voltage power supply line VPHV, which is associated with a logic high level. The drains of P1A and P2A are connected to the sources of PMOS transistors P1B and P2B, respectively. The drains of P1B and P2B are connected to nodes S1 and S2, respectively.

[0052] Figure 2 The document depicts a single instance of PMOS transistors P1A, P1B, P2A, and P2B, and a single instance of NMOS transistors N1A, N1B, N2A, and N2B. The number of NMOS and PMOS transistors used in the cross-coupled inverters 202 and 204 can be selected to balance performance, area, and power consumption. Multiple transistors can be stacked in the presence of one or more of the PMOS transistors P1A, P1B, P2A, and P2B or the NMOS transistors N1A, N1B, N2A, and N2B. In a stacked configuration, the transistors are arranged such that the drain of one transistor is connected to the source of another transistor. This stacking allows for voltage division across the transistors, thereby helping to manage voltage stress within the device (e.g., ensuring that the voltage across the terminal nodes of the transistors is within tolerances, but not limited thereto), including during access operations discussed herein (e.g., read operations and two-stage write operations discussed herein, but not limited thereto).

[0053] Uneven voltage tolerance

[0054] The first access transistor 206, PMOS transistors P1A, P1B, P2A, and P2B, and NMOS transistors N1A, N1B, N2A, and N2B exhibit non-uniform voltage tolerances. Non-uniform voltage-tolerant transistors can withstand different voltage levels across their different terminals (e.g., gate-drain (Vgd), gate-source (Vgs), and drain-source (Vds)). In one or more examples, such transistors can handle higher voltages across Vgs and Vgd, and have a lower voltage tolerance across Vds. If the Vds voltage exceeds a tolerance threshold (the amount of time the transistor can withstand), the transistor may be damaged over time, potentially leading to breakdown, short circuits, or leakage current.

[0055] Here, the first access transistor 206, PMOS transistors P1A, P1B, P2A, and P2B, and NMOS transistors N1A, N1B, N2A, and N2B are not resistant to high voltages across their drain-source nodes. These transistors can withstand voltages up to VDD across their drain-source nodes, but not higher than VDD (e.g., not resistant to VPHV). These transistors can withstand voltages at least up to VPHV and optionally exceeding VPHV across their gate-drain nodes and their gate-source nodes.

[0056] NBIAS

[0057] The corresponding gates of N1B and N2B are connected to the NBIAS line (in Figure 2 In the specific example depicted, NMOS transistors N1A and N2A are not connected to the NBIAS line, which provides the bias voltage V. NBIAS (Voltages not depicted). These transistors are biased NMOS transistors. NBIAS sets the gate-source voltage (Vgs) of the NMOS transistors (N1B and N2B in this case). By setting NBIAS to an appropriate level, the gate-source voltage (Vgs) of the NMOS transistors is managed, allowing the transistors to operate within their safe operating regions. While the NBIAS line directly controls Vgs, it indirectly controls Vds by maintaining appropriate operating conditions for the NMOS transistors to remain within the region. NBIAS helps ensure the source voltage Vds of the NMOS transistors. S Relative to drain voltage V D Keep it low enough to prevent Vds from exceeding the transistor's tolerance. When the gates of N1B and N2B are driven by NBIAS, their source voltages are constrained to the drain voltage V. D This is part of the voltage stress across their ends.

[0058] PBIAS

[0059] The corresponding gates of P1B and P2B are connected to the PBIAS line (in Figure 2 In the specific example depicted, PMOS transistors P1A and P2A are not connected to the PBIAS line, which provides the bias voltage V. PBIAS (Voltages not depicted). These transistors P1A, P1B, P2A, and P2B are biased PMOS transistors. PBIAS sets the gate-source voltage of the PMOS transistors (here, P1B and P2B). By setting PBIAS at an appropriate level, the gate-source voltage (Vgs) of the PMOS transistors is managed, allowing the transistors to operate within their safe operating regions. While PBIAS directly controls Vgs, it indirectly controls Vds by ensuring that the corresponding PMOS transistor remains within the tolerance region of its drain-source voltage. PBIAS ensures that the drain of P1B or P2B does not rise too high relative to its source, thus keeping Vds within tolerance. Therefore, the PBIAS line effectively regulates P1B and P2B such that their respective drain voltages Vgs are within tolerance. D They are constrained to be a portion of their respective source voltages VS, thereby limiting the voltage stress across them.

[0060] In one or more examples, the bias levels of the bias voltages PBIAS and NBIAS applied to the gates of the PMOS and NMOS transistors, and the corresponding set of PMOS and NMOS transistors to which PBIAS or NBIAS voltages are applied, are selected to ensure that the drain-source voltage remains within limits (e.g., limits defined at least in part by specific voltage tolerances across a particular node of the transistor, which may be non-uniform, but are not limited thereto), including for operating memory cell 200 in the high voltage domain VPHV. In one or more examples, the bias amount may be selected to provide sufficient gate control while reducing the effect of voltage stress on the transistors. This ensures that the transistors operate reliably without exceeding the corresponding voltage tolerances.

[0061] In one or more examples, voltage tolerances of the transistors, particularly their drain-source (Vds) limits, may be considered in the design of memory cell 200. The PMOS and NMOS transistors in memory cell 200 are partially breakdown voltages and can therefore withstand higher Vgs and Vgd voltages, but their Vds must be kept below a certain threshold (e.g., 1.2V) that is below the thresholds that Vgs and Vg can tolerate.

[0062] As described above, the various designs envisioned herein ensure, at least in part, that the corresponding tolerances are met (e.g., not exceeding, but not limited to) by allocating voltages across multiple transistors (e.g., in a stacked configuration, but not limited to) and by careful biasing.

[0063] In one or more examples, one or more parameters (transistor count, bias voltage, and voltage tolerance) can be predetermined during the design phase to ensure that memory cell 200 meets various specifications for read and write operations (including two-stage read and write operations) and for SEU tolerance. Process variations and operating conditions can also be considered during optimization to ensure consistent design execution across different manufacturing batches and various operating environments.

[0064] WL and WLB

[0065] The first access transistor 206 and the second access transistor 208 serve as the interface between the bit line (BL) and the memory cell 200. The arrangement of the first access transistor 206 and the second access transistor 208, controlled by word lines (WL and WLB), allows the memory cell 200 to be written to and read from while maintaining high-voltage operation, as described below. The presence of both word lines WL and WLB is an enhancement compared to conventional memory cell designs that may use a single word line. This dual word line provides better control over read and write operations, especially in the high-voltage domain, because it allows for selective activation of the first access transistor 206 and the second access transistor 208 to reduce stress on either individual device.

[0066] The drain of the first access transistor 206 is connected to the node between N1A and N1B in the first inverter 202 (i.e., OUTB), and the drain of the second access transistor 208 is connected to the node between N2A and N2B in the second inverter 204 (i.e., OUTA). The sources of both access transistors are connected to the bit line (BL).

[0067] The gates of the first access transistor 206 and the second access transistor 208 are controlled by word lines (WL) and WLB, respectively. Signals on WL and WLB determine when the access transistors are enabled, thereby allowing data to be written to or read from the memory cell 100 via BL.

[0068] Optional RC components

[0069] An optional RC element is connected between node S2 and the output OUTA of the first inverter 202. This element increases the RC time constant of the circuit, thereby providing tolerance to SEU by helping the inverter maintain or recover to its steady state after a transient event before an incorrect state can be fully established. The output OUTB of the second inverter 204 is coupled to node S1.

[0070] The BL driver (driver circuit not depicted) can be implemented using only low-voltage (LV) tolerance transistors to save area and power. The write line WL and WLB drivers (driver circuits not depicted) can also be implemented using only low-voltage (LV) tolerance transistors, further reducing area and power. Low-voltage transistors are not even partially high-voltage tolerant.

[0071] Figure 3 This is a schematic diagram of a memory cell 300 that provides SEU immunity when operating in the high voltage (HV) domain, according to one or more examples. Memory cell 300 is a non-limiting example of memory cell 100.

[0072] Memory cell 300 is similar to memory cell 200, except that the SEU-resistant element 302 is coupled between the output of the second inverter and node S1. In this example, the SEU-resistant element (RC) comprises two resistive random access memory (ReRam) devices. As a non-limiting example, the number and placement of the resistive ReRam devices (e.g., between output OUTB and S1, between output OUTA and S2, or both, but not limited thereto) may depend on specific operating conditions.

[0073] Figure 4 This is a block diagram depicting a memory system 400 including memory cells 402 and their associated driver circuitry. The system is designed to manage high-voltage operating and low-voltage control signals for read and write operations.

[0074] The memory system 400 includes a BL driver 404, a WL driver 406, a WLB driver 408, and a memory cell 402.

[0075] Memory cell 402 is a memory cell that provides SEU immunity when operating in the high-voltage (HV) domain discussed herein, such as, but not limited to, memory cell 100, memory cell 200, or memory cell 300. Here, memory cell 402 is connected to both high-voltage (VPHV) and low-voltage (VSS / 0V) power supplies. Memory cell 402 is also connected to power supplies for the NBIAS and PBIAS voltages discussed above.

[0076] VPHV is the high-voltage power supply connected to memory cell 402, ensuring its operation in the high-voltage domain. VSS / 0V is the low-voltage (ground) power supply connected to both memory cell 402 and the drivers (BL driver 404, WL driver 406, and WLB driver 408). The drivers can use VSS / 0V as a reference voltage for their low-voltage operation.

[0077] The BL driver 404 controls the bit line (BL), which interfaces with the memory cell 402 for read and write operations. The BL driver 404 is powered by VDD and VSS / 0V, indicating that it operates in a low-voltage domain. The BL driver 404 receives read / write commands and generates appropriate signals to drive the bit line (BL), thereby enabling data to be written to or read from the memory cell.

[0078] WL driver 406 controls (e.g., activates / deactivates, but is not limited to) the word line (WL) used to allow access to memory cell 402 during read and write operations. Similar to BL driver 404, WL driver 406 is powered by VDD and VSS / 0V, indicating that it operates in the low voltage domain. The WL driver receives read commands / write commands and drives the word line (WL) to control access to memory cell 402.

[0079] WLB driver 408 controls (e.g., activates / deactivates, but is not limited to) complementary word lines (WLBs) to selectively access memory cells 402 during read and write operations. WLB driver 408 is powered by VDD and VSS / 0V, indicating that it operates in the low-voltage domain. WLB driver 408 works in coordination with WL driver 406 to ensure proper access to memory cells 402 during access operations (e.g., read and write, but not limited to).

[0080] Here, the term "activate" when used in conjunction with a word line means applying a voltage to the word line that turns on the access transistor connected to that word line. Here, the term "deactivate" when used in conjunction with a word line means applying a voltage (typically 0V or another suitable level) to the word line that turns off the access transistor connected to that word line.

[0081] The read / write control line carries commands that manage the operation of BL drive 404, WL drive 406, and WLB drive 408. This control line determines whether the system is performing a read or write operation and adjusts the drive output accordingly.

[0082] In one or more examples, memory cell 402 may support write operations that include two write phases (phase 1 and phase 2).

[0083] Figure 5 It is a voltage bias and status table that describes the operating states of a memory cell or system (such as memory cell 100, memory cell 200, memory cell 300, or memory system 400) configured according to one or more examples.

[0084] Figure 5 The depicted voltage bias and status table provides a detailed breakdown of the voltage levels on various signals in the memory cells (memory cell 100, memory cell 200, memory cell 300, or memory cell 402) during different operating states. The table shows how the voltages on the bit line (BL), word line (WL), complementary word line (WLB), and outputs (OUT and OUTB) change during idle and write operations, particularly when using a two-stage write process. This process ensures reliable operation of the memory cells under high voltage conditions while minimizing the risk of erroneous state changes due to SEU.

[0085] Regarding the columns of this table: BL (Bit Line) includes the voltage on BL, which is responsible for transferring data to and from memory cells during read and write operations. WL (Word Line) includes the voltage on WL, which controls the access transistor that connects the bit line to the memory node (S1). WLB (Complementary Word Line) includes the voltage on WLB, which controls the complementary access transistor that connects the bit line to the complementary memory node (S2). OUT includes the voltage at memory node (S2). OUTB includes the voltage at complementary memory node (S1).

[0086] The status column lists example states of the memory cell. For idle state 0 and idle state 1: BL, WL, and WLB are all at 0V; OUT and OUTB maintain stable logic levels, where OUT is at 0V and OUTB is at VPHV during idle 0, and vice versa during idle 1; and the memory cell retains its state without any active read or write operations.

[0087] In a two-phase access, word lines and complementary word lines are activated sequentially during the access operation to the configuration memory cell. In one or more examples, in the two-phase operation discussed herein for writing 0 or writing 1, the circuitry pre-tunes the memory nodes S1 and S2 by setting them to the opposite state (pre-tuning state) of the desired final value (write state). This ensures that the correct logic level can be determined more robustly in subsequent phases. The circuitry then completes the state by switching the memory nodes from the pre-tuning state to the state of the desired final value (write state).

[0088] By employing two access transistors controlled by WL and WLB, BL can selectively and directly influence specific memory nodes S1 and S2 during the corresponding phases of an access operation. This direct influence on the memory nodes allows for more precise setting of the desired logic levels.

[0089] This two-stage strategy, combined with the use of two different access devices that provide access to memory nodes S1 and S2 of the memory cell respectively, helps ensure that the state of the memory cell is reliably written. Pre-tuning in stage 1 makes it easier to achieve the correct final state in stage 2, thereby reducing the risk of errors due to transient events such as SEUs.

[0090] Write 0: Phase 1 and Write 0: Phase 2 involve writing logic "0" to memory cells, which is a two-phase operation. During Phase 1, BL sets the initial conditions of memory nodes S1 and S2 to logic "1" at the memory cells, and the NMOS and PMOS transistors of the cross-coupled inverters stabilize the voltage levels at S1 and S2 at 0V and VPHV, respectively. In Phase 2, BL sets the full write conditions of memory nodes S1 and S2 to logic "0" at the memory cells, and the NMOS and PMOS transistors of the cross-coupled inverters stabilize the voltage levels at S1 and S2 at VPHV and 0, respectively, thus completing the write 0 operation.

[0091] In the first stage (stage 0), BL is set to VDD, causing an initial logic "1" to be written to the memory cell. WL is set to VDD to enable the first access transistor. WLB is set to 0 to disable the complementary access transistor. With the first access transistor enabled and the complementary access transistor disabled, BL affects OUT (or S2) and OUTB (or S1). Specifically, the PMOS transistor in the cross-coupled inverter ensures that in response to BL, OUT (or S2) reaches VPHV and OUTB (or S1) reaches 0V.

[0092] In the second stage (stage 1), which occurs immediately after stage 0, BL is set to 0, causing a logic "0" to be written to the memory cell. WL is set to 0V, and WLB is set to VDD, which disables the first access transistor and enables the second complementary access transistor. With the first access transistor disabled and the complementary access transistor enabled, BL can affect OUT (or S2) and OUTB (or S1). Specifically, the NMOS transistor in the cross-coupled inverter ensures that in response to BL, OUT (or S2) reaches 0V and OUTB (or S1) reaches VPHV.

[0093] Write 1: Phase 1 and Write 1: Phase 2 involve writing a logic "1" to a memory cell; these are two-phase operations. During Phase 1, BL sets the initial conditions of memory nodes S1 and S2 to logic "0" at the memory cell, and the NMOS and PMOS transistors of the cross-coupled inverters stabilize the voltage levels at S1 and S2 at VPHV and 0V, respectively. In Phase 2, BL sets the full write conditions of memory nodes S1 and S2 to logic "1" at the memory cell, and the NMOS and PMOS transistors of the cross-coupled inverters stabilize the voltage levels at S1 and S2 at 0V and VPHV, respectively, thus completing the Write 1 operation.

[0094] In the first stage (stage 1), BL is set to 0V, causing an initial logic "0" to be written to the memory cell. WL is set to VDD to enable the first access transistor. WLB is set to 0V to disable the complementary access transistor. With the first access transistor enabled and the complementary access transistor disabled, BL affects OUT (or S2) and OUTB (or S1). Specifically, the NMOS transistor in the cross-coupled inverter ensures that in response to BL, OUT (or S2) reaches 0V and OUTB (or S1) reaches VPHV.

[0095] In the second stage (stage 2), which occurs immediately after stage 1, BL is set to VDD, causing a logic "1" to be written to the memory cell. WL is set to 0V, and WLB is set to VDD, which disables the first access transistor and enables the second complementary access transistor. With the first access transistor disabled and the complementary access transistor enabled, BL affects OUT (or S2) and OUTB (or S1). Specifically, the PMOS transistor in the cross-coupled inverter ensures that in response to BL, OUT (or S2) reaches VPHV and OUTB (or S1) reaches 0V.

[0096] It is worth noting that writing (whether to a 0 or a 1) has two phases, and each phase occupies a single clock cycle. Therefore, the writing to a memory cell discussed in this paper occupies two clock cycles.

[0097] Figure 6 An exemplary procedure 600 is illustrated, according to one or more examples, for a two-stage write-to-zero operation of exemplary memory cells (e.g., memory cell 100, memory cell 200, memory cell 300, memory cell 402) discussed herein.

[0098] Although example process 600 depicts a specific sequence of operations, this sequence can be changed without departing from the scope of this disclosure. For example, some of the operations depicted may be performed in parallel or in a different order that does not substantially affect the functionality of process 600. In other examples, different components of the example device or system implementing process 600 may perform their functions substantially simultaneously or in a specific order.

[0099] In one or more examples, some or all of the operations of process 600 may be performed by memory system 400.

[0100] In one or more examples, some or all of the operations of process 600 may be performed by logic circuitry in cooperation with one or more drivers of the BL, WL, and WLB discussed herein. As a non-limiting example, such logic circuitry may be integrated with a controller (e.g., but not limited to a microcontroller, microprocessor, DSP, or other processor) that issues read / write commands configured to instruct the drivers of the BL, WL, and WLB according to some or all of the operations of process 600. Additionally or alternatively, multiple logic circuits may be integrated with the respective drivers of the BL, WL, and WLB to cause the drivers to operate according to some or all of the operations of process 600.

[0101] According to one or more examples, process 600 may include setting bit line BL to VDD (logic "1") at operation 602. In the case of writing 0, the memory cell is pre-tuned to the state corresponding to logic "1".

[0102] According to one or more examples, process 600 may include setting the write line WL to VDD at operation 604 to enable the first access transistor. The first access transistor can more directly affect the memory node S2 coupled to the output of the memory cell compared to the complementary access transistor.

[0103] According to one or more examples, process 600 may include setting the complementary write line WLB to 0V at operation 606 to disable the complementary access transistor. With the first access transistor enabled and the complementary access transistor disabled, BL affects the state at memory node S2, as discussed herein.

[0104] According to one or more examples, process 600 may include waiting at operation 608 for the storage node to stabilize at a value corresponding to a logic "1" at the memory cell.

[0105] According to one or more examples, process 600 may include setting BL to 0V (logic "0") at operation 610.

[0106] According to one or more examples, process 600 may include setting the write line WL to 0V at operation 612 to disable the first access transistor.

[0107] According to one or more examples, process 600 may include setting the complementary write line WLB to VDD at operation 614 to enable the complementary access transistor. The complementary access transistor affects the memory node S1, which is not coupled to the output of the memory cell, more directly than the first access transistor. When the first access transistor is disabled and the complementary access transistor is enabled, BL affects the state at memory node S1 as discussed herein.

[0108] According to one or more examples, process 600 may include waiting at operation 616 for the storage node to stabilize at a value corresponding to a logic "0" at the memory cell.

[0109] Figure 7 An exemplary procedure 700 is illustrated, according to one or more examples, for a two-stage write-1 operation of exemplary memory cells (e.g., memory cell 100, memory cell 200, memory cell 300, memory cell 402) discussed herein.

[0110] Although example process 700 depicts a specific sequence of operations, this sequence can be changed without departing from the scope of this disclosure. For example, some of the operations depicted may be performed in parallel or in a different order that does not substantially affect the functionality of process 700. In other examples, different components of the example device or system implementing process 700 may perform their functions substantially simultaneously or in a specific order.

[0111] In one or more examples, some or all of the operations of process 700 may be performed by memory system 400.

[0112] In one or more examples, some or all of the operations of process 700 may be performed by logic circuitry in cooperation with one or more drivers of the BL, WL, and WLB discussed herein. As a non-limiting example, such logic circuitry may be integrated with a controller (e.g., but not limited to a microcontroller, microprocessor, DSP, or other processor) that issues read / write commands configured to instruct the drivers of the BL, WL, and WLB according to some or all of the operations of process 700. Additionally or alternatively, multiple logic circuits may be integrated with the respective drivers of the BL, WL, and WLB to cause the drivers to operate according to some or all of the operations of process 700.

[0113] According to one or more examples, process 700 may include setting BL to 0V (logic "0") at process 702. Setting BL to VDD (logic "1").

[0114] According to one or more examples, process 700 may include setting the write line WL to VDD at operation 704 to enable the first access transistor.

[0115] According to one or more examples, process 600 may include setting the complementary write line WLB to 0V at operation 706 to disable the complementary access transistor.

[0116] According to one or more examples, process 700 may include waiting at operation 708 for the storage node to stabilize at a value corresponding to a logic "0" at the memory cell.

[0117] According to one or more examples, procedure 700 may include setting bit line BL to 0V (logic "1") at operation 710.

[0118] According to one or more examples, process 700 may include setting the write line WL to 0V at operation 712 to disable the first access transistor.

[0119] According to one or more examples, process 700 may include setting the complementary write line WLB to VDD at operation 714 to enable the complementary access transistor.

[0120] According to one or more examples, process 700 may include waiting at operation 716 for the storage node to stabilize at a value corresponding to a logic "1" at the memory cell.

[0121] The timing considerations for setting BL, WL, and WLB in processes 600 and 700 depend on specific operating conditions and are omitted for brevity.

[0122] Those skilled in the art will understand that the functional elements (e.g., functions, operations, actions, processes, or methods) of the examples disclosed herein can be implemented in any suitable hardware, software, firmware, or a combination thereof. Figure 8 Non-limiting examples of specific implementations of the functional elements disclosed herein are illustrated. In some examples, some or all portions of the functional elements disclosed herein may be executed by hardware capable of performing the functional elements.

[0123] Figure 8This is a block diagram of circuitry 800 that, in some examples, can be used to implement the various functions, operations, actions, processes, or methods disclosed herein. Circuitry 800 includes one or more processors 802 (sometimes referred to herein as "processor 802") operatively coupled to one or more data storage devices 804 (sometimes referred to herein as "storage device 804"). Storage device 804 includes machine-executable code 806 stored thereon, and processor 802 includes logic circuitry 808. Machine-executable code 806 describes functional elements that can be implemented (e.g., executed by) the logic circuitry 808. Logic circuitry 808 is adapted to implement (e.g., execute) the functional elements described by machine-executable code 806. When executing the functional elements described by machine-executable code 806, circuitry 800 should be considered as dedicated hardware for executing the functional elements disclosed herein. In some examples, processor 802 may execute the functional elements described by machine-executable code 806 sequentially, simultaneously (e.g., on one or more different hardware platforms), or in one or more parallel process flows.

[0124] When implemented by the logic circuitry 808 of processor 802, machine-executable code 806 adapts processor 802 to perform the operations of the examples disclosed herein. As a non-limiting example, machine-executable code 806 may adapt processor 802 to perform some or all of the storage, writing, and reading operations discussed herein, including two-stage memory reads and writes. As a non-limiting example, machine-executable code 806 may adapt processor 802 to perform some or all of the operations of process 600 or process 700, or the operations discussed with respect to state table 500.

[0125] Also by way of non-limiting example, machine-executable code 806 may enable processor 802 to perform some or all of the features, functions or operations disclosed herein on one or more of the following: memory unit 100, memory unit 200, memory unit 300, memory system 400 or state table 500.

[0126] Processor 802 may include a general-purpose processor, special-purpose processor, central processing unit (CPU), microcontroller, programmable logic controller (PLC), digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic unit, discrete hardware unit, other programmable device, or any combination thereof, designed to perform the functions disclosed herein. A general-purpose computer including a processor is considered a special-purpose computer when it executes functional elements corresponding to the machine-executable code 806 (e.g., software code, firmware code, hardware description) associated with the examples of this disclosure. It should be noted that the general-purpose processor (also referred to herein as a host processor or simply host) may be a microprocessor, but in alternative embodiments, processor 802 may include any conventional processor, controller, microcontroller, or state machine. Processor 802 may also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration.

[0127] In some examples, storage device 804 includes volatile data storage devices (e.g., random access memory (RAM)), non-volatile data storage devices (e.g., flash memory, hard disk drive, solid-state drive, erasable programmable read-only memory (EPROM), but not limited thereto). In some examples, processor 802 and storage device 804 may be implemented as a single device (e.g., semiconductor device product, system-on-a-chip (SoC), but not limited thereto). In some examples, processor 802 and storage device 804 may be implemented as separate devices.

[0128] In some examples, machine-executable code 806 may include computer-readable instructions (e.g., software code, firmware code). As a non-limiting example, the computer-readable instructions may be stored in storage device 804, directly accessed by processor 802, and executed by processor 802 using at least logic circuitry 808. Also as a non-limiting example, the computer-readable instructions may be stored on storage device 804, passed to a memory device (not shown) for execution, and executed by processor 802 using at least logic circuitry 808. Therefore, in some examples, logic circuitry 808 includes electrically configurable logic circuitry 808.

[0129] In some examples, machine-executable code 806 may describe hardware (e.g., circuitry) to be implemented in logic circuitry 808 to perform functional elements. This hardware can be described from any of a range of abstraction levels, from low-level transistor layout to high-level description languages. At high-level abstraction, hardware description languages ​​(HDLs), such as the IEEE standard hardware description language (HDL), can be used. As a non-limiting example, Verilog can be used. ® SystemVerilog or VLSI Hardware Description Language (VHDL).

[0130] HDL descriptions can be transformed into descriptions at any of a variety of other levels of abstraction as needed. As a non-limiting example, a high-level description can be transformed into a logic-level description such as Register Pass Language (RTL), Gate-level (GL) description, Placement-level description, or Mask-level description. As a non-limiting example, micro-operations to be performed by the hardware logic circuitry of logic circuitry 808 (e.g., gates, flip-flops, registers, but not limited thereto) can be described in RTL, then transformed into a GL description by a synthesis tool, and the GL description can be transformed into a placement-level description by a placement and routing tool, which corresponds to the physical layout of an integrated circuit of programmable logic devices, discrete gate or transistor logic components, discrete hardware components, or combinations thereof. Therefore, in some examples, machine-executable code 806 may include HDL, RTL, GL descriptions, Mask-level descriptions, other hardware descriptions, or any combination thereof.

[0131] In an example where machine-executable code 806 includes a hardware description (at any level of abstraction), the system (not shown, but including storage device 804) implements the hardware description described by machine-executable code 806. As a non-limiting example, processor 802 may include a programmable logic device (e.g., an FPGA or PLC), and logic circuitry 808 may be electrically controlled to implement circuitry corresponding to the hardware description into logic circuitry 808. Also as a non-limiting example, logic circuitry 808 may include hardwired logic manufactured by a manufacturing system (not shown, but including storage device 804) according to the hardware description of machine-executable code 806.

[0132] Regardless of whether the machine-executable code 806 includes computer-readable instructions or a hardware description, the logic circuit 808 is adapted to execute the functional elements described by the machine-executable code 806 when the functional elements of the machine-executable code 806 are implemented. It should be noted that although the hardware description may not directly describe the functional elements, it indirectly describes the functional elements that the hardware elements described by the hardware description can execute.

[0133] As used in this disclosure, the terms "module" or "component" can refer to a specific hardware implementation that performs actions of a module or component and / or software object or software routine that can be stored on and / or executed by general-purpose hardware (e.g., computer-readable media, processing devices, but not limited thereto) of a computing system. In some examples, the different components, modules, engines, and services described in this disclosure may be implemented as objects or processes (e.g., as separate threads) that execute on a computing system. While some of the systems and methods described in this disclosure are generally described as being implemented in software (stored on and / or executed by general-purpose hardware), specific hardware implementations or combinations of software and specific hardware implementations are also possible and conceivable.

[0134] As used in this disclosure, the term "combination" referring to multiple elements can include a combination of all elements or any one of various different sub-combinations of certain elements. For example, the phrase "A, B, C, D or combinations thereof" can refer to any one of A, B, C, or D; a combination of each of A, B, C, and D; and any sub-combination of A, B, C, or D, such as A, B, and C; A, B, and D; A, C, and D; B, C, and D; A and B; A and C; A and D; B and C; B and D; or C and D.

[0135] The terminology used in this disclosure, and particularly in the appended claims (e.g., in the body of the appended claims, but not limited thereto), is generally intended to be “open-ended” terms (e.g., the term “comprising” should be interpreted as “including but not limited to”, and the term “having” should be interpreted as “at least having, but not limited to”). As used herein, the term “each” means “some or all”. As used herein, the term “each and every” means “all”.

[0136] Furthermore, if a specific number of introduced claim statements are anticipated, such an intent will be explicitly stated in the claims, and without such statements, no such intent exists. For example, as an aid to understanding, the appended claims may contain the use of the introductory phrases “at least one” and “one or more” to introduce claim statements. However, the use of such phrases should not be construed as implying that a claim statement introduced by the indefinite article “a” or “an” limits any particular claim containing such an introduced claim statement to an example containing only one such statement, even when the same claim includes the introductory phrases “one or more” or “at least one” and indefinite articles such as “a” or “an” (e.g., “a” and / or “an” can be interpreted as referring to “at least one” or “one or more”, but is not limited thereto); the same applies to the use of definite articles to introduce claim statements.

[0137] Furthermore, even when a specific number of the introduced claim statements are explicitly stated, those skilled in the art will recognize that such statements should be interpreted as meaning at least the number stated (e.g., the unmodified statement "two statements" means, in the absence of other modifying elements, at least two statements, or two or more statements, but not limited thereto). Additionally, in instances where conventions such as "at least one of A, B, and C, but not limited thereto" or "one or more of A, B, and C, but not limited thereto" are used, such constructions are generally intended to include, but are not limited to, a single A, a single B, a single C, A and B together, A and C together, B and C together, or A, B, and C together.

[0138] Furthermore, any separate word or phrase presenting two or more alternative terms in the specification, claims, or drawings should be understood to contemplate the possibility of including one term, any one term, or both terms. For example, the phrase "A or B" should be understood to include the possibility of including "A" or "B" or "A and B".

[0139] Additional non-limiting embodiments include:

[0140] Example 1: An apparatus comprising: a first inverter and a second inverter, the first inverter and the second inverter being cross-coupled between a first node and a second node to store a signal state represented by voltage values ​​at the first node and the second node, wherein the first inverter and the second inverter are configured to operate reliably under voltage conditions higher than the positive supply voltage of the apparatus; a first access transistor for selectively coupling the first node to a bit line and allowing direct control of the first node during access operation; and a second access transistor for selectively coupling the second node to the bit line and allowing direct control of the second node during access operation, wherein the respective positive supply inputs of the first inverter and the second inverter are coupled to a voltage supply associated with a voltage level higher than the positive supply voltage of the apparatus.

[0141] Example 2: According to the apparatus of Example 1, one or both of the first inverter or the second inverter include stacked transistors to divide the voltage across the respective stacked transistors in the stacked transistors.

[0142] Example 3: The apparatus according to any one of Examples 1 and 2, wherein the number of transistors in the stacked transistors is selected at least in part to maintain the voltage stress on the respective transistors in the stacked transistors within their respective tolerances.

[0143] Example 4: The apparatus according to any one of Examples 1 to 3, the apparatus comprising: at least one input terminal, the at least one input terminal being configured to receive a bias voltage to bias the gate of one or more transistors of one or both of the first inverter or the second inverter.

[0144] Example 5: The apparatus according to any one of Examples 1 to 4, wherein the bias level of the bias voltage is set to manage the drain-source voltage of the corresponding transistor by controlling the gate-source voltage of the corresponding transistor.

[0145] Example 6: The apparatus according to any one of Examples 1 to 5, wherein the transistors of the first inverter and the second inverter exhibit non-uniform voltage tolerance at their respective terminal nodes.

[0146] Example 7: The apparatus according to any one of Examples 1 to 6, wherein the corresponding transistor of one or both of the first inverter or the second inverter exhibits a lower drain-source voltage tolerance than the gate-drain voltage tolerance and the gate-source voltage tolerance.

[0147] Example 8: The apparatus according to any one of Examples 1 to 7, wherein the drain of the first access transistor is coupled to an internal node of the first inverter, and the internal node is switchably coupled to the output of the first inverter.

[0148] Example 9: The apparatus according to any one of Examples 1 to 8, wherein the drain of the second access transistor is coupled to an internal node of the second inverter, and the internal node is switchably coupled to the output of the second inverter.

[0149] Example 10: The apparatus according to any one of Examples 1 to 9, the apparatus comprising one or more impedance elements arranged between one or more of the first node or the second node and the respective output terminals of the first inverter and the second inverter.

[0150] Example 11: A system comprising: a configuration memory cell; a bit line driver coupled to the configuration memory cell via a bit line; a word line driver coupled to the gate of an access transistor of the configuration memory cell via a word line; a complementary word line driver coupled to the gate of an annotation access transistor of the configuration memory cell via an annotation word line; and logic circuitry configured to control the bit line driver, the word line driver, and the annotation word line driver during a two-stage access operation of the configuration memory cell.

[0151] Example 12: According to the system of Example 11, the logic circuitry is integrated with the bitline driver, the word line driver and the comment word line driver, respectively, and controls the bitline driver, the word line driver and the comment world line driver in response to an access command.

[0152] Example 13: The system according to any one of Examples 11 and 12, the system includes a controller, and the logic circuit is present in the controller and issues access commands to control the bit line driver, the word line driver and the annotation world line driver.

[0153] Example 14: A system according to any one of Examples 11 to 13, wherein the logic circuitry is used to sequentially activate the word line and the complementary word line during the access operation to the configuration memory cell in the two-stage access.

[0154] Example 15: A system according to any one of Examples 11 to 14, wherein the logic circuitry is configured in a two-stage write logic-low operation to: set the bit line to VDD; set the write line to VDD to enable the first access transistor; set the complementary write line to VSS to disable the complementary access transistor; and wait for the memory node of the configuration memory cell to stabilize at a value corresponding to logic high: set the bit line to VSS; set the write line to VSS to disable the first access transistor; set the complementary write line to VDD to enable the complementary access transistor; and wait for the memory node of the configuration memory cell to stabilize at a value corresponding to logic low.

[0155] Example 16: A system according to any one of Examples 11 to 15, wherein the logic circuitry is configured in a two-stage write logic-low operation to: set the bit line to VSS; set the write line to VDD to enable the first access transistor; set the complementary write line to VSS to disable the complementary access transistor; and wait for the memory node of the configuration memory cell to stabilize at a value corresponding to logic high: set the bit line to VDD; set the write line to VSS to disable the first access transistor; set the complementary write line to VDD to enable the complementary access transistor; and wait for the memory node of the configuration memory cell to stabilize at a value corresponding to logic low.

[0156] While this disclosure has been described with respect to certain exemplary embodiments, those skilled in the art will recognize and understand that the invention is not limited thereto. Rather, many additions, deletions, and modifications may be made to the exemplary and described embodiments without departing from the scope of the invention as claimed below and its legal equivalents. Furthermore, features from one embodiment may be combined with features from another embodiment while still being included within the scope of the invention as contemplated by the inventors.

Claims

1. An apparatus, the apparatus comprising: A first inverter and a second inverter, the first inverter and the second inverter being cross-coupled between a first node and a second node to store a signal state represented by voltage values ​​at the first node and the second node, wherein the first inverter and the second inverter are configured to operate reliably under voltage conditions higher than the positive power supply voltage of the device; A first access transistor is configured to selectively couple the first node to a bitline and allow direct control of the first node during an access operation. and A second access transistor is used to selectively couple the second node to the bit line and allows direct control of the second node during access operations. The respective positive power supply input terminals of the first inverter and the second inverter are coupled to a voltage power supply associated with a voltage level higher than the positive power supply voltage of the device.

2. The apparatus of claim 1, wherein one or both of the first inverter or the second inverter comprises stacked transistors to divide the voltage across respective stacked transistors in the stacked transistors.

3. The apparatus of claim 2, wherein the number of transistors in the stacked transistors is selected at least in part to maintain the voltage stress on the respective transistors in the stacked transistors within their respective tolerances.

4. The apparatus according to claim 1, wherein the apparatus comprises: At least one input terminal is provided for receiving a bias voltage to bias the gate of one or more transistors of one or both of the first inverter or the second inverter.

5. The apparatus of claim 4, wherein the bias level of the bias voltage is configured to manage the drain-source voltage of the respective transistor by controlling the gate-source voltage of the respective transistor.

6. The apparatus of claim 1, wherein the transistors of the first inverter and the second inverter collectively exhibit non-uniform voltage tolerances at their respective terminal nodes.

7. The apparatus of claim 1, wherein the respective transistor of one or both of the first inverter or the second inverter exhibits a lower drain-source voltage tolerance than the gate-drain voltage tolerance and the gate-source voltage tolerance.

8. The apparatus of claim 1, wherein the drain of the first access transistor is coupled to an internal node of the first inverter, and the internal node is switchably coupled to the output of the first inverter.

9. The apparatus of claim 1, wherein the drain of the second access transistor is coupled to an internal node of the second inverter, and the internal node is switchably coupled to the output of the second inverter.

10. The apparatus of claim 1, wherein the apparatus comprises one or more impedance elements arranged between one or more of the first node or the second node and the respective output terminals of the first inverter and the second inverter.

11. A system comprising: Configure memory units; Bit line driver, the bit line driver being coupled to the configuration memory cell via bit lines; A word line driver, the word line driver being coupled to the gate of the access transistor of the configured memory cell via a word line; A complementary word line driver, the complementary word line driver being coupled to the gate of the annotation access transistor of the configured memory cell via an annotation word line; and A logic circuit for controlling the bit line driver, the word line driver, and the comment word line driver during a two-stage access operation of the configuration memory cell of the logic.

12. The system of claim 11, wherein the logic circuitry is functionally integrated with the bitline driver, the word line driver, and the comment word line driver, respectively, and controls the bitline driver, the word line driver, and the comment world line driver in response to an access command.

13. The system of claim 11, wherein the system includes a controller, and the logic circuitry is present in the controller and issues access commands to control the bitline driver, the wordline driver, and the annotation worldline driver.

14. The system of claim 11, wherein the logic circuitry is configured to sequentially activate the word line and the complementary word line during the access operation to the configuration memory cell in the two-stage access.

15. The system of claim 14, wherein the logic circuitry is used in a two-stage write logic-low operation to: Set the bit line to VDD; Set the write line to VDD to enable the first access transistor; Set the complementary write line to VSS to disable the complementary access transistor; Wait for the storage node of the configured memory unit to stabilize at the value corresponding to a logic high: Set the bit line to VSS; Set the write line to VSS to disable the first access transistor; Set the complementary write line to VDD to enable the complementary access transistor; and Wait for the storage node of the configured memory unit to stabilize at a value corresponding to a low logic level.

16. The system of claim 14, wherein the logic circuitry is used in a two-stage write logic-low operation to: Set the bit line to VSS; Set the write line to VDD to enable the first access transistor; Set the complementary write line to VSS to disable the complementary access transistor; Wait for the storage node of the configured memory unit to stabilize at the value corresponding to a logic high: Set the bit line to VDD; Set the write line to VSS to disable the first access transistor; Set the complementary write line to VDD to enable the complementary access transistor; and Wait for the storage node of the configured memory unit to stabilize at a value corresponding to a low logic level.

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