Random mismatch compensation for high frequency injection locked ring oscillators

Abstract

An injection locked oscillator includes a plurality of delay elements, two or more voltage control circuits, a phase comparator, and a controller. A plurality of delay elements are connected in a loop and coupled to a global power supply. Each delay element has an input end driven by a previous stage and an output end driving a next stage. Each voltage control circuit couples one of the plurality of delay elements to a global power supply. A phase comparator is coupled to the in-phase output and the quadrature output of the injection-locked oscillator. A controller is coupled to the output of the phase comparator and is configured to drive the control inputs of the two or more voltage control circuits. A control input of each voltage control circuit determines a level of voltage drop across each voltage control circuit.

Description

Cross-reference to related applications

[0001] This patent application claims priority to pending U.S. non-provisional application No. 18 / 459,125, filed August 31, 2024, which has been assigned to the assignee of this application and is expressly incorporated herein by reference, as fully set forth below and for all applicable purposes. Technical Field

[0002] This disclosure relates generally to clock and data recovery circuitry, and more specifically to circuitry for generating multiple clock signals in different phases. Background Technology

[0003] Electronic device technology has experienced explosive growth in recent years. For example, better communication, hardware, larger networks, and more reliable protocols have driven the development of cellular and wireless communication technologies. Wireless service providers are now able to offer their customers an ever-expanding range of features and services, providing users with unprecedented levels of access to information, resources, and communications. To keep pace with these service enhancements, mobile electronic devices (e.g., cellular phones, tablets, laptops, etc.) have become more powerful and complex than ever before. Wireless devices may include high-speed bus interfaces for signal communication between hardware components.

[0004] High-speed serial buses offer advantages over parallel communication links when reduced power consumption and a smaller footprint are required, for example, in integrated circuit (IC) devices. In a serial interface, a serializer converts data from parallel words into a serial bit stream, and a deserializer converts the data back into parallel words at the receiver. For example, high-speed bus interfaces can be implemented using peripheral component interconnect high-speed (PCIe) buses, universal serial bus (USB), or serial advanced technology accessory (SATA).

[0005] IC devices may include serializers / deserializers (SERDES) that transmit and receive via serial communication links. In high-speed applications, the timing of SERDES operation can be controlled by multiple clock signals. The use of multiple clock signals with increasing frequencies leads to increased power consumption. Furthermore, SERDES typically receive clock signals with the same frequency but different phases. The performance, accuracy, or reliability of SERDES can depend on the phase relationship of the clock signals, and deviations or other variations in the phase relationship of the clock signals can cause errors in the received data. Therefore, there is a continuous need for new technologies that provide reliable, low-power clock generation and calibration circuitry for high-speed serial links. Summary of the Invention

[0006] Some aspects of this disclosure relate to systems, apparatus, methods, and techniques for controlling and managing the phase relationship in a clock signal generated by an oscillator for use with a high-frequency deserializer. Other aspects relate to a low-power, high-speed injection-locked oscillator architecture and its calibration circuitry. This calibration circuitry can compensate for phase or duty cycle errors during normal operation.

[0007] In various aspects of this disclosure, an injection-locked oscillator includes a plurality of delay elements, two or more voltage control circuits, a phase comparator, and a controller. The plurality of delay elements are connected in a loop and coupled to a global power supply. Each delay element has an input driven by a preceding stage and an output driven by a subsequent stage. Each voltage control circuit couples one of the plurality of delay elements to the global power supply. The phase comparator is coupled to the non-inverting and quadrature outputs of the injection-locked oscillator. The controller is coupled to the output of the phase comparator and is configured to drive the control inputs of the two or more voltage control circuits. The control input of each voltage control circuit determines the level of voltage drop across that voltage control circuit.

[0008] In various aspects of this disclosure, an apparatus includes: components for measuring the frequency of a clock signal generated by an injection-locked ring oscillator; components for determining whether the measured frequency matches a target frequency defined for the injection-locked ring oscillator; components for adjusting voltage drops on two or more voltage control circuits when the measured frequency does not match the target frequency; and a controller configured to calibrate the duty cycle or phase associated with the in-phase and quadrature outputs of the injection-locked oscillator when the measured frequency matches the target frequency. Each voltage control circuit couples a delay element of the injection-locked oscillator to a global power supply.

[0009] In various aspects of this disclosure, a method for calibrating an injection-locked oscillator includes: measuring the frequency of a clock signal generated by the injection-locked oscillator; determining whether the measured frequency matches a target frequency defined for the injection-locked ring oscillator; adjusting voltage drops across two or more voltage control circuits when the measured frequency does not match the target frequency; and calibrating the duty cycle or phase associated with the in-phase and quadrature outputs of the injection-locked oscillator when the measured frequency matches the target frequency. Each voltage control circuit couples a delay element of the injection-locked oscillator to a global power supply.

[0010] In one aspect, at least two of the plurality of delay elements are directly coupled to the global power supply. In some aspects, the controller is further configured to provide a multi-bit control signal to each of the two or more voltage control circuits. In one example, the multi-bit control signal may be configured based on the phase difference between the in-phase output and the quadrature output, determined by a phase comparator. In another example, the multi-bit control signal may be configured based on an input received from the phase comparator indicating the duty cycle associated with the in-phase output and the quadrature output.

[0011] In some aspects, the injection phase generation circuit can be configured to generate a plurality of injection clock signals from a reference clock signal. The injection phase generation circuit may include a delay circuit that provides two or more of the plurality of injection clock signals by delaying the reference clock signal by an duration configured by the controller. The injection phase generation circuit may include a polyphase filter. The injection phase generation circuit may include one or more phase interpolators.

[0012] In one aspect, the controller is further configured to calibrate the global power supply to obtain the desired free operating frequency of the in-phase output and the quadrature output. Attached Figure Description

[0013] Figure 1 Examples of System-on-Chip (SOC) according to certain aspects of this disclosure are illustrated.

[0014] Figure 2 An example of a system employing a multi-channel data communication link is shown.

[0015] Figure 3 Examples of injection-locked ring oscillators (ILOs) that can be adapted according to certain aspects of this disclosure are illustrated.

[0016] Figure 4 Examples of injection elements that can be adapted to certain aspects of this disclosure, examples of ring oscillators, and examples of dummy injection structures are illustrated.

[0017] Figure 5 Examples of quadrature calibration oscillator circuits that can be adapted or configured according to certain aspects of this disclosure are illustrated.

[0018] Figure 6 Examples can be found Figure 5 An example of a delay element used in the illustrated oscillator circuit.

[0019] Figure 7 An example of an ILO calibration timing diagram is shown.

[0020] Figure 8An example of a duty cycle control circuit in an injection-locked ring oscillator configured according to certain aspects of this disclosure is illustrated.

[0021] Figure 9 A first example of an ILO that supports orthogonal calibration and dynamic runtime recalibration according to certain aspects of this disclosure is illustrated.

[0022] Figure 10 A second example of an ILO that supports orthogonal calibration and dynamic runtime recalibration according to certain aspects of this disclosure is illustrated.

[0023] Figure 11 Examples can be found Figure 10 An example of an injection phase generation circuit used in an ILO is illustrated.

[0024] Figure 12 A third example of an ILO that supports orthogonal calibration and dynamic runtime recalibration according to certain aspects of this disclosure is illustrated.

[0025] Figure 13 This is a flowchart illustrating an example of initial calibration in ILO according to certain aspects of this disclosure.

[0026] Figure 14 This is a flowchart illustrating an example of duty cycle calibration of an ILO according to certain aspects of this disclosure.

[0027] Figure 15 This is a flowchart illustrating an example of phase calibration of an ILO according to certain aspects of this disclosure. Detailed Implementation

[0028] The detailed description below, illustrated with reference to the accompanying drawings, is intended as a description of various configurations and not as representing the only configuration in which the concepts described herein can be practiced. To provide a thorough understanding of the various concepts, the detailed description includes specific details. However, it will be apparent to those skilled in the art that these concepts can be practiced without these specific details. In some instances, well-known structures and components are shown in block diagram form to avoid obscuring such concepts.

[0029] Several exemplary aspects of this disclosure will now be described with reference to the accompanying drawings. The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any aspect described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other aspects.

[0030] The terms “computing device” and “mobile device” are used interchangeably herein to refer to any or all of the following: servers, personal computers, smartphones, cellular phones, tablet computers, laptop computers, netbooks, ultrabooks, handheld computers, personal data assistants (PDAs), wireless email receivers, cellular phones with multimedia internet support, global positioning system (GPS) receivers, wireless game controllers, and similar personal electronic devices that include programmable processors. While these aspects are particularly useful in mobile devices (e.g., smartphones, laptops, etc.) with limited resources (e.g., processing power, battery, size, etc.), they are generally useful in any computing device that can benefit from improved processor performance and reduced power consumption.

[0031] The term "multi-core processor" is used herein to refer to a single integrated circuit (IC) chip or chip package containing two or more independent processing units or cores (e.g., CPU cores) configured to read and execute program instructions. The term "multiprocessor" is used herein to refer to a system or device comprising two or more processing units configured to read and execute program instructions.

[0032] The term "System-on-a-Chip" (SoC) is used herein to refer to a single IC chip containing multiple resources and / or processors integrated on a single substrate. A single SoC may contain circuitry for digital, analog, mixed-signal, and radio frequency functions. A single SoC may also include any number of general-purpose and / or special-purpose processors (digital signal processors (DSPs), modem processors, video processors, etc.), blocks of memory (e.g., read-only memory (ROM), random access memory (RAM), flash memory, etc.), and resources (e.g., timers, regulators, oscillators, etc.), any or all of which may be included in one or more cores.

[0033] The memory technologies described herein are suitable for storing instructions, programs, control signals, and / or data for use in or by a computer or other digital electronic device. Any references to terms and / or technical details relating to individual memory types, interfaces, standards, or memory technologies are for illustrative purposes only and are not intended to limit the scope of the claims to a particular memory system or technology, unless specifically stated in the language of the claims. The complexity of mobile computing device architectures has increased and now typically includes multiple processor cores, SoCs, coprocessors, functional modules including dedicated processors (e.g., communication modem chips, GPS receivers, etc.), complex memory systems, intricate electrical interconnects (e.g., buses and / or structures), and many other resources for executing complex and power-intensive software applications (e.g., video streaming applications, etc.).

[0034] The process technologies used to manufacture semiconductor devices, including IC devices, are constantly being improved. Process technologies include manufacturing methods used to manufacture IC devices and define transistor size, operating voltage, and switching speed. Features that are components of the circuitry in an IC device can be referred to as technology nodes and / or process nodes. The terms "technology node," "process node," and "process technology" are used to characterize a specific semiconductor manufacturing process and its corresponding design rules. By using smaller feature sizes to produce smaller transistors that enable the manufacture of higher-density ICs, faster and more efficient technology nodes are continuously being developed.

[0035] Figure 1 Example components and interconnects in a System-on-Chip (SoC) 100 suitable for implementing certain aspects of this disclosure are illustrated. The SoC 100 may include multiple heterogeneous processors, such as a central processing unit (CPU) 102, a modem processor 104, a graphics processor 106, and an application processor 108. Each processor 102, 104, 106, 108 may include one or more cores, and each processor / core may perform operations independently of the other processors / cores. The processors 102, 104, 106, 108 may be organized in close proximity to each other (e.g., on a single substrate, die, integrated chip, etc.), allowing the processors to operate at much higher frequencies / clock rates than would be possible with off-chip signal propagation. The proximity of the cores also allows for the sharing of on-chip memory and resources (e.g., voltage rails), and allows for more coordinated cooperation between the cores.

[0036] SoC 100 may include system components and resources 110 for managing sensor data, analog-to-digital conversion, and / or wireless data transmission, as well as for performing other specialized operations such as decoding high-definition video, video processing, etc. System components and resources 110 may also include components such as voltage regulators, oscillators, phase-locked loops (PLLs), peripheral bridges, data controllers, system controllers, access ports, timers, and / or other similar components for supporting processors and software clients running on computing devices. System components and resources 110 may also include circuitry for interfacing with peripheral devices such as cameras, electronic displays, wireless communication devices, external memory chips, etc.

[0037] SoC 100 may also include a Universal Serial Bus (USB) or other serial bus controller 112, one or more memory controllers 114, and a Centralized Resource Manager (CRM) 116. SoC 100 may also include input / output modules (not shown) for communicating with resources outside the SoC, each of which may be shared by two or more internal SoC components.

[0038] Processors 102, 104, 106, and 108 can be interconnected via interconnect / bus module 122 to USB controller 112, memory controller 114, system components and resources 110, CRM 116, and / or other system components. This interconnect / bus module may include reconfigurable gate arrays and / or implement a bus architecture. Communication may also be provided by advanced interconnects such as high-performance on-chip networks (NoC).

[0039] Interconnect / bus module 122 may include or provide a bus master system configured to grant exclusive control of the bus to SoC components (e.g., processors, peripherals, etc.) (e.g., data transfer in burst mode, block transfer mode, etc.) to set duration, number of operations, number of bytes, etc. In some cases, interconnect / bus module 122 may implement an arbitration scheme to prevent multiple master components from attempting to drive the bus simultaneously. Memory controller 114 may be a dedicated hardware module configured to manage the flow of data to and from memory 124 via memory interface / bus 126.

[0040] The memory controller 114 may include one or more processors configured to perform read and write operations on the memory 124. Examples of processors include microprocessors, microcontrollers, digital signal processors (DSPs), field-programmable gate arrays (FPGAs), programmable logic devices (PLDs), state machines, gated logic units, discrete hardware circuitry, and other suitable hardware configured to perform various functionalities described throughout this disclosure. In some aspects, the memory 124 may be part of a SoC 100.

[0041] Figure 2 An example of a system employing a multi-channel data communication link 250 to couple a transmitting device 200 to a receiving device 220 is illustrated. The data communication link 250 includes data channels 2521-252. K These data channels 2521-252 provide the transmission medium through which signals are propagated from the first device to the second device. In the illustrated example, the transmitting device 200 may be configured to transmit signals through one or more data channels 2521-252 based on timing information provided by a clock signal transmitted on clock channel 254. K Transmitting data signals. Transmitting device 200 may include components configured to convert parallel data into serial data for transmission on data channels 2521-252. K A serializer (not shown) is used for transmission. Transmitting device 200 also includes data drivers 2061-206. K These data drivers are configured to transmit timing information via data communication link 250 through one or more data channels 2521-252 based on clock signals forwarded by clock driver 204 on clock channel 254. KThe data signal generated is sent to the receiving device 220.

[0042] Clock forwarding is common in communication systems and offers the benefit of eliminating the need for a phase-locked loop (PLL) and other clock recovery circuitry in the receiving device 220. Long-term jitter originating from the PLL 202 in the transmitting device 200 is transparent to the system. Typically, only one phase of the clock signal generated by the transmitter is forwarded to save power and space that would otherwise be occupied by another clock channel. In some examples, multiple phases of the clock signal generated by the transmitter are forwarded. In some examples, the clock signal generated by the transmitter is forwarded as a differential clock signal.

[0043] The receiving device 220 can be configured to receive and process data signals. The receiving device 220 can generate an additional phase of the clock signal to obtain the phase interpolation unit 2281-228. K The clock signal used is an in-phase quadrature (I / Q) version. The phase of the quadrature signal is offset by 90° relative to the in-phase signal. Phase interpolator 2281-228 K It can provide an output as a phase-adjusted or phase-corrected I / Q version of a clock signal. In one example, the phase interpolator is 2281-228. K The output of each phase interpolator in the circuit is provided to sampling circuits 2241-224. K .

[0044] Receiving device 220 may include an injection-locked oscillator (ILO) that receives a clock signal from a line receiver 222 coupled to clock channel 254 and generates a phase-shifted version of the clock signal, including an I / Q version of the clock signal. Oscillators are a fundamental building block of modern electronics and are typically implemented as ring oscillators (ROs), which offer advantages over other types of oscillators, including reduced footprint, power efficiency, and scalability of the technology.

[0045] Figure 3An example of an injection-locked ring oscillator (ILO 300) is shown. The ILO 300 can be locked to an injected external signal with a frequency close to its operating frequency or free-running frequency. The ILO 300 includes multiple stages 3021-3028 connected in a loop. In one example, pairs of back-to-back inverters 3061-3064 are configured to generate a sufficient phase shift between stages 3021-3024 and their corresponding stages 3025-3028 to produce oscillation. The gain in the loop is equal to 1, and the cumulative phase shift is equal to an integer multiple of 360°. In one example, each of the stages 3021-3028 connected in the loop includes an inverter configured with an input driven by the preceding stage 3021-3028 and an output driving the next stage 3021-3028. For an odd number of inverters n, the inverter delay τ sets the free-running oscillation frequency f0 = (2nτ). -1 The phase difference between stages is 360° / n. The ILO 300 provides multiple quadrature phases of the same clock. The ILO 300 shown is a ring oscillator with an even number of stages 3021-3028, and can produce accurate quadrature phase outputs if an oscillation mode (180° offset between each stage 3021-3028) can be excited. Injection element 304 or dummy loads 3141-3143 can be configured to cross-couple each differential phase of the oscillator. This cross-coupling can be used to overcome DC-mode gain. See also... Figure 4 The current digital-to-analog converter (IDAC402) in injection element 304 provides an injection current 406 controlled by the value of injection strength control input 404. In some instances, ILO 300 can be implemented using a voltage-controlled RO. In some examples, ILO 300 can be implemented using a current-deficient RO where the bias current or supply current is provided by a current source. In some examples, the bias current is provided by an IDAC (e.g., Figure 4 The IDAC 402 is provided. Compared to voltage-controlled ROs, current-deficient ROs more easily control variations in process voltage and temperature (PVT). Including the IDAC to control bias current or supply current allows the ILO 300 to operate as a numerically controlled oscillator. This architecture can be used to inject timing current bursts and lock the oscillator to a desired frequency.

[0046] exist Figure 4 In the exemplary injection element 304 shown, IDAC 402 outputs a reference current 408 (i refA scaled version of the injection current 406 is used. Injection current 406 is used to control the injection strength based on the value of injection strength control input 404. When enable control signal 412 is high, injection current 406 is alternately injected into one phase or the other phase of the oscillator based on the input reference clock polarity 410p, 410n. In the illustrated example, injection element 304 is coupled to a pair of nodes 308, 310 (Clk) for injection in ILO 300. 315 and Clk 135 ).

[0047] The dummy loads 3141-3143 are coupled to the other pairs of nodes: Clk0 and Clk. 180 ,Clk 225 and Clk 45 and Clk 90 and Clk 270 In some examples, it can be used Figure 4 The dummy injection structure 420 shown implements dummy loads 3141-3143. The dummy injection structure 420 can be coupled to each of the other node pairs in the ILO 300 for load matching purposes and to ensure that all phase delay elements have the same circuit elements.

[0048] Figure 4 Some aspects of a ring oscillator 440 that can be adapted according to certain aspects of this disclosure are shown. The ring oscillator 440 includes a plurality (N) of inverters 4441-444 that receive a supply current 450 from a current source 442. N The supply current 450 can be adjusted to tune the ring oscillator 440. The first inverter 4441 is shown with a pair of transistors 446, 448, but other configurations and types of inverters can be used. Inverters 4441-444 N It can be arranged or configured to provide ILO 300.

[0049] The ILO 300 can be configured to operate freely at frequencies close to the target frequency. In one example, the target frequency could be 10 GHz, and the ILO 300 could be configured to operate freely at 9.9 GHz. When in free-running mode, each stage 3021-3028 introduces a delay of 12.6 picoseconds, which is calculated as... When under injection lock, one of levels 3021-3028 is forced to switch faster, with a delay of 11.8 ps in the illustrated example. Total lock oscillation frequency ( f 锁定 The following can be calculated: The output signal can be generated using a differential input clock signal at the target frequency. Most of the jitter in the output signal is inherited from the input clock signal, not from a free-running current-controlled oscillator.

[0050] Figure 5 An example of an orthogonal calibration oscillator circuit 500 that can be adapted or configured according to certain aspects of this disclosure is illustrated. The orthogonal calibration oscillator circuit 500 includes an injection-locked ring oscillator 502 and an analog orthogonal calibration circuit 504 that constitute an analog orthogonal calibration loop.

[0051] The injection-locked ring oscillator 502 includes four cascaded delay elements 5161-5164, wherein the output of the fourth delay element 5164 is inverted and fed back to the input of the first delay element 5161. In the illustrated example, the phase difference between the input of the first delay element 5161 and the output of the fourth delay element 5164 is 180°. The first delay element 5161 additionally receives an injection-locked signal generated by a clock source 512. The delay elements 5161-5164 can be considered as a differential circuit with differential signal inputs and differential signal outputs (as indicated by "+" and "-" indicators). The effect of the delay introduced by each of the delay elements 5161-5164 is to introduce a stage-to-stage phase shift in the oscillation signal. In the illustrated example, the differential signal output by the first delay element 5161 has a 45° phase shift relative to the input differential signal (Clk0 520) provided to the input terminal of the first delay element 5161; the differential signal output by the second delay element 5162 (Clk90 522) has a 90° phase shift relative to Clk0 520; the differential signal output by the third delay element 5163 has a 135° phase shift relative to Clk0 520; and the differential signal output by the fourth delay element 5164 has a 180° phase shift relative to Clk0 520. The differential signals output by the first delay element 5161 and the third delay element 5163 have a quadrature phase relationship (i.e., offset by 90°). The differential signals output by the second delay element 5162 and the fourth delay element 5164 also have a quadrature phase relationship.

[0052] The free-running frequency of the injection-locked ring oscillator 502 can be digitally tuned using a frequency tuning and control circuit 514, which provides a multi-bit control signal 524 to each of the delay elements 5161-5164. In one example, the multi-bit control signal 524 selects or adjusts the delay provided by the delay elements 5161-5164. The frequency tuning and control circuit 514 is used to configure the multi-bit control signal 524 so that the free-running frequency of the injection-locked ring oscillator 502 is matched with the frequency of the injection-locked signal generated by the clock source 512. When frequency matching is complete, the phase of the differential signal at the output of the successive delay elements 5161-5164 is offset by 45°. In operation, the relative phase error between the successive delay elements 5161-5164 is expected to be proportional to the difference between the free-running frequency of the injection-locked ring oscillator 502 and the frequency of the injection-locked signal.

[0053] Digital calibration using the frequency tuning and control circuit 514 can accommodate process variations during initialization. However, recalibration using the frequency tuning and control circuit 514 is typically unavailable or impractical during normal operation of the quadrature calibration oscillator circuit 500. After digital calibration is complete, compensation for temperature and supply voltage variations can be provided using the analog quadrature calibration circuit 504. Temperature and supply voltage variations can cause phase errors in the output signal. The bias replication circuit 518 receives a multi-bit control signal 524 provided by the frequency tuning and control circuit 514, and the output 526 of the bias replication circuit 518 is configured during the digital calibration of the injection-locked ring oscillator 502.

[0054] Figure 6 Examples are shown that can be used to implement Figure 5 Examples of delay elements 600 for each of the illustrated delay elements 5161-5164 are provided. Delay element 600 is used herein to illustrate the operation of an analog quadrature calibration circuit 504. Each delay element 600 includes a tail current source 608 that biases a differential input transistor pair 602. The bias provided by the tail current source 608 is controlled by a bias replication circuit 518, which responds to a multi-bit control signal 524 provided by a frequency tuning and control circuit 514. In the illustrated example, the tail current source 608 is coupled to a ground power supply rail. The gate terminals of the transistors in the differential input transistor pair 602 provide inverting and non-inverting input terminals (In- and In+) for the delay element 600. The non-inverting output terminal and the inverting differential output terminal (Out+ and Out-) of the delay element 600 are located at the drain terminals of the transistors in the differential input transistor pair 602.

[0055] In the illustrated example, the variable load circuit 610 is coupled to the differential input transistor pair 602. The variable load circuit 610 includes a first variable resistor 614 coupled in series with transistor 604 in the differential input transistor pair 602 and a second variable resistor 616 coupled in series with transistor 606 in the differential input transistor pair 602. The variable resistors 614 and 616 are coupled to the power supply rail (Vdd). A multi-bit control signal 524, provided by the frequency tuning and control circuit 514, provides… n Bit control word, the n The bit control word can be used to select, adjust, or otherwise control the resistance provided by the variable resistors 614, 616. In one example, each variable resistor 614, 616 can use a... n Selecting one bit from the bits in the bit control word. n This is achieved using a MOS transistor.

[0056] The variable load circuit 610 also includes a load transistor 612, whose source-drain circuit path is coupled between the drain terminals of the differential input transistor pair 602. The gate terminal of the load transistor 612 receives a control signal (Ld_Cntrl signal 552) provided by the analog quadrature calibration circuit 504. The gate voltage modulates the conduction of the load transistor 612, thereby effectively realizing a variable resistance coupled between the drain terminals of the differential input transistor pair 602. The variable resistance provided by the load transistor 612 can change in real time during the operation of the quadrature calibration oscillator circuit 500. Modifying the resistance provided by the load transistor 612 changes the resistance of the variable load circuit 610, the delay provided by the delay element 600, and ultimately changes the frequency of the free-running frequency of the injection-locked ring oscillator 502 and / or the phase difference between the signals output by the delay elements 5161-5164 in the quadrature calibration oscillator circuit 500.

[0057] The analog quadrature calibration circuit 504 includes buffer circuits 542 and 544 that provide a quadrature phase signal (Q) and an in-phase signal (I), respectively. In the illustrated example, the quadrature phase signal is generated from the output of the second delay element 5162, and the in-phase signal is generated from the output of the fourth delay element 5164. Buffer circuits 542 and 544 decouple the core circuitry of the injection-locked ring oscillator 502 from the analog quadrature calibration circuit 504. It will be noted that the quadrature phase signal and the in-phase signal are differential signals that have a quadrature phase relationship with respect to each other. Although quadrature-dependent phase is used for the purposes of this description, it should be understood that some concepts disclosed herein apply to other combinations of phase or phase relationships.

[0058] The analog quadrature calibration circuit 504 includes a phase detector circuit that includes a mixer circuit 546 configured to mix quadrature-phase and in-phase signals (Q and I) output from delay elements 5162 and 5164. The mixer circuit 546 generates a phase difference signal 550 representing the phase difference (Φ) between the quadrature-phase and in-phase signals. In the illustrated example, the phase difference signal 550 has a differential amplitude as a function of Φ. The quadrature-phase and in-phase signals have the same frequency, and the phase difference signal 550 can be expected to be a DC signal indicating the presence and / or amplitude of a quadrature phase error between the quadrature-phase and in-phase signals. The phase detector circuit includes a transimpedance amplifier 548 that converts the phase difference signal 550 into a control voltage for an Ld_Cntrl signal 552. The Ld_Cntrl signal 552 is provided to each of the delay elements 5161-5164 to complete the feedback loop. In one example, the Ld_Cntrl signal 552 controls or adjusts the load provided by the variable load circuit 610 during operation of the injection-locked ring oscillator 502.

[0059] Figure 5 The digital and analog calibration circuitry employed in the illustrated quadrature calibration oscillator circuit 500 provides global control. As used herein, the term "global control" refers to a system in which all delay elements 5161-5164 are calibrated as a group. Calibration codes and adjustment signals are generated by the digital and analog calibration circuitry and are applied equally to all delay elements 5161-5164 in the injection-locked ring oscillator 502. These digital and analog calibration circuits typically cannot calibrate, compensate for, or otherwise accommodate systematic mismatches among delay elements 5161-5164.

[0060] Some examples of the circuits described herein are implemented using P-type metal-oxide-semiconductor (PMOS) transistors, N-type metal-oxide-semiconductor (NMOS) transistors, or some combination of NMOS and PMOS transistors. These examples are provided by way of example only, and it is expected that the concepts disclosed herein can be implemented in circuits using various combinations of NMOS and PMOS transistors.

[0061] Figure 7 This illustrates some limitations of conventional ILO calibration techniques, including those associated with the digital and analog calibration circuitry used in conventional ILOs. Figure 5In the illustrated quadrature calibrating oscillator circuit 500, the phases of Clk0 520 (and Clk180) are effectively fixed by injection lock, while the phase of Clk90 522 may drift or otherwise change relative to the phase of Clk0 520 when the delay through one or more delay elements 5161-5164 changes during operation. PVT variations can alter the duration of the delay provided by the delay elements 5161-5164. For example, the phase of Clk90 522 may change when the delay through one or more delay elements 5161-5164 changes based on the influence of PVT variations on certain tuning parameters, including the voltage or current supplied by the power supply of the quadrature calibrating oscillator circuit 500.

[0062] The first timing diagram 700 illustrates the following example: when the delay of one or more delay elements 5161-5164 changes, the mismatch of the delay of the delay elements 5161-5164 results in a phase difference 712 (Φ) between the quadrature phase signal (Clk90 704) and the in-phase signal (Clk0 702). 0_to_90 The phase difference of 714 (Φ) between the quadrature phase signal (Clk90 704) and the 180° signal (Clk180 706) is less than that between the quadrature phase signal (Clk90 704) and the 180° signal (Clk180 706). 90_to_180 The mismatched phase differences of 712 and 714 result in a duty cycle that is not equal to 50%. Duty cycle error is expressed as a percentage. E DC The phase difference 712 (Φ) between the quadrature phase signal (Clk90 704) and the in-phase signal (Clk0702) can be determined. 0_to_90 Phase error (Φ) in ) err ): .

[0063] The second timing diagram 720 illustrates the following example: a phase difference of 732 (Φ) between the quadrature phase signal (Clk90 724) and the in-phase signal (Clk0 722). 0_to_90 The phase difference 734 (Φ) between the quadrature phase signal (Clk90 724) and the 180° signal (Clk180 726) is equal to the phase difference between them. 90_to_180 (The situation is as follows.)

[0064] The accuracy of the phase difference between the quadrature phase signal and the in-phase signal determines the operational limitations of the SERDES interface. Data transmission and data recovery circuitry rely on the accuracy of this phase difference to achieve maximum data throughput. The phase difference between the quadrature phase signal and the in-phase signal can be described as a change relative to a nominal 90° phase difference. A 90° phase difference is achieved by maintaining a precise 50% duty cycle. A 50% duty cycle requires edge 742 in Clk90724 to be centered between the corresponding edges 740 and 744 in Clk0 722 and Clk180 726, as illustrated in the second timing diagram 720.

[0065] For the purposes of this disclosure, terms such as "phase of a 5 GHz clock signal" refer to signals derived from a 5 GHz clock signal that are phase-shifted from each other. In another example, the term "phase of a 10 GHz clock signal" refers to signals derived from a 10 GHz clock signal that are phase-shifted from each other.

[0066] In many systems, it is expected that the oscillator will generate a high-frequency clock signal while operating at low power levels. These and other expectations can be met by using circuits constructed from small components. However, the use of small components in the ILO and other components employing matching circuitry can lead to significant mismatch effects. In the ILO, the resulting systematic mismatch may manifest as phase errors and / or duty cycles with a 50% drift. As technology advances to accommodate the ever-increasing demand for higher frequencies, systematic mismatch may be expected to become even more problematic.

[0067] Certain aspects of this disclosure relate to compensation for systematic mismatches that may occur in a high-frequency injection-locked ring oscillator (ILO) during normal operation. Certain compensation circuits disclosed herein can dynamically recalibrate the ILO when, for example, different delay elements are subjected to different effects of voltage and temperature variations. Duty cycle correction can be implemented internally to the ring oscillator without requiring external hardware circuitry. In one example, duty cycle correction can be used to calibrate or recalibrate the ILO to reduce or eliminate systematic mismatches, including, for example, mismatch delays affecting two or more delay elements or stages in the ILO. In some implementations, calibration of the in-phase and quadrature (IQ) output signals can be provided within the ILO. In some examples, multiple injection phases are provided to the ILO to facilitate IQ calibration.

[0068] According to certain aspects of this disclosure, the power supply in the injection-locked ring oscillator can be localized and controlled for individual circuits. In some embodiments, runtime calibration may include changing the voltage and / or current levels supplied to the delay elements to modify the delay associated with the delay elements. In some embodiments, the duty cycle of the clock signal generated by the injection-locked ring oscillator can be optimized by independently controlling the voltage supplied to each of two or more delay elements.

[0069] Figure 8 This illustration illustrates aspects of a power supply configuration that can be used to control the duty cycle in an injection-locked ring oscillator configured according to certain aspects of this disclosure. In circuit 800, the power supply in the injection-locked ring oscillator can be localized and configured or adjusted to manage the duty cycle of the clock signal generated by the injection-locked ring oscillator. In the illustrated example, a first inverting delay element 802 receives an input clock signal 812. The output of the first inverting delay element 802 is coupled to the input of a second inverting delay element 804, which provides an output clock signal 814. When the inverting delay elements 802 and 804 are located close to each other on the IC device and when powered from the same power supply, the inverting delay elements are expected to introduce delays of the same duration. In the illustrated example, a voltage control circuit 806 couples the first inverting delay element 802 to rail 810 of a tuned power supply. This power supply can be tuned to determine or obtain a voltage level on rail 810 that produces the desired free-running frequency of the injection-locked ring oscillator. In the illustrated example, the second inverting delay element 804 is directly coupled to the rail 810 of the tuned power supply.

[0070] Voltage control circuit 806 can be configured to adjust the voltage drop between the power input of the first inverting delay element 802 and the rail 810 of the tuning power supply. In one example, voltage control circuit 806 is configured using input code 816, which is determined based on a duty cycle error detected or measured in the output clock signal 814. Voltage control circuit 806 can be used to cause inverting delay elements 802 and 804 to operate at different voltage levels and produce delays of different durations. In some embodiments, a second voltage control circuit (not shown) can be configured to couple the second inverting delay element 804 to the rail 810 of the tuning power supply, thereby enabling the duty cycle to be increased or decreased. In some embodiments, the power input of the first inverting delay element 802 can be directly coupled to rail 810, and voltage control circuit (not shown) can be configured to couple the second inverting delay element 804 to rail 810, thereby enabling the duty cycle to be adjusted by modifying the delay provided by the second inverting delay element 804.

[0071] Figure 8Figure 820 illustrates the change in the duty cycle 822 caused by the voltage drop 824 introduced by the voltage control circuit 806. In some implementations, the voltage drop can be introduced into the inverter's power supply at a designated, predefined, or desired stage within the locked-loop oscillator to achieve a target duty cycle correction.

[0072] In some implementations, the voltage control circuit can be implemented using PMOS transistors. Voltage control circuits implemented using PMOS transistors provide consistent performance as PVT variations affect the oscillator core. For example, process and / or temperature variations affecting the ILO may cause the ILO's delay element to draw increased current. If the current increases, the on-resistance of the corresponding PMOS transistor in the voltage control circuit decreases, and the voltage control circuit can be configured to produce a stable voltage drop over a wide range of PVT variations.

[0073] when Figure 3 and Figure 5 When the illustrated injection-locked ring oscillators have been adapted or configured according to certain aspects of this disclosure, the concepts disclosed herein can be applied to these injection-locked ring oscillators. The concepts disclosed herein can be applied to other types of injection-locked ring oscillators that have been adapted or configured according to certain aspects of this disclosure. The concepts disclosed herein can be applied to certain circuitry included in an injection-locked ring oscillator to improve the operation of the injection-locked ring oscillator in some way. In one example, the injection-locked ring oscillator may include a subordinate feedback loop that couples the output of a delay element to the input of a preceding delay element. In another example, the injection-locked ring oscillator may have a feedforward path that couples the output of a first delay element to the input of a second delay element, thereby bypassing one or more other delay elements between the first and second delay elements in the forward path. Certain concepts disclosed herein can be applied to compensate for mismatches or variations affecting delay elements associated with subordinate feedback loops or feedforward paths. Certain concepts disclosed herein can be applied to other types of injection-locked ring oscillators or injection-locked ring oscillators that include these additional or different adaptations.

[0074] Figure 9 A first example of an ILO 900 supporting orthogonal calibration and dynamic runtime recalibration according to certain aspects of this disclosure is illustrated. The ILO 900 corresponds in certain aspects to... Figure 5 The illustrated quadrature calibration oscillator circuit 500. In some specific implementations, the free-running frequency of the ILO 900 can be used... Figure 5 The illustrated frequency tuning and control circuit 514 is used for digital tuning and may include an equivalent circuit. Figure 5The illustrated equivalent circuit of the analog quadrature calibration circuit 504. The ILO 900 can be calibrated to have an operating frequency locked to a two-phase injected clock signal 918, which can be derived from a reference clock signal 930, or a free-running frequency. Initial calibration ensures that the duty cycles of the in-phase output signal 916 and the quadrature output signal 914 do not vary relative to 50% beyond a predefined maximum duty cycle error.

[0075] ILO 900 includes voltage control circuit 902 p 902 n 904 p and 904 n These will correspond to delay element 906 p 906 n 908 p and 908 n The power input terminal is coupled to a global power supply 920. For the purposes of this description, the term "global power supply" refers to a power supply having a calibration voltage and used to power all delay elements within the ILO 900. In the illustrated example, the voltage of the global power supply 920 is calibrated and / or controlled by a finite state machine 910. The voltage of the global power supply 920 can be tuned during initial system calibration to obtain the desired free-running frequency of the ILO 900 and / or acceptable duty cycles for the in-phase output signal 916 and the quadrature output signal 914. In the illustrated example, the finite state machine 910 provides the voltage control circuitry 904. p 902 n 902 p and 904 n The finite state machine 910 can configure the multi-bit codewords 922, 924 based on signaling 926 provided by the duty cycle and phase comparator circuit 912. The duty cycle and phase comparator circuit 912 can be configured to monitor and / or measure the characteristics of the in-phase output signal 916 and the quadrature output signal 914, which can be used to determine the phase relationship and duty cycle between and within the in-phase output signal 916 and the quadrature output signal 914.

[0076] In some implementations, the duty cycle and phase comparator circuit 912 and the finite state machine 910 can cooperate to measure the elapsed time between the edges in the in-phase output signal 916 and the quadrature output signal 914. In one example, the elapsed time information may indicate the phase relationship between the edges in the in-phase output signal 916 and the quadrature output signal 914 relative to the edge in the in-phase output signal 914. In another example, the elapsed time information may provide sufficient information to calculate the duty cycle of the in-phase output signal 916 and the quadrature output signal 914, or the change in the in-phase output signal 916 and the quadrature output signal 914 relative to a 50% duty cycle.

[0077] In some implementations, the finite state machine 910 can adjust the phase or duty cycle associated with the in-phase output signal 916 and the quadrature output signal 914 by incrementing or decrementing the value of one or more of the multiple codewords 922, 924. In some implementations, the finite state machine 910 can adjust the phase or duty cycle associated with the in-phase output signal 916 and the quadrature output signal 914 by selecting the value of one or more of the multiple codewords 922, 924 from a lookup table indexed based on information provided in signaling 926 obtained from the duty cycle and phase comparator circuit 912.

[0078] In some implementations, the finite state machine 910 can monitor or control the voltage of the global power supply 920. It can configure and / or provide a local power supply for each of a set of delay elements configured in the ILO 900. Figure 9 In the illustrated example, a set of four delay elements 906 p 906 n 908 p 908 n Through voltage control circuit 904 p 902 n 902 p and 904 n Power is received from global power supply 920, while other delay elements receive power directly from global power supply 920. In other examples, each delay element in ILO 900 receives independent local power from global power supply 920 via a corresponding voltage control circuit, thereby achieving maximum control over phase and duty cycle. Finite state machine 910 can be configured to control the voltage control circuit (including voltage control circuit 902). p 902 n 904 p and 904 n The voltage drop provided is used to correct systematic duty cycle errors in the clock signal generated by the ILO 900 and / or to correct phase mismatch within the ILO 900.

[0079] exist Figure 9 In the illustrated example, the core circuitry of the ILO 900 is used to control the noise suppression bandwidth and the phase error occurring between the in-phase output signal 916 and the quadrature output signal 914. These phase errors may be caused by variations in the PVT, which may alter the phase error caused by the delay element 906. p 906 n 908 p 908 n The duration of the provided delay. Due to injection locking, the phase of the edges in the in-phase output signal 916 is effectively fixed relative to the two-phase injected clock signal 918, while when passing through the delay element 906... p 906 n 908 p 908 n When the delay of one or more of the components changes during operation, the phase of the edges in the quadrature output signal 914 may drift or otherwise change relative to the two-phase injected clock signals 918. This can be achieved by modifying the delay element 906. p 906 n 908 p 908 n The associated delay can reduce or eliminate phase error. Modify delay element 906. p 906 n 908 p 908 n It can affect the noise suppression bandwidth of ILO 900.

[0080] Figure 10A second example of an ILO1000 supporting quadrature calibration and dynamic runtime recalibration according to certain aspects of this disclosure is illustrated. In this example, quadrature injection is provided in the ILO1000. The ILO1000 can be configured to separate the control of noise suppression bandwidth from the control of phase errors occurring between the in-phase output signal 1016 and the quadrature output signal 1014. Some systematic phase mismatches in the ILO1000 may remain uncorrected by the core circuitry of the ILO1000 and may generate phase errors between the in-phase output signal 1016 and the quadrature output signal 1014. The effects of these systematic phase mismatches can be reduced or eliminated by adjusting a tunable delay that defines the phase angle between the in-phase differential injection signal 1018 and the quadrature differential injection signal 1028 provided by the injection phase generation circuitry 1040. In one example, a systematic phase mismatch in the ILO1000 may generate a +3° phase error between the in-phase output signal 1016 and the quadrature output signal 1014. The ILO 1000 can be designed or configured such that the phase error between the in-phase differential injection signal 1018 and the quadrature differential injection signal 1028 is attenuated by a factor of 10 in the phase angle between the in-phase output signal 1016 and the quadrature output signal 1014. In this example, the tunable delay can be configured to introduce a -30° phase correction in the phase angle between the in-phase differential injection signal 1018 and the quadrature differential injection signal 1028. In this example, the phase angle between the in-phase differential injection signal 1018 and the quadrature differential injection signal 1028 is set to 60°. The -30° phase correction is attenuated by a factor of 10, and the resulting -3° attenuated phase correction eliminates the +3° phase error caused by the systematic phase mismatch in the ILO 1000, and produces a 90° phase angle between the in-phase output signal 1016 and the quadrature output signal 1014.

[0081] ILO 1000 corresponds to in some respects Figure 5 The illustrated quadrature calibrated oscillator circuit 500. In some specific implementations, the free-running frequency of the ILO 1000 can be used as follows: Figure 5 The illustrated frequency tuning and control circuit 514 uses an equivalent circuit for digital tuning and may include, for example, Figure 5The illustrated analog quadrature calibration circuit 504. The ILO 1000 can be calibrated to have four phase-locked operating frequencies or free-running frequencies using the injected input clock signal 1030. In the illustrated example, an in-phase differential injection signal 1018 and a quadrature differential injection signal 1028 are injected into the ILO 1000. The injected phase generation circuit 1040 generates the quadrature differential injection signal 1028 by delaying the in-phase differential injection signal 1018 using a tunable delay circuit 1026. The tunable delay circuit 1026 can be configured during initial calibration to minimize or eliminate the phase error between the in-phase differential injection signal 1018 and the quadrature differential injection signal 1028. The tunable delay circuit 1026 can be configured during operation to correct the phase drift between the in-phase output signal 1016 and the quadrature output signal 1014. Initial calibration ensures that the duty cycle of the in-phase output signal 1016 and the quadrature output signal 1014 does not change from 50% beyond the predefined maximum duty cycle error. Initial calibration controls the noise suppression bandwidth and the phase error occurring between the in-phase output signal 1016 and the quadrature output signal 1014.

[0082] ILO 1000 includes voltage control circuit 1002 p 1002 n 1004 p and 1004 n These will correspond to delay element 1006 p 1006 n 1008 p and 1008 n The power input terminal is coupled to the global power supply 1020. For the purposes of this description, the term "global power supply" refers to a power supply having a calibration voltage and used to power the delay elements within the ILO 1000. In the illustrated example, the voltage of the global power supply 1020 is calibrated and / or controlled by the finite state machine 1010 and can be tuned during initial system calibration to obtain the desired free-running frequency of the ILO 1000 and / or acceptable duty cycles for the in-phase output signal 1016 and the quadrature output signal 1014. In the illustrated example, the finite state machine 1010 provides the voltage control circuit 1004 defined in the voltage control circuit. p 1002 n 1002 p and 1004 nThe finite state machine 1010 can configure the multi-bit codewords 1022, 1024 based on signaling 1038 provided by the duty cycle and phase comparator circuit 1012. The duty cycle and phase comparator circuit 1012 can be configured to monitor and / or measure the characteristics of the in-phase output signal 1016 and the quadrature output signal 1014, which can be used to determine the phase relationship and duty cycle between and within the in-phase output signal 1016 and the quadrature output signal 1014.

[0083] In some implementations, the duty cycle and phase comparator circuit 1012 and the finite state machine 1010 cooperate to measure the elapsed time between the edges in the in-phase output signal 1016 and the quadrature output signal 1014. In one example, the elapsed time information may indicate the phase relationship between the edges in the in-phase output signal 1016 and the quadrature output signal 1014 relative to the edges in the in-phase output signal 1014. In another example, the elapsed time information may provide sufficient information to calculate the duty cycle of the in-phase output signal 1016 and the quadrature output signal 1014, or the change in the in-phase output signal 1016 and the quadrature output signal 1014 relative to a 50% duty cycle.

[0084] In some implementations, finite state machine 1010 can adjust the phase relationship between the in-phase differential injection signal 1018 and the quadrature differential injection signal 1028. Finite state machine 1010 can provide codeword 1036 or other signaling to control the operation of tunable delay circuit 1026. Finite state machine 1010 can adjust the delay between the edges of the in-phase and quadrature versions of the input clock signal 1030 by incrementing or decrementing the value of codeword 1036. In some implementations, finite state machine 1010 can adjust the delay between the in-phase and quadrature versions of the input clock signal 1030 by selecting the value of codeword 1036 from a lookup table indexed based on information provided from duty cycle and phase comparator circuit 1012 or from other phase detection circuitry. Injecting the four phases of the input clock signal 1030 can suppress errors or changes in the phase relationship between the in-phase output signal 1016 and the quadrature output signal 1014 by eliminating or minimizing the phase errors in the four phases of the input clock signal 1030.

[0085] In some implementations, the finite state machine 1010 can adjust the phase or duty cycle associated with the in-phase output signal 1016 and the quadrature output signal 1014 by incrementing or decrementing the value of one or more of the multiple codewords 1022, 1024. In some implementations, the finite state machine 1010 can adjust the phase or duty cycle associated with the in-phase output signal 1016 and the quadrature output signal 1014 by selecting the value of one or more of the multiple codewords 1022, 1024 from a lookup table indexed based on information provided in signaling 1038 obtained from the duty cycle and phase comparator circuit 1012.

[0086] In some implementations, the finite state machine 1010 can monitor or control the voltage of the global power supply 1020. It can configure and / or provide a local power supply for each of a set of delay elements configured in the ILO 1000. Figure 10 In the example shown, a set of four delay elements 1006 p 1006 n 1008 p 1008 n Through voltage control circuit 1004 p 1002 n 1002 p and 1004 n Power is received from the global power supply 1020, while other delay elements receive power directly from the global power supply 1020. In other examples, each delay element in the ILO 1000 receives independent local power from the global power supply 1020 via a corresponding voltage control circuit, thereby achieving maximum control over the phase and duty cycle. The finite state machine 1010 can be configured to control the voltage control circuit (including voltage control circuit 1002). p 1002 n 1004 p and 1004 n The voltage drop provided is used to correct systematic duty cycle errors in the clock signal generated by the ILO1000 and / or to correct phase mismatch within the ILO1000.

[0087] exist Figure 10In the illustrated example, the core circuitry of the ILO 1000 can be used to control the free-running frequency of the ILO 1000 and define its noise suppression bandwidth. A tunable delay circuit 1026 can be used to control the phase error occurring between the in-phase differential injection signal 1018 and the quadrature differential injection signal 1028. The tunable delay circuit 1026 can be configured to correct the phase drift between the in-phase output signal 1016 and the quadrature output signal 1014 during operation, thereby maintaining a calibrated phase relationship between the in-phase output signal 1016 and the quadrature output signal 1014. A finite state machine 1010 can control or adjust the delay provided by the tunable delay circuit 1026 to compensate for any remaining systematic phase mismatch in the ILO 1000.

[0088] The ILO 1000 receives four injection phases, which are provided as an in-phase differential injection signal 1018 and a quadrature differential injection signal 1028. In other examples, different numbers of injection phases can be provided to the ILO 1000. The number of injection phases provided to the ILO 1000 can be determined based on application requirements. In one example, the number of injection phases provided to the ILO 1000 can be selected based on the amplitude and distribution of the delay element mismatch within the ILO 1000. In another example, the number of injection phases provided to the ILO 1000 can be selected to facilitate duty cycle calibration.

[0089] Figure 11 Examples are shown that can be used as Figure 10 Examples of injection phase generation circuits 1100 and 1120 as alternatives to the illustrated tunable delay circuit 1026. Injection phase generation circuits 1100 and 1120 can generate phases that can be used for injection locking. Figure 10 The ILO 1000 is illustrated with various injection phases. Each of the injection phase generation circuits 1100 and 1120 can be used to correct the phase drift between the in-phase output signal 1016 and the quadrature output signal 1014 during operation, thereby maintaining the calibrated phase relationship between the in-phase output signal 1016 and the quadrature output signal 1014. A finite state machine 1010 can control or adjust a delay that defines the phase provided to the ILO 1000 for each injection phase.

[0090] The first injection phase generation circuit 1100 includes a multiphase filter (PPF 1102) and multiple delay lines 1104a-1104d. The PPF 1102 receives a reference clock signal 1110 at its differential input and outputs four phase signals (PPF phase signals 1108) with corresponding phase angles of 0°, 90°, 180°, and 270°. Each of the PPF phase signals 1108 is provided to a corresponding delay line 1104a, 1104b, 1104c, 1104d, which outputs a selectively delayed version of its input signal. Each of the delay lines 1104a-1104d receives a portion of a multi-bit control signal 1106 received from the controller. Figure 10 In the illustrated example, the controller function can be implemented using a finite state machine 1010. The controller can independently configure the delay duration provided by each of delay lines 1104a-1104d, such that the combination of delays provided by delay lines 1104a-1104d produces an output injected clock signal 1112 with a desired phase interval. In one example, the desired phase interval may correspond to the phase relationship required to produce in-phase and quadrature output injected clock signals 1112 without phase error. In another example, the desired phase interval may produce one or more phases including phase correction. Phase correction can be introduced to compensate for residual phase errors in the output signal of the ILO1000.

[0091] The second injection phase generation circuit 1120 includes a polyphase filter 1122 and multiple phase mixing circuits 1124a-1124d. The polyphase filter 1122 receives a reference clock signal 1130 at its differential input and outputs four phase signals (PPF phase signals 1128) with corresponding phase angles of 0°, 90°, 180°, and 270°. The phase mixing circuits 1124a-1124d may also be referred to as phase interpolators or phase interpolation circuits. A pair of PPF phase signals 1128 is provided to each phase mixing circuit 1124a, 1124b, 1124c, 1124d, each outputting a selectively mixed version of its input signal. The signals in each pair of PPF phase signals 1128 are phase-separated by a 90° phase angle. Each phase mixing circuit 1124a, 1124b, 1124c, 1124d mixes its input signal by effectively performing a weighted summation of the input signals. The weight applied to each signal in the pair is determined by a portion of a multi-bit control signal 1126 received from the controller. In one example, this portion of the multi-bit control signal 1126 includes two values ​​that indicate the corresponding weight to be applied to the corresponding PPF phase signal 1128 of the pair.

[0092] exist Figure 10In the illustrated example, the controller function can be implemented using a finite state machine 1010. The controller can independently configure the weights applied by each of the phase mixing circuits 1124a, 1124b, 1124c, and 1124d, such that the phase mixing circuits 1124a, 1124b, 1124c, and 1124d generate an output injected clock signal 1132 with a desired phase interval. In one example, the desired phase interval may correspond to the phase relationship required to generate in-phase and quadrature injected clock signals without phase error. In another example, the desired phase interval may generate one or more phases including phase correction. Phase correction can be introduced to compensate for residual phase errors in the output signal of the ILO 1000.

[0093] The injection phase generation circuits 1100 and 1120 can be configured during initial calibration to minimize or eliminate the phase error between the in-phase differential injection signal 1018 and the quadrature differential injection signal 1028. During operation, the injection phase generation circuits 1100 and 1120 can be configured to correct phase drift or difference between the in-phase output signal 1016 and the quadrature output signal 1014.

[0094] Figure 12 A third example of the ILO1200, supporting orthogonal calibration and dynamic runtime recalibration according to certain aspects of this disclosure, is illustrated. The ILO 1200 can be configured to... Figure 10 The illustrated ILO 1000 operates in essentially the same manner. In this example, the ILO 1200 receives multiple injected phases from a polyphase filter 1202. The polyphase filter 1202 can be implemented using a resistor-capacitor (RC) network. The polyphase filter 1202 can be configured to generate a desired number of injected phases for injection-locking the ILO 1200. In one example, the polyphase filter 1202 can be configured to generate four injected phases. In another example, the polyphase filter 1202 can be configured to generate eight injected phases. In some cases, the polyphase filter 1202 includes cascaded polyphase filter stages configured to generate eight or sixteen injected phases.

[0095] The polyphase filter 1202 can generate a desired number of injection phases while consuming less power than other phase generation circuits, including, for example, delay-locked loops. In some specific implementations, the benefits gained from polyphase injection may outweigh the shortcomings of the PPF1102's tuning capability.

[0096] Figure 13This is a flowchart 1300 illustrating an example of an initial calibration procedure for an injection-locked ring oscillator configured according to certain aspects of this disclosure. The initial calibration procedure may be initiated after a power-on or reset event. At block 1302, the injection-locked ring oscillator is enabled and clock signal generation begins. At block 1304, the frequency of the generated clock signal is measured. At block 1306, it is determined whether the measured frequency exceeds a target frequency (f) defined for the injection-locked ring oscillator. 目标 If it is determined at box 1306 that the measured frequency is greater than the target frequency, then at box 1308 the voltage of the global power supply injected into the locked-loop oscillator is reduced by a step value, and the process returns to box 1304. Reducing the voltage of the global power supply reduces the frequency of the clock signal generated by the injected-locked-loop oscillator. If it is determined at box 1306 that the measured frequency is not greater than the target frequency, the process proceeds to box 1310.

[0097] At box 1310, it is determined whether the measured frequency is substantially equal to the target frequency defined for the injection-locked ring oscillator. Here, the measured frequency is substantially equal to the target frequency if the difference between the measured frequency and the target frequency is within the tolerance defined by the specification or protocol. A measured frequency substantially equal to the target frequency can be considered matched to the target frequency. If it is determined at box 1310 that the measured frequency is not substantially equal to the target frequency, the voltage of the global power supply in the injection-locked ring oscillator is increased by a step value at box 1312, and the process returns to box 1304. Increasing the voltage of the global power supply increases the frequency of the clock signal generated by the injection-locked ring oscillator. If it is determined at box 1310 that the measured frequency is substantially equal to the target frequency, the process proceeds to box 1314.

[0098] At box 1314, the frequency of the generated clock signal is substantially equal to the target frequency, and duty cycle calibration can be performed. Figure 14 An example of duty cycle calibration is illustrated below. After the duty cycle has been calibrated, injection locking can be enabled at box 1316. At box 1318, the phase of the generated clock signal can be calibrated. Figure 15 An example of phase calibration is illustrated below. After phase calibration is completed, the injected lock-in ring oscillator is considered calibrated at box 1320.

[0099] Figure 14 This is a flowchart 1400 illustrating an example of a duty cycle calibration process for an injection-locked ring oscillator configured according to certain aspects of this disclosure. In some cases, the duty cycle calibration process is initiated during the initial calibration process.

[0100] At box 1402, the duty cycle of the clock signal generated by the injection-locked ring oscillator can be determined. A duty cycle not sufficiently equal to 50% can be indicated as a calibration direction with one of two calibration directions, where the calibration direction indicates the time between the 0° edge and the next 180° edge to be reduced (see [reference]). Figure 7 The time between the 180° edge and the next 0° edge still needs to be reduced. Here, if the duty cycle is within the tolerance defined by the specification or protocol, the duty cycle can be considered sufficiently equal to 50%. At box 1404, it is determined whether the calibration direction has changed (switched) since the previous iteration of the 0° / 180° duty cycle calibration cycle. If it is determined at box 1404 that the calibration direction has not changed, the process proceeds to box 1406. At box 1406, it is determined whether the time between the 180° edge and the next 0° edge needs to be reduced. If it is determined at box 1406 that the time between the 180° edge and the next 0° edge needs to be reduced, then at box 1408, voltage control circuitry associated with the time between the 180° edge and the next 0° edge can be added, and the process then returns to box 1402. If it is determined at box 1406 that the duration between the 0° edge and the next 180° edge should be reduced, then at box 1410, a voltage control circuit associated with the duration between the 0° edge and the next 180° edge can be added, and the process then returns to box 1402.

[0101] If it is determined at box 1404 that the calibration direction has changed, then the 0° / 180° duty cycle calibration is considered complete, and the process proceeds to box 1412.

[0102] At box 1412, the duty cycle of the clock signal generated by the injection-locked ring oscillator is determined. A duty cycle not sufficiently equal to 50% can be indicated as one of two calibration directions, where the calibration direction indicates whether to reduce the duration between the 90° edge and the next 270° edge or to reduce the duration between the 270° edge and the next 90° edge. At box 1414, it is determined whether the calibration direction has changed (switched) since the previous iteration of the 90° / 270° duty cycle calibration cycle. If it is determined at box 1414 that the calibration direction has not changed, the process proceeds to box 1416. At box 1416, it is determined whether to reduce the duration between the 270° edge and the next 90° edge. If it is determined at box 1416 that the duration between the 270° edge and the next 90° edge needs to be reduced, then at box 1418, voltage control circuitry associated with the duration between the 270° edge and the next 90° edge can be added, and the process then returns to box 1412. If it is determined at box 1416 that the duration between the 90° edge and the next 270° edge needs to be reduced, then at box 1420, voltage control circuitry associated with the duration between the 90° edge and the next 270° edge can be added, and the process then returns to box 1412.

[0103] If the calibration direction is determined to have changed at box 1414, the 0° / 180° duty cycle calibration and the 90° / 270° duty cycle calibration are considered complete, and the process terminates.

[0104] Figure 15 This is a flowchart 1500 illustrating an example of a phase calibration process for an injection-locked ring oscillator configured according to certain aspects of this disclosure. In some cases, the phase calibration process is initiated during an initial calibration process. In one example, the phase calibration process involves iteratively reconfiguring... Figure 10 The tunable delay circuit 1026 is shown.

[0105] At block 1502, the tunable delay circuit 1026 is configured to provide a 90° phase angle between the in-phase differential injection signal 1018 and the quadrature differential injection signal 1028. At block 1504, the phase angle (Φ) between the 0° phase and the 90° phase is... 0 / 90 The phase angle (Φ) between the 90° phase and the 180° phase. 90 / 180 The comparison can be made by subtracting the phase angle between the 90° and 180° phases from the phase angle between the 0° and 90° phases (Φ). 0 / 90 -Φ 90 / 180 This comparison can be performed by subtracting the phase angle between the 0° and 90° phases from the phase angle between the 90° and 180° phases (Φ). 90 / 180 -Φ0 / 90 The comparison is performed using a specific method. At box 1506, it is determined whether the sign of the phase angle difference has changed (switched) since the previous iteration of the phase calibration process. If the sign of the phase angle difference is determined not to have changed at box 1506, the process proceeds to box 1508. At box 1508, it is determined whether the sign of the phase angle difference is positive. If the sign of the phase angle difference is determined to be positive at box 1508, the tunable delay circuit 1026 is reconfigured at box 1510 to provide a reduced delay, and the process returns to box 1504. If the sign of the phase angle difference is determined to be negative at box 1508, the tunable delay circuit 1026 is reconfigured at box 1512 to provide an increased delay, and the process returns to box 1504.

[0106] If it is determined at box 1506 that the sign of the output phase error value has changed, then the phase is considered to have been calibrated and the phase calibration process is terminated.

[0107] The operational steps described in any of the exemplary aspects herein are for illustrative purposes only. The described operations may be performed in numerous different orders other than those illustrated. Furthermore, the operations described in a single operational step may actually be performed in multiple different steps. Additionally, one or more operational steps discussed in the exemplary aspects may be combined. It will be understood that, as will be apparent to those skilled in the art, numerous different modifications may be made to the operational steps illustrated in the flowcharts. Those skilled in the art will also understand that any of a variety of different techniques and arts can be used to represent information and signals. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be mentioned throughout the above description may be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or optical particles, or any combination thereof.

[0108] The various operations of the methods described above can be performed by any suitable component capable of performing the corresponding function. This component can include various hardware and / or software components and / or modules, including but not limited to circuits, application-specific integrated circuits (ASICs), or processors. Generally, in the presence of operations illustrated in the figures, those operations may have corresponding components with similar numbering plus functional components. In some aspects, an apparatus includes: components for measuring the frequency of a clock signal generated by an injection-locked ring oscillator; components for determining whether the measured frequency matches a target frequency defined for the injection-locked ring oscillator; components for adjusting voltage drops on two or more voltage control circuits when the measured frequency does not match the target frequency; and a controller configured to calibrate the duty cycle or phase associated with the in-phase and quadrature outputs of the injection-locked oscillator when the measured frequency matches the target frequency. Each voltage control circuit couples a delay element of the injection-locked oscillator to a global power supply.

[0109] In one example, at least two delay elements of the injection-locked oscillator are directly coupled to the global power supply. In some examples, the controller is further configured to provide a multi-bit control signal to each of the two or more voltage control circuits. This multi-bit control signal may be configured based on the phase difference between the in-phase and quadrature outputs, determined by a phase comparator coupled to the in-phase and quadrature outputs of the injection-locked oscillator. The controller may be further configured to provide a multi-bit control signal to each of the two or more voltage control circuits. This multi-bit control signal may be configured based on an indication of the duty cycle associated with the in-phase and quadrature outputs. This indication may be received in a signal provided by a phase comparator coupled to the in-phase and quadrature outputs of the injection-locked oscillator received from the phase comparator.

[0110] In some examples, the apparatus includes components for generating a plurality of injected clock signals from a reference clock signal. In some embodiments, the components for generating the plurality of injected clock signals include a delay circuit that provides two or more of the plurality of injected clock signals by delaying the reference clock signal by an duration configured by the controller. In some embodiments, the components for generating the plurality of injected clock signals include a polyphase filter. In some embodiments, the components for generating the plurality of injected clock signals include one or more phase interpolators.

[0111] In some examples, the controller is further configured to calibrate the global power supply to obtain the desired free operating frequency for the in-phase output and the quadrature output.

[0112] Some specific implementation examples are described in the following numbered clauses: 1. An injection-locked oscillator, the injection-locked oscillator comprising: a plurality of delay elements connected in a loop and coupled to a global power supply, and having an input driven by a preceding stage and an output driving a next stage; two or more voltage control circuits, each voltage control circuit coupling one of the plurality of delay elements to the global power supply; a phase comparator coupled to a non-inverting output and a quadrature output of the injection-locked oscillator; and a controller coupled to the output of the phase comparator, the controller being configured to drive control inputs of the two or more voltage control circuits, the control input of each voltage control circuit determining a level of voltage drop across each voltage control circuit.

[0113] 2. The injection-locked oscillator according to Clause 1, wherein at least two of the plurality of delay elements are directly coupled to the global power supply.

[0114] 3. The injection-locked oscillator according to Clause 1 or Clause 2, wherein the controller is further configured to provide a multi-bit control signal to each of the two or more voltage control circuits, the multi-bit control signal being configured based on the phase difference between the in-phase output and the quadrature output determined by the phase comparator.

[0115] 4. An injection-locked oscillator according to any one of clauses 1 to 3, wherein the controller is further configured to provide a multi-bit control signal to each of the two or more voltage control circuits, the multi-bit control signal being configured based on an input received from the phase comparator indicating the duty cycle associated with the in-phase output and the quadrature output.

[0116] 5. The injection-locked oscillator according to any one of clauses 1 to 4, the injection-locked oscillator further comprising: an injection phase generation circuit configured to generate a plurality of injection clock signals from a reference clock signal.

[0117] 6. The injection-locked oscillator according to Clause 5, wherein the injection phase generation circuitry includes a delay circuitry that provides two or more of the plurality of injection clock signals by delaying the reference clock signal by an duration configured by the controller.

[0118] 7. The injection-locked oscillator according to Clause 5, wherein the injection phase generation circuitry includes a polyphase filter that provides the plurality of injected clock signals.

[0119] 8. The injection-locked oscillator according to Clause 5, wherein the injection phase generation circuitry includes a multiphase filter and one or more phase interpolators.

[0120] 9. An injection-locked oscillator according to any one of clauses 1 to 8, wherein the controller is further configured to: calibrate the global power supply to obtain the desired free-running frequencies of the in-phase output and the quadrature output.

[0121] 10. An apparatus comprising: means for measuring the frequency of a clock signal generated by an injection-locked ring oscillator; means for determining whether the measured frequency matches a target frequency defined for the injection-locked ring oscillator; means for adjusting voltage drops on two or more voltage control circuits when the measured frequency does not match the target frequency, wherein each voltage control circuit couples a delay element of the injection-locked oscillator to a global power supply; and a controller configured to: calibrate the duty cycle or phase associated with the in-phase and quadrature outputs of the injection-locked oscillator when the measured frequency matches the target frequency.

[0122] 11. The apparatus according to Clause 10, wherein at least two delay elements of the injection-locked oscillator are directly coupled to the global power supply.

[0123] 12. The apparatus according to Clause 10 or Clause 11, wherein the controller is further configured to provide a multi-bit control signal to each of the two or more voltage control circuits, the multi-bit control signal being configured based on a phase difference between the in-phase output and the quadrature output determined by a phase comparator coupled to the in-phase output and the quadrature output of the injection-locked oscillator.

[0124] 13. The apparatus according to any one of claims 10 to 12, wherein the controller is further configured to provide a multi-bit control signal to each of the two or more voltage control circuits, the multi-bit control signal being configured based on an indication of a duty cycle associated with the in-phase output and the quadrature output, wherein the indication is received in a signal provided by a phase comparator coupled to the in-phase output and the quadrature output of the injection-locked oscillator received from the phase comparator.

[0125] 14. The apparatus according to any one of clauses 10 to 13, the apparatus further comprising: a component for generating a plurality of injected clock signals from a reference clock signal.

[0126] 15. The apparatus according to Clause 14, wherein the component for generating the plurality of injected clock signals comprises: a delay circuit that provides two or more of the plurality of injected clock signals by delaying the reference clock signal by an duration configured by the controller.

[0127] 16. The apparatus according to Clause 14, wherein the component for generating the plurality of injected clock signals includes: a polyphase filter.

[0128] 17. The apparatus according to Clause 16, wherein the component for generating the plurality of injected clock signals comprises: one or more phase interpolators.

[0129] 18. The apparatus according to any one of clauses 10 to 17, wherein the controller is further configured to: calibrate the global power supply to obtain the desired free operating frequency of the in-phase output and the quadrature output.

[0130] 19. A method for calibrating an injection-locked oscillator, the method comprising: measuring the frequency of a clock signal generated by the injection-locked oscillator; determining whether the measured frequency matches a target frequency defined for the injection-locked ring oscillator; when the measured frequency does not match the target frequency, adjusting voltage drops on two or more voltage control circuits, wherein each voltage control circuit couples a delay element of the injection-locked oscillator to a global power supply; and when the measured frequency matches the target frequency, calibrating the duty cycle or phase associated with the in-phase and quadrature outputs of the injection-locked oscillator.

[0131] 20. The method according to Clause 19, wherein at least two delay elements of the injected locked oscillator are directly coupled to the global power supply.

[0132] 21. The method according to Clause 19 or Clause 20, further comprising: providing a multi-bit control signal to each of the two or more voltage control circuits, the multi-bit control signal being configured based on a phase difference between the in-phase output and the quadrature output determined by a phase comparator coupled to the in-phase output and the quadrature output of the injection-locked oscillator.

[0133] 22. The method according to any one of claims 19 to 21, further comprising: providing a multi-bit control signal to each of the two or more voltage control circuits, the multi-bit control signal being configured based on an indication of a duty cycle associated with the in-phase output and the quadrature output, wherein the indication is received in a signal provided by a phase comparator coupled to the in-phase output and the quadrature output of the injection-locked oscillator received from the phase comparator.

[0134] 23. The method according to any one of clauses 19 to 22, the method further comprising: generating a plurality of injected clock signals from a reference clock signal.

[0135] 24. The method according to Clause 23, wherein generating the plurality of injected clock signals comprises: delaying the reference clock signal by an duration, the duration being configured to provide a desired phase angle between two or more of the plurality of injected clock signals.

[0136] 25. The method according to Clause 23, wherein generating the plurality of injected clock signals comprises: using a polyphase filter to generate the plurality of injected clock signals.

[0137] 26. The method according to Clause 25, wherein generating the plurality of injected clock signals comprises: using one or more phase interpolators to generate the plurality of injected clock signals.

[0138] 27. The method according to any one of Clauses 19 to 26, the method further comprising: calibrating the global power supply to obtain the desired free operating frequencies of the in-phase output and the quadrature output.

[0139] As used in this article, the phrase “at least one of the items” refers to any combination of these items, including a single member. As an example, “at least one of a, b, or c” is intended to cover: a, b, c, ab, ac, bc, and abc, as well as any combination with multiple identical elements (e.g., aa, aaa, aab, aac, abb, acc, bb, bbb, bbb, cc, and ccc, or any other ordering of a, b, and c).

[0140] This disclosure is provided so that any person skilled in the art can make or use various aspects of it. Various modifications to this disclosure will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the spirit or scope of this disclosure. Therefore, this disclosure is not intended to be limited to the examples and designs described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. An injection-locked oscillator, the injection-locked oscillator comprising: Multiple delay elements are connected in a loop and coupled to a global power supply. Each delay element has an input driven by the previous stage and an output driven by the next stage. Two or more voltage control circuits, each voltage control circuit coupling one of the plurality of delay elements to the global power supply; A phase comparator coupled to the in-phase and quadrature outputs of the injection-locked oscillator; and A controller coupled to the output of the phase comparator is configured to drive the control inputs of the two or more voltage control circuits, each voltage control circuit determining the level of voltage drop across each voltage control circuit.

2. The injection-locked oscillator of claim 1, wherein at least two of the plurality of delay elements are directly coupled to the global power supply.

3. The injection-locked oscillator of claim 1, wherein the controller is further configured to: A multi-bit control signal is provided to each of the two or more voltage control circuits, the multi-bit control signal being configured based on the phase difference between the in-phase output and the quadrature output determined by the phase comparator.

4. The injection-locked oscillator of claim 1, wherein the controller is further configured to: A multi-bit control signal is provided to each of the two or more voltage control circuits, the multi-bit control signal being configured based on an input received from the phase comparator indicating the duty cycle associated with the in-phase output and the quadrature output.

5. The injection-locked oscillator according to claim 1, further comprising: An injection phase generation circuit is configured to generate a plurality of injection clock signals from a reference clock signal.

6. The injection-locked oscillator of claim 5, wherein the injection phase generation circuit includes a delay circuit that provides two or more of the plurality of injection clock signals by delaying the reference clock signal by an duration configured by the controller.

7. The injection-locked oscillator of claim 5, wherein the injection phase generation circuit includes a polyphase filter that provides the plurality of injection clock signals.

8. The injection-locked oscillator of claim 5, wherein the injection phase generation circuit includes a multiphase filter and one or more phase interpolators.

9. The injection-locked oscillator of claim 1, wherein the controller is further configured to: The global power supply is calibrated to obtain the desired free operating frequency of the in-phase output and the quadrature output.

10. An apparatus comprising: A component used to measure the frequency of a clock signal generated by an injection-locked ring oscillator; A component used to determine whether the measured frequency matches a target frequency defined for the injected locked ring oscillator; A component for adjusting the voltage drop across two or more voltage control circuits when the measured frequency does not match the target frequency, wherein each voltage control circuit couples a delay element injected into a locked oscillator to a global power supply. and A controller configured to calibrate the duty cycle or phase associated with the in-phase and quadrature outputs of the injection-locked oscillator when the measured frequency matches the target frequency.

11. The apparatus of claim 10, wherein at least two delay elements of the injection-locked oscillator are directly coupled to the global power supply.

12. The apparatus of claim 10, wherein the controller is further configured to: A multi-bit control signal is provided to each of the two or more voltage control circuits, the multi-bit control signal being configured based on the phase difference between the in-phase output and the quadrature output determined by a phase comparator coupled to the in-phase output and the quadrature output of the injection-locked oscillator.

13. The apparatus of claim 10, wherein the controller is further configured to: A multi-bit control signal is provided to each of the two or more voltage control circuits, the multi-bit control signal being configured based on an indication of the duty cycle associated with the in-phase output and the quadrature output, wherein the indication is received in a signal provided by a phase comparator coupled to the in-phase output and the quadrature output of the injection-locked oscillator received from the phase comparator.

14. The apparatus of claim 10, further comprising: A component used to generate multiple injected clock signals from a reference clock signal.

15. The apparatus of claim 14, wherein the component for generating the plurality of injected clock signals comprises: A delay circuit that provides two or more of the plurality of injected clock signals by delaying the reference clock signal by an duration configured by the controller.

16. The apparatus of claim 14, wherein the component for generating the plurality of injected clock signals comprises a polyphase filter.

17. The apparatus of claim 16, wherein the component for generating the plurality of injected clock signals comprises one or more phase interpolators.

18. The apparatus of claim 10, wherein the controller is further configured to: The global power supply is calibrated to obtain the desired free operating frequency of the in-phase output and the quadrature output.

19. A method for calibrating an injection-locked oscillator, the method comprising: Measure the frequency of the clock signal generated by the injection-locked oscillator; Determine whether the measured frequency matches the target frequency defined for the injected locked ring oscillator; When the measured frequency does not match the target frequency, the voltage drop on two or more voltage control circuits is adjusted, wherein each voltage control circuit couples the delay element of the injected lock-in oscillator to the global power supply; as well as When the measured frequency matches the target frequency, calibrate the duty cycle or phase associated with the in-phase and quadrature outputs of the injection-locked oscillator.

20. The method of claim 19, wherein at least two delay elements of the injected lock oscillator are directly coupled to the global power supply.

21. The method according to claim 19, further comprising: A multi-bit control signal is provided to each of the two or more voltage control circuits, the multi-bit control signal being configured based on the phase difference between the in-phase output and the quadrature output determined by a phase comparator coupled to the in-phase output and the quadrature output of the injection-locked oscillator.

22. The method according to claim 19, further comprising: A multi-bit control signal is provided to each of the two or more voltage control circuits, the multi-bit control signal being configured based on an indication of the duty cycle associated with the in-phase output and the quadrature output, wherein the indication is received in a signal provided by a phase comparator coupled to the in-phase output and the quadrature output of the injection-locked oscillator received from the phase comparator.

23. The method according to claim 19, further comprising: Multiple injected clock signals are generated from the reference clock signal.

24. The method of claim 23, wherein generating the plurality of injected clock signals comprises: The reference clock signal is delayed for a duration that is configured to provide a desired phase angle between two or more of the plurality of injected clock signals.

25. The method of claim 23, wherein generating the plurality of injected clock signals comprises: A polyphase filter is used to generate the plurality of injected clock signals.

26. The method of claim 25, wherein generating the plurality of injected clock signals comprises: The plurality of injected clock signals are generated using one or more phase interpolators.

27. The method of claim 19, further comprising: The global power supply is calibrated to obtain the desired free operating frequency of the in-phase output and the quadrature output.

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