Data processing device and data driving device

Abstract

The embodiment of the invention discloses a data processing device and a data driving device, and the data processing device comprises a first data mapping part which converts original data into a plurality of data packets; and an encoder that inverts a portion of bits of the plurality of packets; the encoder includes: a data comparison section that compares a most significant bit (MSB) of a first packet and a least significant bit (LSB) of a second packet adjacent to each other among a plurality of packets; a code conversion unit that, when the most significant bit of the first packet and the least significant bit of the second packet are the same, inverts the least significant bit of the second packet; and a bit generation unit that generates an instruction packet in which conversion information for the least significant bit of the second packet is stored.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to a data processing apparatus and a data driving apparatus. BACKGROUND

[0002] A data processing apparatus such as a time controller can transmit a signal to a source driver according to an interface protocol, and a receiver can process the received signal to acquire data corresponding to the received signal. In order to respond to a clock and act, the source driver can extract or recover a clock from the received signal. To this end, the source driver can include a clock-data recovery (CDR) circuit. The source driver can appropriately recover data corresponding to the received signal in response to a clock extracted or recovered through the clock-data recovery circuit.

[0003] In a high-speed clock-embedded transmission system, in order to enable a clock-data recovery (CDR) circuit to easily recover a clock, it is necessary to periodically embed a clock in transmission data. A data run length refers to the number of consecutive identical values in the transmission data, and is related to a maximum period in which clock embedding is not performed.

[0004] In order to smooth clock recovery of a clock-data recovery (CDR) circuit, it is necessary to adjust a maximum run length to be constant. Therefore, a data encoding technique capable of implementing clock embedding at a constant period is required. SUMMARY

[0005] Problems to be Solved by the Invention

[0006] An embodiment can provide a data processing apparatus and a data driving apparatus capable of encoding data to have a constant maximum run length.

[0007] An embodiment can provide an encoding technique capable of improving a degree of freedom by setting a number of data packets and a number of data bits to be different.

[0008] The problems to be solved by the present application are not limited to the above-mentioned problems, and other problems not mentioned can be clearly understood by those skilled in the art from the following description.

[0009] Technical Solution to Solve the Problems

[0010] A data processing apparatus according to one aspect of the present invention includes a first data mapping section that converts original data into a plurality of data packets, and an encoder that inverts a part of bits of the plurality of data packets, the encoder including a data comparison section that compares a most significant bit (MSB) of a first data packet and a least significant bit (LSB) of a second data packet that are adjacent in the plurality of data packets, a code conversion section that inverts the least significant bit of the second data packet in a case where the most significant bit of the first data packet and the least significant bit of the second data packet are identical, and a bit generation section that generates an indicator packet in which conversion information of the least significant bit of the second data packet is stored.

[0011] The data processing apparatus can further include a data group generation section that generates a plurality of data groups by inserting the indicator packet into the plurality of data packets after encoding.

[0012] The plurality of data groups can each have the same number of packets.

[0013] The indicator packet can have a plurality of bits in the data group, and the number of bits of the indicator packet can be identical to the number of data packets in the data group.

[0014] The number of bits of the indicator packet can be identical to the number of bits of the data packet.

[0015] The indicator packet can have a plurality of bits in the data group, and the number of bits of the indicator packet can be different from the number of the plurality of data packets.

[0016] The data comparison section can perform an exclusive OR (XOR) operation on the most significant bit (MSB) of the first data packet and the least significant bit (LSB) of the second data packet that are adjacent, and the code conversion section can invert or not invert the least significant bit of the second data packet according to a result of the XOR operation.

[0017] The bit generation section can store a result of an XOR operation on the most significant bit (MSB) of the first data packet and the least significant bit (LSB) of the second data packet that are adjacent in a bit position of the indicator packet.

[0018] The indicator packet can include a least significant bit, a most significant bit, and a storage bit disposed between the least significant bit and the most significant bit, the most significant bit can have a value that inverts a most significant bit of a data packet immediately before the indicator packet, and the most significant bit can have a value that inverts a least significant bit of a data packet immediately after the indicator packet.

[0019] The data driving device according to one aspect of the present application includes a data receiving section that receives a plurality of data groups including an indicator packet and a plurality of data packets, and a decoder that restores the data packets to original data, the decoder including an indicator packet storing section that separates and stores the indicator packet, and a second data mapping section that inverts or does not invert the least significant bits of the plurality of data packets based on conversion information stored in the least significant bits of each data packet of the indicator packet to restore the original data.

[0020] The decoder can include a second data mapping section that restores clock information and data information from the restored original data.

[0021] Effects of the Invention

[0022] According to the embodiment, since a clock edge is generated at the boundary of a packet, a maximum run length can be constantly ensured, thereby making it easy to restore a clock and data.

[0023] In addition, the number of data packets and the number of bits can be freely changed, thereby increasing the degree of freedom and enabling high-speed transmission.

[0024] Effects of the present application are not limited to the above-mentioned effects, and other effects not mentioned can be clearly understood by those skilled in the art from the recitations of the claims. BRIEF DESCRIPTION OF DRAWINGS

[0025] Figure 1 is a conceptual diagram of a transceiving device according to one embodiment of the present application.

[0026] Figure 2 is a conceptual diagram of an encoder according to one embodiment of the present application.

[0027] Figure 3 is a conceptual diagram of a decoder according to one embodiment of the present application.

[0028] Figure 4 is a diagram showing a data structure according to one embodiment of the present application.

[0029] Figure 5 is a flowchart showing a data encoding step according to one embodiment of the present application.

[0030] Figure 6 is a diagram showing an original data packet.

[0031] Figure 7 is a diagram showing a data encoding method according to one embodiment of the present application.

[0032] Figure 8 is a diagram showing an XOR operation table according to one embodiment of the present application.

[0033] Figure 9is a diagram showing encoded data of an embodiment of the present application.

[0034] Figure 10 is a diagram showing a decoding process of an embodiment of the present application.

[0035] Figure 11 is a diagram showing a data encoding method of another embodiment of the present application.

[0036] Figure 12 is a diagram showing a data encoding method of still another embodiment of the present application.

[0037] Figure 13 and Figure 14 is a diagram showing a process of encoding by a data encoding method of still another embodiment of the present application.

[0038] Figure 15 is a diagram showing a first modification example of Figure 12

[0039] Figure 16 is a diagram showing a second modification example of Figure 12

[0040] Figure 17 is a diagram showing a decoding process of still another embodiment of the present application. DETAILED DESCRIPTION

[0041] The advantages, features and methods of achieving them of the present application will become clear if reference is made to the embodiments to be described in detail together with the accompanying drawings. The present application is not limited to the embodiments disclosed below, and can be realized in various modes different from each other, but the embodiments are provided in order to make the explanation of the present application complete and to inform completely the scope of the present application to those skilled in the art to which the present application pertains, and the present application is defined only by the scope of the claims. Figure 1

[0042] Since the shapes, sizes, proportions, angles, numbers and the like disclosed in the drawings for explaining the embodiments of the present application are exemplary, the present application is not limited to what is shown in the drawings. Throughout the specification, the same reference numerals essentially represent the same constituent elements. In addition, in the course of explaining the present application, when it is judged that the specific explanation of the well-known technology related to the present application will obscure the gist of the present application, the detailed explanation thereof is omitted.

[0043] The following embodiments can be partially or wholly combined or integrated with each other, and various linkages and drives can be technically realized. The embodiments can be independently implemented with respect to each other, or can be implemented together in a related relationship.

[0044] Hereinafter, various embodiments of the present application will be explained in detail with reference to the accompanying drawings.

[0045] ​​​Figure 1 is a conceptual diagram of a data transceiving apparatus of an embodiment of the present application. Figure 2 is a conceptual diagram of an encoder of a transmitter of an embodiment of the present application. Figure 3 is a conceptual diagram of a decoder of a receiver of an embodiment of the present application.

[0046] Referring to Figure 1 and Figure 2 , the transceiving apparatus of the embodiment can include a transmitter 100 and a receiver 200. Such a transceiving apparatus can be a smart phone, a TV, or various display apparatuses such as a display in a vehicle interior, but embodiments of the present application are not limited thereto. The transmitter 100 can include various transmitters that encode and transmit data. For example, the transmitter 100 can be a data processing apparatus such as a timing controller, but embodiments of the present application are not limited thereto.

[0047] The receiver 200 can include various receivers that decode encoded data and restore original data. For example, the receiver 200 can be a data driving apparatus such as a source driver, but embodiments of the present application are not limited thereto.

[0048] The transmitter 100 can include a first data mapping part 110 that converts input data into a data packet, an encoder 120 that encodes data, and a transmission part 130 that serially transmits encoded data.

[0049] The first data mapping part 110 can be a TX logic that receives and stores original data in units of frames, and transmits the data packed to the encoder. The first data mapping part 110 can convert the original data into a packet of N bits. For example, N bits can be a multiple of 2, a multiple of 3, or a multiple of 5, but embodiments of the present application are not limited thereto. The bits of the packet can be predetermined in consideration of a maximum run length. In the case where the maximum run length is 12 UI, each packet can be 12 bits, but is not necessarily limited thereto.

[0050] The first data mapping part 110 can count and convert the bits input in succession into a packet of N bits. The first data mapping part 110 can include a counter (not shown). The first data mapping part 110 can count the input bits and generate a packet of N bits according to a predetermined protocol.

[0051] The encoder 120 can include a data comparison part 121, a bit generation part 122, a code conversion part 123, and a data group generation part 124.

[0052] The data comparison unit 121 can compare the most significant bit (MSB) of the first data packet and the least significant bit (LSB) of the second data packet. The first data packet can be the last data packet transmitted to the encoder, and the second data packet can be the current data packet, but embodiments of the present application are not limited thereto. For example, the data comparison unit 121 can also be simultaneously input with a plurality of data packets stored in the frame memory and compare the bits at the packet boundaries.

[0053] In the case where the most significant bit of the first data packet and the least significant bit of the second data packet are the same, the data comparison unit 121 outputs an inversion signal, and in the case where the most significant bit of the first data packet and the least significant bit of the second data packet are different, the data comparison unit 121 outputs a non-inversion signal. The same can mean the same value of 0 or 1. In addition, the different can mean different values of 0 or 1 from each other.

[0054] The data comparison unit 121 can perform an exclusive OR (XOR) operation. In the case where the most significant bit of the first data packet and the least significant bit of the second data packet are both 0 or both 1, the data comparison unit 121 outputs an inversion signal 0.

[0055] In the case where the most significant bit of the first data packet is 1 and the least significant bit of the second data packet is 0, or the most significant bit of the first data packet is 0 and the least significant bit of the second data packet is 1, the data comparison unit 121 outputs a non-inversion signal 1. The data comparison unit 121 can include a logic operation circuit that can perform an exclusive OR (XOR) operation.

[0056] The bit generation unit 122 can map the conversion information of the corresponding bit to the indication packet by generating the indication packet and receiving the inversion signal or the non-inversion signal output from the data comparison unit 121. The conversion information can be the inversion signal or the non-inversion signal output from the data comparison unit 121. For example, if the conversion information is input as 1, the corresponding bit is not inverted in the decoder 220, and if the conversion information is input as 0, the corresponding bit is inverted in the decoder 220.

[0057] The code conversion unit 123 can invert or non-invert the least significant bit of the data packet according to the inversion signal or the non-inversion signal. However, embodiments of the present application are not limited thereto. For example, in the case where the most significant bit of the first data packet and the least significant bit of the second data packet are compared and the bits are the same, the most significant bit of the first data packet can also be inverted. According to embodiments, in the case where two adjacent data packets are compared and the adjacent bits at the boundaries of the packets are the same value, in order to generate a clock edge, one of the adjacent bits can be inverted.

[0058] Accordingly, the least significant bit of the data packet can be a value different from the most significant bit of the adjacent data packet. According to an embodiment, since the bits at the boundaries of the respective data packets are values different from each other, a clock edge can be generated at the boundary of the packet. Accordingly, it is possible to secure the set maximum run length.

[0059] For example, in the case where the set maximum run length is 3 UI, in the case where the bits of the first data packet are

[0100] and the bits of the second data packet are

[0000] , since 0 is continuously present six times in the two data packets, the maximum run length 3 UI can be exceeded. However, according to an embodiment, since the least significant bit of the second data packet is inverted from 0 to 1, the bits of the second data packet can be encoded as

[1000] . Accordingly, since the bits at the boundary between the first data packet and the second data packet are different and a clock edge is generated, it is possible to satisfy the maximum run length.

[0060] The data group generating part 124 can generate a data group having N data packets by inserting one indicator packet in N-1 data packets. According to an embodiment, one data group can have N packets, and each data packet can be N bits. That is, the number of data packets and the number of bits can be the same. Accordingly, there is an advantage that efficient clock recovery is possible in the receiver 200.

[0061] The encoder 120 can include a counter 125. The counter 125 can count the respective bits or packets to identify the packet and the boundary position between the packets. However, it is not necessarily limited thereto, and the counter can be configured to the first data mapping part 110, not to the encoder 120. The first data mapping part 110 can generate a packet of the same bits using the counter. The encoder 120 can identify the boundary position between the packets through the counting information of the first data mapping part 110 even without an additional counter.

[0062] Referring to Figure 3 and Figure 4 , the receiver 200 can include a data receiving part 210 receiving the encoded data, a decoder 220 converting the encoded data into original data, and a second data mapping part 230 recovering the clock and the data from the original data.

[0063] The decoder 220 can include an indicator packet storing part 221 extracting and storing the indicator packet in the encoded data, and a code recovery part 222 recovering the inverted bits of the data packet. The indicator packet storing part 221 can extract the mapping data except for the least significant bit and the most significant bit in the indicator packet. The code recovery part 222 can convert or maintain the value of the least significant bit of each data packet based on the mapping data of the indicator packet. The decoder 220 can further include a counter 223 for counting the bits or the packets, but it is not necessarily limited thereto. The decoder 220 can sequentially transmit the data packet in which the indicator packet is separated and the bits are recovered.

[0064] The second data mapping unit 230 can include a Clock-Data Recovery (CDR) circuit that recovers a clock and data from the data packet.

[0065] According to an embodiment, the encoder 120 can ensure a maximum run length by inverting a bit at a boundary of a data packet, and the decoder 220 can effectively ensure original data by restoring the inverted data.

[0066] Figure 4 FIG. 1 is a diagram illustrating a data structure according to an embodiment of the present application.

[0067] Referring to Figure 5 One data group can include one indicator packet (IDP) and N-1 data packets (Packet1 to Packet(n-1)) and is composed of a total of N packets. The data packet can be defined as effective data as RGB image data, but embodiments of the present application are not limited thereto. The data packet can also include control data. The data group can continuously transmit a previous data group, a current data group, and a next data group.

[0068] The indicator packet (IDP) can be N bits (HD1, I1 to I(n-1), and HD2). The least significant bit (LSB) and the most significant bit (MSB) of the indicator packet (IDP) can be a clock bit (CK), a guard bit, or a redundant bit. Transition information (BI) of each data packet can be mapped between the least significant bit (LSB) and the most significant bit (MSB) of the indicator packet. In an embodiment, the least significant bit can be a bit closest to a previous packet within each packet, and the most significant bit can be a bit closest to a next packet within each packet, but embodiments of the present application are not limited thereto.

[0069] The least significant bit (LSB) of the indicator packet can be mapped as a value different from the most significant bit (B(n-1)) of the previous data packet. For example, in a case where the last bit (B(n-1)) of the previous data group is 0, the least significant bit (LSB) of the indicator packet can be written as 1. For example, in a case where the last bit (B(n-1)) of the previous data group is 1, the least significant bit (LSB) of the indicator packet can be written as 0. Accordingly, a clock edge can be generated at a boundary between the previous data group and the current data group.

[0070] The most significant bit (MSB) of the indication packet can invert and map the value of the least significant bit B0 of the first data packet Packetl within the current data group. For example, in the case that the least significant bit B0 of the first data packet within the current data group is 1, the most significant bit (MSB) of the indication packet can map 0. For example, in the case that the least significant bit B0 of the first data packet Packetl within the current data group is 0, the most significant bit (MSB) of the indication packet can map 1. Thus, since a clock edge can be generated at the boundary of the indication packet and the adjacent first data packet Packetl, the maximum run length can be satisfied.

[0071] Figure 6 FIG. 1 is a flowchart illustrating a data encoding step according to an embodiment of the present application. Figure 7 FIG. 2 is a diagram illustrating original data. Figure 8 FIG. 3 is a diagram illustrating a data encoding method according to an embodiment of the present application. Figure 9 FIG. 4 is a diagram illustrating an encoding table according to an embodiment of the present application. Figure 5 FIG. 5 is a diagram illustrating encoded data according to an embodiment of the present application.

[0072] Referring to FIG. 1, a data encoding method can include a step S110 of comparing the most significant bit of an adjacent first data packet and the least significant bit of a second data packet, a step S120 of inverting the least significant bit of the second data packet according to a comparison result, a step S130 of mapping conversion information and generating an indication packet, and a step S140 of inserting the indication packet into an encoded data packet to generate a data group. Figure 6 to Figure 9 The steps will be described. Figure 6

[0073] Referring to FIG. 1, a data encoding method can include a step S110 of comparing the most significant bit of an adjacent first data packet and the least significant bit of a second data packet, a step S120 of inverting the least significant bit of the second data packet according to a comparison result, a step S130 of mapping conversion information and generating an indication packet, and a step S140 of inserting the indication packet into an encoded data packet to generate a data group. Figure 7 The original data can be converted into a packet of N bits. The original data can also be scrambled data, but is not necessarily limited thereto. The original data can be RGB image data, but is not necessarily limited thereto, and can also include control data.

[0074] Referring to FIG. 1, a data encoding method can include a step S110 of comparing the most significant bit of an adjacent first data packet and the least significant bit of a second data packet, a step S120 of inverting the least significant bit of the second data packet according to a comparison result, a step S130 of mapping conversion information and generating an indication packet, and a step S140 of inserting the indication packet into an encoded data packet to generate a data group. Figure 8 Figure 9 In the comparison step, an exclusive OR (XOR) operation can be performed on the most significant bit (MSB) of the first data packet and the least significant bit (LSB) of the second data packet.

[0075] In the case that the most significant bit (MSB) of the first data packet and the least significant bit (LSB) of the current data packet are both 0 or 1, the data comparison unit 121 can output an inversion signal 0.

[0076] In the case that the most significant bit (MSB) of the first data packet and the least significant bit (LSB) of the second data packet have bit values different from each other, the data comparison unit 121 can output a non-inversion signal 1. ​​

[0077] For example, in a case where the most significant bit (MSB) of the first data packet Packet1 is 1 and the least significant bit (LSB) of the second data packet is 1, since the bit values are the same, the data comparison section 121 can output an inversion signal 0 that inverts the least significant bit (LSB) of the second data packet.

[0078] Since the inversion signal 0 is output, the code conversion section 123 can invert the least significant bit (LSB) of the second data packet and convert it to 0 (~B0). The bit generation section 122 can map the conversion information 0 to the I1 position of the indication packet (~P2[B0]).

[0079] Thereafter, the data comparison section 121 can compare the most significant bit (MSB) of the second data packet and the least significant bit (LSB) of the third data packet, and output an inversion signal in a case where the bit values are the same. For example, in a case where the most significant bit (MSB) of the second data packet Packet2 is 1 and the least significant bit (LSB) of the third data packet Packet2 is 0, since the bit values are different, the data comparison section 121 can output a non-inversion signal 1.

[0080] The code conversion section 123 can not invert and maintain the least significant bit (LSB) of the third data packet Packet3 according to the non-inversion signal 1 (B0). The bit generation section 122 can map the conversion information 1 to the I2 position of the indication packet (P3[B0]).

[0081] In the same manner as this, the data comparison section 121 can compare the most significant bit (MSB) of the previous data packet and the least significant bit (LSB) of the current data packet in sequence and output an inversion signal or a non-inversion signal.

[0082] The code conversion section 123 can invert or not invert the bit value of the least significant bit (LSB) of the current data packet according to the inversion signal or the non-inversion signal. The bit generation section 122 can map the conversion information (BI) to the position of the corresponding bit in sequence.

[0083] The least significant bit (LSB) of the indication packet (IDP) can invert and map the bit value 0 of the most significant bit (MSB) of the previous data packet to 1, and the most significant bit (MSB) of the indication packet (IDP) can invert and map the bit value 1 of the least significant bit (LSB) of the first data packet Packet1 of the current data group to 0.

[0084] The conversion information (BI) of the least significant bit (LSB) of the second data packet Packet2 to the eleventh data packet Packet11 can be mapped in sequence between the least significant bit (LSB) and the most significant bit (MSB) of the indication packet (IDP).

[0085] According to an embodiment, since the most significant bit (MSB) of the indication packet is mapped to a value different from the least significant bit (LSB) of the first data packet Packetl, the least significant bit (LSB) of the first data packet Packetl is not encoded. Within the data group, the least significant bits (LSBs) of the remaining ten data packets other than the first data packet Packetl can be inverted or maintained by an XOR operation.

[0086] For example, the data group can be composed of a total of twelve packets including one indication packet and eleven data packets. The indication packet and the data packets are composed of 12 bits, respectively. Accordingly, the total number of bits of the data group can be 144 bits. However, the description of the present application is not limited to this. For example, the data group can be composed of eight packets including one indication packet and seven data packets. In the case where each packet is composed of 8 bits, the total number of bits of the data group can also be 64 bits. According to an embodiment, since the number of packets and the number of bits of the packets are the same, the maximum run length is constantly maintained.

[0087] Referring to Figure 10 Since the encoded data inverts the bit value at the edge point (EP) of the packet, a clock edge can be generated between the packets. Accordingly, all of the maximum run lengths (MRL0~MRL11) between the packets can be the same.

[0088] According to this configuration, regular run lengths can be ensured, thereby having an advantage of being able to optimize clock embedding. In addition, since there is a relatively small overhead, a bit rate can be improved.

[0089] Figure 10 FIG. 4 is a diagram illustrating a decoding process of an embodiment of the present application.

[0090] Referring to Figure 5 The indication packet and the data packets of the data group can be separated, the indication packet can be stored in the indication packet storage unit 221, and the data packets can be stored in the code recovery unit 222. The decoder 220 can invert or non-invert the least significant bits of the data packets according to the conversion information (BI) of the indication packet. The conversion information (BI) can be an indication bit mapped to a bit position.

[0091] Since the bit information of the I1 position in the conversion information (BI) is 0, the decoder can invert the least significant bit (LSB) of the second data packet Packet2 to 1.

[0092] Since the bit information of the I2 position in the conversion information (BI) is 1, the decoder can non-invert the least significant bit (LSB) of the third data packet Packet3 and maintain it as 0.

[0093] Since the bit information of the I3 position in the conversion information (BI) is 0, the decoder can invert the least significant bit (LSB) of the fourth packet Packet4 to 0.

[0094] Since the bit information of the I10 position in the conversion information (BI) is 1, the decoder can non-invert the least significant bit (LSB) of the eleventh packet Packet11 and maintain it to 0.

[0095] The restored data information can be restored to be the same as the original data of Figure 11 According to an embodiment, since decoding is performed using the conversion information stored in the indication packet, an additional memory for decoding is not required.

[0096] Figure 11 FIG. 1 is a diagram showing a data encoding method according to an embodiment of the present application.

[0097] Referring to Figure 4 , the data group can be composed of N packets in total, including one indication packet and N-1 data packets. The data packets can be defined as valid data packets as RGB image data, but embodiments of the present application are not limited thereto. The data packets can also include control data. In the data group, the previous data group, the current data group, and the next data group can be continuously configured.

[0098] The indication packet (IDP) can be N bits. The least significant bit of the indication packet can be a clock bit (CK), a guard bit, or a redundancy bit. The inversion information of each data packet can be mapped in turn after the least significant bit of the indication packet.

[0099] The least significant bit (LSB) of the indication packet can be mapped to a value different from the most significant bit (B(n-1)) of the previous data packet. For example, in the case where the last bit (B(n-1)) of the previous data group is 0, the least significant bit (LSB) of the indication packet can be written as 1. Accordingly, a clock edge can be generated at the boundary between the previous data group and the current data group.

[0100] According to an embodiment, the most significant bit of the indication packet can not invert and write the value of B0 of the least significant bit of the first packet Packet1 within the current data group. In the case where the bit has the same value by comparing B0 of the least significant bit of the first packet Packet1 and I(n-1) of the most significant bit of the indication packet, B0 of the least significant bit of the first packet can be inverted and the conversion information can be mapped to the corresponding bit position (I1) within the indication packet. Accordingly, after the indication packet maps the conversion information at the boundary of each data packet, the last mapped bit is compared with B0 of the least significant bit of the first packet Packet1.

[0101] According to this configuration, the indication packet can include N bits in total, but the remaining bits except the least significant bit (LSB) can be bits for mapping conversion information. In addition, the least significant bits of the data packets can be inverted or non-inverted by the XOR operation. In Figure 7 and Figure 12 , the least significant bit of the first data packet is not subjected to the XOR operation, but in the present embodiment, the least significant bit of the first data packet is also subjected to the XOR operation, which is different.

[0102] Figure 13 is a diagram showing a data encoding method according to another embodiment of the present application. Figure 14 and Figure 15 are diagrams showing a data structure according to another embodiment of the present application. Figure 12 is a diagram showing a first modification example of Figure 16 . Figure 12 is a diagram showing a second modification example of Figure 12 .

[0103] Referring to Figure 13 and Figure 14 , according to the embodiment, the number of packets of a data group can be different from the number of bits of the packets. For example, a first data group can be configured of M packets, and each packet can be configured of N bits. At this time, M and N can be the same or different natural numbers from each other. For example, the number of packets can be greater than the number of bits, and the number of packets can be less than the number of bits. Alternatively, the number of packets and the number of bits can be the same. For example, within a data group, the number of packets can be two, and each packet can be configured of 10 bits.

[0104] According to the embodiment, a data encoding rule in which the number of packets and the bit depth within a data group are set to be different can be provided. Thus, the optimal number of packets and the number of bits can be adjusted according to various conditions such as the type and size of data.

[0105] The data comparison unit 121 can perform the XOR operation on the most significant bit B9 of the first data packet Packetl and the least significant bit B0 of the second data packet and output an inverted signal. The output inverted signal can be stored in the bit position S of the indication packet. The indication packet can be a clock bit (CK). According to the embodiment, since only the boundary of two packets is compared and encoded, it has an advantage that a data group can be generated faster.

[0106] According to the embodiment, the technology is different from the data encoding rule described above, and the maximum run length (MRL) can increase the bit of the indication packet. For example, in the case where the indication packet has a

[00] bit and the immediately preceding data packet has a [1000000000] bit, since 0 appears eleven times in succession, the run length can be lengthened by the bit of the indication packet. In consideration of this, the number of bits can be adjusted appropriately.

[0107] Referring toFigure 15 The first data group can be composed of three data packets, each of which can be composed of 8 bits. The data comparison unit 121 can compare the bits at the boundaries (B7 and B0) of the first and second data packets and the boundaries (B7 and B0) of the second and third data packets and output an inverted signal or a non-inverted signal.

[0108] For example, in the case of RGB data, in the case where each pixel data is 8 bits, the first data group can be composed of three data packets, each of which can be composed of 8 bits. In this case, the first data group can display RGB pixel data.

[0109] Therefore, since the encoder can generate only an inverted signal at the boundaries of the three data packets and generate a data group, encoding can be performed in real time, thereby having an advantage of being able to be driven at high speed. That is, data can be compared at the boundaries of the RGB data and an inverted signal can be generated, and the inverted signal can be mapped at the clock bits S1 and S2. Therefore, it is possible to shorten the physical time required to map data.

[0110] Referring to Figure 16 The least significant bit (LSB) of the indication packet can be generated by inverting the last bit of the previous data group, and the most significant bit (MSB) of the indication packet can be generated by inverting the least significant bit (LSB) of the first data packet Packet1 of the current data group. According to this configuration, since a clock edge is generated at the boundaries of the indication packet and the data packet, it is possible to improve a case where the run length is lengthened due to the indication bit. According to this configuration, the number of bits of the data packet and the number of bits of the indication packet can be different. In addition, the number of data packets and the number of bits of the data packet can be different. Therefore, it is possible to freely change the number of data packets and the number of bits, thereby improving the degree of freedom and achieving high-speed transmission.

[0111] Referring to Figure 17 The number of bits of the indication packet can be made identical to the number of bits of the data packet by inserting redundant bits (D0 to D4) in the indication packet. For example, the indication packet and the data packet can each be composed of 8 bits.

[0112] In addition, the least significant bit (LSB) of the indication packet can be generated by inverting the last bit of the previous data group, and the most significant bit (MSB) of the indication packet can be generated by inverting the least significant bit (LSB) of the first data packet Packet1 of the current data group. In this case, since a clock edge is generated at the boundaries of the indication packet and the data packet, it is possible to secure the maximum run length. According to the embodiment, it is possible to maintain a constant run length while maintaining the degree of freedom of the number of data packets and the bit depth.

[0113] According to the embodiment, adjacent bits at the boundary of the input packet can be XORed and inverted or non-inverted, and the conversion information can be mapped to the packet and transmitted immediately. Therefore, the constitution of an additional counter or data group generation section can be omitted.

[0114] Figure 17 FIG. 4 is a diagram illustrating a decoding process of another embodiment of the present application.

[0115] Referring to FIG. 4, ​ The receiver 200 can extract the conversion information in the clock region of the input first data group, and can invert or non-invert the least significant bit of the data packet according to the conversion information. For example, since the bit information of the S1 position in the mapping data is 0, the least significant bit of the second data packet is inverted to 1, and since the bit information of the S1 position in the mapping data of the next first data group is 1, the least significant bit of the second data packet is non-inverted and maintained as 1.

[0116] The contents of the specification described in the above problems to be solved by the invention, technical solutions for solving the problems, and effects of the invention are not limited to the necessary features of the claims, and the scope of the claims is not limited to the contents described in the specification.

[0117] Although the above embodiments have been described in further detail with reference to the accompanying drawings, the present application is not necessarily limited to these embodiments, and various modifications can be made within the scope of the technical idea of the present application. Therefore, the embodiments disclosed in the present application are not intended to limit the technical idea of the present application, but to explain the technical idea, and the scope of the technical idea of the present application is not limited to these embodiments. Therefore, it should be understood that the above-described embodiments are exemplary in all aspects and are not restrictive.

Claims

1. A data processing apparatus, wherein, include: The first data mapping unit generates a plurality of data packets; as well as An encoder that inverts a portion of the bits in a plurality of the data packets; The encoder includes: The data comparison unit compares the most significant bit of a first data packet and the least significant bit of a second data packet among a plurality of data packets; The code conversion unit, when the most significant bit of the first data packet and the least significant bit of the second data packet have the same value, reverses the least significant bit of the second data packet; and The bit generation unit generates an instruction packet that stores the conversion information of the least significant bit of the second data packet.

2. The data processing apparatus according to claim 1, wherein, When the most significant bit of the first data packet and the least significant bit of the second data packet have different values, the code conversion unit retains the least significant bit of the second data packet.

3. The data processing apparatus according to claim 1, wherein, It also includes a data group generation unit that inserts the instruction packet into a plurality of data packets to generate a plurality of data groups.

4. The data processing apparatus according to claim 3, wherein, Each of the plurality of said data groups has the same number of packets; The number of bits in the instruction packet is the same as the number of data packets in the data group.

5. The data processing apparatus according to claim 4, wherein, The number of bits in the instruction packet is the same as the number of bits in the data packet.

6. The data processing apparatus according to claim 3, wherein, In the data group, the indicator packet has a plurality of bits; The number of bits in the instruction packet differs from the number of the plurality of data packets.

7. The data processing apparatus according to claim 1, wherein, The data comparison unit performs an XOR operation on the most significant bit of the adjacent first data packet and the least significant bit of the second data packet; The code conversion unit reverses or does not reverse the least significant bit of the second data packet based on the XOR operation result.

8. The data processing apparatus according to claim 7, wherein, The bit generation unit stores the result of an XOR operation between the most significant bit of the adjacent first data packet and the least significant bit of the second data packet in the indicator packet.

9. The data processing apparatus according to claim 8, wherein, The instruction packet includes the least significant bit, the most significant bit, and storage bits configured between the least significant bit and the most significant bit; The least significant bit of the indicator packet has a value that inverts the most significant bit of the data packet immediately preceding the indicator packet; The most significant bit of the indicator packet has a value that inverts the least significant bit of the data packet immediately following the indicator packet.

10. A data-driven device, wherein, include: The data receiving unit receives multiple data groups, including instruction packets and multiple data packets; as well as The decoder restores the data packet to its original form. The decoder includes: Indication packet storage unit, which stores the indication packet; as well as Based on the conversion information of the least significant bit of each data packet stored in the instruction packet, the least significant bit of a plurality of data packets is either reversed or not reversed to restore the original data.

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