Three-dimensional semiconductor device and manufacturing method thereof

Abstract

Systems, devices, and methods of manufacture of semiconductor devices are provided. In one aspect, a semiconductor device includes a first semiconductor structure and a second semiconductor structure. The first semiconductor structure includes a memory array. The memory array includes a first memory sub-array and a second memory sub-array stacked in a first direction. The first row of memory cells of the first memory sub-array and the first row of memory cells of the second memory sub-array are coupled to a same bit line. Same bit lines are located in a first direction between the first memory sub-array and the second memory sub-array. The second semiconductor structure includes control circuitry coupled to the memory array. The semiconductor device includes a second via structure coupled to a pad lead-out structure of the second semiconductor structure through the first via structure and the interconnect structure.

Description

Technical Field

[0001] This disclosure relates to semiconductor devices and manufacturing processes for semiconductor devices. Background Technology

[0002] Semiconductor devices can be categorized into non-volatile memory devices (such as flash memory devices) and volatile memory devices (such as dynamic random access memory (DRAM)). Semiconductor memory devices can have different structures, with varying densities of memory cells and lines on the chip. Memory devices typically include a memory array of memory cells and a control circuitry system. The control circuitry system facilitates the operation of the memory array. Summary of the Invention

[0003] This disclosure describes methods, apparatus, systems, and techniques for three-dimensional (3D) semiconductor devices having supervias extending through multiple conductive layers and sharing the same bit lines.

[0004] One aspect of this disclosure features a semiconductor device comprising: a first semiconductor structure including a memory array comprising a first memory subarray and a second memory subarray stacked along a first direction, first row memory cells of the first memory subarray and the first row memory cells of the second memory subarray coupled to the same bit line, the same bit line being located along the first direction between the first row memory cells of the first memory subarray and the first row memory cells of the second memory subarray; a second semiconductor structure stacked with the first semiconductor structure along the first direction, wherein the second semiconductor structure includes an interconnect structure, a pad lead-out structure, a control circuit system coupled to the memory array, and a first via structure coupling the interconnect structure to the pad lead-out structure, the control circuit system being located along the first direction between the interconnect structure and the pad lead-out structure; and a second via structure extending through the first semiconductor structure, the second via structure being coupled to the pad lead-out structure of the second semiconductor structure through the first via structure and the interconnect structure.

[0005] In some implementations, the second via structure extends into the second semiconductor structure and contacts the interconnect structure.

[0006] In some embodiments, the first memory subarray includes a plurality of first memory cells, and the second memory subarray includes a plurality of second memory cells. The first memory cells in the plurality of first memory cells are aligned along a first direction with corresponding second memory cells in the plurality of second memory cells. Each of the first memory cells and the corresponding second memory cells extends along the first direction and includes a transistor and a capacitor, and the transistor is closer to the same bit line along the first direction than the capacitor.

[0007] In some embodiments, the transistor includes a semiconductor body extending along a first direction, and the semiconductor body includes a metal-oxide-semiconductor material.

[0008] In some embodiments, the transistor further includes a first terminal, a second terminal, and a gate terminal, wherein the first terminal is on a first end of the semiconductor body and contacts a bit line, the second terminal is on a second end of the semiconductor body and contacts a capacitor, and the gate terminal is on at least one side of the semiconductor body between the first and second ends of the semiconductor body.

[0009] In some embodiments, the second via structure includes multiple portions, each extending along a first direction, the multiple portions being arranged along a second direction different from the first direction and separated by an interlayer dielectric material, and the interconnect structure including multiple conductive lines, wherein first ends of the multiple portions of the second via structure are coupled to the same interconnect structure, and second ends of the multiple portions of the second via structure are coupled to the same conductive line among the multiple conductive lines of the interconnect structure.

[0010] In some embodiments, the spacing between multiple portions of the second via structure along the second direction is less than or equal to 1 μm.

[0011] In some embodiments, a portion of a plurality of portions of the second via structure along a second direction has a dimension less than or equal to 0.5 μm.

[0012] In some embodiments, the interconnect structure includes a first conductive layer, at least one second conductive layer, and a third conductive layer, wherein the at least one second conductive layer is located between the first conductive layer and the third conductive layer along a first direction, wherein a first end of the first via structure is connected to the first conductive layer, a second end of the first via structure is connected to the third conductive layer, and the conductive material of the first via structure is isolated from the at least one second conductive layer by a dielectric material.

[0013] In some implementations, the dimension of the first via structure along the second direction is less than or equal to 0.5 μm.

[0014] In some embodiments, the first via structure includes a plurality of portions arranged along a second direction, and the spacing between the plurality of portions of the first via structure along the second direction is less than or equal to 1 μm.

[0015] In some embodiments, the second semiconductor structure includes a plurality of first via structures, the plurality of first via structures including a first via structure and an additional first via structure, the additional first via structure coupling an interconnect structure to a control circuit system, a first end of the additional first via structure being aligned with a first end of the first via structure, and a second end of the additional first via structure being aligned with a second end of the first via structure.

[0016] In some embodiments, the second semiconductor structure includes a substrate, an interconnect layer, and a device layer. The interconnect layer includes interconnect structures, and the device layer includes a control circuit system. The interconnect layer and the device layer are located on a first side of the substrate, and the pad lead-out structure is located on a second side of the substrate. The first side and the second side are opposite to each other along a first direction. The through-via structure includes: a first segment extending in the interconnect layer and coupled to the second via structure through the interconnect structure; a second segment extending in the device layer and coupled to the first segment; and a third segment extending in the substrate and coupled to the second segment and the pad lead-out structure at opposite ends of the third segment along the first direction. The second segment is located between the first segment and the third segment along the first direction.

[0017] In some embodiments, the dimension of the second via structure along a second direction different from the first direction is less than or equal to 0.5 μm.

[0018] In some implementations, the second via structure includes tungsten (W).

[0019] In some embodiments, the second semiconductor structure includes a first dielectric layer at the surface of the second semiconductor structure, and the first semiconductor structure includes a second dielectric layer at the surface of the second semiconductor structure, wherein the first dielectric layer is in contact with the second dielectric layer.

[0020] In some embodiments, a memory array of a first semiconductor structure is placed on an interconnect structure of a second semiconductor structure, and the memory array is coupled to the interconnect structure via a conductive via, wherein the conductive via has a first end coupled to the memory array and a second end coupled to the interconnect structure, and the size of the first end of the conductive via along a second direction different from the first direction is greater than the size of the second end of the conductive via.

[0021] In some embodiments, the second semiconductor structure includes one or more first contact structures that extend through the first dielectric layer along a first direction and are isolated from each other in the first dielectric layer, and the first semiconductor structure includes one or more second contact structures that extend through the second dielectric layer along the first direction and are isolated from each other in the second dielectric layer, wherein the first dielectric layer contacts the second dielectric layer along the first direction, and at least one of the one or more first contact structures contacts at least one of the one or more second contact structures, and wherein the memory array is coupled to a control circuitry system through at least one of the one or more first contact structures and at least one of the one or more second contact structures.

[0022] In some embodiments, the second semiconductor structure is coupled to the first semiconductor structure via at least one contact structure, and the at least one contact structure includes at least one of bonding pads, solder bumps, microbumps, or pillars.

[0023] In some embodiments, the memory array is a first memory array, and the first semiconductor structure includes a second memory array, wherein the control circuitry includes a first circuitry and a second circuitry, the first circuitry being coupled to the first memory array and configured to control the first memory array, and the second circuitry being coupled to the first memory array and configured to control the first memory array.

[0024] Another aspect of this disclosure provides a semiconductor device comprising: a plurality of memory devices sequentially stacked along a first direction, wherein the memory devices among the plurality of memory devices include a first pad lead-out structure at a first surface and a second pad lead-out structure at a second surface opposite to the first surface along the first direction, wherein the memory devices include: a first semiconductor structure comprising: (i) a memory array including a first memory subarray and a second memory subarray stacked along the first direction, a first row memory cell of the first memory subarray and a first row memory cell of the second memory subarray coupled to a common bit line, the common bit line being located along the first direction between the first row memory cell of the first memory subarray and the first row memory cell of the second memory subarray; and (ii) the second pad lead-out structure; and a second semiconductor structure stacked along the first direction with the second semiconductor structure, wherein the second semiconductor structure includes an interconnect structure, the first pad lead-out structure, and a control circuitry system coupled to the memory array, wherein the plurality of memory devices are coupled to each other, wherein the first pad lead-out structure contacts a corresponding second pad lead-out structure.

[0025] In some embodiments, the second semiconductor structure includes a first via structure that couples an interconnect structure to a first pad lead-out structure, wherein a memory device among a plurality of memory devices includes: a second via structure extending through a portion of the first semiconductor structure and the second semiconductor structure, the second via structure being coupled to the first via structure via the interconnect structure, and wherein the first pad lead-out structure is coupled to a corresponding second pad lead-out structure via the first via structure and the second via structure.

[0026] In some embodiments, the second via structure includes multiple portions, each extending along a first direction, the multiple portions being arranged along a second direction different from the first direction and separated by an interlayer dielectric material, the interconnect structure including multiple conductive lines, and wherein first ends of the multiple portions of the second via structure are coupled to the same interconnect structure, and second ends of the multiple portions of the second via structure are coupled to the same conductive line among the multiple conductive lines of the interconnect structure.

[0027] In some embodiments, the first memory subarray includes a plurality of first memory cells, and the second memory subarray includes a plurality of second memory cells. The first memory cells in the plurality of first memory cells are aligned along a first direction with corresponding second memory cells in the plurality of second memory cells. Each of the first memory cells and the corresponding second memory cells extends along the first direction and includes a transistor and a capacitor, and the transistor is closer to the same bit line along the first direction than the capacitor.

[0028] In some embodiments, the second semiconductor structure includes one or more first contact structures that extend through the first dielectric layer along a first direction and are isolated from each other in the first dielectric layer, and the first semiconductor structure includes one or more second contact structures that extend through the second dielectric layer along the first direction and are isolated from each other in the second dielectric layer, wherein the first dielectric layer contacts the second dielectric layer along the first direction, and at least one of the one or more first contact structures contacts a corresponding one of the one or more second contact structures, and wherein the memory array is coupled to a control circuitry system through at least one of the one or more first contact structures and at least one of the one or more second contact structures.

[0029] In some embodiments, at least one of the first pad lead-out structure or the second pad lead-out structure includes at least one of a bonding pad, a solder bump, a microbump, or a pillar.

[0030] In some embodiments, the semiconductor device includes a substrate structure including a circuit system and a substrate pad lead-out structure coupled to the circuit system, wherein the plurality of memory devices are sequentially stacked on top of the substrate structure along a first direction, and the plurality of memory devices are coupled to the circuit system of the substrate structure through a first pad lead-out structure, a second pad lead-out structure and a substrate pad lead-out structure.

[0031] Another aspect of this disclosure features a method comprising: forming a memory device including: a first semiconductor structure including a memory array comprising a first memory subarray and a second memory subarray stacked along a first direction, a first row of memory cells of the first memory subarray and a first row of memory cells of the second memory subarray coupled to a common bit line located along the first direction between the first row of memory cells of the first memory subarray and the first row of memory cells of the second memory subarray; and a second semiconductor structure stacked with the first semiconductor structure along the first direction, the second semiconductor structure including a substrate, a control circuit system located on a first side of the substrate, an interconnect structure coupled to the control circuit system, and a first portion of a through-via structure coupled to the interconnect structure and on the first side of the substrate, the first portion of the through-via structure including a first via structure; forming a second via structure extending through the first semiconductor structure, the second via structure coupled to the first via structure through the interconnect structure; and forming a second portion of the through-via structure extending in the substrate and connected to the first portion of the through-via structure.

[0032] In some embodiments, the method includes forming a pad lead-out structure coupled to a first via structure on a second side of a substrate of a second semiconductor structure, wherein a memory array of the first semiconductor structure is coupled to the pad lead-out structure through the first via structure and the second via structure.

[0033] In some embodiments, the method includes: providing a substrate structure comprising a plurality of substrate dies, wherein one of the substrate dies includes a circuit system and a substrate pad lead-out structure coupled to the circuit system; and stacking a memory device on top of the substrate die, wherein the pad lead-out structure contacts the substrate pad lead-out structure.

[0034] In some embodiments, the memory device is a first memory device, and the method includes: forming a plurality of memory devices including the first memory device, the plurality of memory devices including a first via structure and a second via structure; and sequentially stacking the plurality of memory devices on a substrate die along a first direction, the plurality of memory devices being coupled to each other through the first via structure and a corresponding second via structure, the plurality of memory devices being coupled to a circuit system of the substrate structure through the first via structure, the second via structure and a substrate pad lead-out structure.

[0035] In some embodiments, forming a memory device includes: forming a second semiconductor structure including one or more first contact structures that pass through a first dielectric layer and are isolated from each other in the first dielectric layer; forming a first semiconductor structure including one or more second contact structures that pass through a second dielectric layer and are isolated from each other in the second dielectric layer; and stacking the second semiconductor structure and the first semiconductor structure along a first direction, the first dielectric layer contacting the second dielectric layer, and at least one of the one or more first contact structures contacting a corresponding one of the one or more second contact structures, wherein the memory array is coupled to a control circuitry system through at least one of the one or more first contact structures and at least one of the one or more second contact structures.

[0036] Details of one or more embodiments of the subject matter of this disclosure are set forth in the accompanying drawings and the description below. Other features, aspects, and advantages of this subject matter will become apparent from the specification, drawings, and claims. Attached Figure Description

[0037] The accompanying drawings, which are incorporated herein and form part of this disclosure, illustrate various aspects of this disclosure and, together with the description, further serve to explain the principles of this disclosure and enable those skilled in the art to make and use this disclosure.

[0038] Figure 1A A side view of a 3D semiconductor device is shown.

[0039] Figure 1B A schematic diagram of a cross-section of an example 3D memory die is shown.

[0040] Figure 1C A schematic diagram of a cross-section of an example 3D memory die is shown.

[0041] Figure 2A A plan view of an example of a first semiconductor structure for a memory die is shown.

[0042] Figure 2B It shows Figure 2A A cross-sectional view of the memory die along the A-A' axis.

[0043] Figure 2C yes Figure 2A A magnified view of region A of the memory die.

[0044] Figure 2D yes Figure 2A A magnified view of region B of the memory die.

[0045] Figure 2E A cross-sectional view of an example memory array with a first semiconductor structure is shown.

[0046] Figure 3A A schematic diagram of two stacked memory dies is shown.

[0047] Figure 3B A schematic diagram of a semiconductor device having multiple stacked memory dies is shown.

[0048] Figure 3C It shows Figure 3B A cross-sectional view of a semiconductor device.

[0049] Figure 4A A cross-sectional view of another example of a semiconductor device is shown.

[0050] Figure 4B It shows Figure 4A An enlarged view of region A of the semiconductor device.

[0051] Figures 5A to 5C A schematic diagram showing an example of the layout of the control circuitry in the second semiconductor structure of a memory die is provided.

[0052] Figures 6A to 6E Cross-sectional views of examples of semiconductor devices during various stages of the manufacturing process are shown.

[0053] Figures 7A to 7C The die-to-wafer bonding process for forming a chip package is shown.

[0054] Figure 8 A flowchart illustrating an example of a method for forming a semiconductor device is shown.

[0055] Figure 9 A block diagram of a system having one or more semiconductor devices is shown.

[0056] The same reference numerals and names in the various figures indicate the same elements. It should be understood that the various exemplary embodiments shown in the figures are merely illustrative representations and are not necessarily drawn to scale. Detailed Implementation

[0057] In chip packaging (e.g., high-bandwidth memory (HBM)), memory dies can be stacked vertically on a substrate die. The memory can be a DRAM die. Stacked memory devices can share a common interface (e.g., an interposer) for communicating with the processor. In some cases, through-silicon vias (TSVs) can be formed to extend vertically through the corresponding memory device to establish communication between the memory device and the substrate die. TSVs can occupy additional lateral space in the memory die because the aspect ratio of the TSV needs to be lower than certain levels for ease of fabrication. Additionally, in some cases, DRAM memory cells may include vertical channels (e.g., 4F). 2(Memory cell). However, in the fabrication process of DRAM cells with vertical channels, the formation process of the gate structure can be complex. For example, achieving a uniform height of the gate structure may require multiple deposition and etching processes. Furthermore, it may be difficult to penetrate the bottom of the conductive layer to isolate adjacent gate structures. As feature sizes continue to shrink, the process margin for forming word lines may become increasingly tight. Additionally, due to 4F… 2 Cell configuration, the process margin for forming word lines may be limited by bit line layout and / or length. Limited process margins for word lines can further restrict die size scaling. Therefore, forming HBMs with high memory density and large process margins for word lines can be challenging.

[0058] Embodiments of this disclosure provide semiconductor devices and methods for forming such semiconductor devices. In some embodiments, the semiconductor device includes a first semiconductor structure and a second semiconductor structure stacked with the first semiconductor structure. The first semiconductor structure includes a memory array. The memory array includes a first memory subarray and a second memory subarray stacked along a first direction. First row memory cells of the first memory subarray and the first row memory cells of the second memory subarray are coupled to the same bit line. The same bit line is located along the first direction between the first row memory cells of the first memory subarray and the first row memory cells of the second memory subarray. The second semiconductor structure includes an interconnect structure, a pad lead-out structure, a control circuitry coupled to the memory array, and a first via structure coupling the interconnect structure to the pad lead-out structure. The control circuitry is located along the first direction between the interconnect structure and the pad lead-out structure. The semiconductor device includes a second via structure extending through the first semiconductor structure. The second via structure is coupled to the pad lead-out structure of the second semiconductor structure through the first via structure and the interconnect structure.

[0059] Embodiments of this disclosure may provide one or more of the following technical advantages, effects, and / or benefits. For example, the techniques described in this disclosure can increase memory density and reduce word line manufacturing complexity. In some embodiments, two memory cells with vertical channels can be stacked vertically. The stacked memory cells can share the same bit lines disposed vertically between the two memory cells. Sharing bit lines by the upper and lower memory cells can shorten the bit line length. Shortening the bit line length can reduce the resistance-capacitance (RC) constant. The reduction in RC delay can enhance the sensing margin, thereby allowing for faster data operations. Shorter bit lines can also allow for higher array densities. On the other hand, for the same bit line length, the process margin used to form word lines can be increased (e.g., doubled), thereby reducing manufacturing complexity and increasing yield.

[0060] Furthermore, this technology can reduce manufacturing costs (e.g., by 20% or more) by introducing supervias. In some embodiments, supervias can be formed to replace at least a portion of a TSV. Compared to TSVs, which can be formed after the array die is bonded to the control die to form a memory die or after the memory die is bonded to the substrate die, supervias can be formed during the wafer fabrication process. Compared to copper vias that can couple adjacent conductive layers (e.g., back-end metal layers), supervias can have greater depth and extend between non-adjacent conductive layers (e.g., between the top metal (TM) layer and the first metal layer (M1)). Therefore, supervias can form a direct conductive channel between the TM layer and the M1 layer, thereby reducing wiring space that might otherwise be occupied by multiple back-end metal layers. Additionally, supervias can be a replacement for TSVs. Compared to TSVs, which may require additional manufacturing steps, supervias can be formed during the fabrication process of the memory die. For example, supervias can be formed simultaneously in device regions (e.g., for communication within a memory die) and via regions (e.g., for communication with an external die), thereby simplifying the manufacturing process and reducing manufacturing costs.

[0061] The technology can be applied to various types of semiconductor devices, volatile memory devices (e.g., DRAM memory devices), or non-volatile memory (NVM) devices (e.g., NAND flash memory, NOR flash memory, resistive random access memory (RRAM)), phase-change memory (PCM) (e.g., PCRAM), spin-transfer torque (STT)-magnetoresistive random access memory (MRAM), and so on. The technology can also be applied to charge-trapping based memory devices, such as silicon-oxide-nitride-oxide-silicon (SONOS) memory devices and floating-gate based memory devices. The technology can be applied to three-dimensional (3D) memory devices. The technology can be applied to various memory types, such as SLC (single-cell) devices, MLC (multi-cell) devices (e.g., 2-cell devices), TLC (three-cell) devices, QLC (four-cell) devices, or PLC (five-cell) devices. Alternatively or concurrently, the technology can be applied to various types of devices and systems, such as secure digital (SD) cards, embedded multimedia cards (eMMC) or solid-state drives (SSDs), embedded systems, and so on.

[0062] Figure 1AA side view of a 3D semiconductor device 100 according to some embodiments of the present disclosure is shown. The semiconductor device 100 may be a high-bandwidth memory (HBM) device. In this disclosure, the semiconductor device 100 may also be referred to as a semiconductor package or a chip package. The semiconductor device 100 may include memory dies 102-108, a substrate die 112, a computing die 146, and an interposer 148. In this disclosure, the computing die 146 may also be referred to as a controller or processor.

[0063] Each of memory dies 102-108 may include at least one memory array, and each memory array may include a plurality of memory cells. Memory dies 102, 104, 106, and 108 may be DRAM memory dies, NAND memory dies, ferroelectric memory dies, or any other suitable memory dies. In some embodiments, each memory die 102, 104, 106, and 108 includes a vertically stacked memory structure and a control structure. The memory structure may include at least one memory array. The control structure may include control circuitry configured to control the operation of at least one memory array. The control circuitry may include, but is not limited to, data buffers / sensor amplifiers, column decoders / bit line drivers, row decoders / word line drivers, input-output (I / O) circuitry systems, address decoders, row and column address buffers, read / write control logic, row and column decoders, clock generation and control, error correction code (ECC) logic, power management circuitry systems, any combination thereof, or any other suitable circuitry systems. In this disclosure, the term "control circuitry" may be used interchangeably with the term "control circuitry system".

[0064] Memory dies 102-108 and substrate die 112 may be stacked along the Z direction (e.g., sequentially). Substrate die 112 and computing die 146 may be integrated along the X direction at different locations on interposer 148.

[0065] In some embodiments, substrate die 112 includes substrate control circuitry 113 configured to control the operation of memory dies 102, 104, 106, and 108. The substrate control circuitry 113 of substrate die 112 may be coupled to the control circuitry of memory dies 102, 104, 106, and 108 (e.g., in a control substructure). Substrate control circuitry 113 may include at least one of a direct access (DA) port or a PHY interface. The DA port may provide a test channel for memory dies 102-108 in the HBM chip, and the PHY interface may connect the memory device to computing die 146. In some embodiments, base control circuitry 113 includes multiple transistors (e.g., planar transistors and / or 3D transistors). Trench isolation (e.g., shallow trench isolation (STI)) and doped regions (e.g., the well, source, and drain of transistors) may also be formed in substrate die 112. In some examples, complementary metal-oxide-semiconductor (CMOS) technology is used to form substrate control circuitry 113. In some embodiments, the substrate die 112 includes a through-silicon contact (TSC) region 115 having one or more TSCs (also referred to as vias 150) extending through the substrate die 112 in the Z direction. One end of the via 150 can be coupled to the interposer 148 via a conductive terminal 164, while the other end of the via 150 can be coupled to the bottommost memory die 102 via a contact structure 154. In this disclosure, the contact structure may also be referred to as a conductive contact structure.

[0066] The substrate die 112 can be coupled to the computing die 146 via an interposer 148. The interposer 148 has surfaces 158 and 160. Vias 150 in the substrate die 112 can be connected to conductive terminals 164 on surface 158 of the interposer 148. The computing die 146 can be connected to conductive terminals 166 on surface 158 of the interposer 148. The semiconductor device 100 may include conductive terminals 162 connected to surface 160 of the interposer 148. Conductive terminals 164, 166, and / or 162 can be coupled via conductive lines (e.g., conductive lines 169) in the interposer 148. Conductive terminal 162 can be coupled to an external device. In some embodiments, conductive terminals 164, 166, and 162 can be microbumps, solder bumps, bonding pads, copper pillars, or any other suitable structure. It should be understood that in practice, the substrate die 112, the computing die 146, and the interposer 148 can be integrated together using any suitable packaging technology, including, for example, chip-wafer-substrate stack (CoWoS).

[0067] like Figure 1AAs shown, the semiconductor device 100 includes bonding layers (e.g., bonding layers 134, 136, and 138) between adjacent memory dies 102-108, and a bonding layer 140 between memory die 102 and substrate die 112. Each of these bonding layers may include a dielectric material such as silicon oxide. In some embodiments, bonding layers 134, 136, 138, and 140 may be referred to as direct bonding layers. Each of bonding layers 134, 136, 138, and 140 may include at least one dielectric material and does not include conductive bonding contacts.

[0068] In some embodiments, bonding layers 134, 136, 138, and 140 may be referred to as hybrid bonding layers. Hybrid bonding may include a combination of metal-to-metal bonding and direct oxide bonding. Bonding layers 134, 136, 138, and 140 may include at least one dielectric material for contact structures 154, 172, 174, 176, and isolation contact structures. Contact structure 154 may be configured to connect memory die 102 and substrate die 112. Contact structure 172 may be configured to connect memory die 102 and memory die 104. Contact structure 174 may be configured to connect memory die 104 and memory die 106. Contact structure 176 may be configured to connect memory die 106 and memory die 108.

[0069] In some embodiments, the memory die 102 may include an interconnect layer in contact with the bonding layer 140. The interconnect layer may include interconnect conductive structures. The interconnect conductive structures may be coupled to the substrate die 112 via contact structures 154 in the bonding layer 140.

[0070] In some embodiments, each memory die includes a via region 118 configured to transmit electrical signals from and to a substrate die 112. The via region 118 may include a first via structure and a second via structure stacked along the Z-direction. Reference is made below. Figures 2A to 7C The first via structure and the second via structure are described in more detail.

[0071] In some implementations, such as Figure 1A As shown, memory dies 102-106 can have a reduced thickness (along the Z direction) by thinning their substrate. The topmost memory die 108 (e.g., the memory die furthest from the substrate die 112 among memory dies 102-108) may not be thinned. Therefore, the thickness of each of memory dies 102-106 can be less than the thickness of memory die 108. The thickness of each of memory dies 102-108 can be within any suitable range.

[0072] Although not shown, it should be understood that the interposer 148, computing die 146, substrate die 112, and memory dies 102, 104, 106, and 108 can be stacked sequentially along the Z-direction, such that the computing die 146 is located between the substrate die 112 and the interposer 148 along the Z-direction. Similar to the via 150 of the substrate die 112, the computing die 146 may include through-holes extending along the Z-direction through the computing die 146 and coupled to the interposer 148 via corresponding conductive terminals.

[0073] Figure 1B A schematic cross-sectional view of an exemplary 3D memory die 180 according to one or more embodiments of the present disclosure is shown. The 3D memory die 180 represents an example of a bonded chip. The 3D memory die 180 can be implemented as... Figure 1A The memory dies 102, 104, 106, and 108 are used. Components of the 3D memory die 180 (e.g., memory array and peripheral circuitry) may be formed separately on different substrates and then bonded to form a bonded chip. In some embodiments, the memory array includes an array of DRAM memory cells.

[0074] The first semiconductor structure 182 may be a DRAM memory device, wherein memory cells are provided in the form of an array of DRAM memory cells. The memory cells may be organized into pages or fingers, which are then organized into blocks in which each memory cell is electrically coupled to a corresponding bit line (BL) and a corresponding word line (WL). In some embodiments, the memory surface comprises a number of blocks electrically connected via the same bit lines. The first semiconductor structure 182 may include one or more memory surfaces, and the peripheral circuitry required to perform all read / program (write) / erase operations may be included in the second semiconductor structure 184.

[0075] Each DRAM cell may include a transistor and a capacitor coupled to the transistor. A DRAM cell may be a 1T1C cell consisting of one transistor and one capacitor. It should be understood that a DRAM cell may be any suitable configuration, such as a 2T1C cell, a 3T1C cell, etc. The transistor may be a MOSFET for switching the corresponding DRAM cell. In some embodiments, the transistor includes a semiconductor body (in which an active region may form a channel) and a gate structure coupled to the semiconductor body. In some embodiments, the gate structure includes a gate electrode and a gate dielectric located between the gate electrode and the semiconductor body. In some embodiments, the gate dielectric is adjacent to one side of the semiconductor body, and the gate electrode is adjacent to the gate dielectric.

[0076] like Figure 1BAs shown, the 3D memory die 180 may also include a second semiconductor structure 184, which includes peripheral circuitry for the memory array of the first semiconductor structure 182. The peripheral circuitry (also referred to as control and sensing circuitry) may include any suitable digital, analog, and / or mixed-signal circuitry for facilitating the operation of the memory array. For example, the peripheral circuitry may include one or more of page buffers, decoders (e.g., row decoders and column decoders), sense amplifiers, drivers (e.g., word line drivers), I / O circuitry, charge pumps, voltage sources or generators, current or voltage references, any portion (e.g., sub-circuits) of the functional circuitry mentioned above, or any active or passive component of the circuitry (e.g., transistors, diodes, resistors, or capacitors). The peripheral circuitry in the second semiconductor structure 184 utilizes CMOS technology, and for example, it may be implemented using logic processes (e.g., technology nodes such as 90nm, 65nm, 60nm, 45nm, 32nm, 28nm, etc.). As described in detail above and below, consistent with the scope of this disclosure, the technology node used to manufacture the peripheral circuitry in the second semiconductor structure 184 may be higher than 22nm in order to reduce leakage current, maintain a specific voltage level (e.g., 1.2V and above), and reduce cost.

[0077] like Figure 1B As shown, the 3D memory die 180 also includes a bonding interface 186 located vertically (e.g., along the Z-direction) between the first semiconductor structure 182 and the second semiconductor structure 184. In some embodiments, the first semiconductor structure 182 and the second semiconductor structure 184 can be manufactured separately (and in some embodiments in parallel), such that the thermal budget for manufacturing one of the first semiconductor structure 182 and the second semiconductor structure 184 does not limit the process for manufacturing the other of the first semiconductor structure 182 and the second semiconductor structure 184. Furthermore, in contrast to long-distance (e.g., millimeter or centimeter-scale) chip-to-chip data buses on a circuit board (such as a printed circuit board (PCB)), a large number of interconnects can be formed via the bonding interface 186 to form direct, short-distance (e.g., micrometer-scale) electrical connections between the first semiconductor structure 182 and the second semiconductor structure 184, thereby eliminating chip interface latency and achieving high-speed I / O throughput with reduced power consumption. Data transfer between the memory array in the first semiconductor structure 182 and the peripheral circuitry in the second semiconductor structure 184 can be performed via interconnects across the bonding interface 186. By vertically integrating the first semiconductor structure 182 and the second semiconductor structure 184 (e.g., along the Z direction), the chip size can be reduced and the memory cell density can be increased.

[0078] It should be understood that the relative positions of the stacked first semiconductor structure 182 and the second semiconductor structure 184 are not restricted. Figure 1CA schematic cross-sectional view of an example 3D memory die 181 according to one or more embodiments of the present disclosure is shown. The 3D memory die 181 can be implemented as... Figure 1A Any of the memory dies 102, 104, 106, and 108. A second semiconductor structure 184, including peripheral circuitry, is positioned above the first semiconductor structure 182, which includes the memory array. Figure 1B Unlike the 180 3D memory die, in Figure 1C In the 3D memory die 181, a first semiconductor structure 182 including a memory array is located above a second semiconductor structure 184 including peripheral circuitry. However, according to some embodiments, a bonding interface 186 is formed vertically between the first semiconductor structure 182 and the second semiconductor structure 184 in the 3D memory die 181, and the first semiconductor structure 182 and the second semiconductor structure 184 are vertically joined by bonding (e.g., hybrid bonding). Hybrid bonding, also known as "metal / dielectric hybrid bonding," is a direct bonding technique (e.g., forming a bond between surfaces without using an intermediate layer, such as solder or adhesive), and can simultaneously achieve metal-to-metal (e.g., Cu-Cu) bonding and dielectric-to-dielectric (e.g., SiO2-SiO2) bonding). Data transfer between the memory array in the first semiconductor structure 182 and the peripheral circuitry in the second semiconductor structure 184 can be performed via an interconnect spanning the bonding interface 186. In some embodiments, the bonding interface 186 may include a first bonding layer in the first semiconductor structure 182 and a second bonding layer in the second semiconductor structure 184. The first bonding layer may include a first conductive structure isolated by a first insulating material (e.g., SiO2 or other dielectric material). The second bonding layer may include a second conductive structure isolated by a second insulating material (e.g., SiO2 or other dielectric material). For example, depending on actual manufacturing needs, the first and second insulating materials may be the same or different. Each of the second conductive structures may correspond to a first conductive structure in the first conductive structure. Therefore, when the first semiconductor structure 182 and the second semiconductor structure 184 are stacked together, the second conductive structure may contact the corresponding first conductive structure to form a conductive bond (e.g., metal-to-metal bonding) through the bonding interface 186.

[0079] Figure 2A A plan view is shown of an example of a first semiconductor structure 202 of a memory die 200 according to one or more embodiments of the present disclosure. The first semiconductor structure 202 may be implemented as follows: Figure 1B and Figure 1C The first semiconductor structure 182. (e.g.) Figure 2AAs shown, in some embodiments, the first semiconductor structure 202 may include a plurality of memory arrays 206 arranged in a lateral direction (e.g., the X and Y directions). The first semiconductor structure 202 may also include via regions 208 between the plurality of memory arrays 206. See below for reference. Figure 2B As described in further detail, via region 208 may include coupling memory array 206 to a second semiconductor structure (e.g., Figure 1B and Figure 1C The second semiconductor structure 184) is a via structure for the control circuit. The via region 208 can be... Figure 1A The via area is 118. It should be noted that... Figure 2A This is for illustrative purposes only and is not intended to be interpreted in a limiting sense. Other arrangements of the memory array 206 and / or via region 208 may also be implemented. For example, via region 208 may be positioned off-center (e.g., as shown in the image). Figure 1A (As shown). In another example, the via region 208 may be adjacent to the edge of the memory die 200. In other words, the space between the via region 208 and the edge of the memory die 200 may not contain the memory array 206.

[0080] In some implementations, each memory array 206 includes multiple pairs of rows of memory cells 207 arranged along a lateral direction (e.g., the Y direction). For example, in Figure 2A In an example implementation, each memory array 206 may include four pairs of memory cell rows 207. See below for reference. Figure 2B In further detail, each pair 207 of memory cell rows may include two memory cell rows stacked vertically along the Z direction. Each of the two memory cell rows may include a plurality of memory cells arranged along the X direction.

[0081] It should be noted that although each memory array 206 has been Figure 2A The diagram shows four pairs of 207 memory cell rows, but memory array 206 may include any other number of pairs. For example, each memory array 206 may include 216 pairs of memory cell rows, 512 pairs of memory cell rows, 1024 pairs of memory cell rows, 2000 pairs of memory cell rows, 4000 pairs of memory cell rows, or any other suitable number.

[0082] Figure 2B It shows Figure 2A A cross-sectional view of the memory die 200 along the A-A' axis. Figure 2C yes Figure 2A A magnified view of region A of memory die 200. Figure 2D yes Figure 2AAn enlarged view of region B of the memory die 200. For ease of description, reference will be made when describing the structure of the memory die 200. Figures 2B to 2D .

[0083] The memory die 200 may include a first semiconductor structure 202 and a second semiconductor structure 204. The second semiconductor structure 204 may be implemented as follows: Figure 1B and Figure 1C The second semiconductor structure 184. The first semiconductor structure 202 and the second semiconductor structure 204 can be stacked along a vertical direction (e.g., the Z direction).

[0084] The first semiconductor structure 202 may include multiple memory arrays 206. For simplicity, Figure 2B Two memory arrays 206 are shown, arranged laterally (e.g., in the X direction) on opposite sides of a via region 208. In some embodiments, each memory array 206 includes a first memory subarray 216-1 and a second memory subarray 216-2 stacked along the Z direction. The first memory subarrays 216-1 from multiple memory arrays 206 may be positioned at the same or similar vertical levels. Similarly, the second memory subarrays 216-2 from multiple memory arrays 206 may be positioned at the same or similar vertical levels. Generally, in this disclosure, the first memory subarrays 216-1 from multiple memory arrays 206 may be collectively referred to as the upper memory layer 236-U, and the second memory subarrays 216-2s may be referred to as the lower memory layer 236-L. Figure 2B As shown, each memory die 200 may include two memory layers stacked vertically together along the Z direction, such as an upper memory layer 236-U and a lower memory layer 236-L.

[0085] Each memory subarray 216 may include multiple rows of memory cells arranged along the Y direction. Each row of memory cells may include multiple memory cells 224 arranged along the X direction. In this disclosure, the memory cells 224 in the first memory subarray 216-1 may be referred to as first memory cells, and the memory cells 224 in the second memory subarray 216-2 may be referred to as second memory cells.

[0086] The memory cell can be a DRAM memory cell with vertical transistors (e.g., 4F). 2 (Memory unit). Reference Figure 2C In some implementations, each DRAM cell 224 includes a capacitor 228 and at least one transistor 226 (e.g., 1T1C cell, 2T1C cell, 3T1C cell, etc.) coupled to the capacitor 228. Figure 2BThe example implementation illustrates a 1T1C cell. In some implementations, both transistor 226 and capacitor 228 extend in a vertical direction (e.g., the Z direction). Transistor 226 may include a semiconductor body 237 extending in the Z direction. In some implementations, semiconductor body 237 comprises a metal-oxide-semiconductor material. In some implementations, the metal-oxide-semiconductor material comprises indium gallium zinc oxide (IGZO) or indium gallium silicon oxide (IGSO) or a combination thereof. Reference is made below. Figure 2E An example implementation of memory cell 224 is described in more detail.

[0087] Transistor 226 may further include a first terminal 238, a second terminal 239, and a gate terminal 254. The first terminal 238 (e.g., a drain terminal) may be located at a first end of semiconductor body 237 and coupled to bit line 223, and the second terminal 239 (e.g., a source terminal) may be located at a second end of semiconductor body 237 and coupled to capacitor 228. Gate terminal 254 may be located on at least one side of semiconductor body 237 between the first and second ends. The source and drain terminals may be doped with an N+ type dopant (e.g., phosphorus (P) or arsenic (As)) or a P type dopant (e.g., boron (B) or gallium (Ga)) at a desired doping level, or may include silicon germanium (SiGe). Gate terminal 254 may include a gate dielectric layer and a gate electrode. The gate dielectric may be adjacent to at least one side of semiconductor body 237, and the gate electrode may be adjacent to the gate dielectric layer. Depending on how many sides of the semiconductor body 237 the gate terminal 254 can be adjacent to, the gate terminal 254 can be a single-sided gate structure, a double-sided gate structure, a triple-sided gate structure, or a gate all-around (GAA) structure. The gate terminal 254 can be connected to a word line, or a portion of a word line. In some embodiments, the first semiconductor structure 202 does not have a substrate (e.g., a silicon substrate).

[0088] Continue to refer to Figure 2C The first memory subarray 216-1 may include a first row 216-1A of first memory cells extending along the X direction, and the second memory subarray 216-2 may include a first row 216-2A of second memory cells extending along the X direction. The first row 216-1A of the first memory cells may be stacked on and / or aligned with the first row 216-2A of the second memory cells along the Z direction. In this disclosure, the combination of a row of first memory cells in the first memory subarray 216-1 and a corresponding row of second memory cells in the second memory subarray 216-2 may be referred to as a pair 207 of memory cell rows. Each memory array 206 may include multiple pairs 207 of memory cell rows (e.g., Figure 2A The four pairs of 207 shown are illustrated.

[0089] In some implementations, each pair of 207s in a row of memory cells is coupled to a corresponding bit line. For example, as... Figure 2C As shown, the first row 216-1A of the memory cells in the first memory subarray 216-1 and the first row 216-2A of the memory cells in the second memory subarray 216-2 can form a first pair 207-A, and the first pair 207-A can be coupled to the same bit line (e.g., the first bit line 223-1). The first bit line 223-1 can be located along the Z direction between the first row 216-1A of the memory cells in the first memory subarray 216-1 and the first row 216-2A of the memory cells in the second memory subarray 216-2. Similarly, the second pair 207-B of the memory cell rows (e.g., as shown) Figure 2A The bits shown can be coupled to the same bit line (e.g., a second bit line). The second bit line can be separate from the first bit line 223-1. Alternatively, in some embodiments, two or more pairs 207 of the memory cell row are coupled to the same bit line. Sharing bit lines by upper and lower memory cell rows can shorten the bit line length. Shortening the bit line length can reduce the resistance-capacitance (RC) constant. The reduction in RC delay can enhance the sensing margin, thereby allowing for faster data operations. Furthermore, by using the same bit line length, word line processing margin can be improved as described above.

[0090] In some implementations, a first memory cell among a plurality of first memory cells is aligned along the Z-direction with a corresponding second memory cell among a plurality of second memory cells. For example, as... Figure 2C As shown, the first memory cell 224-1 can be in the upper memory layer 236-U, while the corresponding second memory cell 224-2 can be in the lower memory layer 236-L. Both the first memory cell 224-1 and the second memory cell 224-2 can be in the first pair 207-A of the memory cell row. The first memory cell 224-1 can be aligned with the corresponding second memory cell 224-2, and the transistor 226 of the first memory cell 224-1 and the transistor 226 of the second memory cell 224-2 can be located along the Z-direction between the capacitor 228 of the first memory cell 224-1 and the capacitor 228 of the second memory cell 224-2. Here, when the lateral offset of the central axis of the first memory cell is 50% or less, 30% or less, 20% or less, or 5% or less, the first memory cell can be considered aligned with the corresponding memory cell.

[0091] return Figure 2BIn some embodiments, the memory die 200 includes a second via structure 210 extending through the first semiconductor structure 202. The second via structure 210 may be in a via region 208. As described above, the via region 208 may be between memory arrays 206. The second via structure 210 has a first end (e.g., an upper end) and a second end (e.g., a lower end). The first end of the second via structure 210 may be connected to a connection structure 212, and the second end of the second via structure 210 may extend into and couple to an interconnect structure 282 of the second semiconductor structure 204. The connection structure 212 of the first semiconductor structure 202 may be at or above the same level as the memory array 206, and the connection structure 212 may be configured to transmit electrical signals to and from the first semiconductor structure 202. The connection structure 212 may include multiple interconnects (also referred to herein as “contacts”), including lateral conductive lines and VIA contacts. The connection structure may also include one or more interlayer dielectric (ILD) layers, in which conductive lines and via contacts can be formed. That is, connection structure 212 may include conductive lines and via contacts in multiple ILD layers. See below for reference. Figures 6A to 6E In further detail, a second via structure 210 and / or a connection structure 212 may be formed after bonding the first semiconductor structure 202 and the second semiconductor structure 204. In some embodiments, the connection structure 212 includes a first pad lead-out structure 247, and the first pad lead-out structure 247 may be a bonding pad, solder ball, microbump, or pillar.

[0092] In some embodiments, the second via structure 210 includes multiple portions 211 (e.g., in...). Figure 2B The diagram shows two portions of each via structure 210, and each portion 211 extends along the Z direction. Multiple portions 211 can be arranged along the X direction and separated by an interlayer dielectric material 214. Multiple portions 211 in each second via structure 210 can be connected in parallel to each other and act as a single via. For example, the first ends (e.g., upper ends) of multiple portions 211 of the second via structure 210 can be coupled to the same interconnect structure 212, while the second ends (e.g., lower ends) of multiple portions 211 of the second via structure 210 can be coupled to the same conductive lines of the interconnect structure 282 of the second semiconductor structure 204. Without being limited to any particular theory, connecting multiple portions 211 in parallel can reduce contact resistance and improve electrical performance.

[0093] In some embodiments, the spacing 218 of the plurality of portions 211 of the second via structure 210 along the X direction is 0.5 μm or less, 1 μm or less, 2 μm or less, or 5 μm or less. In some embodiments, the dimension 222 of an individual portion 211 of the second via structure 210 along the X direction is 0.3 μm or less, 0.5 μm or less, or 0.7 μm or less. In embodiments where the second via structure 210 includes only a single portion 211, the dimension of the second via structure 210 along the X direction may be 0.3 μm or less, 0.5 μm or less, or 0.7 μm or less. In embodiments where each portion of the second via structure 210 has a different dimension (e.g., the upper end is larger than the lower end), the dimension of each portion 211 along the X direction may refer to the average dimension of each portion along the X direction, or the maximum dimension of each portion along the X direction.

[0094] The second via structure 210 may include a conductive material, including but not limited to W, Co, Cu, Al, doped silicon, silicide, or any combination thereof. In some embodiments, the second via structure 210 includes tungsten (W). The interlayer dielectric material 214 may be formed of a dielectric material including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric, or any combination thereof.

[0095] Continue to refer to Figure 2B The memory die 200 may further include a second semiconductor structure 204 stacked along the Z-direction with the first semiconductor structure 202. In some embodiments, the second semiconductor structure 204 includes a device layer 232 on the front side of the substrate 201. The device layer 232 may include one or more control circuits 284 coupled to the memory array 206. The control circuits 284 may be as described above. Figure 1B and Figure 1CThe peripheral circuitry described. Control circuitry 284 (also referred to as control and sensing circuitry) may include any suitable digital, analog, and / or mixed-signal circuitry for facilitating the operation of memory array 206. For example, control circuitry 284 may include one or more of the following: page buffers, decoders (e.g., row decoders and column decoders), sense amplifiers, drivers (e.g., word line drivers), I / O circuitry, charge pumps, voltage sources or generators, current or voltage references, any portion 211 of the aforementioned functional circuitry (e.g., sub-circuits), or any active or passive component of the circuitry (e.g., transistors, diodes, resistors, or capacitors). Control circuitry 284 in the second semiconductor structure 204 may be implemented using CMOS technology, for example, using logic processes (e.g., technology nodes such as 90nm, 65nm, 60nm, 45nm, 32nm, 28nm, etc.). Substrate 201 may include silicon (e.g., single-crystal silicon, c-Si), silicon-germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), or any other suitable material.

[0096] In some embodiments, the second semiconductor structure 204 includes multiple sets of control circuits 284. Each set of control circuits 284 can be configured to control a corresponding memory array 206. For example, as Figure 2B As shown, the second semiconductor structure 204 may include a first set of control circuits 284-1 and a second set of control circuits 284-2. Different sets of control circuits 284 may be arranged laterally (e.g., along the X direction) and positioned below the corresponding memory array 206. For example, the first set of control circuits 284-1 may be positioned below the first memory array 206-1 and configured to control the first memory array 206-1. Similarly, the second set of control circuits 284-2 may be positioned below the second memory array 206-2 and configured to control the second memory array 206-2. Positioning the control circuits 284 below the corresponding memory array 206 reduces electrical interconnect wiring, thereby reducing resistance and improving device performance.

[0097] The second semiconductor structure 204 may further include an interconnect layer 234 located on the device layer 232. In some embodiments, the interconnect layer 234 may be located between the first semiconductor structure 202 and the device layer 232 along the Z-direction. (Refer to...) Figure 2DInterconnect layer 234 may include interconnect structure 282. Interconnect structure 282 may be configured to transmit electrical signals between memory array 206 of first semiconductor structure 202 and control circuitry 284 of second semiconductor structure 204. In some embodiments, interconnect structure 282 includes a plurality of conductive layers 230 stacked along the Z direction. Each conductive layer 230 may include (i) one or more interlayer dielectric (ILD) layers 246, and (ii) lateral conductive lines 242 and / or VIA contacts 244 extending through ILD layers 246. Lateral conductive lines 242 and VIA contacts 244 may transmit electrical signals. Adjacent conductive lines 242 or VIA contacts 244 may be isolated by ILD layers 246.

[0098] In some embodiments, the interconnect structure 282 includes a first conductive layer 230A, at least one second conductive layer 230B, and a third conductive layer 230C. The at least one second conductive layer 230B may be located between the first conductive layer 230A and the third conductive layer 230C along the Z-direction. For example, the third conductive layer 230C may be a top metal (TM) layer, the first conductive layer 230A may be a first metal (M1) layer, and the at least one second semiconductor layer 230B may be an intermediate layer (e.g., a second metal (M2) layer, etc.). However, the embodiments of the first conductive layer 230A and the third conductive layer 230C are not limited thereto.

[0099] In some embodiments, the VIA contact 244 connects the conductive lines 242 of two adjacent conductive layers 230. For example, as... Figure 2D As shown, the first VIA contact 244-1 can connect the conductive line 242 in the first conductive layer 230A (e.g., layer M1) to the corresponding conductive line 242 in the second conductive layer 230B (e.g., layer M2). In some examples, the VIA contact 244 may not connect the conductive line 242 in non-adjacent conductive layers 230 separated by another conductive layer 230.

[0100] In some embodiments, the second semiconductor structure 204 includes at least one through-via structure 220. In some embodiments, the through-via structure 220 includes a plurality of segments stacked along the Z-direction. In some embodiments, the through-via structure 220 includes: (i) a first segment 220A extending in the interconnect layer 234 and coupled to the second via structure 210 via an interconnect structure 282; (ii) a second segment 220B extending in the device layer 232 and coupled to the first segment 220A; and (iii) a third segment 220C extending in the substrate 201 and coupled to the second segment 220B and a second pad lead-out structure 248 at opposite ends of the third segment 220C along the Z-direction. The second segment 220B may be located between the first segment 220A and the third segment 220C along a first direction. In this disclosure, the first segment 220A of the through-via structure 220 may be referred to as the first via structure 240.

[0101] In some embodiments, the second semiconductor structure 204 includes one or more first via structures 240. The first via structures 240 may be disposed in via regions 208 and / or device regions 209. Via region 208 may refer to a region including via structures 220, while device region 209 may refer to a region including control circuitry 284. In some embodiments, via region 208 is at least partially surrounded by device region 209, such as... Figure 2D As shown, but not limited to, the first via structure 240 in both regions can have the same or similar structure.

[0102] Unlike the VIA contact 244, the first via structure 240 can extend through two or more conductive layers 230. In other words, the first via structure 240 can connect conductive lines 242 in non-adjacent conductive layers 230. For example, as Figure 2D As shown, the first via structure 240-1 can connect the third conductive layer 230C to the first conductive layer 230A. In other words, the first end (e.g., the lower end) of the first via structure 240-1 can be connected to the first conductive layer 230A, and the second end (e.g., the upper end) of the first via structure 240-1 can be connected to the third conductive layer 230C.

[0103] It should be noted that, although Figure 2DThe exemplary embodiment shows a first via structure 240 extending from the third conductive layer 230C to the first conductive layer 230A. However, in some embodiments, the first via structure 240 may extend at different depths within the interconnect layer 234. For example, the first via structure 240 may extend from one of the second conductive layers 230B to the first conductive layer 230A, while another first via structure 240 may extend from the third conductive layer 230C to one of the second conductive layers 230B. In another example, the first via structure 240 may extend from the third conductive layer 230C to a contact 252 (e.g., a source contact, a gate contact, or a drain contact). As described above, the main difference between the first via structure 240 and the VIA contact 244 is that the first via structure 240 may extend through at least two conductive layers 230, thereby connecting conductive lines 242 in non-adjacent conductive layers 230. In some embodiments, the height of the first via structure 240 along the Z-direction is greater than the height of the VIA contact 244 along the Z-direction. In some embodiments, the conductive material (e.g., tungsten, ruthenium) of the first via structure 240 is isolated from the conductive lines 242 of at least one second conductive layer 230B (which extend through the at least one second conductive layer 230B) by a dielectric material (e.g., silicon oxide) in the ILD layer 246.

[0104] When the first via structure 240 is disposed in the via region 208, the first via structure 240 can be a first segment 220A passing through the via structure 220 and configured to transmit electrical signals between the first semiconductor structure 202 and the second semiconductor structure 204. Therefore, the first via structure 240 in the via region 208 can be an alternative to a TSV. When the first via structure 240 is disposed in the device region 209, the first via structure 240 can transmit electrical signals within the second semiconductor structure 204 (e.g., within the interconnect layer 234) or between the interconnect layer 234 and the device layer 232.

[0105] In some embodiments, the first via structure 240 in via region 208 and device region 209 are formed together in the same manufacturing process. Therefore, the upper ends of the first via structure 240 in via region 208 and device region 209 can be aligned. In some embodiments, the lower ends of the first via structure 240 are also aligned. In some other embodiments, the lower ends of the first via structure 240 are not aligned, and it may extend at different depths.

[0106] By forming a first via structure 240 between non-adjacent layers (e.g., between the third conductive layer 230C and the first conductive layer 230A), a vertical interconnect channel can be formed, thereby reducing the wiring space that might otherwise be occupied by multiple back-end metal layers. Additionally, as described above, the first via structure 240 can be an alternative to a TSV. Compared to a TSV, which requires additional manufacturing steps, forming the first via structure 240 together in the device region 209 and the via region 208 simplifies the manufacturing process and reduces manufacturing costs.

[0107] In some implementations, such as Figure 2D As shown, the second segment 220B of the through-hole structure 220 extends in the device layer 232. The second segment 220B of the through-hole structure 220 may be formed together with other contacts 252 that connect the source terminal, drain terminal, or gate terminal of the CMOS transistor to the first conductive layer 230A.

[0108] In some embodiments, a third segment 220C of the through-hole structure 220 extends through the substrate 201 of the second semiconductor structure 204. The third segment 220C of the through-hole structure 220 can connect a second segment 220B of the through-hole structure 220 to a second pad lead-out structure 248 formed on the back side of the substrate 201. The second pad lead-out structure 248 can couple the memory die 200 to an external device (e.g., a controller, a substrate die, or another memory die). Figure 2D As shown, the control circuit 284 can be located between the interconnect structure 282 and the second pad lead-out structure 248 along the Z direction, and the control circuit 284 can be coupled to the second pad lead-out structure 248 through the third segment 220C of the through-hole structure 220.

[0109] Although Figure 2D The exemplary embodiment shown illustrates a through-via structure 220 comprising three segments stacked along the Z direction, but in some embodiments, the through-via structure 220 may include two segments. The first segment 220A of the through-via structure 220 may be a first via structure 240, while the second segment of the through-via structure 220 may extend directly from the first conductive layer 230A to the second pad lead-out structure 248.

[0110] In some embodiments, the second and third segments of the via structure 220, the conductive line 242, and / or the VIA contact 244 comprise conductive materials, including but not limited to W, Co, Cu, Al, doped silicon, silicides, or any combination thereof. In some embodiments, the first via structure 240 comprises tungsten, ruthenium, or a combination thereof, while the VIA contact 244 comprises copper. The ILD layer 246 may be formed of a dielectric material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof.

[0111] In some embodiments, similar to the second via structure 210, the first via structure 240 includes a plurality of portions 221 arranged in the X direction within the via region 208. The plurality of portions 221 may be connected in parallel with each other. In some embodiments, the spacing between the plurality of portions 221 of the first via structure 240 in the X direction is 0.5 μm or less, 1 μm or less, 2 μm or less, or 5 μm or less. In some embodiments, the dimension of each of the plurality of portions 221 of the first via structure 240 in the X direction is 0.3 μm or less, 0.5 μm or less, or 0.7 μm or less. In embodiments where the first via structure 240 includes a single portion 221, the dimension of the first via structure 240 is 0.3 μm or less, 0.5 μm or less, or 0.7 μm or less. In embodiments where each portion of the first via structure 240 has a different size (e.g., the upper end is larger than the lower end), the size of each portion 221 along the X direction may refer to the average size of each portion along the X direction, or the maximum size of each portion along the X direction. In some embodiments, each first via structure 240 includes two portions in the via region 208, while the first via structure 240 includes a single portion in the device region 209.

[0112] In some implementations, return Figure 2B Both the first via structure 240 and the second via structure 210 are located in the via region 208. The second via structure 210 can be stacked on top of the first via structure 240 along the Z-direction. The second via structure 210 can be coupled to the second pad lead-out structure 248 of the second semiconductor structure 204 through at least the first via structure 240 and the interconnect structure 282. In some embodiments, the number of second via structures 210 is equal to the number of first via structures 240. In some embodiments, the number of second via structures 210 is not equal to the number of first via structures 240. In this disclosure, the combination of the first via structure 240 and the second via structure 210 can be referred to as via structure 250.

[0113] In some embodiments, the first semiconductor structure 202 and the second semiconductor structure 204 are bonded by direct bonding. For example, the second semiconductor structure 204 may include a first dielectric layer 261, and the first semiconductor structure 202 may include a second dielectric layer 263 in contact with the first dielectric layer 261. Direct bonding may involve oxide-oxide bonding.

[0114] In some embodiments, the first semiconductor structure 202 and the second semiconductor structure 204 are bonded via conductive contact structures. For example, the first semiconductor structure 202 may include one or more first contact structures 262 isolated by a first dielectric layer 261. The second semiconductor structure 204 may include one or more second contact structures 264 isolated by a second dielectric layer 263. The first contact structures 262 may contact one or more second contact structures 264 to form a hybrid bond. In some embodiments, the bonding process involves an annealing process to allow copper-to-copper connections between the first contact structures 262 and their corresponding second contact structures 264. Therefore, the first contact structures 262 and the second contact structures 264 may form a combined contact structure 260, and the interface between the first contact structures 262 and the second contact structures 264 may be indistinguishable in a real device.

[0115] In some embodiments, the first contact structure 262 and the second contact structure 264 include at least one of a bonding pad, a solder bump, a microbump, or a pillar. In some embodiments, both the first contact structure 262 and the second contact structure 264 include a bonding pad. The first semiconductor structure 202 and the second semiconductor structure 204 can be bonded by hybrid bonding. Hybrid bonding can include a combination of metal-to-metal bonding (e.g., bonding pad to bonding pad) and direct oxide bonding. In some embodiments, the first contact structure 262 is a solder ball, a microbump, or a pillar, while the second contact structure 264 is a bonding pad. In some embodiments, the first contact structure 262 is a bonding pad, while the second contact structure 264 is a solder ball, a microbump, or a pillar.

[0116] Figure 2E A cross-sectional view of an example memory array of the first semiconductor structure 1102 is shown. The first semiconductor structure 1102 can be implemented as follows: Figure 2B The first memory structure 202. It should be understood that, Figure 2E This is for illustrative purposes only and may not necessarily reflect the actual device structure (e.g., interconnection) in practice.

[0117] like Figure 2E As shown, the memory array 1106 includes a first memory subarray 1116-1 and a second memory subarray 1116-2 stacked along the Z direction. The memory array 1106 can be implemented as follows: Figure 2B The memory array 206. The first memory subarray 1116-1 can be implemented as Figure 2B The first memory subarray 216-1. The second memory subarray 1116-2 can be implemented as follows: Figure 2BThe second memory subarray 216-2. As described above, the first memory subarray 1116-1 and the second memory subarray 1116-2 can share the same bit line 1123.

[0118] Each memory subarray 1116 includes a plurality of DRAM cells 1124. Each DRAM cell 1124 may include a vertical transistor 1126 and a capacitor 1128 coupled to the vertical transistor 1126. DRAM cell 1124 may be a 1T1C cell consisting of one transistor and one capacitor. It should be understood that DRAM cell 1124 may be any suitable configuration, such as a 2T1C cell, a 3T1C cell, etc. The vertical transistor 1126 may be a MOSFET for switching the corresponding DRAM cell 1124. In some embodiments, the vertical transistor 1126 includes a vertically (in the z-direction) extending semiconductor body 1130 (in which an active region may form a channel) and a gate structure 1136 contacting at least one side of the semiconductor body 1130. In a single-gate vertical transistor, the semiconductor body 1130 may have a cuboid or cylindrical shape, and the gate structure 1136 may be adjacent to one side of the semiconductor body 1130 in a cross-sectional view, for example, as shown in the figure. Figure 2E As shown. In some embodiments, the gate structure 1136 includes a gate electrode 1134 and a gate dielectric 1132 laterally located between the gate electrode 1134 and the semiconductor body 1130 in the bit line direction (e.g., in the X direction). In some embodiments, the gate dielectric 1132 is adjacent to one side of the semiconductor body 1130, and the gate electrode 1134 is adjacent to the gate dielectric 1132.

[0119] In some embodiments, the gate electrode 1134 includes multiple conductive layers, such as a W layer above a TiN layer. Figure 2E As shown, the gate electrode 1134 comprises two layers: a first gate electrode layer 1134(a) (e.g., TiN) and a second gate electrode layer 1134(b) (e.g., W). The first gate electrode layer 1134(a) may have angled or curved ends, for example, an L-shape in an XZ plane view. The L-shaped gate electrode 1134(a) comprises two portions: a first portion extending along the Z-axis or along an angle of inclination relative to the Z-axis and a second portion extending along the X-axis. Additionally, the second portion of the gate electrode 1134(a) extending along the X-axis may be closer to the bit line or the corresponding capacitor 1128. In some embodiments, the second portion of the gate electrode 1134(a) in the first memory subarray 1116-1 and the second memory array 1116-2 is located at the upper end of the corresponding semiconductor body 130. For example, as... Figure 2EAs shown, the second portion of the gate electrode 1134(a) in the first memory subarray 1116-1 can be located at the upper end of the corresponding semiconductor body 1130 and coupled to the corresponding capacitor 1128. The second portion of the gate electrode 1134(a) in the second memory subarray 1116-1 can also be located at the upper end of the corresponding semiconductor body 1130, but coupled to bit line 1123. In some embodiments, the second portion of the gate electrode 1134(a) in both the first memory subarray 1116-1 and the second memory array 1116-2 is located at the lower end of the corresponding semiconductor body 130.

[0120] It should be understood that the configuration structure of gate structure 1136 is not limited to... Figure 2E Examples are provided, and any suitable structure and configuration can be included, such as a single-sided gate structure, a double-sided gate structure, a triple-sided gate structure, or a gate all-around (GAA) structure.

[0121] like Figure 2E As shown, in some embodiments, the semiconductor body 1130 has two ends in the vertical direction (z-direction). Figure 2E The semiconductor body 1130 has two ends (upper and lower) extending beyond the gate electrode 1134 in the vertical direction (z-direction). In some embodiments, one end of the semiconductor body 1130 is aligned with or coplanar with the corresponding end of the gate electrode 1132. In some embodiments, both ends (upper and lower) of the semiconductor body 1130 extend beyond the gate electrode 1134 in the vertical direction (z-direction). That is, the semiconductor body 1130 may have a larger vertical dimension (e.g., depth) than the vertical dimension (e.g., in the z-direction) of the gate electrode 1134, and the upper and lower ends of the semiconductor body 1130 may not be aligned with the corresponding ends of the gate electrode 1134. Therefore, the risk of short circuits between the bit line 1123 and the word line / gate electrode 1134 or between the word line / gate electrode 1134 and the capacitor 1128 can be reduced. The vertical transistor 1126 may further include a first terminal 1138 and a second terminal 1139, respectively disposed at two opposite ends of the semiconductor body 1130 in the vertical direction (z direction), namely the source and the drain. In some embodiments, the first terminal 1138 is coupled to the capacitor 1128, and the second terminal 1139 is coupled to the bit line 1123.

[0122] In some embodiments, the semiconductor body 1130 comprises a semiconductor material such as indium gallium zinc oxide (IGZO) or indium gallium silicon oxide (IGSO), any other semiconductor material, or any combination thereof. Two memory subarrays 1116-1 and 1116-2 may be sequentially formed on the same substrate. Terminals 1138 and 1139 may be doped with an N+ type dopant (e.g., phosphorus (P) or arsenic (As)) or a P type dopant (e.g., boron (B) or gallium (Ga)) at a desired doping level, or comprise silicon germanium (SiGe).

[0123] In some embodiments, a silicide layer, such as a metal silicide layer, is formed between the second terminal 1139 of the vertical transistor 1126 and the bit line 1123 as a bit line contact, or between the first terminal 1138 of the vertical transistor 1126 and the first electrode of the capacitor 1128 as a capacitor contact, to reduce contact resistance. In some embodiments, the gate dielectric 1132 comprises a dielectric material, such as silicon oxide, silicon nitride, or a high-k dielectric, including but not limited to Al2O3, HfO2, Ta2O5, ZrO2, TiO2, or any combination thereof. In some embodiments, the gate electrode 1134 comprises a conductive material, including but not limited to W, Co, Cu, Al, TiN, TaN, polysilicon, silicides, or any combination thereof. In some embodiments, the gate electrode 1134 comprises multiple conductive layers, such as a W layer above a TiN layer. In one example, the gate structure 1136 may be a "gate oxide / gate polysilicon" gate, wherein the gate dielectric 1132 comprises silicon oxide and the gate electrode 1134 comprises doped polysilicon. In another example, the gate structure 1136 may be an HKMG, wherein the gate dielectric 1132 comprises a high-k dielectric and the gate electrode 1134 comprises a metal. The high-k material may include any material with a dielectric constant greater than or equal to a threshold (e.g., 3.9). In this disclosure, the gate electrode 1134 may also be referred to as word line 1134.

[0124] As described above, since the gate electrode 1134 can be part of a word line or extend as a word line in the word line direction (e.g., the Y direction), the first semiconductor structure 1102 can also include multiple word lines, each extending in the word line direction. Each word line 1134 can be coupled to a row of DRAM cells 1124. That is, the bit line 1123 and the word line 1134 can extend in two perpendicular lateral directions, and the semiconductor body 1130 of the vertical transistor 1126 can extend in a direction perpendicular to the two lateral directions in which the bit line 1123 and the word line 1134 extend. The word line 1134 contacts a word line contact portion. In some embodiments, the word line 1134 includes a conductive material, including but not limited to W, Co, Cu, Al, TiN, TaN, polysilicon, silicide, or any combination thereof. In some embodiments, the word line 1134 includes multiple conductive layers, such as a W layer above a TiN layer, as... Figure 2E As shown in the image.

[0125] In some implementations, such as Figure 2E As shown, the vertical transistor 1126 extends vertically through and contacts the word line 1134, and the second terminal 1139 of the vertical transistor 1126 contacts the bit line 1123 (or the bit line contact portion, if any). Therefore, due to the vertical arrangement of the vertical transistor 1126, the word line 1134 and the bit line 1123 can be arranged in different planes in the vertical direction, which simplifies the wiring of the word line 1134 and the bit line 1123.

[0126] In some implementations, the vertical transistors 1126 can be arranged in a mirror-symmetric manner to increase the density of DRAM cells 1124 in the bit-line direction (X direction). For example... Figure 2EAs shown, two adjacent vertical transistors 1126 in the bit line direction are mirror-symmetrical with respect to the trench isolation region 1160. That is, the first semiconductor structure 1102 may include a plurality of trench isolation regions 1160, each extending parallel to the word line 1134 in the word line direction (Y direction) and disposed between two adjacent rows of vertical transistors 1126. In some embodiments, rows of vertical transistors 1126 separated by the trench isolation regions 1160 are mirror-symmetrical with respect to the trench isolation regions 1160. The trench isolation regions 1160 may be formed of a dielectric material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric, or any combination thereof. It should be understood that the trench isolation regions 1160 may include air gaps, each laterally disposed between adjacent transistors. Air gaps can be formed due to the relatively small spacing of the vertical transistors 1126 in the bit line direction (e.g., the X direction). On the other hand, the relatively large dielectric constant of air in the air gap (e.g., about 4 times that of silicon oxide) compared to some dielectrics (e.g., silicon oxide) can improve the insulation effect between the vertical transistors 1126 (and the rows of DRAM cells 1124). In some embodiments, a conductive material (e.g., a metal such as W) fills the 1180 region between two adjacent semiconductor bodies 130, and the conductive material may be surrounded by a dielectric material such that it is insulated from the semiconductor bodies 130.

[0127] like Figure 2E As shown, in some embodiments, capacitor 1128 includes a first electrode 1144 coupled to a first terminal 1138 of vertical transistor 1126. In some embodiments, the first electrode 1144 is coupled to the first terminal 1138 of vertical transistor 1126 via a capacitor contact. In some embodiments, the capacitor contact is an ohmic contact, such as a metal silicide contact, rather than a Schottky contact. For example, the capacitor contact may include a metal silicide, such as WSi, CoSi, CuSi, AlSi, or any other suitable metal silicide having higher conductivity than doped silicon.

[0128] In some embodiments, capacitor 1128 includes a dielectric structure 1149 that may have a cylindrical shape. A first electrode 1144 covers at least one surface of the dielectric structure 1149. In some embodiments, a first portion of the first electrode 1144 is coupled to a first terminal 1138 of a corresponding vertical transistor 1126 via an ohmic contact (e.g., a capacitor contact made of a metal silicide material). A capacitor body 1145 comprising a dielectric material (e.g., a high-k material) may be deposited on at least a portion of the surface of the first electrode 1144, followed by the deposition of a second electrode 1143. In other words, the capacitor body 1145 is located between the first electrode 1144 and the second electrode 1143, wherein the capacitor body 1145 at least partially covers the first electrode 1144, and the second electrode 1143 at least partially covers the capacitor body 1145. The second electrode 1143 may include one or more metal layers stacked together. In some examples, for example, as Figure 2E As shown, the second electrode 1143 is formed by depositing a first metal layer 1143a (e.g., TiN) on the surface of the capacitor body 1145 and depositing a second metal layer 1143b (e.g., SiGe) on the first metal layer 1143a. One or more support structures 1150 may extend along the X-axis and be distributed between the first electrode 1144 and the second electrode 1143 and / or between the first electrodes 1144 of two adjacent capacitors 1128, for example, as shown. Figure 2E As shown in the image.

[0129] In some embodiments, each first electrode 1144 is coupled to the first terminal 1138 of a corresponding vertical transistor 1126 in the same DRAM cell via a capacitor contact, while all second electrodes are coupled to a common plate 1146 coupled to ground (e.g., common ground).

[0130] It should be understood that the structure and configuration of capacitor 1128 are not limited to... Figure 2E Examples are provided, and any suitable structure and configuration may be included, such as cylindrical capacitors, cup-shaped capacitors, planar capacitors, stacked capacitors, multi-fin capacitors, trench capacitors, or substrate capacitors. In some embodiments, the capacitor body 1145 includes a dielectric material, such as silicon oxide, silicon nitride, or a high-k dielectric, including but not limited to Al2O3, HfO2, Ta2O5, ZrO2, TiO2, or any combination thereof. It should be understood that in some examples, the capacitor 1128 may be a ferroelectric capacitor used in an FRAM cell, and the capacitor body 145 may be replaced by a ferroelectric layer having a ferroelectric material (such as PZT or SBT). In some embodiments, the electrodes include conductive materials, including but not limited to W, Co, Cu, Al, TiN, TaN, polycrystalline silicon, silicides, or any combination thereof.

[0131] Figure 3A A schematic diagram of two stacked memory dies is shown. Figure 3B A schematic diagram of a semiconductor device 300 having multiple stacked memory dies is shown. Figure 3C It shows Figure 3B A cross-sectional view of the semiconductor device 300.

[0132] In some implementations, the semiconductor device includes multiple memory dies. For example, such as Figure 3A As shown, two memory dies can be stacked together. Each memory die can be implemented as... Figures 2A to 2D The memory die 200. As described above, the memory die 200 may include a memory layer having two memory layers (e.g., Figure 2B The first semiconductor structure 202 and the second semiconductor structure 204 (e.g., a control structure) comprise an upper memory layer 236-U and a lower memory layer 236-L. In this disclosure, this configuration may be referred to as a 2A1C configuration. Within each memory die, the control circuitry 284 in the second semiconductor structure 204 can be configured to control the two memory layers in the first semiconductor structure 202. Different memory dies 200 can be led out via corresponding pad structures (e.g., ...). Figure 2B The first pad lead-out structure 247 and the second pad lead-out structure 248 are electrically coupled to each other.

[0133] like Figure 3B and Figure 3C As shown, in some embodiments, the semiconductor device 300 includes four memory dies 302, 304, 306, and 308 stacked on a substrate die 312. The semiconductor device 300 can be implemented as... Figure 1A The semiconductor device 100. Memory dies 302, 304, 306, and 308 can be memory dies 102, 104, 106, and 108, respectively. Each of the memory dies 302, 304, 306, and 308 can be implemented as... Figures 2A to 2D The memory die 200. Each of the memory dies 302, 304, 306, and 308 may include a 2A1C configuration. Although the semiconductor device 300 is described as having four memory dies, any other number of memory dies may be implemented, such as one (e.g., as shown in the image). Figure 2B As shown), 2 (for example, such as) Figure 3A (as shown), 3, 5, 6 or 10.

[0134] In some implementations, multiple memory dies are stacked together by hybrid bonding, as referenced above. Figure 1A and Figures 2A to 2DAs described above, each memory die may include a first pad lead-out structure 347 on the surface of the first semiconductor structure and a second pad lead-out structure 348 on the surface of the second semiconductor structure. Multiple memory dies may be stacked together, wherein the first pad lead-out structure 347 of one memory die contacts the corresponding second pad lead-out structure 348 of an adjacent memory die. Multiple memory dies may be stacked on a substrate die 312, wherein the substrate pad lead-out structure 349 contacts the corresponding first or second pad lead-out structure. Figure 3C As shown, the base pad lead-out structure 349 can contact the corresponding second pad lead-out structure 348. The first pad lead-out structure 347, the second pad lead-out structure 348, and the base pad lead-out structure 349 can be collectively referred to as pad lead-out structures in this disclosure. In some embodiments, the pad lead-out structures include solder balls, microbumps, pillars, or any other suitable bonding technology.

[0135] In some embodiments, the via regions 318 of memory dies 302, 304, 306, and 308 are stacked along the Z-direction, such as... Figure 3C As shown. In other words, the via regions 318 of different memory dies can be substantially aligned, thereby reducing electrical wiring between the via structures 350 of different memory dies. The via structure 350 can be implemented as follows: Figure 2B The via structure is 250. The via region 318 can be implemented as... Figure 1A Via area 118 or Figures 2A to 2D The via region 208. Multiple via structures 350 can be electrically coupled to each other through pad lead-out structures of each memory die, and the via structure 350 can be configured to transmit electrical signals between the substrate die 312 and the corresponding memory die. The pad lead-out structures can be implemented as follows: Figure 1A The conductive terminals are 164, 154, 172, 174, and 176. For simplicity, the details related to... Figure 1A and Figures 2A to 2D A detailed description of the overlapping content.

[0136] Figure 4A Another example of a semiconductor device 400 according to one or more embodiments of the present disclosure is shown. Figure 4B It shows Figure 4A This is an enlarged view of region A of semiconductor device 400. The main difference between semiconductor device 400 and semiconductor device 300 lies in the structure of the memory die. Figure 4A As shown, instead of separately manufacturing the first semiconductor structure and the second semiconductor structure (e.g., Figure 2BEach memory die 402, 404, 406, 408 in the semiconductor device 400 can be formed in a single semiconductor structure. In other words, the first semiconductor structure 420 and the second semiconductor structure 422 in a memory die (e.g., memory die 408) can form an integral part. For example, the first semiconductor structure 420 and the second semiconductor structure 422 are sequentially fabricated on the same substrate 401. Therefore, the memory array 466 of the first semiconductor structure 420 can be directly formed on the interconnect structure 482 of the second semiconductor structure 422 on the front side of the substrate 401.

[0137] In some implementations, the memory array 466 is coupled to the interconnect structure 482 via one or more conductive vias 430. (Reference) Figure 4B In some embodiments, the conductive via 430 has a first end 430A coupled to the memory array 466 and a second end 430B coupled to the interconnect structure 482. The dimension 432 of the first end 430A of the conductive via 430 along the X direction may be larger than the dimension 434 of the second end 430B of the conductive via 430 along the same direction. This feature may differ from the combined contact structure 260 (e.g., annealed bonded contact) at the bonding interface between the first semiconductor structure 202 and the second semiconductor structure 204 of the memory die 200. (Return to Reference) Figure 2B The combined contact structure 260 can have dimensions that gradually increase from one end toward the bonding interface and then gradually decrease toward the other end.

[0138] Forming each of memory dies 402, 404, 406, and 408 may involve sequentially forming the following components on substrate 401: control circuitry 284, interconnect structure 482, and memory array 466. Forming memory array 466 may involve depositing at least one dielectric layer 412 on interconnect structure 482, and then forming memory array 466 in dielectric layer 412. In some embodiments, each transistor in memory array 466 includes a semiconductor body formed using IGZO, IGSO, or a combination thereof. Therefore, a silicon substrate may not be required in the formation of memory array 466.

[0139] Although the manufacturing processes for memory dies differ, the memory array 466 and the via structure 450 (including the first via structure 440) can be substantially similar. Figures 2A to 2D Those in the memory die 200. For the sake of brevity, details related to... Figures 2A to 3C A detailed description of the overlapping content.

[0140] Figures 5A to 5CA schematic diagram illustrating an example layout of the control circuitry in the second semiconductor structure is shown. (See above reference.) Figure 2B The control circuit 284 can be directly disposed below the corresponding memory array 206, thereby reducing the electrical wiring from the control circuit 284 to the corresponding memory array 206, thus reducing manufacturing costs and enhancing device performance. Figures 5A to 5C As shown, region 501 can refer to a physical region located below the corresponding memory array 206. For example, let's temporarily return to... Figure 2B Region 501 may be region 270 below the corresponding first memory array 206-1. A first set of control circuits 284-1 for the first memory array 206-1 may be formed in region 270.

[0141] Return to Figure 5A In some embodiments, sense amplifier (SA) regions 502 are arranged on opposite sides of region 501 along a lateral direction (e.g., the Y direction), while word line driver (WLD) regions 504 may be arranged on opposite sides of region 501 along another lateral direction (e.g., the X direction). Each SA region 502 may include one or more SAs, and each WLD region 504 may include one or more WLDs. Each SA may be configured to control one or more bit lines, and each WLD may be configured to control one or more word lines.

[0142] In some implementations, such as Figure 5B As shown, the SA region 502 is diagonally disposed in the region 501 along the first diagonal direction (e.g., the D1 direction), while the WLD region 504 may be diagonally disposed along the second diagonal direction (e.g., the D2 direction) that intersects the first diagonal direction D1.

[0143] In some implementations, such as Figure 5C As shown, WLD region 504 is arranged in the central portion of region 501, while SA region 502 may be arranged on the opposite side of WLD region 504 (e.g., along the Y direction).

[0144] It should be noted that Figures 5A to 5C This is for illustrative purposes only and is not intended to be interpreted in a limiting sense. Any other suitable arrangement of WLD area 504 and SA area 502 may be implemented, for example, inside and / or outside area 501.

[0145] Figures 6A to 6E A cross-sectional view of an example of a semiconductor device 600 during various stages of the manufacturing process is shown. The semiconductor device 600 may include a memory die 650 and a substrate die 612 (e.g., as shown in the image). Figure 6E (As shown). The memory die 650 can be... Figure 1Amemory die 102, Figure 1B 3D memory die 180, Figure 1C 3D memory die 181, Figures 2A to 2D memory die 200 or Figure 3C The memory die 302.

[0146] like Figure 6A As shown, a first semiconductor structure 602 and a second semiconductor structure 604 can be fabricated separately. The first semiconductor structure 602 may include a memory array 606, wherein a shared bit line is disposed along the Z-direction between an upper memory subarray 616-1 and a lower memory subarray 616-2. The memory array 606 may be formed on a first substrate 601. The second semiconductor structure 604 may include control circuitry 684 configured to control the memory array 606. The control circuitry 684 may be formed on a second substrate 661. The first substrate 601 and / or the second substrate 661 may include silicon (e.g., single-crystal silicon, c-Si), silicon-germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), or any other suitable material.

[0147] The formation of the first semiconductor structure 602 and the second semiconductor structure 604 can involve a variety of processes, including but not limited to photolithography, dry / wet etching, thin film deposition, thermal growth, implantation, chemical mechanical polishing (CMP) and any other suitable process.

[0148] In some embodiments, forming the second semiconductor structure 604 includes forming a first via structure 640 extending in the interconnect structure 682. Forming the first via structure 640 may involve the following process steps: (i) forming a plurality of conductive layers 230 on the control circuit 684, wherein each conductive layer 630 may include one or more conductive lines 642 separated by a dielectric material (e.g., ILD layer 646); (ii) forming an upper dielectric layer that will later be used to form an upper conductive layer 630C on top of the plurality of conductive layers 630; (iii) forming a hard mask (e.g., titanium nitride) on the upper ILD layer to define the upper via pattern and the conductive line pattern; (iv) etching to form a first via structure hole and trench for the conductive lines, wherein the first via structure hole extends through the upper ILD layer and at least one conductive layer 630, and the trench extends in the upper ILD layer; and (v) depositing a conductive material (e.g., tungsten, ruthenium) into the first via structure hole and trench to form the first via structure 640 and the upper conductive layer 630C, respectively.

[0149] In some embodiments, the plurality of conductive layers 630 include a first conductive layer 630A (e.g., M1) and a second conductive layer 630B (e.g., M2) stacked on M1. The upper ILD layer may be a third ILD layer (e.g., ILD3). The upper conductive layer 630C may be a third conductive layer (e.g., M3). A first via structure hole may extend from the upper surface of ILD3 to the upper surface of M1. The first via structure 640 and M3 may be formed together. Therefore, the first via structure 640 and M3 may have the same material (e.g., ruthenium).

[0150] In some embodiments, the first via structure 640 is formed in both the device region 607 and the via region 608, as referenced above. Figures 2A to 2D As described above. In some embodiments, a second segment 620B is also formed through the through-hole structure 620, which is connected to the first through-hole structure 640, as shown. Figure 6A As shown. The second segment 620B of the through-hole structure 620 can be formed before the formation of the first through-hole structure 640. The second segment 620B of the through-hole structure 620 can be, but is not limited to, TiN, TaN, Al, W, Cu, doped polysilicon, silicides, or any combination thereof. In this disclosure, the combination of the first through-hole structure 640 and the second segment 620B of the through-hole structure 620 can be referred to as the first portion 620-1 of the through-hole structure 620.

[0151] Continue to refer to Figure 6A The first semiconductor structure 602 and the second semiconductor structure 604 can be bonded to couple the control circuitry 684 to the memory array 606. In some embodiments, as described above, hybrid bonding is used to bond the first semiconductor structure 602 and the second semiconductor structure 604. In some embodiments, the first semiconductor structure 602 and the second semiconductor structure 604 are bonded using solder balls, pillars, or microbumps.

[0152] like Figure 6B As shown, the second substrate 661 of the second semiconductor structure 604 can be thinned, for example, by a polishing process, to reduce its thickness. Polishing processes may include, but are not limited to, chemical mechanical polishing (CMP), mechanical polishing, electrochemical polishing, ultrasonic polishing, or any combination thereof.

[0153] like Figure 6CAs shown, the third segment 620C of the through-hole structure 620 can be formed to extend through the thinned second substrate 661. In this disclosure, the third segment 620C of the through-hole structure 620 can be referred to as the second portion 620-2 of the through-hole structure 620. The second portion 620-2 of the through-hole structure 620 can be stacked on the first portion 620-1 of the through-hole structure 620 along the Z-direction. The second portion 620-2 of the through-hole structure 620 can be, but is not limited to, TiN, TaN, Al, W, Cu, doped polysilicon, silicides, or any combination thereof.

[0154] The second pad lead-out structure 648 may be formed on the back side of the second substrate 661 and coupled to the second portion 620-2 of the through-hole structure 620. The second pad lead-out structure 648 may extend through the dielectric layer 649 deposited on the back side of the second substrate 661. The second pad lead-out structure 648 may be configured to transmit electrical signals from the second semiconductor structure 604 to the second semiconductor structure. The second pad lead-out structure 648 may include, but is not limited to, TiN, TaN, Al, W, Cu, doped polysilicon, silicide, or any combination thereof.

[0155] like Figure 6D As shown, the memory die 650 can then be bonded to the substrate die 612. The substrate die 612 can be... Figure 1A The base die 112 or Figure 3C The substrate die 612 may include at least one of a direct access (DA) port, a PHY interface, and / or a power supply unit. The substrate die 612 may also include a substrate pad lead-out structure 688 on its upper surface. Bonding the memory die 650 to the substrate die 612 may involve aligning the second pad lead-out structure 648 of the second semiconductor structure 604 with the substrate pad lead-out structure 688 of the substrate die 612, and then annealing the second pad lead-out structure 648 and the substrate pad lead-out structure 688 to form a Cu-Cu bond. The control circuitry 684 in the second semiconductor structure 604 may be electrically coupled to the substrate die 612 via the corresponding second pad lead-out structure 648 and substrate pad lead-out structure 688.

[0156] like Figure 6EAs shown, the first substrate 601 can be removed. A second via structure 610 can be formed to extend through the first semiconductor structure 602. Forming the second via structure 610 may involve etching the second via through the first semiconductor structure 602, followed by depositing a conductive material into the second via. The conductive material of the second via structure 610 includes, but is not limited to, W, Co, Cu, Al, TiN, TaN, polysilicon, or any combination thereof. The first via structure 640 and the second via structure 610 may have the same or different conductive materials.

[0157] In some implementations, such as Figure 6E As shown, the second via structure 610 can extend into the second semiconductor structure 604 and contact the interconnect structure 682 of the second semiconductor structure 604. Therefore, the first via structure 640 and the second via structure 610 can be coupled through the interconnect structure 682 of the second semiconductor structure 604.

[0158] In some embodiments, the second via structure 610 extends within the first semiconductor structure 602 and connects to the first contact structure 662 at the lower surface of the first semiconductor structure 602. Then, the first contact structure 662 of the first semiconductor structure 602 can contact a corresponding second contact structure 664 at the upper surface of the second semiconductor structure 604. The second contact structure 664 can be coupled to the first via structure 640. Therefore, the first via structure 640 and the second via structure 610 can be coupled at the bonding interface via the first contact structure 662 and the second contact structure 664.

[0159] Continue to refer to Figure 6E The connection structure 613 and the first pad lead-out structure 647 can be formed on the second via structure 610. The first pad lead-out structure 647 of the first semiconductor structure 602 can be formed using a similar process to the second pad lead-out structure 648 of the second semiconductor structure 604, as described above. The first pad lead-out structure 647 can be coupled to the second pad lead-out structure 648 through the second via structure 610 and the first via structure 640.

[0160] At this stage of the process, the first semiconductor structure 602 can be Figure 1A and Figure 1B The first semiconductor structure 182, Figures 2A to 2D First semiconductor structure 202 or Figure 3C The first semiconductor structure 322. The second semiconductor structure 604 can be... Figure 1A and Figure 1B The second semiconductor structure 184 Figures 2A to 2D The second semiconductor structure 204 or Figure 3CThe second semiconductor structure 324. The first semiconductor structure 602 and the second semiconductor structure 604 can form a memory die 650. The memory die 650 and the substrate die 612 can form a semiconductor device 600.

[0161] Figures 7A to 7C The die-to-wafer bonding process for forming chip package 700 is illustrated. For example... Figure 7A As shown in schematic diagram (a), a substrate die 712 can be provided in a wafer configuration. Wafer 702 may include multiple substrate dies 712. Wafer 702 may be stacked on an interposer 748 (e.g., Figure 1A The interposer 748 is placed above the substrate 706. The interposer 748 may have surface bonding contacts 764 coupled to the substrate die 712 to form an electrical communication channel. In some embodiments, the interposer 748 is stacked above the substrate 706.

[0162] like Figure 7B As shown, a single memory die 750 can be stacked on top of a corresponding substrate die 712. The memory die 750 can be... Figure 1A memory die 102, Figure 1B 3D memory die 180, Figure 1C 3D memory die 181, Figures 2A to 2D Memory die 200, Figure 3C memory die 302 or Figure 6E The memory die 750. Stacking the memory die 750 on top of the substrate die 712 may involve bonding contact structures (e.g., pad lead-out structures 749 of the memory die 750) to corresponding contact structures (e.g., substrate pad lead-out structures 722) of the substrate die 712. Since the substrate die 712 is provided in a wafer configuration, bonding the memory die 750 to the substrate die 712 may be referred to as a die-to-wafer bonding process in this disclosure.

[0163] like Figure 7C As shown, after the first memory die 750 is stacked on top of the base die 712, additional memory dies 750 can be sequentially stacked on top of the first memory die 750 along the Z direction, for example, to increase storage capacity. Figure 7C Schematic diagram (a) shows that four memory dies 750 can be stacked on a base die 712, and Figure 7C Schematic diagram (b) shows that two memory dies 750 can be stacked on the base die 712. It should be noted that... Figure 7C The examples in this paper are not intended to be interpreted in a limiting sense. Any other number of memory dies 750 can be implemented in the chip package 700.

[0164] After stacking multiple memory dies 750 onto a substrate die 712, the wafer can be diced into multiple slabs, each slab comprising a single substrate die 712 and multiple memory dies 750 vertically stacked on the substrate die 712. Each cell can be Figure 1A The semiconductor device 100. In some embodiments, the cutting process includes, but is not limited to, laser cutting, blade cutting, plasma cutting, mechanical stamping cutting, or laser-assisted waterjet cutting.

[0165] Die-to-wafer bonding technology can offer several advantages. For example, a known good memory die 750 (e.g., a pre-tested functional die) can be used to form a chip package 700 by vertically and sequentially stacking it on a substrate die 712. Compared to wafer-to-wafer bonding, attaching only good memory dies 750 to a wafer during the bonding process can significantly improve the yield of the chip package 700, as the wafer may include defective dies. Die-to-wafer bonding can allow heterogeneous integration, where the stacked dies can be different. For example, the stacked dies may include memory dies 750 and controllers. In another example, the stacked dies may include DRAM dies and NAND dies.

[0166] Figure 8 A flowchart illustrating an example of a method 800 for forming a semiconductor device is shown. The semiconductor device can be, for example... Figure 1A Semiconductor device 100 Figure 1B 3D memory die 180, Figure 1C 3D memory die 181, Figures 2A to 2D Memory die 200, Figure 3C Semiconductor device 300, Figure 4A Semiconductor device 400, Figures 6A to 6E Semiconductor device 600 or Figures 7A to 7C The chip is packaged in 700.

[0167] At step 802, a memory device is formed. The memory device includes: (i) a first semiconductor structure including a memory array, wherein the memory array includes a first memory subarray and a second memory subarray stacked along a first direction, first row memory cells of the first memory subarray and the first row memory cells of the second memory subarray being coupled to the same bit line, and the same bit line being located along the first direction between the first row memory cells of the first memory subarray and the first row memory cells of the second memory subarray; and (ii) a second semiconductor structure stacked with the first semiconductor structure along the first direction, wherein the second semiconductor structure includes a substrate, a control circuit system located on a first side of the substrate, an interconnect structure coupled to the control circuit system, and a first portion of a through-hole structure coupled to the interconnect structure and located on the first side of the substrate. The first portion of the through-hole structure includes a first via structure. The memory device may be, for example, Figure 1A Any one of the memory chips 102, 104, 106, and 108 Figure 1B 3D memory die 180, Figure 1C 3D memory die 181, Figures 2B to 2D Memory die 200, Figure 3C Any one of the memory chips 302, 304, 306, and 308 Figure 4A Any one of the memory chips 402, 404, 406, and 408 Figures 6A to 6E memory die 650 or Figures 7A to 7C The memory die 750. The first semiconductor structure can be, for example... Figure 1B and Figure 1C The first semiconductor structure 182, Figures 2B to 2D and Figure 3A First semiconductor structure 202 Figure 3C First semiconductor structure 322 Figure 4A First semiconductor structure 420 Figures 6A to 6E The first semiconductor structure 602 or Figure 7B and Figure 7C The first semiconductor structure 772. The memory array can be, for example... Figures 2A to 2D Memory array 206 Figure 3C Memory array 366, Figure 4A Memory array 466, Figures 6A to 6E Memory array 606 or Figures 7B to 7C The memory array 766. The first memory subarray can be, for example... Figures 2B to 2D The first memory subarray is 216-1. The second memory subarray can be, for example... Figures 2B to 2D The second memory subarray 216-2. The first row of memory cells in the first memory subarray can be, for example... Figures 2B to 2DThe first row 216-1A of the first memory cell in the first memory subarray 216-1. The first row of memory cells in the second memory subarray can be, for example... Figures 2B to 2D The first row 216-2A of the first memory cell of the second memory subarray 216-2. Bit lines can be, for example... Figure 2B Bit line 223. The second semiconductor structure can be, for example... Figure 1B and Figure 1C The second semiconductor structure 184 Figures 2B to 2D and Figure 3A The second semiconductor structure 204 Figure 3C The second semiconductor structure 324 Figure 4A The second semiconductor structure 422 Figures 6A to 6E The second semiconductor structure 604 or Figure 7B and Figure 7C The second semiconductor structure 774. The substrate can be, for example... Figures 2B to 2D substrate 201 or Figures 6A to 6E The second substrate 661. The interconnect structure can be, for example... Figures 2B to 2D Interconnection structure 282, Figure 4A Interconnection structure 482 or Figures 6A to 6E The interconnect structure 682. The through-hole structure can be, for example... Figures 2B to 2D 220 or through-hole structure Figures 6A to 6E The through-hole structure 620. The first through-hole structure can be, for example... Figures 2B to 2D First via structure 240 Figure 3C First via structure 340 Figure 4A First via structure 440 or Figures 6A to 6E The first via structure is 640.

[0168] In step 804, a second via structure extending through the first semiconductor structure is formed. The second via structure is coupled to the first via structure via an interconnect structure. The second via structure can be, for example... Figures 2B to 2D Second via structure 210 Figure 3C Second via structure 310 Figure 4A The second via structure 410 or Figure 6E The second via structure 610.

[0169] In step 806, a second portion of the through-hole structure is formed, extending in the substrate and coupled to the first portion of the through-hole structure. The first portion of the through-hole structure may be, for example... Figures 6A to 6E The first part of the through-hole structure 620-1. The second part of the through-hole structure can be, for example... Figures 6C to 6E The second part of the through-hole structure 620-2.

[0170] In some embodiments, method 800 includes: forming a pad lead-out structure coupled to a first via structure on a second side of a substrate of a second semiconductor structure, wherein a memory array of the first semiconductor structure is coupled to the pad lead-out structure through the first via structure and a second via structure; providing a substrate structure including a plurality of substrate dies, wherein one of the substrate dies includes a circuit system and a substrate pad lead-out structure coupled to the circuit system; and stacking memory devices on top of the substrate dies, wherein the pad lead-out structure contacts the substrate pad lead-out structure. The substrate structure may be, for example... Figures 7A to 7C The 702 chip. The substrate pad lead-out structure can be, for example... Figure 3C Base pad lead-out structure 349, Figures 6D to 6E The base pad lead-out structure 688 or Figure 7B and Figure 7C The base pad lead-out structure 722. The pad lead-out structure can be, for example... Figures 2B to 2D The second pad lead-out structure 248, Figure 3C The second pad lead-out structure 348, Figures 6C to 6E The second pad lead-out structure 648, or Figures 7B to 7C The second pad leads out of structure 749.

[0171] In some embodiments, the memory device is a first memory device. Method 800 includes: forming a plurality of memory devices including the first memory device, wherein the plurality of memory devices includes a first via structure and a second via structure; and sequentially stacking the plurality of memory devices on a substrate die along a first direction. The plurality of memory devices are coupled to each other through the first via structure and a corresponding second via structure. The plurality of memory devices are coupled to a circuit system of the substrate structure through the first via structure, the second via structure, and substrate pad lead-out structures, such as... Figures 1A to 7C As shown.

[0172] In some embodiments, forming a memory device includes: forming a second semiconductor structure including one or more first contact structures that pass through a first dielectric layer and are isolated from each other in the first dielectric layer; forming a first semiconductor structure including one or more second contact structures that pass through a second dielectric layer and are isolated from each other in the second dielectric layer; and stacking the second semiconductor structure and the first semiconductor structure along a first direction. The first dielectric layer is in contact with the second dielectric layer. At least one of the one or more first contact structures is in contact with a corresponding one of the one or more second contact structures. The memory array is coupled to a control circuitry system via at least one of the one or more first contact structures and at least one of the one or more second contact structures, as referenced above. Figures 1A to 7C As described.

[0173] Figure 9A block diagram of a system 900 having one or more semiconductor devices (e.g., memory devices) according to one or more embodiments of this disclosure is shown. System 900 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having a storage device therein. Figure 9 As shown, system 900 may include a host device 908 and a memory system 902 having one or more 3D memory devices 904 and a memory controller 906. The host device 908 may include a processor of an electronic device, such as a central processing unit (CPU), or a system-on-a-chip (SoC), such as an application processor (AP). The host device 908 may be configured to send data to or receive data from one or more 3D memory devices 904.

[0174] 3D memory device 904 can be any 3D memory device disclosed herein, such as Figure 1A Any one of the memory chips 102, 104, 106, and 108 Figure 1B 3D memory die 180, Figure 1C 3D memory die 181, Figures 2B to 2D Memory die 200, Figure 3C Any one of the memory chips 302, 304, 306, and 308 Figure 4A Any one of the memory chips 402, 404, 406, and 408 Figures 6A to 6E memory die 650, or Figures 7A to 7C The memory die 750.

[0175] In some embodiments, the 3D memory device 904 includes NAND flash memory. A memory controller 906 (also referred to as controller circuitry) is coupled to the 3D memory device 904 and the host device 908. Consistent with embodiments of this disclosure, the 3D memory device 904 may include a plurality of conductive interconnects passing through a cover layer that contact conductive pads in a conductive pad layer, and the memory controller 906 may be coupled to the 3D memory device 904 via at least one of the plurality of conductive interconnects. The memory controller 906 is configured to control the 3D memory device 904. For example, the memory controller 906 may be configured to operate a plurality of channel structures via word lines. The memory controller 906 may manage data stored in the 3D memory device 904 and communicate with the host device 908.

[0176] In some embodiments, the memory controller 906 is designed / configured to operate in low duty cycle environments, such as Secure Digital (SD) cards, Compact Flash (CF) cards, Universal Serial Bus (USB) flash drives, or other media used in electronic devices such as personal computers, digital cameras, mobile phones, etc. In some embodiments, the memory controller 906 is designed / configured to operate in high duty cycle environments, such as SSDs or embedded multimedia cards (eMMCs) used as data storage devices in mobile devices such as smartphones, tablets, laptops, etc., and enterprise storage arrays. The memory controller 906 can be configured to control the operation of the 3D memory device 904, such as read, erase, and program (or write) operations. The memory controller 906 can also be configured to manage various functions regarding data stored or to be stored in the 3D memory device 904, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some implementations, the memory controller 906 is also configured to process error correction codes (ECC) regarding data read from or written to the 3D memory device 904. The memory controller 906 may also perform any other suitable function, such as formatting the 3D memory device 904.

[0177] The memory controller 906 can communicate with external devices (e.g., host device 908) according to a specific communication protocol. For example, the memory controller 906 can communicate with external devices through at least one of various interface protocols, such as USB protocol, MMC protocol, Peripheral Component Interconnect (PCI) protocol, Fast PCI (PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial-ATA protocol, Parallel-ATA protocol, Small Computer Small Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, Integrated Drive Electronics (IDE) protocol, FireWire protocol, etc.

[0178] The memory controller 906 and one or more 3D memory devices 904 can be integrated into various types of storage devices, for example, included in the same package, such as a Universal Flash Memory (UFS) package or an eMMC package. That is, the memory system 902 can be implemented and packaged into different types of end electronic products. Figure 9 In one example shown, the memory controller 906 and a single 3D memory device 904 can be integrated into the memory card 902. The memory card 902 may include PC cards (PCMCIA, Personal Computer Memory Card International Association), CF cards, Smart Media (SM) cards, Memory Sticks, Multimedia Cards (MMC, RS-MMC, MMCmicro), SD cards (SD, miniSD, microSD, SDHC), UFS, etc.

[0179] The subjects and embodiments of action and operation described in this disclosure can be implemented in digital electronic circuit systems, in tangibly embodied computer software or firmware, or in computer hardware, including the structures disclosed in this disclosure and their structural equivalents, or combinations thereof. Embodiments of the subjects described in this disclosure can be implemented as one or more computer programs, for example, one or more modules of computer program instructions encoded on a computer program carrier for execution by or control of the operation of a data processing device. The carrier can be a tangible, non-transitory computer storage medium. Alternatively or additionally, the carrier wave can be an artificially generated propagation signal, such as a machine-generated electrical, optical, or electromagnetic signal, generated to encode information for transmission to a suitable receiver device for execution by the data processing device. The computer storage medium can be a machine-readable storage device, a machine-readable storage substrate, a random or serial access memory device, or a combination thereof, or a portion thereof. The computer storage medium is not a propagating signal.

[0180] Note that references to "an embodiment," "embodiment," "example embodiment," "some embodiments," "some implementations," "one implementation," "implementation," "example implementation," etc., in this disclosure indicate that the described embodiments may include specific features, structures, or characteristics, but each embodiment may not necessarily include that specific feature, structure, or characteristic. Furthermore, such phrases do not necessarily refer to the same embodiment. Additionally, when a specific feature, structure, or characteristic is described in connection with an embodiment, whether explicitly described or not, incorporating other implementations to affect such feature, structure, or characteristic will be within the knowledge of those skilled in the art.

[0181] Generally, terms can be understood at least partly from their use in context. For example, depending at least partly on the context, the term "one or more" as used herein can be used to describe any feature, structure, or characteristic in a singular sense, or it can be used to describe a combination of features, structures, or characteristics in a plural sense. Similarly, terms such as "a," "an," or "the" can also be understood to convey either a singular or a plural usage, depending at least partly on the context. Furthermore, the term "based on" can be understood not necessarily to convey an exclusive set of factors, but rather to allow for the presence of additional factors that are not necessarily explicitly described, again depending at least partly on the context.

[0182] It should be readily understood that the meanings of “on,” “above,” and “on top of” in this disclosure should be interpreted in the broadest possible sense, such that “on” means not only “directly on” but also includes “on” with an intermediate feature or layer in between. Furthermore, “above” or “on top of” means not only “above” or “on top of” but can also include its meaning of “above” or “on top of” without an intermediate feature or layer (i.e., directly on).

[0183] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” are used herein to describe the relationship between one element or component and one or more other elements or components, as shown in the figures. In addition to the orientations shown in the figures, the spatial relative terms are intended to cover different orientations of the apparatus during use or process steps. The apparatus may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptive terms used herein may be interpreted accordingly.

[0184] As used herein, the term "substrate" refers to the material on which subsequent material layers are added. A substrate includes a "top" surface and a "bottom" surface. Unless otherwise stated, the top surface of the substrate is typically the location where the semiconductor device 300 is formed, and thus the semiconductor device 300 is formed on the top side of the substrate. The bottom surface is opposite to the top surface, and thus the bottom side of the substrate is opposite to the top side of the substrate. The substrate itself may be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. Furthermore, the substrate may comprise a wide variety of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of a non-conductive material, such as glass, plastic, or a sapphire wafer.

[0185] As used herein, the term "layer" refers to a portion of material 921 comprising a region having thickness. A layer has a top side and a bottom side, wherein the bottom side of the layer is relatively close to the substrate, and the top side is relatively far from the substrate. A layer may extend over the entire underlying or upper structure, or may have a range smaller than that of the underlying or upper structure. Furthermore, a layer may be a region of a uniform or non-uniform continuous structure with a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any set of horizontal planes at the top and bottom surfaces of a continuous structure. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, and may include one or more layers, and / or may have one or more layers on, above, and / or below it. A layer may include multiple layers. For example, an interconnect layer may include one or more conductive layers and contact layers (where contacts, conductive lines 942, and / or vertical interconnect pathways (VIA) are formed) and one or more dielectric layers.

[0186] As used herein, the term "nominal" refers to the expected or target value of a characteristic or parameter of a component or process step set during the design phase of a product or process, and the range of values ​​higher and / or lower than the expected value. As used herein, the range of values ​​may be due to slight variations in manufacturing processes or tolerances. As used herein, the term "about" indicates a given quantity value that may vary based on a specific technology node associated with the subject semiconductor device 300. Based on a specific technology node, the term "about" may indicate a given quantity value that varies, for example, within 10 to 30% of the value (e.g., + / - 10%, + / - 20%, or + / - 30% of the value).

[0187] As used in this disclosure, the terms “substantially” or “truly” mean the majority or the majority, such as at least about 50%, 60%, 70%, 80%, 90%, 95%, 96%, 97%, 98%, 99%, 99.5%, 99.9%, 99.99%, or at least about 99.999% or more.

[0188] In this disclosure, the terms “horizontal / horizontally / laterally” mean a lateral surface nominally parallel to the substrate, and the terms “vertical” or “perpendicularly” mean a lateral surface nominally perpendicular to the substrate.

[0189] As used herein, the term “3D memory” refers to a three-dimensional (3D) semiconductor device 300 having vertically oriented strings (referred to herein as “memory strings”, such as NAND strings) of memory cell transistors 926s on a laterally oriented substrate, such that the memory strings extend in the vertical direction relative to the substrate.

[0190] As used in this article, the term "surrounded by" means being at least partially surrounded by. For example, "A is surrounded by B" can mean that A is at least partially surrounded by B.

[0191] As used herein, the term "and / or" refers to and covers any and all possible combinations of one or more of the related listed terms. For example, the term "A and / or B" means that option A, option B, or both options A and B are possible, where A and B can be singular or plural.

[0192] This disclosure provides numerous different implementations or examples for achieving various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component on or over a second component may include implementations where the first and second features can be in direct contact, and may also include implementations where an additional feature can be formed between the first and second features, such that the first and second features are not in direct contact. Additionally, reference numerals and / or letters may be repeated in various examples of this disclosure. Such repetition is for simplicity and clarity and does not in itself indicate a relationship between the various implementations and / or configurations discussed.

[0193] The foregoing description of the specific embodiments can be readily modified and / or adapted to various applications. Therefore, based on the teachings and guidance presented herein, such adjustments and modifications are intended to fall within the meaning and scope of equivalents of the disclosed embodiments.

[0194] While this disclosure includes numerous specific details of implementation, these should not be construed as limiting the scope of the claims, but rather as a description of features specific to particular embodiments of a particular invention, wherein the scope of the claims is defined by the claims themselves. Certain features described in the context of different embodiments in this disclosure may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented individually or in any suitable sub-combination in multiple embodiments. Furthermore, although features may be described above as functioning in certain combinations and even initially claimed in this way, in some cases, one or more features from the claimed combination may be removed from the combination, and the claims may be directed to sub-combinations or variations thereof.

[0195] Similarly, although the operations are depicted in a specific order in the accompanying drawings and recited in the claims, this should not be construed as requiring the operations to be performed in the specific order shown or sequentially, or requiring the execution of all shown operations to achieve the desired result. In some cases, multitasking and parallel processing may be advantageous. Furthermore, the separation of various system modules and components in the above embodiments should not be construed as requiring such separation in all embodiments, and it should be understood that the described program components and systems can generally be integrated together in a single software product or packaged into multiple software products.

[0196] Specific embodiments of the subject matter have been described. Other embodiments are also within the scope of the appended claims. For example, the actions recited in the claims can be performed in different orders and still achieve the desired result. As an example, the processes depicted in the drawings do not necessarily require the specific or sequential order shown to achieve the desired result. In some cases, multitasking and parallel processing may be advantageous.

[0197] The scope and extent of this disclosure should not be limited by any of the exemplary embodiments described above, but should be defined solely by the appended claims and their equivalents.

Claims

1. A semiconductor device, comprising: A first semiconductor structure, the first semiconductor structure including a memory array, the memory array including a first memory subarray and a second memory subarray stacked along a first direction, a first row memory cell of the first memory subarray and a first row memory cell of the second memory subarray coupled to the same bit line, the same bit line being located along the first direction between the first row memory cell of the first memory subarray and the first row memory cell of the second memory subarray; A second semiconductor structure is stacked with the first semiconductor structure along the first direction, wherein the second semiconductor structure includes an interconnect structure, a pad lead-out structure, a control circuit system coupled to the memory array, and a first via structure coupling the interconnect structure to the pad lead-out structure, and the control circuit system is located between the interconnect structure and the pad lead-out structure along the first direction. as well as A second via structure extends through the first semiconductor structure and is coupled to the pad lead-out structure of the second semiconductor structure via the first via structure and the interconnect structure.

2. The semiconductor device according to claim 1, wherein, The first memory subarray includes a plurality of first memory cells, and the second memory subarray includes a plurality of second memory cells. The first memory cells in the plurality of first memory cells are aligned with the corresponding second memory cells in the plurality of second memory cells along the first direction. Each of the first memory cells and the corresponding second memory cells extends along the first direction and includes a transistor and a capacitor. The transistor is closer to the same bit line along the first direction than the capacitor.

3. The semiconductor device according to claim 2, wherein, The transistor includes a semiconductor body extending along the first direction, and the semiconductor body includes a metal-oxide-semiconductor material.

4. The semiconductor device according to any one of claims 1 to 3, wherein, The second via structure includes multiple portions, each extending along the first direction, the multiple portions being arranged along a second direction different from the first direction and separated by an interlayer dielectric material, and the interconnect structure including multiple conductive lines. In this configuration, the first ends of the plurality of portions of the second via structure are coupled to the same connection structure, and the second ends of the plurality of portions of the second via structure are coupled to the same conductive line among the plurality of conductive lines of the interconnect structure.

5. The semiconductor device according to claim 4, wherein, The spacing between the plurality of portions of the second via structure along the second direction is less than or equal to 1 μm.

6. The semiconductor device according to claim 4 or 5, wherein, A portion of the plurality of portions of the second via structure has a dimension of less than or equal to 0.5 μm along the second direction.

7. The semiconductor device according to any one of claims 1 to 6, wherein, The interconnect structure includes a first conductive layer, at least one second conductive layer, and a third conductive layer, wherein the at least one second conductive layer is located between the first conductive layer and the third conductive layer along the first direction. Wherein, the first end of the first via structure is connected to the first conductive layer, the second end of the first via structure is connected to the third conductive layer, and the conductive material of the first via structure is isolated from the at least one second conductive layer by a dielectric material.

8. The semiconductor device according to claim 7, wherein, The dimension of the first via structure along the second direction is less than or equal to 0.5 μm.

9. The semiconductor device according to any one of claims 1 to 8, wherein, The memory array of the first semiconductor structure is on the interconnect structure of the second semiconductor structure, and the memory array is coupled to the interconnect structure through conductive vias. The conductive via has a first end coupled to the memory array and a second end coupled to the interconnect structure, and the dimension of the first end of the conductive via along a second direction different from the first direction is greater than the dimension of the second end of the conductive via.

10. The semiconductor device according to any one of claims 1 to 8, wherein, The second semiconductor structure is coupled to the first semiconductor structure through at least one contact structure, and the at least one contact structure includes at least one of bonding pads, solder bumps, microbumps, or pillars.

11. A semiconductor device, comprising: Multiple memory devices, which are stacked sequentially along a first direction. The memory device among the plurality of memory devices includes a first pad lead-out structure on a first surface and a second pad lead-out structure on a second surface opposite to the first surface along a first direction. The memory device includes: A first semiconductor structure, comprising: (i) a memory array including a first memory subarray and a second memory subarray stacked along a first direction, wherein a first row memory cell of the first memory subarray and a first row memory cell of the second memory subarray are coupled to a common bit line, the common bit line being located along the first direction between the first row memory cells of the first memory subarray and the first row memory cells of the second memory subarray; and (ii) a first pad lead-out structure; and A second semiconductor structure, stacked with the first semiconductor structure along the first direction, wherein the second semiconductor structure includes an interconnect structure, a second pad lead-out structure, and a control circuit system coupled to the memory array. The plurality of memory devices are coupled to each other, wherein the first pad lead-out structure is in contact with the corresponding second pad lead-out structure.

12. The semiconductor device according to claim 11, wherein, The second semiconductor structure includes a first via structure that couples the interconnect structure to the second pad lead-out structure. The memory device among the plurality of memory devices includes: a second via structure extending through a portion of the second semiconductor structure and the first semiconductor structure, the second via structure being coupled to the first via structure through the interconnect structure, and The first pad lead-out structure is coupled to the corresponding second pad lead-out structure through the first via structure and the second via structure.

13. The semiconductor device according to claim 12, wherein, The second via structure includes multiple portions, each extending along the first direction, the multiple portions being arranged along a second direction different from the first direction and separated by an interlayer dielectric material, the interconnect structure including multiple conductive lines, and In this configuration, the first ends of the plurality of portions of the second via structure are coupled to the same connection structure, and the second ends of the plurality of portions of the second via structure are coupled to the same conductive line among the plurality of conductive lines of the interconnect structure.

14. The semiconductor device according to any one of claims 11 to 13, wherein, The first memory subarray includes a plurality of first memory cells, and the second memory subarray includes a plurality of second memory cells. The first memory cells in the plurality of first memory cells are aligned with the corresponding second memory cells in the plurality of second memory cells along the first direction. Each of the first memory cells and the corresponding second memory cells extends along the first direction and includes a transistor and a capacitor, and the transistor is closer to the same bit line along the first direction than the capacitor.

15. The semiconductor device according to any one of claims 11 to 14, wherein, The second semiconductor structure includes one or more first contact structures that extend through the first dielectric layer along the first direction and are isolated from each other in the first dielectric layer, and the first semiconductor structure includes one or more second contact structures that extend through the second dielectric layer along the first direction and are isolated from each other in the second dielectric layer. Wherein, along the first direction, the first dielectric layer is in contact with the second dielectric layer, and at least one of the one or more first contact structures is in contact with a corresponding one of the one or more second contact structures, and The memory array is coupled to the control circuit system through at least one of the one or more first contact structures and at least one of the one or more second contact structures.

16. The semiconductor device according to any one of claims 11 to 15, comprising: A substrate structure, the substrate structure including a circuit system and substrate pad lead-out structures coupled to the circuit system. The plurality of memory devices are stacked sequentially on top of the substrate structure along the first direction, and the plurality of memory devices are coupled to the circuit system of the substrate structure through the first pad lead-out structure, the second pad lead-out structure and the substrate pad lead-out structure.

17. A method comprising: Forming a memory device, the memory device comprising: A first semiconductor structure, comprising a memory array, the memory array including a first memory subarray and a second memory subarray stacked along a first direction, a first row memory cell of the first memory subarray and a first row memory cell of the second memory subarray coupled to the same bit line, the same bit line being located along the first direction between the first row memory cells of the first memory subarray and the first row memory cells of the second memory subarray; and A second semiconductor structure is stacked with the first semiconductor structure along the first direction. The second semiconductor structure includes a substrate, a control circuit system on a first side of the substrate, an interconnect structure coupled to the control circuit system, and a first portion of a through-hole structure coupled to the interconnect structure and on the first side of the substrate. The first portion of the through-hole structure includes a first via structure. Forming a second via structure extending through the first semiconductor structure, the second via structure being coupled to the first via structure via the interconnect structure; and A second portion of the through-hole structure is formed in the substrate and extends and coupled to the first portion of the through-hole structure.

18. The method of claim 17, comprising: A pad lead-out structure coupled to the first via structure is formed on the second side of the substrate of the second semiconductor structure, and the memory array of the first semiconductor structure is coupled to the pad lead-out structure through the first via structure and the second via structure; A substrate structure is provided comprising a plurality of substrate dies, wherein one of the substrate dies includes a circuit system and a substrate pad lead-out structure coupled to the circuit system; as well as The memory device is stacked on top of the substrate die, wherein the pad lead-out structure is in contact with the substrate pad lead-out structure.

19. The method according to claim 18, wherein, The memory device is a first memory device, and the method includes: Forming a plurality of memory devices including the first memory device, the plurality of memory devices including a first via structure and a second via structure, and The plurality of memory devices are sequentially stacked on the substrate die along the first direction. The plurality of memory devices are coupled to each other through a first via structure and a corresponding second via structure. The plurality of memory devices are coupled to the circuit system of the substrate structure through the first via structure, the second via structure and the substrate pad lead-out structure.

20. The method according to any one of claims 17 to 19, wherein, The memory device comprises: The second semiconductor structure is formed, the second semiconductor structure including one or more first contact structures that pass through the first dielectric layer and are isolated from each other in the first dielectric layer; The first semiconductor structure includes one or more second contact structures that pass through the second dielectric layer and are isolated from each other in the second dielectric layer; and The second semiconductor structure and the first semiconductor structure are stacked along the first direction, the first dielectric layer is in contact with the second dielectric layer, and at least one of the one or more first contact structures is in contact with a corresponding one of the one or more second contact structures. The memory array is coupled to the control circuit system through at least one of the one or more first contact structures and at least one of the one or more second contact structures.

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