Vertical field effect device and method of manufacturing same

Abstract

The invention relates to a vertical field effect transistor (FET). A vertical FET according to the present invention includes a substrate and a first electrode configured as a source or drain of the transistor. The device includes a second electrode configured as the other of the source and drain of the transistor, the second electrode at least partially overlapping the first electrode at an overlap region. Further, the device includes an active layer sandwiched between the first electrode and the second electrode, and a gate having a gate conductor portion and a gate insulating layer disposed between the active layer and the gate conductor portion to avoid direct contact of the active layer and the gate conductor portion. The active layer includes a 1D material configured with a longitudinal axis substantially parallel to the substrate, and / or a 2D material configured with a plane substantially parallel to the substrate. The invention further comprises a method for manufacturing such a vertical field effect transistor and a method for manufacturing a complementary logic device.

Description

Technical Field

[0001] This application relates to field-effect devices, such as field-effect transistors, and more specifically to vertical field-effect transistors and methods of manufacturing the same. Background Technology

[0002] As predicted by Moore's Law, semiconductor devices used in integrated circuits have shrunk dramatically over the past few decades. Transistor channel lengths have decreased from a few micrometers to a few nanometers. This miniaturization has allowed for increased transistor integration on a single chip and improved the performance of the manufactured devices.

[0003] A field-effect transistor (FET) comprises three main terminals: source, drain, and gate. A fourth terminal is associated with the body or substrate, but is typically connected to the source, allowing the FET to be controlled as a three-terminal device. Current can flow from the source to the drain through channels created in the active (e.g., semiconductor) material, the conductivity of which is controlled by the voltage applied to the gate.

[0004] In existing designs, both the source and drain are disposed on a two-dimensional plane and formed on the surface of a semiconductor substrate to provide a so-called planar transistor. A conductive channel is then fabricated on the semiconductor substrate, the length of which is defined by the distance between the source and drain. To adjust the conductivity of the channel, a voltage is applied to a gate electrode disposed in the region between the source and drain and separated from the semiconductor substrate by a dielectric. When a voltage is applied, current flows horizontally (primarily), i.e., parallel to the plane containing the source, drain, and channel.

[0005] The length of a channel affects the performance of a transistor in various metrics, such as speed and power. In particular, the switching speed of a planar transistor can be increased by shrinking the channel (i.e., reducing its length). However, the miniaturization of existing planar transistors has reached its physical limits. In fact, when the channel length is on the same order of magnitude as the depletion layer width at the source and drain junctions, short-channel effects (SCEs) occur, such as leakage current and drain-induced barrier degradation or speed saturation. This reduces the gate's ability to properly control the current in the channel.

[0006] To mitigate channel efficiency (SCE) issues, various gate device architectures have been proposed, such as FinFETs or Gate All-Around (GAA) FETs, which improve gate control by providing a larger contact area between the gate and the channel region. These designs incorporate three-dimensional geometries that improve the "wrapping" of the channel through the gate. Thus, in FinFET transistors, the gate wraps around the channel on three sides of the silicon fin, rather than just one side as in planar configurations. This wrapping results in improved controllability, allowing for shorter channel lengths and faster switching times. GAA FET transistors go further, wrapping the channel on all four sides with the gate, resulting in better controllability with even shorter channel lengths, leading to even faster switching times. In summary, these three-dimensional architectures allow for channel lengths reduced to a few nanometers. Nevertheless, the fabrication processes involved are highly complex, requiring sophisticated techniques such as extreme ultraviolet (EUV) lithography. Furthermore, the three-dimensional geometry presents new limitations on miniaturization due to the mechanical and structural properties of the resulting structures.

[0007] As a further step to increase the integration of transistors within the substrate, vertical transport field-effect transistors (VTFETs) have been proposed (e.g., in US10134893B2 or US10134642B2). In these designs, the source and drain are no longer configured on the same horizontal two-dimensional plane. Instead, they are confined at different heights relative to the substrate, such that current flows along at least a portion of the channel in a direction substantially perpendicular to the substrate surface. This configuration allows for a higher integration density of transistors per unit area of ​​the substrate.

[0008] Throughout this invention, a vertical field-effect transistor (VFET) refers to a transistor in which the source and drain are not located on the same horizontal plane, i.e., the channel between the source and drain extends at least partially vertically.

[0009] In addition to novel gate architectures, materials other than silicon have been evaluated as active materials. Indeed, electron mobility drops significantly as bulk materials like silicon move down to the nanoscale, making a shift to different materials necessary to continue miniaturizing. Therefore, two-dimensional (2D) materials such as carbon nanotubes (CNTs) or metal sulfides (TMDs) have been proposed as silicon alternatives in modern FET channels. The use of these new materials also faces its own challenges, particularly related to the fabrication of the materials themselves and their integration into functional operating devices.

[0010] In summary, the ongoing demand for increased integration in field-effect devices has led to the emergence of a wide variety of transistor geometries and architectures using diverse materials. A transistor design is still needed to maintain or even improve the performance of FET transistors while achieving greater integration, thereby shrinking channels to the nanometer scale. Corresponding manufacturing processes are also required. Summary of the Invention

[0011] In this invention, a vertical field-effect transistor (FET) is provided. The vertical FET includes a substrate and a first electrode disposed on the substrate and configured as either the source or drain of the transistor. The transistor further includes a second electrode configured as the other of the source and drain of the transistor, at least partially overlapping the first electrode in an overlap region. An active layer is sandwiched between the first and second electrodes. The vertical FET includes a gate having a gate conductor portion and a gate insulating layer disposed between the gate conductor portion and the active layer. The active layer may include a 1D material configured such that its longitudinal axis is substantially parallel to the substrate, and / or the active layer may include a 2D material configured such that its plane is substantially parallel to the substrate.

[0012] Furthermore, this invention proposes a vertical FET where current flows from the source to the drain through the active layer. The direction of current flow is approximately perpendicular to the plane defined by the substrate, and the channel length is determined by the thickness of the active layer. In other words, in the case of a 1D material, the current flows laterally along the longitudinal axis of the 1D material. In the case of using a 2D material, the current flows laterally along the plane of the 2D material. Therefore, lateral transport can be considered as transport along the direction in which the corresponding material exhibits quantum confinement. VFETs of this type can increase the integration of the number of transistors in a given region of the substrate while reducing the channel length.

[0013] Furthermore, a gate insulating layer is disposed between the gate conductor portion and the active layer to avoid direct contact between the gate conductor and the active layer; that is, the gate insulating layer forms an energy barrier between the gate conductor and the active layer. However, the gate insulating layer cannot prevent the active layer from experiencing field effects.

[0014] Throughout this invention, the term "active material" refers to a material whose conductivity can be actively adjusted (e.g., by applying a voltage) in order to establish a conductive channel. In particular, active materials can include semiconductor materials. Accordingly, an active layer refers to a layer comprising these active materials.

[0015] Throughout this invention, the overlapping region can be understood as an area or region on top of the first electrode where the second electrode is positioned, i.e., in a top view, the second electrode obscures at least a portion of the first electrode. This overlapping region can take on various shapes and sizes. The outer overlap perimeter can be considered as the outer edge of the overlapping region, i.e., the edge surrounding the overlapping region. It should be understood that, in any case, the overlap does not imply any direct contact between the electrodes within the overlapping region.

[0016] Throughout this invention, the terms "sandwiching" and "sandwich structure" can be used to refer to a configuration in which an active layer is disposed between and directly adjacent to two electrodes. Therefore, throughout this invention, a sandwich configuration is understood to mean that the active layer extends over the overlapping region to prevent any direct contact between the electrodes.

[0017] Throughout this invention, 1D material should be understood as a material containing 1D elements, such as nanotubes. Accordingly, when referring to the vertical axis of 1D material, it should be understood as referring to the vertical axis of the 1D element forming the 1D material.

[0018] In another aspect of the invention, a method for manufacturing a vertical field-effect transistor is provided. The method includes: forming a first electrode on a substrate; forming an active layer on the first electrode and forming a second electrode on the active layer, thereby creating a sandwich structure having overlapping regions at their peripheries. The method further includes defining a gate region that exposes at least a portion of the active layer. A gate insulating layer is then deposited to at least cover the exposed portion of the active layer, and a gate conductor is deposited on the gate insulating layer. Finally, the method includes defining electrical contacts between the first electrode, the second electrode, and the gate.

[0019] In a specific example of the above method, a method for manufacturing a vertical FET with minimal or reduced process steps is provided. This method embodiment allows for smaller channel dimensions and / or greater contact lengths between the channel and the source / drain electrodes, which reduces contact resistance and improves performance.

[0020] For the sake of completeness, the various concepts of this invention will be set forth in the following numbered clauses: Clause 1 A vertical field-effect transistor comprising: substrate; The first electrode is on the substrate and is configured as the source or drain of a transistor. The second electrode is configured as the other of the source and drain of the transistor, wherein the second electrode overlaps with the first electrode at least partially in the overlapping region. An active layer, sandwiched between the first electrode and the second electrode; and The gate has a gate conductor portion and a gate insulating layer, the gate insulating layer being disposed between the gate conductor portion and the active layer.

[0021] Clause 2 is a vertical field-effect transistor as described in Clause 1, wherein the active layer comprises a 1D material, particularly carbon nanotubes (CNTs), and particularly wherein the longitudinal axis of the 1D material is arranged parallel to the substrate.

[0022] Clause 3: The vertical field-effect transistor as described in Clause 2, wherein the active layer comprises at least one of the following: a single layer of single-walled carbon nanotubes (SWCNTs); a single layer of multi-walled CNTs; a single layer of bonded SWCNTs; a layer of multi-column aligned SWCNTs; a layer of multi-column aligned multi-walled CNTs; a network of non-aligned SWCNTs; and a network of non-aligned multi-walled CNTs.

[0023] Clause 4: A vertical field-effect transistor as described in any of the preceding clauses, wherein the active layer comprises a two-dimensional (2D) structure, specifically, wherein the active layer comprises a transition metal dichalcogenide (TMD) material, and more specifically, MX2, such as MoS2, WeS2 or WS2, and in particular, wherein the plane of the 2D material is arranged parallel to the substrate.

[0024] Clause 5 is a vertical field-effect transistor as described in Clause 4, wherein the active layer comprises a stack of 2D material sheets.

[0025] Clause 6: A vertical field-effect transistor as described in any one of Clauses 2 to 5, wherein the active layer further comprises a conformal dielectric.

[0026] Clause 7: A vertical field-effect transistor as described in any of the preceding clauses, wherein at least one of the first electrode and the second electrode comprises a metal, a semiconductor, or a 1D conductor, a 2D conductor, or a doped semiconductor.

[0027] Clause 8: A vertical field-effect transistor as described in any of the preceding clauses, wherein the gate conductor portion comprises at least one of a metal, a half-metal, or a 1D conductor, or a 2D transition metal dichalcogenide, or a doped semiconductor.

[0028] Clause 9: A vertical field-effect transistor as described in any of the preceding clauses, wherein the overlapping region has an outer periphery, and wherein the gate is at least partially disposed within the outer periphery of the overlapping region.

[0029] Clause 10: A vertical field-effect transistor as described in Clause 9, wherein the gate includes a first insulating layer having a U-shaped cross-section and a second insulating layer having a U-shaped cross-section, wherein the first insulating layer and the second insulating layer are separated by a first electrode, an active layer, and a portion of a second electrode.

[0030] Clause 11: A vertical field-effect transistor as described in any of Clauses 9 or 10, wherein the gate is entirely disposed within the outer periphery of the overlapping region.

[0031] Clause 12: A vertical field-effect transistor as described in any one of Clauses 9 or 10, wherein the gate extends beyond at least one side of the outer periphery of the overlapping region.

[0032] Clause 13: A vertical field-effect transistor as described in any one of Clauses 1 to 8, wherein the overlapping region has an outer periphery, and wherein the gate is disposed on the outer side and adjacent to the outer periphery of the overlapping region.

[0033] Clause 14: A vertical field-effect transistor as described in any of Clauses 12 or 13, wherein the gate is configured to be substantially flush with the active layer.

[0034] Clause 15: A vertical field-effect transistor as described in any of the preceding clauses, wherein the active layer comprises multiple sublayers.

[0035] Clause 16: A vertical field-effect transistor as described in Clause 15, wherein at least two sublayers each comprise different types of active materials.

[0036] Clause 17: A vertical field-effect transistor as described in Clause 16, wherein at least one first sublayer comprises a 1D semiconductor and at least one second sublayer comprises a 2D semiconductor.

[0037] Clause 18 A vertical field-effect transistor as described in any of the preceding clauses, wherein the materials of the first electrode, the second electrode, and / or the active layer are selected such that the transistor behaves as a P-type or N-type field-effect transistor.

[0038] Clause 19 A semiconductor structure comprising a first vertical field-effect transistor as described in any of the preceding clauses, and a second vertical field-effect transistor as described in any of the preceding clauses, the second vertical field-effect transistor being disposed on the first vertical field-effect transistor.

[0039] Clause 20 A semiconductor structure comprising a first vertical field-effect transistor as described in any of the preceding clauses, and a second vertical field-effect transistor as described in any of the preceding clauses, the second vertical field-effect transistor being disposed on one side of the first vertical field-effect transistor.

[0040] Clause 21 The semiconductor structure described in Clause 19 or 20, wherein the first vertical field-effect transistor is a P-type transistor or an N-type transistor, and the second vertical field-effect transistor is the other of a P-type transistor or an N-type transistor.

[0041] Clause 22 A method of manufacturing a vertical field-effect transistor, specifically a method of manufacturing a vertical field-effect transistor as described in any one of Clauses 1 to 18, comprising: A first electrode is formed on the substrate; An active layer is deposited on the first electrode; A second electrode is deposited on the active layer to form a sandwich structure with overlapping regions on the periphery; A gate region is formed, which exposes at least a portion of the active layer; Deposit a gate insulating layer covering the exposed portion of the active layer; A gate conductor is deposited on the gate insulating layer, such that the gate insulating layer is disposed between the gate conductor and the active layer; Electrical contact is formed between the first electrode, the second electrode, and the gate conductor.

[0042] Clause 23 The method of manufacturing a vertical field-effect transistor as described in Clause 22, wherein depositing an active layer includes depositing a layer comprising carbon nanotubes and / or two-dimensional materials as semiconductor materials.

[0043] Clause 24 describes a method of manufacturing a vertical field-effect transistor as described in Clause 23, wherein depositing an active layer includes depositing a single column of CNTs, particularly SWCNTs.

[0044] Clause 25 refers to a method of manufacturing a vertical field-effect transistor as described in Clause 23, wherein the deposition of the active layer includes the deposition of multiple rows of aligned CNTs, particularly SWCNTs.

[0045] Clause 26. A method of manufacturing a vertical field-effect transistor as described in any one of Clauses 23 to 25, wherein the method further comprises: After depositing the active layer, a conformal dielectric layer is deposited on top of the active layer; Before depositing the second electrode, the conformal dielectric layer is etched to expose the active material of the active layer.

[0046] Clause 27 The method of manufacturing a vertical field-effect transistor as described in Clause 26, wherein etching a conformal dielectric layer to expose the active material of the active layer prior to depositing the second electrode includes partially etching the active material.

[0047] Clause 28. A method of manufacturing a vertical field-effect transistor as described in any one of Clauses 22 to 27, wherein forming a gate region includes forming a gate region that partially overlaps with an overlapping region.

[0048] Clause 29 The method of manufacturing a vertical field-effect transistor as described in Clause 28, wherein forming a gate region includes forming at least two gate regions separated by a first electrode, an active layer and a portion of a second electrode.

[0049] Clause 30: A method of manufacturing a vertical field-effect transistor as described in Clauses 28 or 29, wherein forming the gate region includes forming the gate region in a region completely disposed within the outer periphery of the overlapping region.

[0050] Clause 31. A method of manufacturing a vertical field-effect transistor as described in Clauses 28 or 29, wherein forming a gate region includes forming a gate region in a region extending beyond the outer periphery of the overlapping region.

[0051] Clause 32. A method of manufacturing a vertical field-effect transistor as described in any one of Clauses 22 to 27, wherein forming a gate region includes forming a gate region in a region surrounding the outer periphery of an overlapping region.

[0052] Clause 33. A method of manufacturing a vertical field-effect transistor as described in Clause 31 or 32, wherein the method further comprises: Before depositing the gate insulating layer, an isolation element is formed in the gate region, such that the bottom horizontal plane of the resulting gate region has a height that causes the bottom surface of the gate conductor to be flush with the bottom surface of the active layer, and, The gate insulating layer and gate conductor are etched during deposition so that the top of the remaining gate insulating layer and gate conductor is approximately flush with the top surface of the active layer.

[0053] Clause 34. A method of manufacturing a vertical field-effect transistor as described in any one of Clauses 22 to 33, wherein forming a gate region includes forming a cavity, and depositing a gate insulating layer includes depositing a gate insulating layer covering the inner wall of the cavity.

[0054] Clause 35 The method of manufacturing a vertical field-effect transistor as described in any one of Clauses 22 to 34, wherein depositing an active layer on a first electrode includes depositing a plurality of sublayers.

[0055] Clause 36. A method of manufacturing a vertical field-effect transistor as described in Clause 35, wherein depositing multiple sublayers includes depositing at least a first sublayer and a second sublayer, the first sublayer comprising an active material different from that of the second sublayer.

[0056] Clause 37 A method of manufacturing a vertical field-effect transistor structure, comprising manufacturing a first vertical field-effect transistor in accordance with any one of Clauses 22 to 36 and manufacturing a second field-effect transistor on top of a previously manufactured transistor. Attached Figure Description

[0057] Figure 1 The top view and cross-sectional views of the (A-A') side and (B-B') side of a vertical field-effect transistor according to an embodiment are shown schematically. Figure 2 An embodiment illustrating the configuration of four vertical FETs on a substrate; Figures 3A to 3L The sequence of steps in an embodiment of a method for manufacturing a vertical field-effect transistor is illustrated schematically. Figures 4A to 4L The sequence of steps in another embodiment of a method for manufacturing a vertical field-effect transistor is schematically shown, the vertical field-effect transistor including fins; Figures 5A to 5O The sequence of steps in yet another embodiment of a method for manufacturing a vertical field-effect transistor is schematically shown. The vertical field-effect transistor includes fins, side gates, and gate alignment to minimize overlap with the source and / or drain. Figures 6A to 6O The sequence of steps in an embodiment of a method for manufacturing a vertical field-effect transistor is illustrated schematically. The vertical field-effect transistor includes a gate-all-around (GAA) with gate alignment to minimize overlap with the source and / or drain. Figures 7A to 7D The illustration schematically shows the initial steps (up to the deposition of the second electrode) in an embodiment of a method for fabricating a vertical field-effect transistor, the vertical field-effect transistor comprising carbon nanotubes (CNTs) as the active material; Figures 8A to 8D The diagram schematically illustrates the initial steps (up to the deposition of the second electrode) in another embodiment of a method for fabricating a vertical field-effect transistor, the vertical field-effect transistor comprising a stack of single-walled carbon nanotubes (SWCNTs) as the active material; Figures 9A to 9D The initial steps (up to the deposition of a second electrode) of yet another embodiment of a method for fabricating a vertical field-effect transistor are schematically shown, the vertical field-effect transistor comprising a network of SWCNTs (mesh); Figures 10A to 10D The initial steps (up to the deposition of the second electrode) of another embodiment of a method for manufacturing a vertical field-effect transistor are schematically shown, the vertical field-effect transistor comprising a two-dimensional transition metal dichalcogenide (TMD) as the active material; Figures 11A to 11O An embodiment of a method for manufacturing a complementary field-effect transistor (CFET) converter is schematically illustrated, wherein the CFET is manufactured by configuring a second (upper) vertical FET on a first (lower) vertical FET. These figures illustrate, according to... Figures 3A to 3L The illustrated embodiment shows the process after the first (lower) FET is manufactured; Figure 12 An embodiment of a CFET converter with top and bottom contacts is schematically shown; Figure 13An embodiment of a CFET converter is schematically illustrated, wherein the CFET converter is obtained by configuring a second vertical FET on a first vertical FET, the vertical FET being based on... Figures 4A to 4L An embodiment of a transistor with fins is shown; Figure 14 An embodiment of a CFET converter is schematically illustrated, wherein the CFET converter is obtained by configuring a second vertical FET on a first vertical FET, the vertical FET being based on... Figures 6A to 6O An embodiment of a transistor with a gate-all-around (GAA) configuration is shown; Figure 15 An embodiment of a CFET converter is schematically illustrated, wherein the CFET converter is obtained by configuring a second vertical FET on a first vertical FET, the vertical FET being based on... Figures 7A to 7D The embodiment shown has SWCNT as the active material; Figure 16 An embodiment of a CFET converter is schematically illustrated, which is obtained by configuring a second vertical FET on a first vertical FET, the vertical FET comprising unzipped SWCNTs; Figure 17 An embodiment of a CFET converter is schematically shown, wherein, as Figures 10A to 10D The two-dimensional transition metal dichalcogenide (TMD) shown is used as an active material; Figure 18 An embodiment of a CFET converter is schematically shown, wherein different semiconductors serve as the active layers of the upper and lower transistors; Figure 19 An embodiment of a CFET converter is schematically illustrated, wherein the active layer of each transistor comprises multiple sublayers, each sublayer comprising a different family of low-dimensional materials; Figure 20 An embodiment of a CFET converter is schematically illustrated, wherein the active layer comprises multiple sublayers, each sublayer comprising a similar family of low-dimensional materials; Figures 21A to 21H Another sequence of steps is illustrated in an embodiment of a method for manufacturing a vertical field-effect transistor; Figures 22A to 22P The sequence of steps in an embodiment of a method for manufacturing a vertical field-effect transistor including a dual-gate structure is illustrated schematically. Figure 23 A flowchart illustrating an embodiment of a method for manufacturing a vertical field-effect transistor; Figure 24 A flowchart illustrating an embodiment of a method for fabricating the active layer of a vertical field-effect transistor. Detailed Implementation

[0058] This specification is illustrated by way of example, including preferred embodiments, to enable those skilled in the art to implement the invention. This includes making and using any apparatus or system, and performing any incorporated methods. The scope of protection of the invention is defined by the claims, and may include other embodiments that can be conceived by those skilled in the art. These other embodiments are intended to fall within the scope of the claims if they have structural elements that are not literally different from those of the claims, or if they include equivalent structural elements that are not substantially different from those of the claims. Aspects of the various embodiments described, and other known equivalents of each such aspect, can be mixed and matched by those skilled in the art to construct additional embodiments and techniques according to the principles of this application. If element symbols related to the drawings are enclosed in parentheses in the claims, they are only intended to increase the comprehensibility of the claims and should not be construed as limiting the scope of the claims.

[0059] Reference will now be made in detail to embodiments, one or more of which are illustrated in the drawings. Each embodiment is provided for illustrative purposes and not for limitation. In fact, it will be apparent to those skilled in the art that various modifications and variations can be made to the invention. For example, a feature shown or described as part of one embodiment may be used with another embodiment to produce another embodiment. The invention is intended to cover such modifications and variations that fall within the scope of the appended claims and their equivalents. Furthermore, the drawings are intended to illustrate different embodiments and manufacturing processes. For clarity, the dimensions of different elements are not drawn to scale to facilitate identification of different parts.

[0060] Figure 1 This is a view of an embodiment of a vertical field-effect transistor (FET) 100. The diagram illustrates three different views of the transistor: a top view (left-hand side), a side cross-sectional view (i.e., along plane A-A' shown in the top view), and a front cross-sectional view (i.e., along plane B-B' shown in the top view). The arrangement of the top and cross-sectional views is repeated in many other diagrams.

[0061] The vertical FET 100 includes a substrate 101. The substrate 101 can be silicon, Si, or a wafer, but can also be other substrates known in the art, such as silicon-germanium (SiGe) or III-V semiconductor wafers. Figure 1In this embodiment, a first electrode 102 is disposed on a substrate 101. The first electrode 102 serves as the source or drain of a vertical field-effect transistor 100. Different conductive materials can be used as the first electrode 102, including metals (Pd, Rh, Mo, Sc, Au, Pt, W, Ti, etc.), nitrides (TiN), oxides (TCOs), 2D materials (e.g., graphene), or 1D materials (e.g., metallic carbon nanotubes).

[0062] In the full text of this specification, 2D materials can be considered as crystalline materials composed of a single layer or a few layers of atoms. In 2D materials, the two dimensions are beyond the nanometer scale. 2D materials include, for example, graphene, nanofilms, nanolayers, and nanocoatings. 1D materials can be considered as materials with only one dimension beyond the nanometer scale. 1D materials include, for example, nanotubes (e.g., CNTs, MoS2 nanotubes, or WS2 nanotubes), nanopillars, nanowires, etc.

[0063] In the full text of this specification, low-dimensional materials can be considered as materials with physical properties that are at least small enough (nanoscale) to fall between those of single-atom and bulk materials. They can include 0D, 1D, 2D, and 3D materials.

[0064] The first electrode 102 can be obtained using standard semiconductor manufacturing techniques, including chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), or ink-based additive methods.

[0065] An active layer (material) (e.g., semiconductor) 103 is disposed on top of the first electrode 102. Figure 1 In this embodiment, the active layer 103 only partially covers the first electrode 102. However, different configurations are possible in other embodiments. Various choices are feasible as the active material for the active layer 103, including: 2D materials (TMDs [MX2], such as MoS2, WS2, WSe2); half-metals, such as half-metallic graphene; Xenes (such as phosphorene, silylene); MXenes; semiconductor alloys; amorphous silicon; 1D materials (such as semiconductor CNTs, MoS2 nanotubes, WS2 nanotubes, nanowires, or nanopillars); organic semiconductors; perovskites and other inorganic semiconductors, such as indium gallium zinc oxide (IGZO).

[0066] like Figure 1As shown, the second electrode 104 is deposited on the active layer 103. The same materials mentioned with respect to the first electrode 102 can also be used as the second electrode 104. Different materials can be used for the first electrode 102 and the second electrode 104 of the same transistor. For example, this allows for the use of different conductors in operating function engineering to adjust the resistance at the contact with the active material. The active layer 103 serves as the channel of the transistor, and the channel length of the transistor depends on the thickness of the active layer 103.

[0067] The second electrode 104 overlaps the first electrode 102 in a certain overlapping region. In this embodiment, the overlapping region forms a rectangular ring. The overlapping region defines the outer perimeter. Figure 1 In the illustrated embodiment, rectangular shapes with length d1 and width d2 can be observed in the diagram. The sum of the length d1 and width d2 of the overlapping region (perimeter) is similar to the channel width concept in conventional planar FETs.

[0068] The figure also shows the first interlayer dielectric layer 105. Different materials can be used as the interlayer dielectric (ILD) layer, including several organic and inorganic oxides, or other low-K materials. The ILD layer can be obtained by standard deposition techniques such as chemical vapor deposition (CVD) or atomic layer deposition (ALD), sputtering, spin coating (e.g., SOD).

[0069] The vertical field-effect transistor 100 further includes a gate having a gate conductor portion 107 and a gate insulating layer 106, the gate insulating layer 106 having a U-shaped cross-section and surrounding the gate conductor portion 107, and being configured in contact with the active layer 103.

[0070] The gate insulating layer 106 contacts a portion of the active layer 103 along its thickness. The gate insulating layer 106 is preferably made of a material with a high dielectric constant. Therefore, SiO2, SiO2, etc., can be used. x N y A, or preferably, high-K materials (e.g., HfO2, Al2O3, HfSiON, ZrO2, La2O, Ta2O5, TiO2, BaTiO3) can be used. The gate structure further includes a gate conductor portion 107 disposed within the inner volume defined by a U-shaped gate insulating layer 106.

[0071] like Figure 1As shown, the gate conductor portion 107 is deposited (i.e. formed or grown) on top of the gate insulating layer 106, thereby preventing direct contact between the gate conductor portion 107 and either the first electrode 102 or the second electrode 104, or between the active layer 103. Applying a certain voltage to the gate conductor portion 107 determines the current flow between the first electrode 102 and the second electrode 104 via the active layer 103.

[0072] As in Figure 1 As observed, this design is characterized by current flowing in a direction substantially perpendicular to the substrate, i.e., vertically when the substrate is assumed to be disposed on a flat horizontal surface. The second interlayer dielectric (ILD) 108 can be disposed in the vertical field-effect transistor 100. While it is understood that different dielectrics can be used in the same transistor, the same dielectric material as the first interlayer dielectric layer 105 can be used for the second interlayer dielectric 108.

[0073] Finally, three contacts defining the three terminals of the transistor can be provided. Specifically, a first source / drain contact 109 is used to contact the first electrode 102, a second source / drain contact 110 is used to contact the second electrode 104, and a third contact 111 is used to contact the gate conductor portion 107. Similar to the electrodes, different materials can also be used for the contacts. These include conductive 2D materials such as metals (e.g., Ti, Ru, W, Co, Ni), nitrides (TiN, TaN), binary alloys, metallic CNTs, or graphene.

[0074] Figure 1 A schematic diagram of a single vertical field-effect transistor 100 is provided. Those skilled in the art will understand that a large number of such transistors can actually be fabricated on a single substrate. This is for illustrative purposes only. Figure 2 A view of a set of four transistors 201-204 is provided, which may represent a small portion of the entire substrate.

[0075] The following will refer to Figures 3A to 3L To explain Figure 1 The manufacturing process flow of the vertical field-effect transistor is shown. Figure 3A The first step in the sequence is shown, which is the formation of the first electrode 302 on the substrate 301. The present invention is not limited to any particular substrate.

[0076] In some embodiments, substrate 301 may be silicon (Si). Additionally, the substrate may include a dielectric layer, such as a thermally grown oxide. Optionally, the dielectric layer may be deposited using standard deposition techniques such as chemical vapor deposition (CVD), physical vapor deposition (PVD), and atomic layer deposition (ALD).

[0077] As Figure 1As shown, different materials can be used for the first electrode 302. The choice of one material or another can also affect the technology used to form it. Lithography and processes based on lift-off and / or etching, as well as additional methods, can be used for the desired patterning. In some embodiments, the substrate 301 can first be patterned by photolithography and dry etching. Then, the material for the first electrode 302 can be deposited (e.g., by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), etc.). Finally, a chemical mechanical planarization (CMP) process can be used to obtain a smooth surface and remove the necessary amount of material.

[0078] Figure 3B The possible next step is shown. This step includes the deposition (i.e., formation, coating, growth) of the active layer 303. In this embodiment, the active layer 303 is deposited over the entire area of ​​the substrate, thereby completely covering the first electrode 302. As Figure 1 As shown, different materials, including 1D and 2D materials, can be used in the active layer 303.

[0079] Next step( Figure 3C The second electrode 304 is deposited, and in this particular embodiment, the second electrode 304 is also deposited throughout the region. The second electrode 304 may be made of the same or similar materials and processes as the first electrode 302, as detailed in [reference needed]. Figure 1 During this stage of the manufacturing process, a sandwich structure is created with a first electrode 302 at the bottom, a second electrode 304 at the top, and an active layer 303 in between.

[0080] Next step ( Figure 3D Photolithography and / or dry etching can be used to define regions of the transistor. As is well known to those skilled in the art, etch shielding can be used to facilitate etching. In particular, this step defines the dimensions of the active layer 303 and the second electrode 304. This step further defines the shape and size of the overlapping region, i.e., the area where the second electrode 304 overlaps with the first electrode 302. This overlapping region defines the overlapping periphery, which in the embodiment corresponds to a rectangle having a length d1 and a width d2.

[0081] After completing and defining the sandwich structure, the next step may include the deposition of the first interlayer dielectric (ILD) layer 305. Figure 3E This ILD can help with, for example... Figure 3F The next step shown involves defining the gate region 317 using photolithography or dry etching, in which case the gate region 317 resembles a cavity or well. As is well known to those skilled in the art, etch shielding can be used to facilitate etching. Figure 3FAs shown, in this particular embodiment, the gate region 317 is entirely located within or embedded within the outer perimeter of the overlapping region. Therefore, the gate in this transistor is completely surrounded by semiconductor, providing a semiconductor-all-around (SAA) configuration. This configuration provides a large surface area between the gate and the active layer 303, allowing the gate to better control the current in the channel defined by the active layer 303.

[0082] After defining the gate region 317 (cavity-shaped), the next step ( Figure 3G This can be achieved by forming or depositing a gate dielectric to form a gate insulating layer 306 with a U-shaped cross-section. For example... Figure 3G As shown, in this manufacturing process, the gate dielectric is first deposited across the entire substrate, not only in the gate region 317 but also on top of the first ILD layer 305. The gate dielectric can include various materials, such as, but not limited to, silicon oxide, aluminum oxide, titanium oxide, tantalum oxide, yttrium oxide, silicon oxynitride, silicon nitride, boron nitride, zirconium oxide, hafnium oxide, zirconium oxide, lanthanum oxide, or preferably high-k materials (e.g., HfO2, HfSiO4, or O4SiZr). Depending on the selected material, the gate insulating layer 306 can be formed using standard techniques, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), spin coating, or preferably atomic layer deposition (ALD), as is well known to those skilled in the art.

[0083] After the deposition of the gate insulator, the gate conductor 307 is deposited in the next step. Figure 3H Similar to the deposition of the gate insulator, the gate conductor in this embodiment is also deposited over the entire area, i.e., on the previously deposited insulating layer.

[0084] Figure 3I The steps for removing excess portions of both the insulating layer and the gate conductor are illustrated, specifically removing material from those regions extending beyond the boundary of the gate region 317 shown in Figure 3. For this purpose, an etching and chemical mechanical planarization (CMP) process can be used. This step can also be used directly after gate insulator deposition and repeated after gate conductor deposition.

[0085] like Figure 3J As shown, a second interlayer dielectric (ILD) layer 308 can then be deposited. This occurs before the formation of contact regions 319, 320, and 321 for the electrodes and for the gate. Figure 3K The patterning of the ILD layers (305 and 308) is shown. This process involves photolithography and dry etching, and exposes the first electrode 302 by creating contact region 319, the second electrode 304 in contact region 320, and the gate conductor 307 in contact region 321.

[0086] Finally, as Figure 3L As shown, contact material can be deposited to fabricate the first electrode contact 309, the second electrode contact 310, and the gate structure contact 311. In this case, although not shown in sequence, the contact material can be deposited over the entire surface (equivalent to...). Figure 3G and Figure 3H The process involves depositing insulating material and gate conductors, followed by selective removal of areas not aligned with the electrodes and gate using a chemical mechanical planarization (CMP) process. Various contact material stacks can be used, such as barrier layers (TiN, Ti) formed via PVD or ALD, followed by subsequent materials (e.g., but not limited to Al, Cu, W deposited via ALD, PVD, or CVD, and 2D or 1D materials deposited via CVD or similar coatings). Other conductors, such as ruthenium oxide and tantalum nitride, can also be employed.

[0087] The aforementioned method requires relatively few process steps, as few as the three photolithography steps used for transistor fabrication and one additional step for contact openings. Another advantage is that sub-10nm scales can be achieved using single-exposure (without multiple patterning) dry DUV (deep ultraviolet) etching, without the need for expensive immersion etching or EUV (extreme ultraviolet) etching. The use of EUV will enable higher resolution and reduce overall size.

[0088] Figures 4A to 4L A second embodiment of the manufacturing sequence for a vertical FET is shown. Although all steps are also presented, this description will focus on the sequence explained previously (see reference...). Figures 3A to 3L Different technical solutions. In the first step, Figure 4A The formation of a first electrode 402 on a substrate 401 is shown. It should be noted that in this sequence, the contact 409 of the first electrode 402 is formed in an early stage of the process. In this embodiment, the transistor includes a bottom contact, while reference... Figure 1 (as well as Figure 3A-3L The transistor shown includes all the contacts on the top. In any case, as will be understood by one of ordinary skill in the art, the two configurations can be combined and, for example, Figure 1 The first source / drain contact 109 can also be configured as a bottom contact. Conversely, Figure 4A The bottom contact 409 can also be arranged as a top contact through the steps shown in the equivalent contact of the embodiment of FIG3.

[0089] Figures 4B to 4E Manufacturing steps and Figures 3B to 3E The manufacturing steps described are largely the same or equivalent, and will not be repeated here. In particular, an interlayer dielectric (ILD) layer 405 is deposited after the patterning of the second electrode 404 and the active layer 403.

[0090] Figure 4F and Figure 3F The difference is that the transistor in this embodiment includes a fin F4. It should be understood that although only a single fin is provided in this embodiment, alternative designs with multiple fins can be implemented in the same way. For clarity, the term fin refers to a fin-like structure originating from the space between two cavities. Therefore, unlike Figure 3, Figure 4F This demonstrates how to define two gate regions or cavities within a structure. More than two cavities can be fabricated in a similar manner.

[0091] Therefore, the first electrode 402, the second electrode 404, and a portion of the active layer 403 remain in the space between the two cavities and form fins F4. The use of these fins allows for a larger contact area between the gate and the active layer. This larger contact area improves the gate's ability to control current in the transistor. Once the two regions or cavities are established, the following steps for this embodiment are shown below. Figures 4G to 4L These steps are equivalent to those already in place. Figure 3G to 3L The only significant difference in the steps shown is the configuration of fins, resulting in two cavities for depositing the gate insulator and gate conductor materials. (As shown...) Figure 4J As shown, after depositing the second dielectric layer 408, the gate insulating layer 406 and the gate conductor 407 are used to form the gate structure of the transistor and to create contacts for the different terminals of the transistor. In particular, Figure 4L The terminals for the first electrode 409, the second electrode 410, and the gate 411 are shown. Furthermore, the same materials and techniques referenced in the embodiment shown in FIG3 can also be applied to this design.

[0092] Figures 5A to 5O The sequence of yet another embodiment of a vertical transistor according to one embodiment is shown. As with the previous process, only variations related to the basic process will be described in detail. In this case, the gate contacts of the vertical transistor are configured on one side and extend beyond the overlapping region, thereby providing a so-called side-gate configuration. This side-gate configuration allows the gate structure to be horizontally aligned with the active layer, thereby reducing parasitic capacitance between the gate conductor and the electrode. In this particular manufacturing process, a vertical transistor including fins is fabricated. Nevertheless, it should be understood that this is only an optional feature, and the same side-gate configuration with a horizontally aligned gate can be used with transistors having multiple fins or without such fins. Referring to the illustrations, it should be clear that... Figures 5A to 5E Equivalent to what was mentioned earlier Figures 3A to 3E Therefore, no further explanation is needed. Figure 5E The diagram shows a first electrode 502, a second electrode 504, an active layer 503, a substrate 501, and a first dielectric layer 505.

[0093] Figure 5FThe formation of the gate region for the gate is shown. (Compared to...) Figure 4F Similarly, in this case, fin F5 is also present, and a portion of the first electrode 502, the second electrode 504, and the active layer 503 formed on the substrate 501 is located in the gate region or cavity within the space between the two elongated portions. Contrary to the previous embodiments, the gate in this fabrication process is not entirely surrounded by the peripheral length of the overlapping region. Instead, a portion of the gate region ( Figure 5F The G5 in the diagram extends laterally beyond the overlapping region. This difference makes the side gate configuration feasible in this embodiment.

[0094] You can refer to Figure 5G and Figure 5H Further distinguishing steps are explained. Unlike the previous embodiment, the gate insulating layer and gate conductor are not deposited or formed immediately after the region gate is formed. Instead, the interlayer dielectric (ILD) layer SP51 is deposited ( Figure 5G Then etch ( Figure 5H The etching of the ILD layer SP51 can be performed using atomic layer etching, ALE, or reactive ion etching (RIE) (with or without plasma etching) and controlled to create an isolation element SP5 at the bottom of this region (similar to a cavity or well). This isolation element ensures that the vertical overlap between the gate structure and the first electrode 502 is reduced or minimized. To this end, the height of the isolation element is controlled so that its top surface is configured slightly lower than the bottom surface of the active layer 503, so that the subsequently deposited gate conductor is approximately at the same level as the active layer 503. In particular, the isolation element SP5 has a gap between the plane of its top surface and the plane of the bottom surface of the active layer 503. As described below, the width of this gap corresponds to the thickness of the gate insulating layer 506 deposited in a later stage.

[0095] Following the definition of the isolation element, the process continues to form the gate insulating layer 506 and deposit the gate conductor 507. Due to the presence of the isolation element SP5 and the gap between its top surface and the bottom surface of the active layer 503, this deposition results in the upper surface of the gate insulating layer being approximately aligned with the bottom surface of the active layer 503, and the bottom surfaces of the gate conductors 507 being approximately flush with, i.e., horizontal, the active layer 503. This is followed by etching and planarization of the same gate insulating layer 506 and gate conductor 507.

[0096] In the region outside the gate region. These process steps are as follows: Figures 5I to 5K As shown, the steps are the same as those described in the aforementioned manufacturing process.

[0097] Further specific concepts in this embodiment are as follows: Figure 5LThe process is explained below. A controlled etching process is used to etch the gate structure, including the gate insulating layer 506 and the gate conductor 507, so that the upper surface of the gate is approximately flush with or horizontally aligned with the upper surface of the active layer 503. The corresponding technical effect is that the gate structure is aligned with the active layer 503, minimizing overlap with the second electrode 504. This helps reduce parasitic capacitance in the transistor. After the gate structure is formed, this process continues by depositing the ILD layer 508 and defining the contacts. This... Figures 5M to 5O As shown, it is equivalent to Figures 3J to 3L Therefore, no further explanation is needed. Thus, contact regions 519, 520, and 521 are opened for the contact portions of the first electrode 509, the second electrode 510, and the gate 511 by photolithography and dry etching.

[0098] In this embodiment, the expression "flush" should be understood as meaning that the gate conductor 507 is configured at approximately the same level as the active layer 503 on both the bottom and top surfaces. The thickness of the gate conductor 507 is approximately the same as the thickness of the active layer 503, and their respective positions minimize the overlap between the gate conductor 507 and the first electrode 502 or the second electrode 504. A further variation under the same concept may include a gate conductor 507 having a thickness less than the active layer 503. By appropriately adjusting the height of the spacer SP5 and the etching following the deposition of the gate insulating layer 506 and the gate conductor 507, a gate conductor 507 with a thickness within the thickness of the active layer 503 can be obtained; in other words, the active layer 503 may overlap with the gate conductor 507 on both the bottom and top surfaces.

[0099] Further embodiments include a gate-all-around (GAA) configuration, which will be referred to Figures 6A to 6O Presented. In this embodiment, a gate surrounding the semiconductor is defined. In particular, the gate is disposed on the outer periphery of the overlapping region between the electrodes. Similar to previous embodiments, this embodiment also allows for large-area contact between the gate and the active layer, which facilitates transistor operation. In variations of the GAA configuration, more than one gate can also be implemented, where each side can serve as a separate control gate.

[0100] and Figures 5A to 5O The illustrated embodiments are similar, and the embodiment in Figure 6 also features a side gate aligned with the active layer. For this reason, only the novel concept of this implementation will be explained below.

[0101] Figures 6A to 6C Roughly equivalent to Figures 4A to 4C Therefore, no further explanation is needed. In particular, in this case, the bottom electrode 609 is also used as the first electrode 602. Figure 6DThe patterning steps defining the overlapping areas are illustrated. Similar to the previous embodiments, this patterning step includes photolithography and dry etching.

[0102] In this case, the first electrode 602, the second electrode 604, and the active layer 603 perfectly overlap, that is, they all have approximately the same size, so that after patterning, none of them extends beyond the others in the horizontal plane.

[0103] Figure 6F The patterning of region 617 for gate arrangement is shown after the deposition of ILD layer 608. As mentioned, this is a GAA embodiment, and unlike previous designs, the gate region is no longer located inside or embedded in the overlap region, but rather surrounds the overlap region, i.e., the region is configured near the outer periphery but outside of it. Furthermore, also... Figure 6F As shown, the recess for the gate region extends laterally, thereby defining the side gate. The remaining steps ( Figures 6G to 6O This involves forming an isolator SP6 using an additional dielectric SP61 and etching the gate structure (gate insulating layer 606 and gate conductor 607) to enable the gate to... Figure 6L The alignment shown is 603 with the active layer. Steps and references are required to achieve this alignment. Figures 5A to 5O The steps described are the same, so it is believed that no further details need to be disclosed.

[0104] When the gate conductor 607 is aligned with the active layer 603, if the thickness of the gate conductor 607 is approximately the same as the thickness of the active layer 603, then the bottom / top surfaces of the gate conductor 607 are aligned with the bottom / top surfaces of the active layer 603. In a variation of this embodiment, the thickness of the gate conductor 607 can be less than the thickness of the active layer 603, such that the active layer 603 overlaps with the gate conductor 607. In other words, by making the thickness of the gate conductor 607 less than the thickness of the active layer 603, a design can be achieved where the bottom surface of the gate conductor 607 is slightly higher than the bottom surface of the active layer 603, while the top surface of the gate conductor 607 is at a slightly lower level than the top surface of the active layer 603. In this manner, improved performance can be obtained by further minimizing any overlap between the gate conductor 607 and the first electrode 602 or the second electrode 604.

[0105] The remaining steps involve defining the contacts of the first electrode 609, the second electrode 610, and the gate 611 after establishing the contact openings for the second electrode 620 and the gate 621. These steps are equivalent to those described in reference to [reference needed]. Figure 5G to Figure 5O The steps explained are so detailed that no further explanation is needed.

[0106] Figures 21A to 21HThe process steps for fabricating another embodiment of a vertical field-effect transistor are shown. In this embodiment, the definition of the gate region is different as illustrated in the figures.

[0107] Figure 21A The situation shown is combined with the previous text. Figure 6D The situation described above is similar. At this stage of the manufacturing process, the system includes a first electrode 752 formed on a substrate 751. In this embodiment, the contact of the first electrode 752 is a bottom electrode 759. On the other hand, an active layer 753 and a second electrode 754 are also present.

[0108] Note that, referring to the previous... Figure 6C and Figure 6D , Figure 21A The stage shown can be achieved after etching the second electrode 754 and the active layer 753 in an area that does not overlap with the first electrode 752, so that the first electrode 752, the second electrode 754, and the active layer 753 perfectly overlap. Nevertheless, patterning and etching in this case can also remove some material from the substrate 751. Therefore, as also... Figure 21A As shown, the upper surface of the substrate 751 after the etching step is not aligned with the lower surface of the active layer 753. In particular, as Figure 21B As shown, there is a gap between the upper surface of the substrate 751 and the lower surface of the active layer 753, the width of which approximately corresponds to the thickness of the gate insulating layer 756. As a result of etching, at least a portion of the active layer 753, corresponding to the thickness of the active layer 753, is exposed and exists in a certain region 777, which serves as the gate region in this embodiment.

[0109] The next possible step in this embodiment is presented as follows: Figure 21B and Figure 21C This involves depositing a gate insulating layer 756 over the entire substrate and subsequently depositing a gate conductor 757 over the previously deposited gate insulating layer 756. In this manner, the gate insulating layer 756 is disposed between the gate conductor 757 and all other portions (i.e., the active layer 753, the substrate 751, and the second electrode 754). It should be noted that, because in such... Figure 21A During the etching process shown, a gap is created between the upper surface of the substrate 751 and the lower surface of the active layer 753, and the upper surface of the gate insulating layer 756 is aligned with the lower surface of the active layer 753. This allows the lower surface of the gate conductor 757 to be substantially aligned with the active layer 753 in its respective lower surface.

[0110] ILD layer 755 is deposited across the entire surface to provide a flat surface, which in Figure 21EThe steps described involve etching. Following etching, a CMP process can be performed to remove the gate conductor 757 and gate insulating layer 756 from the top region of the second electrode 754, thereby enabling subsequent contact with this electrode. To define the contact for both the second electrode 754 and the gate conductor 757, an additional dielectric layer 758 can be deposited to prepare for contact patterning. This can be done... Figure 21G As can be seen, this results in the formation of cavities 771 and 770, which are intended to contact the second electrode 754 and the gate conductor 757, respectively. The deposition of the dielectric layer 758 is selective. In this embodiment, the transistor... Figure 21H The steps in are completed, wherein contact material is deposited to produce contact 761 for the second electrode 754 and contact 760 for the gate conductor 757.

[0111] A similar approach can be used to combine gate-all-around (GAA) and semiconductor-all-around (SAA) configurations. This design increases the gate area for better control of the gate-induced field effect in the active channel material (e.g., semiconductor). This combination is particularly convenient for designs involving relatively large overlap areas. While a gate-all-around semiconductor configuration can provide a large contact area, it may be difficult to induce a field effect across the entire semiconductor layer in some cases. Therefore, combining it with an inner gate not only allows for a larger contact surface but also a better electric field distribution. (See reference...) Figures 22A to 22N Describe this combination.

[0112] Figure 22A Showing a diagram similar to the previous one (e.g.) Figure 6C A similar stage has been described in [the previous section]. A first electrode 852 is formed on a substrate 851. In this embodiment, the first electrode 852 has a bottom contact 859. An active layer 853 is deposited on top of the first electrode 852, and the active layer 853 is sandwiched between the first electrode 852 and the second electrode 854. Figure 22B The patterning and etching steps shown are such that, in this embodiment, the first electrode 852, the active layer 853, and the second electrode 854 overlap in the same overlapping area, i.e., they overlap substantially perfectly. The next step in the manufacturing sequence according to this embodiment is presented in... Figure 22C In the middle, interlayer dielectric 855 was deposited.

[0113] Figure 22D The key differences from other described embodiments are schematically illustrated. Therefore, not only is a single gate region defined, but a combination of SAA and GAA methods is used by defining two regions. In particular, a first gate region 867a is defined, which is disposed on the outer periphery of the overlapping region. This first gate region 867a is consistent with reference to... Figures 3A to 3LThe gate region defined (i.e., in the SAA configuration) is similar. The second gate region 867b is defined to surround the active layer 853. This second gate region 867b has a gate-all-around (GAA) concept, which is similar to the concept regarding... Figures 6A to 6O The illustrated embodiment combines these two methods to achieve a large contact area between the gate and the active layer 853, resulting in more uniform channel formation and better transistor control.

[0114] To improve transistor performance, previous embodiments (see...) Figure 5L or Figure 6L The use of an aligned gate configuration, i.e., a configuration in which the gate conductor is substantially aligned with the active layer, has already been shown. This is also shown in this embodiment. Therefore, Figure 22E This shows the deposition of dielectric SP81, which was then etched to form a structure as shown. Figure 22F The isolation element SP8 is shown. The process for manufacturing the isolation element SP8 is equivalent to that described with reference to the previous embodiments, and therefore further details are not required.

[0115] Figure 22G and Figure 22H The deposition of gate insulating layer 856 and gate conductor 857 is shown. Then, as explained in the previous embodiments, the portions of gate insulating layer 856 and gate conductor 857 that are not on the gate regions (867a and 867b) are removed (see [reference]). Figure 22I In addition, in order to reduce parasitic capacitance and optimize device performance, such as Figure 22J As shown, the gate insulating layer 856 and the gate conductor 867 are etched so that their upper surfaces are approximately aligned with the upper surface of the active layer 853.

[0116] The final step corresponds to the formation of electrical contacts. Next, an interlayer dielectric 858 (equivalent to the process already described) is deposited. Figure 22K And implement as follows Figure 22L The patterning steps shown are used to create cavities for the contacts. Specifically, cavity 870 is created for contacting the second electrode 854. In this embodiment, since we have two gate regions, care must be taken to how the two cavities are used for the gate. In practice, a first gate cavity 871a is formed for the gate region located within the overlap region (i.e., the SAA gate), and a second gate cavity 871b is formed to contact the gate region surrounding the active layer 853. Finally, conductive material is deposited to create the contacts. Specifically, contact 860 is formed for the second electrode, and two contacts 861a and 861b are formed respectively for the gate conductor disposed in the first gate region 867a and the gate conductor disposed in the second gate region 867b.

[0117] In this variation of the embodiment, contacts 861a and 861b can be as follows: Figure 22N The connection shown is shown in the diagram.

[0118] In this embodiment, the contact 860 of the second electrode 854 is not perfectly aligned. This is preferred in this particular embodiment because the second electrode 854 has a small horizontal dimension in the contact area. Nevertheless, in further variations, the contact 860 may be aligned with the second electrode 854. In even further variations, the contact 860 may contact the second electrode 854 on one side. These variations are schematically illustrated in... Figure 22O (Aligned top contact) with Figure 22P (Side contact) is shown.

[0119] So far, different manufacturing processes have been disclosed, resulting in vertical field-effect transistors with different gate architectures. Furthermore, further variations may be possible depending on the specific active material used for the active layer. In the embodiments described below, designs incorporating different materials will be described. Even though they will refer to one of the previous designs (especially those corresponding to...) Figures 3A to 3L The design is intended to be presented in a way that is by no means limiting, as the same material may be used with any previously disclosed variations, or further with the variations covered by this application.

[0120] Figures 7A to 7D The following describes the initial steps of a fabrication process for a vertical field-effect transistor according to another embodiment, wherein single-walled carbon nanotubes (SWCNTs) are used as the active material. Specifically, the transistor of this embodiment has a single row of SWCNTs arranged parallel to the substrate along its longitudinal axis; that is, if the substrate is also arranged horizontally, then the SWCNTs are also arranged horizontally. This arrangement results in current flowing laterally to the SWCNTs rather than simply along their own axis, which can lead to channel lengths in the range of ~1 nm (e.g., the thickness of the active material of the CNTs). In further embodiments, multi-walled CNTs or other 1D materials such as MoS2 nanotubes, WS2 nanotubes, nanowires, or nanopillars can also be used.

[0121] The first step in the process ( Figure 7A This includes forming a first electrode 702 on the substrate 701, thus this is equivalent to the previous method. Subsequently, as... Figure 7A As shown, single-row SWCNTs 703 are formed on a substrate. SWCNTs can be obtained, for example, by chemical vapor deposition (CVD) or arc discharge, followed by pre-cleaning before deposition onto the substrate. Alternatively, carbon nanotubes can also be grown directly on the substrate. It should be noted that when carbon nanotubes are used as the active material, there is a certain risk of short circuit between the first electrode 702 and the second electrode 704. In fact, some gaps G7 can exist on the single-row SWCNTs 703 (see...). Figure 7A(Enlarged view). To mitigate this risk, some additional steps are proposed in this embodiment.

[0122] These additional steps refer to Figure 7B and Figure 7C Explanation. Therefore, after depositing SWCNTs 703, a conformal dielectric 733 (e.g., SiO2) can be deposited on the SWCNTs 703. Standard techniques such as chemical vapor deposition (CVD) can be used to deposit the conformal dielectric 733, with ALD being a preferred technique. This conformal dielectric 733 is the filler material that fills all voids or gaps between the SWCNTs 703 to create a compact structure. Of course, direct contact between the second electrode 704 and the active material, i.e., the single-row SWCNTs 703, is required during operation. Therefore, the method can further include etching of the conformal dielectric 733, for example by atomic layer etching (ALE), in a vapor-based etching environment, wet etching, or plasma etching, until the SWCNTs 703 are exposed. Selective etching that does not affect the CNTs can be used, or a precise etching environment with non-selectivity or limited selectivity can be employed. It is worth noting that ALD deposition of insulators has a relatively low bias towards the nucleation and growth of materials such as CNTs, allowing for etching processes (if necessary) and CNT exposure processes without etching the CNTs. Figure 7B and Figure 7C The process steps result in a dense active layer comprising a row of SWCNTs 703 within a matrix of conformal dielectric 733. Subsequent steps begin with the deposition of a second electrode 704 on the formed active layer and end with the formation of the final contact. Nevertheless, these steps are equivalent to those already performed, for example... Figures 3C to 3L The steps have already been explained, so no further explanation is needed.

[0123] Previous Figures 7A to 7D This refers to using only single-row SWCNTs 703. Nevertheless, the same process can be used for other 1D materials, such as multi-walled CNTs, MoS2 nanotubes, WS2 nanotubes, nanowires, or nanopillars.

[0124] Figures 8A to 8D This illustration shows the use of single-walled carbon nanotubes (SWCNTs) in a stacked configuration. In this case, multiple rows, preferably at least five rows, of SWCNTs 803 are used as the active material. SWCNTs are provided on a substrate 801. Using aligned single-walled carbon nanotubes can increase the nanotube density between electrodes, thereby increasing the carrier density. In alternative embodiments, multi-walled CNTs or other 1D materials can be used instead of SWCNTs. The aligned nanotubes can be pre-purified and aligned during deposition, or they can be grown directly on the first electrode. In the previous case, some gaps may exist in the structure ( Figure 8A (G8 in the enlarged diagram). Therefore, as explained with respect to the previous example, Figure 8B and Figure 8C The image shows the deposition of conformal dielectric material 833 and the subsequent etching process. Figure 8C ).

[0125] In contrast to single-row SWCNTs, the use of multi-row SWCNTs 803 in the active layer offers significant advantages in terms of transistor immunity to the presence of metallic carbon nanotubes. It is known that some SWCNTs may exhibit metallic properties during the fabrication process. Using such SWCNTs in a configuration with single-row SWCNTs (as shown in Figure 7) can cause a short circuit between the first and second electrodes, damaging the transistor. By using multi-row CNTs as shown in Figure 8, the risk of a short circuit between the first electrode 802 and the second electrode 804 is mitigated because current flows laterally through the SWCNTs, and the probability of a complete electrical path for metallic CNTs between the source and drain is extremely low. Using aligned carbon nanotubes can also increase current density.

[0126] Figures 9A to 9D Another variation involves using SWCNTs as the active material. In this case, a network or mesh of carbon nanotubes 903 is used and disposed on a substrate 901. The carbon nanotubes can be pre-purified and deposited in this process. In this embodiment, the density of SWCNTs is lower than in the previously described embodiments. Nevertheless, this solution has advantages in terms of ease of fabrication. In any case, as... Figure 9B and Figure 9C As shown, several steps are proposed to achieve a compact active layer. As previously explained, a conformal dielectric 933 is used to provide a compact structure to avoid short circuits between the first electrode 902 and the second electrode 904. Similar to previous embodiments, by using multiple rows of CNTs as shown in FIG. 9, the risk of short circuits between the first electrode 902 and the second electrode 904 is mitigated because the probability of current flowing laterally to the SWCNTs and having a complete electrical path between the metal CNTs and the source and drain is extremely low. Furthermore, as in previous embodiments, networks or meshes of other 1D materials can be employed in different examples.

[0127] Figures 10A to 10DExamples corresponding to the use of different types of active materials. In this case, a two-dimensional material is employed. In a particularly preferred embodiment, a transition metal dichalcogenide (TMD) such as MoS2 or WS2 is used. The most suitable material selection depends on factors such as whether the transistor has P-type or N-type characteristics. In this sense, different fabrication processes can be used to modify the active layer, such as doping, annealing, or other known operations, thereby altering the characteristics of the active layer. The 2D material can be grown via, for example, chemical vapor deposition (CVD), atomic layer deposition (ALD), transfer, spin coating deposition, chemical deposition by dip coating, etc. The 2D material is arranged with its plane generally parallel to the substrate, such that current flows along the thickness of the 2D material, i.e., transversely to the plane of the 2D material. Figure 10A As shown, the configuration of the 2D material 1003 on the substrate 1001 where the first electrode 1002 is formed may also result in the presence of some voids (G10 in the enlarged view). Therefore, the same steps as in the CNT-based design already explained are still required, and a conformal dielectric 1033 is used to provide a compact active layer to prevent short circuits between the first electrode 1002 and the second electrode 1004.

[0128] The vertical FETs in the embodiments of the present invention exhibit vertical current, which is particularly advantageous for vertical stacks in complementary circuits comprising at least one P-type transistor and one N-type transistor. Further size reduction becomes feasible for complementary configurations by vertically arranging the two transistors. Nevertheless, it should be understood that further embodiments are conceivable in which the P-type vertical FET and the N-type vertical FET can also be configured horizontally, i.e., the first vertical FET is arranged to the side (rather than on top) of the second vertical FET.

[0129] Figures 11A to 11O An embodiment of the converter manufacturing process is provided. To avoid repeating details already provided, the starting point of this sequence corresponds to... Figure 3L This refers to the fabricated vertical FET 1100. This vertical FET 1100 is assumed to be either P-type or N-type. The P-type or N-type characteristics of a transistor depend on the materials used for each electrode, as they determine the deformation of the valence and conduction bands of the semiconductor at the interface. The type can also depend on the properties of the semiconductor itself. Dopants can be added to obtain N-type characteristics (electron donor doping) or P-type characteristics (electron acceptor doping). Environmental dopants can be used, such as those in contact with organic or inorganic dopant materials / molecules. Furthermore, when available, the behavior of the semiconductor can also be defined by the conformal dielectric used to provide a compact active layer. In addition, it is known that some materials exhibit P-type or N-type characteristics, or their effective semiconductor characteristics can be tuned using processes such as doping or annealing. The polarity of a P-type or N-type device can be tuned by changing the metals used for the source and drain.

[0130] Figure 11A Different portions of the first FET 1100 are presented. A substrate 1101 on which a first electrode 1102 is formed is used. An active layer 1103 is sandwiched between the first electrode 1102 and the second electrode 1104. The gate structure is formed as previously explained, and it includes a gate insulating layer 1106 and a gate conductor 1107. Finally, a first contact 1109 is formed for the first electrode 1102, a second contact 1110 is formed for the second electrode 1104, and a third contact 1111 is formed for the gate conductor 1107. As in the previous embodiment, a first dielectric layer 1105 and a second dielectric layer 108 are also provided.

[0131] To manufacture the converter, a second vertical FET 1200 is fabricated on top of the first FET 1100. (As in...) Figure 11B As indicated, the interlayer dielectric layer 1201 is deposited on top of the first (or lower) vertical FET 1100. The ILD layer may include any dielectric material already mentioned when describing the other ILD layers. The ILD layer 1201 serves as the substrate for the second (i.e., upper) vertical FET 1200. Then, Figures 11C to 11I The following manufacturing steps are shown; in this particular embodiment, the corresponding steps are, for example, in... Figures 3A to 3G The steps already presented, namely up to the deposition of the gate insulating layer 1206, are as follows: A first electrode 1202, an active layer 1203, and a second electrode 1204 are fabricated for the upper transistor. Then, an ILD layer 1205 is deposited before defining the region 1217 for the gate configuration of the upper transistor.

[0132] exist Figure 11J The differences can be identified, which is related to the function of the manufactured logic circuit, i.e., the converter. To construct the converter, the gates of both the P-type and N-type transistors are connected. Therefore, Figure 11J The etching of the gate insulating layer 1206 shown in the diagram removes the insulating layer at the bottom of the gate region or the cavity / well of the upper transistor 1200, thereby exposing the third contact 1111 of the first FET 1100. Figure 11K The deposition of gate conductor 1207 is shown. In this case, it allows control not only of the upper vertical FET 1200 but also the gates of both the transistors (1100 and 1200) that are electrically connected. The gate conductor is deposited across the entire surface, therefore, as in the previous case, a CMP process step is required so that the gate insulating layer 1206 and the gate conductor 1207 are deposited only at the gate location. Figure 11L ).

[0133] After the gate conductor is removed, the process is prepared to define the different device contacts. For example... Figure 11M As shown, to achieve these contacts, an additional ILD layer 1208 can be deposited. Subsequently, as... Figure 11N The diagram schematically illustrates how contacts can be patterned using photolithography and dry etching steps. The position of the contacts again depends on the functionality of the logic circuit. The contact of the first electrode 1202 of the upper vertical FET 1200 is aligned with the second contact 1110 of the second electrode 1104 of the lower vertical FET 1100. To achieve this connection, pattern 1229 is fabricated in this structure. This connection corresponds to the output of the converter. On the other hand, pattern 1119 is fabricated for the first electrode 1102 of the first FET 1100, in which case pattern 1119 contacts from the top (see...). Figure 12 As an alternative embodiment, another pattern 1220 is provided for the second electrode 1204 of the upper vertical FET 1200. Finally, a pattern 1221 is fabricated for the gate.

[0134] After all contacts are patterned, contact conductors are deposited to achieve the electrical connection and operation of the converter. Specifically, the first contact 1109 is used to connect the first electrode 1102 of the first FET 1100 to Vdd or Vss. The second electrode 1210 is used to subsequently connect the second electrode 1204 of the upper transistor 1200 to another of Vdd or Vss. The third contact 1211 is used for the gate conductor 1207 of the upper vertical FET 1200, and as previously mentioned, the third contact 1211 is also connected to the gate conductor 1107 of the first FET 1100. This contact is the input of the converter. Finally, the fourth contact 1209 is used for the first electrode 1202 of the upper transistor 1200, which is connected to the second electrode 1104 of the first FET 1100. This fourth contact is the output of the converter.

[0135] Although the converter shown in Figure 11 is based on Figures 3A to 3L The presented vertical FET embodiment is a finless semiconductor all-around (SAA) transistor, but it should be understood that the same principles apply to other embodiments.

[0136] In a non-limiting embodiment (in a specific example?), Figure 12 This illustrates a converter arrangement including a bottom contact 1249 for a first electrode of a lower vertical FET. The bottom contact is also used... Figure 13 and Figure 14 The converters shown are based on Figures 4A to 4L (SAA with fins) and Figures 5A to 5O The architecture described in (GAA). Figure 13The diagram shows vertical FETs, each of which includes a fin. The configuration of the gate insulating layer 1316 and the gate conductor 1317 enables the existence of a transistor with a fin structure. The same applies to the upper transistor based on the configuration of its gate insulating layer 1326 and the gate conductor 1327. (See reference...) Figure 14 The configuration of the gate insulating layers 1416 and 1426 and the gate conductors 1417 and 1427 of the lower transistor and the upper transistor respectively results in the configuration of the gate completely covering the overlapping periphery of the overlapping region of the two transistors.

[0137] In embodiments of the present invention, the materials used in the complementary arrangement of the vertical field-effect transistor stack structure are not limited to a specific type. Figure 15 An embodiment of a converter is provided, comprising single-row SWCNTs 1513 for the lower transistor and another single-row SWCNTs 1523 for the upper transistor. In fact, a shorter channel length can be obtained by using bonded or partially bonded SWCNTs. Such bonded or partially bonded SWCNTs can be considered as bent graphene. This is depicted in... Figure 16 The rheostat includes a column of broken-bonded SWCNTs 1613 for the lower transistor and another column of unbroken-bonded SWCNTs 1623 for the upper transistor. These broken-bonded or partially broken SWCNTs can be prefabricated and deposited on a substrate. Alternatively, a single column of standard SWCNTs can be deposited. A conformal dielectric layer as described above can then be deposited to obtain a compact layer. Finally, the dielectric layer can be etched in such a manner that at least some of the SWCNTs are also etched, resulting in a layer with unbroken SWCNTs. As in the previous embodiments, in this case, 1D materials other than SWCNTs can be used as a further variation of this embodiment. Finally, Figure 17 Examples are provided including 2D materials 1713-1723 for use in the lower and upper transistors.

[0138] The flexibility of manufacturing technology can also be used to combine vertical FETs, including different types of active materials, in the same circuit. As an example, Figure 18 A converter circuit is shown, wherein the lower vertical FET includes an active layer 1813 with a 2D material, and the upper vertical FET includes an active layer 1823 comprising a single-row SWCNTs as the active material. The choice of one active material or another can depend on the functionality required for each device, and more specifically on the desired P-type or N-type characteristics. For example, it is known in the art that most transition metal dichalcogenide (TMD) materials exhibit n-type characteristics without intentional doping, while most semiconductor CNTs exhibit p-type characteristics.

[0139] In a further embodiment, the vertical FET can be fabricated using an active layer comprising multiple sublayers to achieve desired transistor characteristics. Based on this, Figure 19 An exemplary converter is shown, wherein the lower transistor includes an active layer with three sublayers: one of the sublayers 1913b comprises single-row SWCNTs and is sandwiched between two other sublayers (1913a and 1913c) comprising 2D material (e.g., WS2 or MoS2). In this particular embodiment, the upper transistor employs the opposite arrangement, and its active layer also comprises three sublayers. However, in this case, the middle sublayer 1923b is a layer comprising 2D material, while the other two sublayers (1923a and 1923c) comprise single-row SWCNTs. Other compositions are also possible. In particular, different numbers of sublayers can be used in the lower and upper transistors. For other embodiments, the combination of active materials can also vary, and, for example, the active layer may comprise sublayers of different types of semiconductors but having similar geometries, such as a stack of 2D material sublayers comprising, for example, a combination of MoS2 and WS2. This arrangement exists in Figure 20 The converter shown is an example of a design where both the lower and upper converters contain active layers with different sublayers, but they are made of materials with similar geometries. The lower vertical FET includes sublayers 2013a-c, while the upper vertical FET includes sublayers 2023a-c for their respective active layers.

[0140] Although vertical FETs with active layers comprising multiple sublayers have been proposed in the context of rheostat circuits, it should be understood that this is provided only as an example. In fact, the same concept can be used for any other logic circuit and / or a single transistor. Therefore, vertical FETs according to embodiments of the present invention can be used in any electronic device using integrated circuits. Examples of such electronic devices include, but are not limited to, mobile phones, personal computers, televisions, music players, drones, automobiles, radios, medical devices, memory, telecommunications systems, navigation systems, or wearable devices.

[0141] Figure 23A flowchart illustrating a non-limiting method 3000 for manufacturing a vertical field-effect transistor according to an embodiment is shown. In step 3100, method 3000 includes providing a substrate and forming a first electrode on the substrate. In step 3200, an active layer is deposited on the previously obtained first electrode. The method then proceeds to step 3300, where a second electrode is deposited overlapping the first electrode. The next step 3400 consists of patterning the second electrode with the active layer. As a result of this patterning, a specific overlap region is defined where the second electrode overlaps with the first electrode. The overlap region is defined by its periphery. The next step 3500 of method 3000 involves patterning a transistor gate region, which in some embodiments may resemble a cavity or well. This region exposes at least a portion of the previously deposited active layer. The gate structure for controlling the transistor then needs to be formed. In step 3600, a gate insulating layer is formed covering the exposed portion of the active layer, and in step 3700, a gate conductor is deposited on the gate insulating layer. The gate conductor is used to apply a voltage controlling the conduction state of the active layer, while the gate insulating layer ensures that the gate conductor does not directly contact the electrode or channel. Finally, in step 3800, contacts are deposited to enable the first electrode, the second electrode, and the gate to be connected to the outside.

[0142] like Figure 23 As shown in the flowchart, in step 3200, an active layer needs to be deposited on the first electrode. This step becomes particularly challenging when using active materials because the properties or formation process of the active materials can result in a non-dense layer with voids or gaps. This can happen when using 2D materials or carbon nanotubes. Those gaps can lead to direct electrical contact between the first and second electrodes, causing a short circuit in the transistor. To avoid this failure mechanism, Figure 24 The diagram illustrates a method 4000 for fabricating an active layer. In step 4100, a first layer of active material is obtained on the first electrode of the transistor. This layer may exhibit varying degrees of porosity. The process then proceeds to step 4200, where a conformally filled interlayer dielectric (ILD) layer is deposited on top of the active material. This dielectric fills the gaps in the initial active layer, thereby forming a compact structure. The active material must be in clear contact with the second electrode. For this purpose, a third step 4300 is required to complete the active layer. In this step, the ILD layer is etched in a controlled manner (if necessary) until the active material is exposed, and accordingly, as shown in the diagram... Figure 23 In subsequent steps of the entire process shown in step 3300, it contacts the second electrode deposited on its surface.

[0143] For clarity, although most embodiments involving one-dimensional materials are described using carbon nanotubes as an example, it should be understood that other 1D materials, such as MoS2 nanotubes, WS2 nanotubes, nanowires, or nanopillars, can also be used in the examples shown. Similarly, examples involving 2D materials should not be construed as limited to specific 2D materials, and it should be clear that different materials, such as graphene, MoS2, or WS2, can be used in different variations.

Claims

1. A vertical field effect transistor, characterized by, Comprising: a substrate; a first electrode on the substrate configured as a source or drain of the transistor; a second electrode configured as the other of the source and drain of the transistor, wherein the second electrode at least partially overlaps the first electrode in an overlap region; an active layer sandwiched between the first electrode and the second electrode; and a gate having a gate conductor portion and a gate insulating layer configured between the gate conductor portion and the active layer; wherein the active layer comprises a one-dimensional material configured with its longitudinal axis parallel to the substrate, and / or the active layer comprises a two-dimensional material configured with its plane parallel to the substrate.

2. The vertical field effect transistor of claim 1, wherein, The active layer comprises nanocarbon tubes.

3. The vertical field effect transistor according to claim 1 or 2, wherein The active layer further comprises a conformal dielectric.

4. The vertical field effect transistor of claim 1, wherein, The overlap region has a periphery, and wherein the gate is at least partially configured within the periphery of the overlap region.

5. The vertical field effect transistor of claim 4, wherein the gate oxide layer is formed of silicon dioxide. The gate comprises a first insulating layer having a U-shaped cross-section and a second insulating layer having a U-shaped cross-section, wherein the first and second U-shaped insulating layers are separated by a portion of the first electrode, the active layer, and the second electrode.

6. The vertical field effect transistor of claim 4, wherein the gate oxide layer is formed of silicon dioxide. The gate is entirely configured within the periphery of the overlap region.

7. The vertical field effect transistor of claim 4, wherein the gate oxide layer is formed of silicon dioxide. The gate extends beyond at least one side of the periphery of the overlap region.

8. The vertical field effect transistor of claim 1, wherein, The overlap region has a periphery, and wherein the gate is configured outside and adjacent to the periphery of the overlap region.

9. The vertical field effect transistor of claim 7 or 8, wherein the gate electrode is formed of a material having a work function of 4.5 eV or more. The gate is configured to be flush with the active layer.

10. The vertical field effect transistor of claim 1, wherein, The active layer comprises a plurality of sub-layers, wherein at least two of the sub-layers each comprise a different type of active material.

11. A semiconductor structure, characterized by Comprising a first vertical field effect transistor as claimed in claim 1, which is a vertical field effect transistor, and a second vertical field effect transistor as claimed in claim 1, which is a vertical field effect transistor, disposed on top of or on a side of the first vertical field effect transistor, wherein the first vertical field effect transistor is a P-type transistor or an N-type transistor, and the second vertical field effect transistor is the other of the P-type transistor or the N-type transistor.

12. A method of manufacturing the vertical field effect transistor of claim 1, wherein, Comprising the steps of: forming a first electrode on a substrate; depositing an active layer on the first electrode; depositing a second electrode on the active layer to form a sandwich structure having an overlap region with a periphery; forming a gate region exposing at least a portion of the active layer; depositing a gate insulating layer covering the exposed portion of the active layer; depositing a gate conductor on the gate insulating layer such that the gate insulating layer is configured between the gate conductor and the active layer; and forming electrical contacts to the first electrode, the second electrode, and the gate conductor. Forming the gate region comprises forming the gate region in a region extending beyond the periphery of the overlap region, or forming the gate region in a region surrounding the periphery of the overlap region, the method further comprising:

13. The method of fabricating a vertical field effect transistor of claim 12, wherein, ​ forming spacers in the gate region prior to depositing the gate insulating layer such that the resulting bottom level of the gate region has a height that results in the bottom surface of the gate conductor being flush with the bottom surface of the active layer, and etching the gate insulating layer and the gate conductor as they are deposited such that the top of the remaining gate insulating layer and gate conductor is flush with the upper surface of the active layer.

14. The method of fabricating a vertical field effect transistor of claim 12, wherein, forming the gate region includes forming a cavity, and depositing the gate insulating layer includes depositing the gate insulating layer to cover the inner walls of the cavity.

15. The method of fabricating a vertical field effect transistor of claim 12, wherein, depositing the active layer includes depositing a layer that includes nanotubes and / or two-dimensional materials as a semiconducting material, and the method further includes: depositing a conformal dielectric layer on top of the active layer after depositing the active layer; and etching the conformal dielectric layer to expose the active material of the active layer prior to depositing the second electrode. forming spacers in the gate region prior to depositing the gate insulating layer such that the resulting bottom level of the gate region has a height that results in the bottom surface of the gate conductor being flush with the bottom surface of the active layer, and etching the gate insulating layer and the gate conductor as they are deposited such that the top of the remaining gate insulating layer and gate conductor is flush with the upper surface of the active layer. forming the gate region includes forming a cavity, and depositing the gate insulating layer includes depositing the gate insulating layer to cover the inner walls of the cavity. depositing the active layer includes depositing a layer that includes nanotubes and / or two-dimensional materials as a semiconducting material, and the method further includes: depositing a conformal dielectric layer on top of the active layer after depositing the active layer; and etching the conformal dielectric layer to expose the active material of the active layer prior to depositing the second electrode.

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