PCB expansion back cavity packaging process

Abstract

The invention discloses a PCB expansion back cavity packaging technology, and belongs to the technical field of semiconductor packaging. The process comprises the following steps: (1) dispensing and mounting an ASIC integrated chip on a PCB substrate, and baking and curing the ASIC integrated chip; (2) coating glue on the PCB substrate to mount the MEMS capacitive chip, baking and curing, forming an expansion back cavity on the PCB substrate, and enabling the expansion back cavity to correspond to a self-contained cavity of the MEMS capacitive chip; (3) bridging the MEMS capacitive chip and the ASIC chip by using a gold thread, and carrying out gold thread bridging on the ASIC chip and the PCB welding spot; (4) dispensing on the surface of the ASIC chip to protect the chip; (5) coating a tin frame area on the periphery of the product with solder paste; and (6) after the solder paste is coated, SMT shell pasting is carried out, and reflow soldering curing is carried out. According to the invention, the back cavity is expanded to design the packaging layout on the PCB substrate, so that the back cavity space of the MEMS capacitive chip is increased, and the performance is improved; in the packaging process, the harsh requirement for the height of chip glue is reduced, the product operation cost is reduced, the packaging technological process is simplified, and the product performance is optimized.

Description

Technical Field

[0001] This application belongs to the field of semiconductor packaging technology, and in particular relates to a PCB extended cavity packaging process. Background Technology

[0002] Current conventional silicon microphone PCB design and packaging involves placing MEMS capacitor chips and ASIC integrated chips in parallel on a PCB substrate. Adhesive is used to fix the MEMS capacitor chips and ASIC integrated chips to the PCB. Next, gold wire bonding is used with specialized equipment to connect the MEMS capacitor chips to the ASIC integrated chip, and the ASIC integrated chip to the PADs (soldering points) on the PCB substrate. Then, after applying solder to the corresponding positions on the PCB, the outer shell is assembled. After reflow soldering, the outer shell is fixed to the PCB substrate, completely enclosing the MEMS capacitor chips and ASIC integrated chips to form the required cavity, ultimately achieving the product's acoustic-to-electrical signal conversion function. The above packaging process has the following drawbacks: 1. High requirements for the substrate adhesive of MEMS capacitive chips, resulting in high production costs; 2. The product has a compact structure design, but its volume is relatively large, and the gold wire height tolerance requirement is relatively high; 3. The production process is relatively complex; 4. The signal-to-noise ratio (SNR) is low. Summary of the Invention

[0003] The purpose of this application is to provide a PCB extended cavity packaging process, which involves opening an extended cavity in the middle of the PCB to increase the cavity space of the MEMS capacitive chip, optimize the SNR signal-to-noise ratio, simplify the manufacturing process, reduce the production cost, and make the product structure more compact, which is conducive to the miniaturization of the product.

[0004] To achieve the above-mentioned objectives, the technical solution adopted in this application is as follows: This application provides a PCB extended cavity packaging process, including the following steps: (1) Apply adhesive to the ASIC integrated chip on the PCB substrate and bake to cure; (2) Apply adhesive to the PCB substrate, mount the MEMS capacitive chip, bake and cure. An extended back cavity is provided on the PCB substrate, which corresponds to the built-in cavity of the MEMS capacitive chip. (3) Bridge the MEMS capacitive chip and the ASIC chip with gold wire, and bridge the ASIC chip with gold wire to the PCB solder joint; (4) Apply adhesive to the surface of the ASIC chip to protect the chip; (5) Apply solder paste to the solder frame area around the product; (6) After applying solder paste, SMT is installed on the housing and then reflow soldered for curing.

[0005] In some embodiments, the extended back cavity is in the shape of a T.

[0006] In some embodiments, the extended back cavity is in the shape of a Chinese character 'tu'.

[0007] In some embodiments, the maximum width of the extended back cavity is less than the profile width of the MEMS capacitive chip.

[0008] In some embodiments, before step (1), the encapsulation process further includes: forming an extended back cavity.

[0009] In some embodiments, the opening position of the extended back cavity corresponds to the shape of the self - contained cavity of the MEMS capacitive chip, and the shape is circular, triangular, or polygonal.

[0010] In some embodiments, after step (6), the encapsulation process further includes the following steps: (7) Marking on the outer shell; (8) Cutting and sorting the finished PCB into single chips; (9) Testing the single - chip products.

[0011] Compared with the prior art, the beneficial effects of the embodiments of the present application are as follows: A PCB extended back cavity encapsulation process provided by the embodiments of the present application conducts research and design at the PCB substrate end, changes the PCB structure, that is, by opening an extended cavity in the middle of the PCB, and designs by imitating an anechoic chamber to form an extended back cavity design and encapsulation layout, increasing the back cavity space of the MEMS capacitive chip, facilitating performance improvement, and improving the SNR signal - to - noise ratio; the encapsulation reduces the harsh requirements for the height of the chip glue, reduces the product operation cost, simplifies the encapsulation process flow, and optimizes the product performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings required for use in the embodiments or the description of the prior art. Obviously, the following described drawings are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0013] Figure 1 Schematic diagram of the product structure encapsulated by the process of the present invention.

[0014] Figure 2 Schematic cross - sectional view of the product encapsulated by the process of the present invention.

[0015] Figure 3 Schematic enlarged view of the PCB of the present invention.

[0016] Illustration: 1. PCB substrate; 2. ASIC integrated chip; 3. MEMS capacitive chip; 4. Housing; 5. Surface mount adhesive; 51. Adhesive connection point; 6. Gold wire; 7. COB adhesive; 8. Extended back cavity; 9. Built-in cavity. Detailed Implementation

[0017] To make the technical problems, technical solutions, and beneficial effects to be solved by this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and are not intended to limit the scope of this application.

[0018] It should be noted that when a component is referred to as being "fixed to" or "set on" another component, it can be directly on or indirectly on that other component. When a component is referred to as being "connected to" another component, it can be directly connected to or indirectly connected to that other component.

[0019] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0020] To illustrate the technical solution described in this application, specific embodiments are provided below.

[0021] Please see Figures 1 to 3 As shown, this application embodiment provides a PCB extended cavity packaging process, including the following steps: (1) Apply adhesive (e.g., patch adhesive 5) to the PCB substrate 1, mount the ASIC integrated chip 2, and bake to cure.

[0022] (2) Apply adhesive (e.g., patch fixing adhesive 5, adhesive connection position 51) to the PCB substrate 1, mount the MEMS capacitive chip 3, bake and cure. An extended back cavity 8 is provided on the PCB substrate 1, and the extended back cavity 8 corresponds to the built-in cavity 9 of the MEMS capacitive chip 3.

[0023] (3) Bridge the MEMS capacitive chip 3 and the ASIC chip 2 with gold wire 6, and bridge the ASIC chip 2 with the PCB solder joints using gold wire 6. Use solder paste or conductive silver paste for the solder joints.

[0024] (4) Apply adhesive (e.g., COB adhesive 7) to the surface of ASIC chip 2 to protect the chip.

[0025] (5) Apply solder paste to the tin frame area around the product; (6) After applying the solder paste, perform SMT to attach the outer shell 4 (e.g., CAP outer shell) and then carry out reflow soldering for curing.

[0026] In some embodiments, the extended back cavity 8 is in a T shape.

[0027] In some embodiments, the extended back cavity 8 is in a cross shape.

[0028] In some embodiments, the maximum width of the extended back cavity 8 is less than the profile width of the MEMS capacitive chip 3.

[0029] In some embodiments, before step (1), the packaging process further includes: forming the extended back cavity 8.

[0030] In some embodiments, the opening position of the extended back cavity 8 corresponds to the shape of the self - contained cavity 9 of the MEMS capacitive chip 3, and the shape is circular, triangular, or polygonal.

[0031] In some embodiments, after step (6), the packaging process further includes the following steps: (7) Mark on the outer shell 4; (8) Cut and sort the finished PCB into single pieces; (9) Test the single - piece products.

[0032] In summary, a PCB extended back - cavity packaging process provided by the embodiments of the present application is developed and designed at the PCB substrate end, changing the PCB structure. That is, by opening an extended cavity 8 in the middle of the PCB, it is designed by imitating an anechoic chamber to form an extended back - cavity design packaging layout, increasing the back - cavity space of the MEMS capacitive chip 3 and improving the SNR signal - to - noise ratio; the packaging reduces the harsh requirements for the height of the chip glue, reduces the product operation cost, simplifies the packaging process flow, and optimizes the product performance.

[0033] The above - described embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements for some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application, and should all be included within the protection scope of the present application.

Claims

1. A PCB extended cavity package process, characterized in that, It includes the following steps: (1) Dispense glue on the PCB substrate, mount the ASIC integrated chip, and bake and cure it; (2) Coat glue on the PCB substrate, mount the MEMS capacitive chip, bake and cure it. An extended back cavity is provided on the PCB substrate, and the extended back cavity corresponds to the self - contained cavity of the MEMS capacitive chip; (3) Bridge the MEMS capacitive chip and the ASIC chip with gold wires, and bridge the ASIC chip and the PCB solder joints with gold wires; (4) Dispense glue on the surface of the ASIC chip to protect the chip; (5) Coat solder paste in the tin frame area around the product; (6) After coating the solder paste, perform SMT to mount the shell and carry out reflow soldering for curing.

2. The PCB extended cavity package process of claim 1, wherein, The extended back cavity is in a T - shape.

3. The PCB extended cavity package process of claim 1, wherein, The extended back cavity is in a Chinese character "tu" shape.

4. The PCB extended cavity package process according to any one of claims 1 to 3, wherein, The maximum width of the extended back cavity is less than the outline width of the MEMS capacitive chip.

5. The PCB extended cavity package process according to any one of claims 1 to 4, wherein, Before step (1), the encapsulation process further includes: forming the extended back cavity.

6. The PCB extended cavity package process according to any one of claims 1 to 3, wherein, The opening position of the extended back cavity corresponds to the shape of the self - contained cavity of the MEMS capacitive chip, and the shape is circular, triangular, or polygonal.

7. The PCB extended cavity package process according to any one of claims 1 to 3, wherein, After step (6), the encapsulation process further includes: (7) Mark on the shell; (8) Cut and sort the PCB finished product into single pieces; (9) Test the single products.

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