Capacitance detection circuit, system and method

Abstract

The invention is suitable for the technical field of electronic circuits, and provides a capacitance detection circuit, system and method, and the circuit comprises a control module, an excitation module, a probe switching module, a probe, a CV conversion module, and a peak detection module. The probe switching module is connected with the excitation module, the probe and the capacitance detection module, and the peak detection module is connected with the CV conversion module and the control module. According to the detection circuit provided by the invention, the to-be-detected capacitor can be connected to the excitation module and the CV conversion module in sequence under the control of the control module, a capacitance value change signal of the to-be-detected capacitor can be converted into a voltage amplitude signal based on the CV conversion module, and the peak detection module performs peak detection on the voltage amplitude signal and outputs a voltage peak envelope. And then the control module calculates the capacitance value of the to-be-detected capacitor based on the peak envelope, thereby realizing automatic and accurate detection of the capacitance value of the to-be-detected capacitor, and improving the efficiency and reliability of capacitance detection.

Description

Technical Field

[0001] This application belongs to the field of electronic circuit technology, and in particular relates to a capacitance detection circuit, system and method. Background Technology

[0002] With the rapid development of semiconductor manufacturing processes and electronic technologies, especially the widespread application of domestically produced components, incoming material inspectors for electronic components need to test whether the parasitic capacitance or capacitance accuracy of the components meets the requirements in order to identify material defects in advance and avoid them affecting the performance of the circuit board. Traditional material capacitance testing mainly relies on manual measurement with an LCR meter, which is inefficient, expensive, and cannot meet the needs of automated testing systems.

[0003] Therefore, there is an urgent need for a capacitance detection circuit to achieve automated, accurate and efficient capacitance detection. Summary of the Invention

[0004] In view of this, embodiments of this application provide a capacitance detection circuit, system, and method to achieve automated and accurate detection of the capacitance value of the capacitor under test, thereby improving the efficiency and reliability of capacitance detection.

[0005] The first aspect of this application provides a capacitance detection circuit, including a control module, an excitation module, a probe switching module, a probe, a CV conversion module, and a peak detection module; The control module is connected to the excitation module and the probe switching module respectively. The probe switching module is connected to the probe, the excitation module and the CV conversion module respectively. The probe is used to connect to the capacitor under test. The excitation module is used to generate an excitation signal, and the probe switching module is used to switch the probe and the excitation module to be connected, so that the excitation signal is transmitted to the capacitor under test connected to the probe through the probe switching module. The probe switching module is also used to switch the probe and the CV conversion module to be connected. The CV conversion module is used to output a voltage amplitude signal based on the capacitance change signal of the capacitor under test. The peak detection module is connected to the CV conversion module and the control module respectively. The peak detection module is used to perform peak detection on the voltage amplitude signal output by the CV conversion module and output the voltage peak envelope to the control module. The control module is also used to calculate the capacitance value of the capacitor under test based on the peak envelope.

[0006] In one embodiment, the probe switching module includes a first analog switch, the input terminal of the first analog switch is connected to the control module, the data terminal of the first analog switch is connected to the probe, the first switching terminal of the first analog switch is connected to the excitation module, the second switching terminal of the first analog switch is connected to the CV conversion module, the VDD terminal of the first analog switch is connected to the first positive power supply circuit, the VSS terminal of the first analog switch is connected to the first negative power supply circuit, and the ground terminal of the first analog switch is virtual ground.

[0007] In one embodiment, the CV conversion module includes a first operational amplifier unit, a feedback resistor, and a diode protection unit. The probe switching module is connected to the first terminal of the feedback resistor and the diode protection unit. The diode protection unit is connected to the input terminal of the first operational amplifier unit. The output terminal of the first operational amplifier unit is connected to the second terminal of the feedback resistor and the peak detection module, respectively.

[0008] In one embodiment, the capacitance detection circuit further includes a range configuration module, the feedback resistor is connected in parallel with the range configuration module, the range configuration module is also connected to the control module, and the range configuration module includes at least one reference capacitor.

[0009] In one embodiment, the range configuration module includes a second analog switch, which includes at least one single-pole single-throw switch. The number of single-pole single-throw switches is the same as the number of reference capacitors. Each single-pole single-throw switch is connected to one of the reference capacitors, and each reference capacitor is connected to one single-pole single-throw switch. The single-pole single-throw switches are controlled by the control module.

[0010] In one embodiment, the peak detection module includes a second operational amplifier unit, a third operational amplifier unit, a detector diode, and a peak hold capacitor. The non-inverting input of the second operational amplifier unit is connected to the output of the CV conversion module. The output of the second operational amplifier unit is connected to the anode of the detector diode. The cathode of the detector diode is connected to the first terminal of the peak hold capacitor and the non-inverting input of the third operational amplifier unit. The second terminal of the peak hold capacitor is grounded. The output of the third operational amplifier unit is connected to the inverting input of the third operational amplifier unit, the inverting input of the second operational amplifier unit, and the analog-to-digital conversion unit of the control module.

[0011] In one embodiment, the peak detection module further includes a limiting diode and a limiting resistor. The anode of the limiting diode is connected to the inverting input terminal of the second operational amplifier unit, and the cathode of the limiting diode is connected between the output terminal of the second operational amplifier unit and the anode of the detection diode. The first terminal of the limiting resistor is connected to the inverting input terminal of the second operational amplifier unit, and the second terminal of the limiting resistor is connected to the output terminal of the third operational amplifier unit.

[0012] In one embodiment, the excitation module includes an excitation generation unit and a two-stage operational amplifier unit. The input terminal of the two-stage operational amplifier unit is connected to the output terminal of the excitation generation unit, and the output terminal of the two-stage operational amplifier unit is connected to the probe switching module.

[0013] A second aspect of this application provides a capacitance detection system, including a capacitance detection circuit as described in the first aspect, a detection host computer, and a motion control system. The detection host computer is connected to the motion control system, and the detection host computer and the motion control system are respectively connected to the control module of the capacitance detection circuit. The detection host computer is used to send measurement commands to the control module of the capacitance detection circuit, and the motion control system is used to control the movement of the probe.

[0014] A third aspect of this application provides a capacitance detection method, implemented based on the capacitance detection circuit as described in any one of claims 1 to 8, the method comprising: The control module controls the probe switching module to switch the probe and the excitation module to conduct and controls the excitation module to charge the capacitor under test connected to the probe. The control module controls the probe switching module to switch the probe and the CV conversion module to be connected. The CV conversion module is used to output a voltage amplitude signal based on the capacitance change signal of the capacitor under test. The control module receives the voltage peak envelope output by the peak detection module and calculates the capacitance value of the capacitor under test based on the voltage peak. The peak detection module is used to perform peak detection on the voltage amplitude signal and output the voltage peak envelope.

[0015] The beneficial effect of the first aspect of the embodiments of this application is that: through the capacitance detection circuit including a control module, an excitation module, a probe switching module, a probe, a CV conversion module, and a peak detection module, the control module controls the operation of the probe switching module, so that the capacitor under test can be connected to the excitation module and the CV conversion module in sequence. Based on the CV conversion module, the capacitance value change signal of the capacitor under test can be converted into a voltage amplitude signal. The peak detection module performs peak detection on the voltage amplitude signal and outputs the voltage peak envelope. Then, the control module calculates the capacitance value of the capacitor under test based on the peak envelope, thereby realizing the automated and accurate detection of the capacitance value of the capacitor under test and improving the efficiency and reliability of capacitance detection.

[0016] It is understood that the beneficial effects of the second and third aspects mentioned above can be found in the relevant descriptions in the first aspect above, and will not be repeated here. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a system schematic diagram of the capacitance detection circuit provided in the embodiments of this application; Figure 2 This is a schematic diagram of the probe switching module of the capacitance detection circuit provided in the embodiments of this application; Figure 3 This is a schematic diagram of the CV conversion module of the capacitance detection circuit provided in the embodiment of this application; Figure 4 This is a schematic diagram of the range switching module of the capacitance detection circuit provided in the embodiments of this application; Figure 5 This is a schematic diagram of the probe switching module, CV conversion module, and range switching module of the capacitance detection circuit provided in the embodiments of this application; Figure 6 This is a schematic diagram of the peak detection module of the capacitance detection circuit provided in the embodiments of this application; Figure 7 This is a schematic diagram of a two-stage operational amplifier unit of the capacitance detection circuit provided in an embodiment of this application; Figure 8 This is a schematic diagram of the excitation module of the capacitance detection circuit provided in the embodiments of this application; Figure 9 This is a schematic diagram of the capacitance detection system provided in an embodiment of this application; Figure 10This is a schematic diagram illustrating the implementation process of the capacitance detection method provided in the embodiments of this application; Figure 11 This is a schematic diagram of the terminal device provided in the embodiments of this application; Figure 12 This is a schematic diagram of a computer program product provided in an embodiment of this application. Detailed Implementation

[0019] In the following description, specific details such as particular system architectures and techniques are set forth for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of this application. However, those skilled in the art will understand that this application may also be implemented in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, apparatuses, circuits, and methods have been omitted so as not to obscure the description of this application with unnecessary detail.

[0020] It should be understood that, when used in this application specification and the appended claims, the term "comprising" indicates the presence of the described features, integrals, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or a collection thereof.

[0021] It should also be understood that the term “and / or” as used in this application specification and the appended claims means any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0022] As used in this application specification and the appended claims, the term "if" may be interpreted, depending on the context, as "when," "once," "in response to determination," or "in response to detection." Similarly, the phrase "if determined" or "if detected [the described condition or event]" may be interpreted, depending on the context, as meaning "once determined," "in response to determination," "once detected [the described condition or event]," or "in response to detection [the described condition or event]."

[0023] Furthermore, in the description of this application and the appended claims, the terms "first," "second," "third," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0024] References to "one embodiment" or "some embodiments" as described in this specification mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized.

[0025] This application provides a capacitance detection circuit, including a control module, an excitation module, a probe switching module, probes, a CV conversion module, and a peak detection module, for achieving efficient and accurate measurement of the capacitor under test. The capacitance detection circuit provided in this application utilizes the control module to control the operation of the probe switching module, allowing the capacitor under test to be connected to the excitation module and the CV conversion module sequentially. The CV conversion module converts the capacitance change signal of the capacitor under test into a voltage amplitude signal. The peak detection module performs peak detection on the voltage amplitude signal and outputs a voltage peak envelope. Then, the control module calculates the capacitance value of the capacitor under test based on the peak envelope, achieving automated and accurate detection of the capacitance value of the capacitor under test, thus improving the efficiency and reliability of capacitance detection.

[0026] like Figure 1 As shown in the figure, an embodiment of this application provides a capacitance detection circuit, including a control module, an excitation module, a probe switching module, a probe, a CV conversion module, and a peak detection module.

[0027] In this application, the CV conversion module is a capacitor-voltage conversion module, specifically a bridge capacitor detection circuit based on an operational amplifier, which has the advantages of fast dynamic response, high resolution, and strong anti-interference capability.

[0028] The control module is connected to the excitation module and the probe switching module respectively. The probe switching module is connected to the probe, the excitation module and the CV conversion module respectively. The probe is used to connect to the capacitor under test. The excitation module is used to generate an excitation signal, and the probe switching module is used to switch the probe and the excitation module to be connected, so that the excitation signal is transmitted to the capacitor under test connected to the probe through the probe switching module. The probe switching module is also used to switch the probe and the CV conversion module to be connected. The CV conversion module is used to output a voltage amplitude signal based on the capacitance change signal of the capacitor under test. The peak detection module is connected to the CV conversion module and the control module respectively. The peak detection module is used to perform peak detection on the voltage amplitude signal output by the CV conversion module and output the voltage peak envelope to the control module. The control module is also used to calculate the capacitance value of the capacitor under test based on the peak envelope.

[0029] In applications, the capacitor to be tested is a tiny capacitor in a PCB or PCBA board. The capacitance detection circuit provided in this application can be designed as a capacitance tooling detection board, which is easy to embed into a tooling fixture system.

[0030] In one embodiment, the probe switching module includes a first analog switch, the input terminal of the first analog switch is connected to the control module, the data terminal of the first analog switch is connected to the probe, the first switching terminal of the first analog switch is connected to the excitation module, the second switching terminal of the first analog switch is connected to the CV conversion module, the VDD terminal of the first analog switch is connected to the first positive power supply circuit, the VSS terminal of the first analog switch is connected to the first negative power supply circuit, and the ground terminal of the first analog switch is virtual ground.

[0031] In applications, such as Figure 2 As shown, the probe switching module includes a first analog switch U1. The input terminal IN of the first analog switch U1 is connected to the control module and can receive probe switching signals from the control module. The data terminal D of the first analog switch U1 is connected to probe J1. The first switching terminal SA of the first analog switch U1 is connected to the excitation module. The second switching terminal SB of the first analog switch U1 is connected to the CV conversion module. The VDD terminal of the first analog switch U1 is connected to the first positive power supply circuit, which includes a +10V first positive power supply and a first capacitor C1. The VDD terminal of the first analog switch U1 is connected to the first positive power supply, and the first positive power supply is virtually grounded through capacitor C1, which has the function of decoupling and filtering. The VSS terminal of the first analog switch U1 is connected to the first negative power supply circuit, which includes a -10V first negative power supply. The VSS terminal of the first analog switch U1 is connected to the first negative power supply, and the first negative power supply is virtually grounded through capacitor C2, which has the function of decoupling and filtering. The ground terminal GND of the first analog switch is virtually grounded.

[0032] In applications, for example, the operational amplifier can be an SGM8261, and the analog switch U1 can be a single-pole double-throw analog switch. Special attention should be paid to ensuring dual power supply, and the on-resistance and parasitic capacitance should be as small as possible, such as DG186, with capacitors C1 and C2 being 100nF.

[0033] In one embodiment, the CV conversion module includes a first operational amplifier unit, a feedback resistor, and a diode protection unit. The probe switching module is connected to the first terminal of the feedback resistor and the diode protection unit. The diode protection unit is connected to the input terminal of the first operational amplifier unit. The output terminal of the first operational amplifier unit is connected to the second terminal of the feedback resistor and the peak detection module, respectively.

[0034] In applications, such as Figure 3 As shown, the CV conversion module includes a first operational amplifier unit, a feedback resistor R, and a diode protection unit. The probe switching module is connected to the first end of the feedback resistor R and the diode protection unit. The diode protection unit is connected to the input end of the first operational amplifier unit. The output end of the first operational amplifier unit is connected to the second end of the feedback resistor and the peak detection module, respectively.

[0035] Specifically, the first operational amplifier unit includes operational amplifier U2A, a second positive power supply circuit, and a second negative power supply circuit. The second positive power supply circuit includes a +10V second positive power supply, capacitors C3 and C4. The positive power supply terminal of operational amplifier U2A is connected to the second positive power supply, which is virtually grounded through capacitors C3 and C4. Capacitors C3 and C4 are used for decoupling and filtering. The second negative power supply circuit includes a -10V second negative power supply, capacitors C5 and C6. The negative power supply terminal of operational amplifier U2A is connected to the second negative power supply, which is virtually grounded through capacitors C5 and C6. Capacitors C3 and C4 are used for decoupling and filtering. The diode protection unit includes diodes D1 and D2. The inverting input terminal of operational amplifier U2A is connected to the negative terminal of diode D1 and the positive terminal of diode D2. The non-inverting input terminal of operational amplifier U2A is connected to the positive terminal of diode D1 and the negative terminal of diode D2. The negative terminal of diode D2 is virtually grounded. The diode protection unit is used to protect the input terminal of the operational amplifier U2A. At the same time, the inverting input terminal of the operational amplifier U2A is grounded, so that stray capacitance at the operational amplifier terminal will not affect the capacitance detection.

[0036] In the application, the output of the operational amplifier U2A is connected to the peak detection module through jumper JP1, and the second end of the feedback resistor R and the output of the operational amplifier U2A are also virtually grounded through capacitor C7.

[0037] Specifically, capacitors C3 and C5 are 100nF, capacitors C4 and C6 are 10μF, the feedback resistor R is 1MΩ, and capacitor C7 is NA. These are reserved positions that can be configured according to requirements.

[0038] In one embodiment, the capacitance detection circuit further includes a range configuration module, the feedback resistor is connected in parallel with the range configuration module, the range configuration module is also connected to the control module, and the range configuration module includes at least one reference capacitor.

[0039] In the application, the capacitance detection circuit also includes a range configuration module. The feedback resistor R is connected in parallel with the range configuration module. The range configuration module is also connected to the control module. The range configuration module includes at least one reference capacitor.

[0040] In one embodiment, the range configuration module includes a second analog switch, which includes at least one single-pole single-throw switch. The number of single-pole single-throw switches is the same as the number of reference capacitors. Each single-pole single-throw switch is connected to one of the reference capacitors, and each reference capacitor is connected to one single-pole single-throw switch. The single-pole single-throw switches are controlled by the control module.

[0041] Specifically, such as Figure 4 As shown, the range configuration module includes a second analog switch U3, and reference capacitors C8, C9, C10, and C11. The second analog switch U3 includes four single-pole single-throw switches with four control ports IN1, IN2, IN3, and IN4. The control module uses these four control ports to control the switching ports S1, S2, S3, and S4 of the single-pole single-throw switches to be connected to data ports D1, D2, D3, and D4 respectively, thus making the corresponding reference capacitors C8, C9, C10, and C11 connected in parallel with the feedback resistor R. The VDD terminal of the second analog switch U3 is connected to a +10V third positive power supply, which is virtually grounded through capacitor C12. The VSS terminal of the second analog switch U3 is connected to a -10V third negative power supply, which is virtually grounded through capacitor C13. C12 and C13 serve as power supply decoupling or filtering.

[0042] Specifically, capacitor C8 is 10pF±0.25pF, capacitor C9 is 100pF±1%, capacitor C10 is 1nF±1%, capacitor C11 is 10nF±1%, and capacitors C12 and C13 are both 100nF. In applications, capacitors C8-C10 can be high-precision C0G material surface-mount ceramic capacitors.

[0043] In applications, this is typically used when measuring small, unknown capacitances. ( << When using a smaller reference capacitor, Higher sensitivity can be achieved. A smaller reference capacitance Cref results in a larger capacitive reactance. Therefore, reducing the reference capacitance can decrease the measurement error caused by the on-state resistance of the switching analog switch contacts. However, a higher capacitive reactance makes the measurement circuit more susceptible to parasitic parameters and external electromagnetic noise, potentially decreasing the overall signal-to-noise ratio of the measurement circuit. Therefore, selecting a suitable reference capacitance through testing is crucial. It is the key to balancing sensitivity and signal-to-noise ratio.

[0044] like Figure 5 The diagram shown is a schematic of a probe, probe switching module, control module, CV conversion module, and range switching module in a capacitance detection circuit provided in an embodiment of this application.

[0045] In application, the four switch control ports of the second analog switch U3 are respectively connected to the corresponding control ports S1, S2, S3, and S4 of the control module's range 0-range 3 (RANGE 0-RANGE3), and respectively connected to the data ports D1, D2, D3, and D4, realizing the closure of the single-pole single-throw switch. This allows different reference capacitors to be connected in parallel across the feedback resistor R, thereby controlling the measurement range. The excitation module signal output is connected to the probe switching module through operational amplifier U3B. Specifically, the output of the excitation module is connected to the non-inverting input of operational amplifier U3B, and the output of operational amplifier U3B is connected to its inverting input. This connection is then made possible by a 0Ω jumper JP2 and connected to the first switching terminal SA of the probe switching module.

[0046] In one embodiment, the peak detection module includes a second operational amplifier unit, a third operational amplifier unit, a detector diode, and a peak hold capacitor. The non-inverting input of the second operational amplifier unit is connected to the output of the CV conversion module. The output of the second operational amplifier unit is connected to the anode of the detector diode. The cathode of the detector diode is connected to the first terminal of the peak hold capacitor and the non-inverting input of the third operational amplifier unit. The second terminal of the peak hold capacitor is grounded. The output of the third operational amplifier unit is connected to the inverting input of the third operational amplifier unit, the inverting input of the second operational amplifier unit, and the analog-to-digital conversion unit of the control module.

[0047] Specifically, such as Figure 6As shown, the second operational amplifier unit includes operational amplifier U5A, a fourth positive power supply circuit, and a fourth negative power supply circuit. The fourth positive power supply circuit includes a fourth positive power supply, capacitor C14, and capacitor C15. The fourth positive power supply is connected to the positive power supply terminal of operational amplifier U5A and virtually grounded through parallel capacitors C14 and C15. The fourth negative power supply circuit includes a fourth negative power supply, capacitors C16 and C17. The fourth negative power supply is connected to the negative power supply terminal of operational amplifier U5A and virtually grounded through parallel capacitors C16 and C17. Capacitors C14, C15, C16, and C17 have power supply decoupling or filtering functions. The third operational amplifier unit includes operational amplifier U5B. The non-inverting input of operational amplifier U5A is connected to the output of the CV conversion module. The output of operational amplifier U5A is connected to the positive terminal of detector diode D3. The negative terminal of detector diode D3 is connected to the first terminal of peak holding capacitor C18 and the non-inverting input of operational amplifier U5B. The second terminal of peak holding capacitor C18 is grounded. The output of operational amplifier U5B is connected to the inverting input of operational amplifier U5B, the inverting input of operational amplifier U5A, and the analog-to-digital conversion unit of the control module.

[0048] In one embodiment, the peak detection module further includes a limiting diode and a limiting resistor. The anode of the limiting diode is connected to the inverting input terminal of the second operational amplifier unit, and the cathode of the limiting diode is connected between the output terminal of the second operational amplifier unit and the anode of the detection diode. The first terminal of the limiting resistor is connected to the inverting input terminal of the second operational amplifier unit, and the second terminal of the limiting resistor is connected to the output terminal of the third operational amplifier unit.

[0049] like Figure 6 As shown, the peak detection module also includes a limiting diode D4 and a limiting resistor R2. The positive terminal of the limiting diode D4 is connected to the inverting input terminal of the operational amplifier U5A, and the negative terminal of the limiting diode D4 is connected between the output terminal of the operational amplifier U5A and the positive terminal of the detection diode D3. The first terminal of the limiting resistor R2 is connected to the inverting input terminal of the operational amplifier U5A, and the second terminal of the limiting resistor R2 is connected to the output terminal of the operational amplifier U5B.

[0050] In the application, specifically, the fourth positive power supply is +10V, the fourth negative power supply is -10V, capacitors C14 and C16 are 100nF, capacitors C15 and C17 are 10μF, the peak holding capacitor C18 is 470pF, the limiting resistor R2 is 10kΩ, the resistor R6 is 0Ω, and the resistor R6A is connected to the non-inverting input terminal of the operational amplifier U5A and the 10kΩ resistor R4.

[0051] In the application, when the voltage amplitude signal output by the CV conversion module starts to rise from zero, the voltage at the non-inverting input (+) of op-amp U5A also rises. As a high-gain differential amplifier, op-amp U5A immediately generates a very high voltage at its output, attempting to make the voltage at the inverting input (-) follow the voltage at the non-inverting input (+). At this time, diodes D3 and D4 are in a non-biased state and conduct. The conducting diode D4 can be regarded as a very small resistor, and the output current of the op-amp charges the peak holding capacitor C18 through the diode.

[0052] When the voltage amplitude signal output by the CV conversion module begins to decrease from its peak, the voltage at the non-inverting input (+) of op-amp U5A becomes lower than the voltage at the inverting input (-) because the peak holding capacitor C19 still maintains its peak voltage. The output voltage of op-amp U5A drops rapidly, attempting to pull down the voltage at the inverting input to match the non-inverting input. This causes diode D3 to be inverted and thus cut off. Once diode D3 is cut off, it cuts off the discharge path of peak holding capacitor C19 through the op-amp output. At this time, peak holding capacitor C19 cannot discharge through diode D3 or the input of op-amp U5A (because the input impedance of the op-amp is extremely high). Therefore, the charge on the peak holding capacitor is retained, and its voltage remains at the peak voltage of the voltage amplitude signal output by the CV conversion module.

[0053] When the U5A output attempts to exceed a threshold in a certain direction, D4 and R2 prevent the op-amp from entering a deep saturation region for an extended period when driving the diode or capacitor, thus improving recovery speed and diode conduction control.

[0054] like Figure 6 As shown, the output terminal of operational amplifier U5B is further connected to the control module through a 2kΩ resistor R6A, and the output terminal of operational amplifier U5A is connected to the positive terminal of detector diode D3 through a 0Ω resistor R6.

[0055] In one embodiment, the excitation module includes an excitation generation unit and a two-stage operational amplifier unit. The input terminal of the two-stage operational amplifier unit is connected to the output terminal of the excitation generation unit, and the output terminal of the two-stage operational amplifier unit is connected to the probe switching module.

[0056] Specifically, such as Figure 7As shown, the excitation generation unit includes a DDS chip U11 and a two-stage operational amplifier unit U12. U12 includes a first-stage operational amplifier U12A and a second-stage operational amplifier U12B. The inverting input of the first-stage operational amplifier U12A is connected to the output of the DDS chip U11, and the output of U12A is connected to the inverting input of U12A, forming an inverting amplification circuit. The non-inverting input of U12A is connected to a first-stage reference bias network to stabilize the DC reference of the non-inverting input to near 0V, so as to ensure that the first-stage operational amplifier U12A operates with 0V as the reference.

[0057] The inverting input of the second-stage operational amplifier U12B is connected to the output of the first-stage operational amplifier U12A. The output of U12B is connected to the inverting input of U12B, forming an inverting amplification circuit. The non-inverting input of U12B is virtually grounded to provide a 0V non-inverting reference for the second-stage operational amplifier U12B. The output of U12B is connected to the probe switching module, which adjusts the signal of the excitation unit to a standard sine wave signal and sends it to the capacitor under test through the probe switching module.

[0058] Specifically, the output of DDS chip U11 is input to the inverting input (-IN1) of U12A through a 2kΩ resistor R'3. The output (OUT1) of U12A is connected to the inverting input (-IN1) of U12A through a 4.12kΩ first-stage feedback resistor R'1, forming an inverting amplification circuit. The output (OUT1) of U12A is also connected to the inverting input (-IN2) of the second-stage operational amplifier through a 249Ω resistor R'4. The non-inverting input (+IN1) of U12A is connected to a first-stage reference bias network, which includes a 27kΩ resistor R'5, a +5V DDS power supply, a capacitor C'9, and a resistor R'7. This network is used to stabilize the DC reference of the non-inverting input to near 0V, ensuring that the first-stage operational amplifier U12A operates with 0V as the reference.

[0059] Specifically, the inverting input (-IN2) of the second-stage operational amplifier U12B is connected to the output (OUT1) of the first-stage operational amplifier U12A through a 249Ω resistor R'4. The output (OUT2) of U12B and the inverting input (-IN2) of U12B are connected through a 1.8kΩ secondary feedback resistor R'10 to form an inverting amplification circuit. The non-inverting input (+IN2) of U12B is virtually grounded through a 1kΩ resistor R'8 to provide a 0V non-inverting reference for the second-stage operational amplifier U12B. The output (OUT2) of U12B is connected to the probe switching module through a 300Ω resistor R'6 to adjust the signal of the excitation unit to a standard sine wave signal, which is then sent to the capacitor under test through the probe switching module.

[0060] Specifically, the amplitude gain of U12 is the first-level gain multiplied by the second-level gain, i.e., R'1 / R'3*R'10 / R'4=4.12 / 2*1.8 / 0.249=14.9.

[0061] In the application, the DDS chip U11 can be a programmable waveform generator AD9837. This chip generates sine, triangle, and square wave outputs through a programmable configuration register. When the external clock U14 is 16MHz, it can achieve an output frequency resolution of 0.06Hz. To achieve optimal frequency stability of the DDS and obtain a clock signal with extremely low phase noise and extremely high frequency stability, a REF196 (U13) can be used to power the 16MHz active crystal oscillator.

[0062] In one embodiment, this application requires an excitation signal centered at zero with a Vp of 4V. Based on the output characteristics of U11, the typical output range of this chip is 37-645mV. Therefore, a two-stage operational amplifier (U12) is needed to implement DDS waveform signal conditioning. The main function of the first-stage operational amplifier is to perform inverting proportional amplification and waveform shifting to the reference zero position. The second-stage operational amplifier further performs inverting proportional amplification to obtain a standard 4V sinusoidal excitation signal with a Vp of 4V.

[0063] like Figure 8 As shown, the two-stage operational amplifier unit includes a dual operational amplifier chip U12. The two-stage operational amplifier unit based on the dual operational amplifier chip U12 is used to adjust the signal output by the excitation generation unit to a standard signal.

[0064] In applications, the excitation generation unit can be programmed via an SPI interface to generate sine, triangle, and square wave signal sources. The output frequency and phase can be changed via frequency and phase registers. The frequency register has a 28-bit resolution, and the DAC output has a 10-bit resolution, achieving a frequency resolution of 0.06Hz. The output clock of the excitation generation unit is used as the output clock of an active crystal oscillator capable of generating a 16MHz frequency. The accuracy of the excitation generation unit's output frequency is determined by this crystal oscillator. For example,... Figure 7 As shown, the excitation unit can use the Analog Devices (ADI) programmable DDS chip AD9837, and the active crystal oscillator can be the EPSON MA-406 series crystal oscillator, which has a frequency stability of 30ppm. The control module, through configuration, outputs a 100kHz sine wave signal as required by the system via programming. Since the excitation unit signal is powered by a single power supply, the swing is 610mV according to the datasheet. An operational amplifier is needed for signal conditioning before it can be used as the excitation signal. Based on the characteristics of an ideal operational amplifier, the transfer function of U12 is approximately:

[0065] The two-stage operational amplifier unit built using U12 conditions the signal from the excitation generation unit to a sinusoidal signal with Vpp of 8V and zero point at 0V. If there is a deviation in the actual output, the resistance parameters of the two-stage amplifier circuit can be finely adjusted. The excitation generation unit outputs a sinusoidal signal with Vp of 4V as the standard excitation source for capacitance detection.

[0066] In applications, stray capacitance exists between the terminals of the capacitor under test and ground. The inverting input of the operational amplifier is essentially a "virtual ground," so the stray capacitance at the operational amplifier end does not affect capacitance detection. Similarly, the stray capacitance at the excitation signal end is connected in parallel with the DDS excitation signal and also does not affect detection. Ignoring stray parasitic capacitance in the circuit, according to the Laplace transform, the transfer function of the capacitance detection circuit provided in this application is:

[0067] Among them, the feedback impedance Input impedance ; ; when At that time, that is At this time there is

[0068] ; in, Here is the capacitance value of the capacitor under test. R is the capacitance of the reference capacitor and the resistance of the feedback resistor. Let be the excitation frequency, and s be the Laplace variable. s= It characterizes frequency domain properties.

[0069] According to the constraints of the above formula In this circuit, a larger feedback resistor R needs to be selected, or the input DDS signal frequency needs to be appropriately increased. It should be noted that an excessively high DDS frequency will produce a large line parasitic effect, which will adversely affect the measurement. Through experiments, a signal frequency of 10kHz or 100kHz was selected as the excitation signal. The main advantage of this circuit is that it has a strong ability to suppress parasitic capacitance and high capacitance detection accuracy. Finally, we found that the ratio of the measured capacitance to the reference capacitance is equal to the ratio of the magnitude of the output signal amplitude to the magnitude of the input signal amplitude.

[0070] This application also provides a capacitance testing system, which includes the capacitance testing circuit, the host computer, and the motion control system described in the above embodiments, to achieve automated testing of the capacitor under test and realize efficient and accurate capacitance testing.

[0071] like Figure 9As shown in the figure, this application embodiment also provides a capacitance detection system 90, including the capacitance detection circuit as described above, a detection host computer and a motion control system. The detection host computer is connected to the motion control system, and the detection host computer and the motion control system are respectively connected to the control module of the capacitance detection circuit. The detection host computer is used to send measurement commands to the control module of the capacitance detection circuit, and the motion control system is used to control the movement of the probe.

[0072] In the application, after the capacitance detection system is powered on, the control module and motion control system are initialized. After the control module is initialized, it sends a ready signal to the host computer. The host computer reads the coordinate file of the capacitor under test and controls the motion control system to move the probe to the target coordinates. After reaching the target coordinates, it indicates that the probe has been connected to the capacitor under test. The host computer outputs a flag bit to the control module through IO. After receiving the flag bit, the control module starts to perform measurement configuration according to the measurement configuration file. The probe switching module connects the probe to the excitation signal module to charge the capacitor under test connected to the probe. Then, the probe switching module connects the probe to the detection circuit composed of a CV conversion module and a peak detection module. The CV conversion module is used to convert the capacitance change of the capacitor under test into a voltage amplitude signal. The peak detection module is used to perform peak detection on the voltage amplitude signal and output the voltage peak envelope. The control module receives the voltage peak envelope output by the peak detection module and calculates the capacitance value of the capacitor under test based on the peak envelope.

[0073] In the application, after the capacitance detection system is powered on, the control module sequentially initializes the GPIO, excitation module, and analog-to-digital conversion module. Specifically, the GPIO is initialized by configuring the GPIO working mode, switching the measurement range analog switch, and switching the probe analog switch. The excitation module is initialized by initializing the SPI communication interface, configuring SPI communication to a 16-bit frame format, writing to the corresponding registers according to the frequency and phase commands, selecting the output waveform as a sine wave, and outputting the excitation signal required for testing after initialization. The analog-to-digital conversion module is initialized by configuring the working mode of the analog-to-digital converter controller, configuring the range register, sequence register, and control register to prepare for precision voltage sampling.

[0074] In the application, the host computer sends measurement commands to the tooling test board. According to the user's needs, one of the measurement ranges is selected: 10pf, 100pf, 1nF, and 10nF. The range switching uses a 4-channel SPST analog switch. Only one switch is allowed to be turned on at a time. The switching is implemented by the microcontroller's I / O port.

[0075] like Figure 10 As shown, this application provides a capacitance detection method based on the above-described capacitance detection circuit. The method includes: Step S11: The control module controls the probe switching module to switch the probe and the excitation module to conduct and controls the excitation module to charge the capacitor under test connected to the probe.

[0076] Step S12: The control module controls the probe switching module to switch the probe and the CV conversion module to be connected. The CV conversion module is used to output a voltage amplitude signal based on the capacitance change signal of the capacitor under test.

[0077] Step S13: The control module receives the voltage peak envelope output by the peak detection module and calculates the capacitance value of the capacitor under test based on the voltage peak. The peak detection module is used to perform peak detection on the voltage amplitude signal and output the voltage peak envelope.

[0078] In the application, the control module converts the peak voltage envelope into a digital signal through the analog-to-digital converter module, and calculates the capacitance value of the capacitor under test based on the aforementioned transfer function.

[0079] Figure 11 This is a schematic diagram of the structure of a terminal device provided in an embodiment of this application. Figure 6 As shown, the terminal device 6 in this embodiment includes: a processor 60 ( Figure 6 (Only one is shown in the diagram) a processor, a memory 61, and a computer program 62 stored in the memory 61 and executable on the at least one processor 60, wherein the processor 60 executes the computer program 62 to implement the steps in the above-described capacitance detection method embodiments.

[0080] The terminal device may include, but is not limited to, a processor 60 and a memory 61. Those skilled in the art will understand that... Figure 6 This is merely an example of terminal device 6 and does not constitute a limitation on terminal device 6. It may include more or fewer components than shown in the figure, or combine certain components, or different components, such as input / output devices, network access devices, etc.

[0081] The processor 60 can be a Central Processing Unit (CPU), or it can be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor can be a microprocessor or any conventional processor.

[0082] In some embodiments, the memory 61 may be an internal storage unit of the terminal device 6, such as a hard disk or memory of the terminal device 6. In other embodiments, the memory 61 may be an external storage device of the terminal device 6, such as a plug-in hard disk, smart media card (SMC), secure digital (SD) card, flash card, etc., equipped on the terminal device 6. Furthermore, the memory 61 may include both internal and external storage units of the terminal device 6. The memory 61 is used to store the operating system, applications, bootloader, data, and other programs, such as the program code of the computer program. The memory 61 can also be used to temporarily store data that has been output or will be output.

[0083] It should be noted that the information interaction and execution process between the above-mentioned devices / units are based on the same concept as the method embodiments of this application. For details on their specific functions and technical effects, please refer to the method embodiments section, and they will not be repeated here.

[0084] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional units and modules is merely an example. In practical applications, the above functions can be assigned to different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiments can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit. Furthermore, the specific names of the functional units and modules are only for easy differentiation and are not intended to limit the scope of protection of this application. The specific working process of the units and modules in the above system can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0085] This application also provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the steps described in the various method embodiments above.

[0086] like Figure 12 As shown, this application embodiment provides a computer program product 120, including a computer program 62. When the computer program 62 is run, the steps in the above-described capacitance detection method embodiments are executed.

[0087] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, all or part of the processes in the methods of the above embodiments of this application can be implemented by a computer program instructing related hardware. The computer program can be stored in a computer-readable storage medium, and when executed by a processor, it can implement the steps of the various method embodiments described above. The computer program includes computer program code, which can be in the form of source code, object code, executable files, or certain intermediate forms. The computer-readable medium can include at least: any entity or device capable of carrying computer program code to a device / terminal equipment, a recording medium, a computer memory, a read-only memory (ROM), a random access memory (RAM), an electrical carrier signal, a telecommunication signal, and a software distribution medium. Examples include USB flash drives, portable hard drives, magnetic disks, or optical disks. In some jurisdictions, according to legislation and patent practice, computer-readable media cannot be electrical carrier signals or telecommunication signals.

[0088] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0089] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0090] In the embodiments provided in this application, it should be understood that the disclosed terminal devices and methods can be implemented in other ways. For example, the terminal device embodiments described above are merely illustrative. For instance, the division of modules or units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection through some interfaces, devices, or units, and may be electrical, mechanical, or other forms.

[0091] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0092] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A capacitance detection circuit, characterized by, The control module, the excitation module, the probe switching module, the probe, the CV conversion module and the peak detection module are included. The control module is connected with the excitation module and the probe switching module respectively, the probe switching module is connected with the probe, the excitation module and the CV conversion module respectively, and the probe is used for connecting with the capacitor to be measured. The excitation module is used for generating an excitation signal, and the probe switching module is used for switching the probe and the excitation module to be in conduction, so that the excitation signal is transmitted to the capacitor to be measured connected with the probe through the probe switching module. The probe switching module is also used for switching the probe and the CV conversion module to be in conduction, and the CV conversion module is used for outputting a voltage amplitude signal based on the capacitance change signal of the capacitor to be measured. The peak detection module is connected with the CV conversion module and the control module respectively, the peak detection module is used for performing peak detection on the voltage amplitude signal output by the CV conversion module and outputting a voltage peak envelope to the control module, and the control module is also used for calculating the capacitance of the capacitor to be measured based on the peak envelope.

2. The capacitance detection circuit of claim 1, wherein, The probe switching module includes a first analog switch, the input end of the first analog switch is connected with the control module, the data end of the first analog switch is connected with the probe, the first switching end of the first analog switch is connected with the excitation module, the second switching end of the first analog switch is connected with the CV conversion module, the VDD end of the first analog switch is connected with a first positive power supply circuit, the VSS end of the first analog switch is connected with a first negative power supply circuit, and the ground end of the first analog switch is virtually grounded.

3. The capacitance detection circuit of claim 1, wherein, The CV conversion module includes a first operational amplifier unit, a feedback resistor and a diode protection unit, the probe switching module is connected with the first end of the feedback resistor and the diode protection unit, the diode protection unit is connected with the input end of the first operational amplifier unit, and the output end of the first operational amplifier unit is connected with the second end of the feedback resistor and the peak detection module respectively.

4. The capacitance detection circuit of claim 3, wherein, A range configuration module is further included, the feedback resistor is connected with the range configuration module in parallel, the range configuration module is further connected with the control module, and the range configuration module includes at least one reference capacitor.

5. The capacitance detection circuit of claim 4, wherein, The range configuration module includes a second analog switch, the second analog switch includes at least one single-pole single-throw switch, the number of the single-pole single-throw switches is the same as the number of the reference capacitors, each single-pole single-throw switch is connected with a reference capacitor, and each reference capacitor is connected with a single-pole single-throw switch, and the single-pole single-throw switches are controlled by the control module.

6. The capacitance detection circuit of claim 1, wherein, The peak detection module comprises a second operational amplifier unit, a third operational amplifier unit, a detection diode and a peak holding capacitor, the non-inverting input terminal of the second operational amplifier unit is connected with the output terminal of the CV conversion module, the output terminal of the second operational amplifier unit is connected with the anode of the detection diode, the cathode of the detection diode is connected with the first terminal of the peak holding capacitor and the non-inverting input terminal of the third operational amplifier unit respectively, the second terminal of the peak holding capacitor is virtually grounded, and the output terminal of the third operational amplifier unit is connected with the inverting input terminal of the third operational amplifier unit, the inverting input terminal of the second operational amplifier unit and the analog-digital conversion unit of the control module respectively.

7. The capacitance detection circuit of claim 6, wherein, The peak detection module further comprises a limiting diode and a limiting resistor, the anode of the limiting diode is connected with the inverting input terminal of the second operational amplifier unit, the cathode of the limiting diode is connected between the output terminal of the second operational amplifier unit and the anode of the detection diode, the first terminal of the limiting resistor is connected with the inverting input terminal of the second operational amplifier unit, and the second terminal of the limiting resistor is connected with the output terminal of the third operational amplifier unit.

8. The capacitance detection circuit of any one of claims 1 to 7, wherein, The excitation module comprises an excitation generation unit and a two-stage operational amplifier unit, the input terminal of the two-stage operational amplifier unit is connected with the output terminal of the excitation generation unit, and the output terminal of the two-stage operational amplifier unit is connected with the probe switching module.

9. A capacitance detection system characterized by, The capacitive detection circuit comprises a detection host computer and a motion control system, the detection host computer is connected with the motion control system, the detection host computer and the motion control system are connected with the control module of the capacitive detection circuit respectively, the detection host computer is used for sending a measurement instruction to the control module of the capacitive detection circuit, and the motion control system is used for controlling the movement of the probe.

10. A capacitance detection method characterized by, The method is realized based on the capacitive detection circuit, and the method comprises the following steps: controlling the probe switching module to switch the probe and the excitation module to be conducted by the control module, and controlling the excitation module to charge the to-be-detected capacitor connected with the probe; controlling the probe switching module to switch the probe and the CV conversion module to be conducted by the control module, and the CV conversion module is used for outputting a voltage amplitude signal based on the capacitive change signal of the to-be-detected capacitor; receiving the voltage peak envelope output by the peak detection module by the control module, and calculating the capacitance value of the to-be-detected capacitor based on the voltage peak, and the peak detection module is used for performing peak detection on the voltage amplitude signal and outputting the voltage peak envelope.

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