Chip testing device

Abstract

The invention provides a chip testing device, relates to the field of chip testing, and can solve the problem of signal crosstalk caused by an air gap between a testing socket and a circuit board. The chip testing device comprises a circuit board and a testing socket. The test socket comprises a socket body, a middle dielectric layer, a plurality of probes and a plurality of conductive parts. The middle dielectric layer is arranged on one side, close to the circuit board, of the socket body, a plurality of pinholes are formed in the middle dielectric layer, and the conductive parts are filled in the pinholes. The probe penetrates through the socket body, and the tail part of the probe extends into the conductive part and is electrically connected with the circuit board through the conductive part. The contact stability of the probe and the circuit board can be improved through the conductive part, the air gap between the test socket and the circuit board is reduced, and the isolation of the test socket is improved.

Description

Technical Field

[0001] This application relates to the field of chip testing, and more particularly to a chip testing device. Background Technology

[0002] As packaging integration increases, the number of chip pins also increases. To reduce costs, the pin pitch of chips is reduced accordingly. At the same time, due to the demand for high bandwidth and higher data processing and transmission rates, chip speed specifications are constantly increasing, from the early 32Gbps to 60Gbps and even 112 / 224Gbps.

[0003] However, when testing high-speed chips, as the pin pitch decreases and the speed increases, crosstalk between pins intensifies. (Reference) Figure 1 As shown, the main reason for this crosstalk is that there are horizontal and vertical air gaps 'a' between the PCB (printed circuit board) and the test socket. This causes sensitive signals to be scattered at the air gap 'a', resulting in crosstalk problems. Summary of the Invention

[0004] This application provides a chip testing apparatus that can improve the signal crosstalk problem caused by the air gap between the test socket and the circuit board.

[0005] This application provides a chip testing apparatus, which includes a circuit board (PCB) and a test socket. The test socket includes a socket body, an intermediate dielectric layer, multiple probes, and multiple conductive portions. The intermediate dielectric layer is disposed on the side of the socket body near the circuit board, and multiple pinholes are formed in the intermediate dielectric layer, with the conductive portions filling the pinholes. The probes penetrate the socket body, and their tails extend into the conductive portions, and are electrically connected to the circuit board through the conductive portions.

[0006] In this testing device, the probe is connected to the PCB through a conductive part. Since the aperture of the conductive part (or the aperture of the pinhole) is larger than the diameter of the probe tail, the conductive part can better fit the PCB, improving the contact stability between the probe and the PCB, reducing the air gap between the test socket and the PCB, improving the isolation (ISO) of the test socket, and thus improving the problem of crosstalk degradation between signals. It can well meet the requirements of high-speed and ultra-high-speed electrical testing.

[0007] In addition, for grounding probes, the addition of conductive parts can compensate for the shortcomings of the probe tail being too thin, reduce the air gap between adjacent probes, reduce the scattering of electromagnetic signals, and thus improve the shielding effect of the grounding probe.

[0008] In some possible implementations, the thickness of the intermediate dielectric layer is less than or equal to 1 mm. This avoids the increase in electrical signal transmission path caused by an excessively thick intermediate dielectric layer, which would lead to increased insertion / return loss in the link and consequently affect electrical performance.

[0009] In some possible implementations, the ratio of the pinhole diameter to the probe tail diameter is greater than or equal to 5. This allows the diameter of the conductive part to be significantly larger than the diameter of the probe tail. The probe connects to the PCB through the conductive part, thereby greatly increasing the contact stability between the probe and the PCB and better meeting the isolation (ISO) requirements of actual testing.

[0010] In some possible implementations, the conductive parts are made of flexible conductive materials. This allows the conductive parts to have a certain compression stroke, which can better reduce the air gap between the test socket and the PCB, further improving the test socket's isolation (ISO).

[0011] In some possible implementations, conductive adhesive is used for the conductive parts.

[0012] In some possible implementations, the conductive part uses a conductive film.

[0013] In some possible implementations, the contact resistance between the probe tail and the conductive part is below 100 mohm, which can reduce losses and improve electrical performance.

[0014] In some possible implementations, the intermediate dielectric layer includes flexible materials such as plastic or rubber. This allows the intermediate dielectric layer to have a certain compression stroke, enabling it to fit more closely to the PCB, reducing the air gap between the test socket and the PCB, and better meeting the isolation requirements of the test.

[0015] In some possible implementations, spring-loaded probes are used. Because spring-loaded probes have excellent compression properties, they can effectively absorb chip warpage, ensuring a more stable electrical connection between the chip and the PCB during ATE (automated test equipment) testing. This is especially beneficial for large chips, which experience significant warpage; spring-loaded probes, with their longer compression stroke, can effectively absorb this warpage, reducing contact problems between the pins and the probe caused by large warpage.

[0016] In some possible implementations, the spacing between two adjacent probes is less than or equal to 0.8 mm to meet the chip's requirements for packaging, cost, and other aspects.

[0017] In some possible implementations, the top of the probe protrudes from the socket body, and the top of the probe is used to connect to the pins of the high-speed area of ​​the chip, thereby meeting the testing requirements of high-frequency and high-speed chips, such as high-speed loopback testing.

[0018] In some possible implementations, the socket body is made of metal; the multiple probes include a ground probe, a signal probe, and a power probe. The sidewall of the ground probe contacts the socket body, while a dielectric layer is provided between the sidewalls of the signal probe and the power probe and the socket body. In this case, the conductive parts allow for full contact between the ground probe and the socket body, thereby improving the isolation effect of the ground probe. Attached Figure Description

[0019] Figure 1 This is a schematic diagram of a chip detection device provided in the prior art;

[0020] Figure 2 This is a schematic diagram of the structure of a chip provided in an embodiment of this application;

[0021] Figure 3 This is a schematic diagram of the structure of a chip detection device provided in an embodiment of this application;

[0022] Figure 4 This is a schematic diagram of the structure of a chip provided in an embodiment of this application;

[0023] Figure 5 This is a schematic diagram of the structure of a chip provided in an embodiment of this application;

[0024] Figure 6 This is a schematic diagram illustrating an application scenario of a chip testing device provided in an embodiment of this application. Detailed Implementation

[0025] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0026] The terms "first," "second," etc., used in the specification, embodiments, claims, and drawings of this application are for descriptive purposes only and should not be construed as indicating or implying relative importance or order. "At least one" means one or more, and "more" means two or more. "Installation," "connection," "linking," etc., should be interpreted broadly, for example, they can refer to electrical connections or mechanical connections; fixed connections or detachable connections or integral connections; direct connections or indirect connections through an intermediate medium; or internal communication between two elements. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion, such as including a series of steps or units. A method, system, product, or device is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to these processes, methods, products, or devices. Terms such as “up,” “down,” “left,” and “right” are used only in relation to the orientation of the components in the accompanying drawings. These directional terms are relative concepts used for relative description and clarification, and they can change accordingly depending on the orientation of the components in the accompanying drawings.

[0027] This application provides a chip testing apparatus that can improve the signal crosstalk problem caused by the air gap between the test socket and the circuit board. Especially in high-frequency, high-speed testing scenarios (such as network / Turing / RF, etc.), it can well meet the isolation requirements of the test.

[0028] First, a simple illustration of the chip testing device's test object, namely the chip, will be provided.

[0029] refer to Figure 2 As shown, the active surface of chip D has multiple pins 1 (also called traces). Depending on the type of signal transmitted, these pins 1 can be classified as power supply pins, ground pins, and signal pins. Furthermore, pins 1 can be solder balls, pads, etc., and this application does not impose any restrictions on this.

[0030] Chip D interacts with external devices through multiple pins 1, thereby realizing its internal functions.

[0031] Therefore, during the chip manufacturing process, various performance tests need to be performed on the chip through pin 1. Chip testing equipment is an essential device for chip testing, and the performance of chip testing equipment directly affects the reliability and accuracy of the test results.

[0032] However, reference Figure 1 and Figure 2As shown, with the decrease in pin pitch P on the chip and the increase in chip transmission rate (e.g., pin pitch P is less than or equal to 0.8mm, and transmission rate is 60Gbps and above (112Gbps, 224Gbps, etc.), the encoding method of high-speed chips has been upgraded from the original NRZ encoding method to PAM4 encoding. Existing chip testing equipment (see reference) Figure 1 During chip testing, an air gap a exists between the test socket and the PCB, which can cause crosstalk between signal pins, resulting in degradation and failing to meet the isolation (ISO) requirements of actual testing.

[0033] Based on this, such as Figure 3 As shown, this application provides a novel chip testing device 01, which includes a circuit board (PCB) and a test socket 10. The test socket 10 includes a socket body 101, an intermediate dielectric layer 102, multiple probes 103, and multiple conductive portions 104. The intermediate dielectric layer 102 is fixed to the side of the socket body 101 near the PCB, and a pinhole V1 is provided in the intermediate dielectric layer 102, with the conductive portions 104 filling the pinhole V1. The probes 103 penetrate the socket body 101, with their tails (i.e., the end near the PCB) extending into the conductive portions 104, and are electrically connected to test contacts (pads) on the PCB surface via the conductive portions 104. The top of the probe 103 protrudes from the socket body 101 and connects to a pin 1 of the chip. In this way, the chip can be electrically connected to the PCB through the test socket 10, realizing the transmission of electrical signals between the chip and the PCB for chip testing.

[0034] The aforementioned intermediate dielectric layer 102 is made of a non-conductive material, i.e., a non-conductor, while the conductive material filling the pinhole V1 forms a conductive part 104, thereby enabling the tail of the probe 103 to connect to the PCB through the conductive part 104, satisfying the electrical connection between the probe and the PCB. Indicatively, the intermediate dielectric layer 102 can be adhered and fixed to the lower surface of the socket body 101, but is not limited to this.

[0035] In the testing apparatus provided in this application, the probe 103 is connected to the PCB through the conductive part 104. Since the aperture of the conductive part 104 (or the aperture of the pinhole V1) is larger than the diameter of the tail of the probe 103, the conductive part 104 can better fit the PCB, improve the contact stability with the PCB, reduce the air gap between the test socket and the PCB, improve the isolation (ISO) of the test socket 10, and thus improve the crosstalk deterioration problem between signals, which can well meet the requirements of high-speed and ultra-high-speed electrical testing.

[0036] In addition, for the grounding probe, the conductive part 104 can make up for the deficiency of the tail of the probe 103 being too thin, reduce the air gap between adjacent probes, reduce the scattering of electromagnetic signals, and thus improve the shielding effect of the grounding probe. For relevant descriptions of the grounding probe, please refer to the relevant description below.

[0037] In addition, the chip testing device 01 provided in this application has the advantages of simple structure and easy processing, and the chip testing device 01 is assembled from multiple different components, making disassembly and maintenance convenient.

[0038] This application does not limit the specific size of the pinhole V1, as long as it satisfies the filling of the conductive part 104 and ensures that the tail of the probe 103 can extend into the hole V1 and make stable contact with the conductive part 104.

[0039] As illustrated, in some possible implementations, the ratio of the aperture d1 of the pinhole V1 to the diameter d2 of the probe 103 tail is greater than 5, i.e., d1 / d2≥5. This allows the diameter of the conductive part 104 in the pinhole V1 to be significantly larger than the diameter of the probe 103 tail, thereby increasing the contact stability between the probe 103 and the PCB to a greater extent and better meeting the isolation (ISO) requirements of actual testing.

[0040] The following uses actual test data to evaluate existing chip testing devices (…). Figure 1 ) and the chip testing device of this application ( Figure 3 The isolation levels of the two components are compared and explained.

[0041] As illustrated, when using high-frequency AC signals of 6GHz, 13GHz, and 25GHz to test the chip, the existing chip testing devices have near-end isolation of -53dB, -46dB, and -45dB at the signal pins, respectively; while the chip testing device of this application has near-end isolation of -61dB, -56dB, and -48dB at the signal pins, respectively.

[0042] As illustrated, when using high-frequency AC signals of 6GHz, 13GHz, and 25GHz to test the chip, the existing chip testing devices have remote isolation of -57dB, -46dB, and -46dB at the signal pins, respectively; while the chip testing device of this application has remote isolation of -62dB, -56dB, and -55dB at the signal pins, respectively.

[0043] As can be seen from the above, compared with existing chip testing devices, the chip testing device of this application can significantly improve the near-end isolation and far-end isolation of signal pins by 5dB to 10dB, and the chip testing device of this application can meet the requirement that the near-end isolation and far-end isolation are both less than -50dB or close to -50dB.

[0044] The following provides a further explanation of the arrangement of the intermediate dielectric layer 102 and the conductive part 104.

[0045] As illustrated, in some possible implementations, the intermediate dielectric layer 102 can be made of a compressible non-conductive material, such as one or more of plastics and rubber. This allows the intermediate dielectric layer 102 to have a certain compression stroke, enabling it to fit more closely to the PCB, reducing the air gap between the test socket 10 and the PCB, and better meeting the isolation requirements of the test.

[0046] As illustrated, in some possible implementations, the thickness of the intermediate dielectric layer 102 can be less than or equal to 1 mm. This avoids the increase in electrical signal transmission path caused by an excessively thick intermediate dielectric layer 102, which would lead to increased insertion / return loss of the link and thus affect electrical performance.

[0047] As illustrated, in some possible implementations, the conductive part 104 can be made of a conductive material with good conductivity, so that the contact resistance between the tail of the probe 103 and the conductive part 104 is below 100 mohm. This reduces losses and improves electrical performance.

[0048] Of course, in order to enable the conductive part 104 to have a certain compression capability, and thus better absorb the processing errors introduced between the test socket 10 and the PCB, in some possible implementations, the conductive part 104 can be made of a flexible conductive material, so that the conductive part 104 has a certain compression stroke, such as a compression stroke of less than 0.2mm (≤0.2mm), thereby better reducing the air gap between the test socket 10 and the PCB, and further improving the isolation (ISO) of the test socket 10.

[0049] This application does not impose any restrictions on the flexible conductive material used in the conductive part 104; in practice, it can be set according to requirements.

[0050] For example, in some possible implementations, the conductive part 104 can be made of conductive adhesive, which is mainly composed of a base resin and conductive fillers (such as metal powder). The conductive adhesive binds the conductive fillers together through the adhesive effect of the base resin, forming a conductive path and achieving conductive connection of the bonded materials.

[0051] For example, in some possible implementations, the conductive part 104 may be a conductive film, which is a thin film made of a material with conductive properties, such as metal, carbon nanotubes, conductive polymers, etc.

[0052] It should be understood that conductive film can be thinner than conductive adhesive, and in practice, conductive adhesive or conductive film can be selected according to needs.

[0053] Of course, since the conductive part 104 is filled in the via V1 provided on the intermediate dielectric layer 102, the thickness of the intermediate dielectric layer 102 is basically the same as the thickness of the conductive part 104.

[0054] In practice, the material and thickness of the conductive part 104 can be selected according to different scenarios, and this application does not impose any restrictions on this.

[0055] For example, in scenarios involving high speed and high frequency (≥56Gbps, ≥15GHz) and pin pitch of 0.4mm to 0.8mm, the conductive part 104 can be made of conductive adhesive with a thickness of less than or equal to 1mm, or it can be made of conductive film with a thickness of less than or equal to 0.5mm.

[0056] For example, in scenarios involving low-to-medium speed and low-frequency (<32Gbps, <15GHz) and pin pitch of less than 0.4mm, the conductive part 104 can be made of conductive adhesive with a thickness of less than or equal to 1mm, or conductive film with a thickness of less than or equal to 0.5mm.

[0057] This application does not impose any restrictions on the configuration of probe 103; in practice, it can be configured as needed.

[0058] For example, refer to Figure 3 As shown, in some possible implementations, the probe 103 can be a spring-loaded probe (pogo pin). Indicatively, this spring-loaded probe may include an upper moving pin b1 and a lower moving pin b2 connected by a spring. In this case, the upper moving pin b1 is connected to pin 1 of the chip, and the lower moving pin b2 is connected to a test contact point (pad) on the PCB surface via a conductive part 104, thereby achieving an electrical connection between the PCB and the chip.

[0059] Because spring probes have excellent compression performance, they can effectively absorb chip warpage, PCB manufacturing variations, and pad flatness fluctuations. During ATE (automated test equipment) testing, this ensures a more stable electrical connection between the chip and the PCB. This is especially important for large chips, which can experience significant warpage due to differences in the thermal expansion coefficients of their components. Spring probes, with their longer compression stroke, effectively absorb this warpage, reducing contact problems between the pins and probes caused by large warpage.

[0060] Furthermore, it should be understood that the spacing of probes 103 is essentially the same as the pin spacing P on the chip's test surface. For example, when the pin spacing P is 0.8mm, the spacing between the corresponding probes 103 is also 0.8mm. Similarly, when the pin spacing is 0.4mm, the spacing between the corresponding probes 103 is also 0.4mm. Here, the pin spacing P refers to the distance between the centers of two pins, and the spacing between two probes 103 also refers to the distance between the centers of the two probes.

[0061] In addition, refer to Figure 3 As shown, according to the type of chip pins, the multiple probes 103 may include a ground probe G, a signal probe S, and a power probe P. The ground probe G is connected to the ground pin on the chip for grounding. The signal probe S is connected to the signal pin on the chip for signal transmission. The power probe P is connected to the power pin on the chip for providing power. Illustrated, in some scenarios, the detection device may simultaneously include a ground probe G, a signal probe S, and a power probe P; in other scenarios, the detection device may include only a ground probe G and a signal probe S.

[0062] In contrast, the conductive portions 104 located in the intermediate dielectric layer 102 do not need to be divided according to the type of chip pins. All conductive portions 104 can have a consistent structure, which is convenient for manufacturing and processing, and also easy to assemble.

[0063] As illustrated, in some chip detection devices 01 provided in the embodiments of this application, the probe 103 can be set in a coaxial line manner, that is, a coaxial probe, which can achieve a better isolation effect.

[0064] For illustrative purposes only, please refer to the following: Figure 3 As shown, in the case of using a coaxial probe, the socket body 101 can be made of metal. The sidewall of the grounding probe G is in direct contact with the socket body 101. The sidewalls of the signal probe S and the power probe P are provided with a dielectric layer 105 between them and the socket body 101.

[0065] Compared to existing coaxial probes (G), in order to ensure smooth movement of the probe within the pinhole during each compression and oscillation, the probe tube is thinner than the probe hole. This results in a certain probability that the probe tube will not make full contact with the socket body 101 during multiple crimping operations. On the other hand, for large-size chips, the number of pins is greater, and the number of grounding probes is relatively more, further increasing the probability of poor contact. Therefore, there may be localized issues with abnormal isolation performance.

[0066] In the coaxial solution of this application, the diameter of the conductive part 104 is larger than the diameter of the probe tail. The conductive part 104 enables the grounding probe G to make full contact with the socket body 101, thereby improving the isolation effect of the grounding probe G.

[0067] In addition, the chip testing device 01 provided in this application can be used for different high-speed and high-frequency scenarios.

[0068] For example, refer to Figure 4 As shown, in some possible implementations, the high-speed region A1 and the low-speed region A2 of the chip are located on the same test surface. In this case, the chip testing device 01 of this application can be connected to the pins of the high-speed region A1 for electrical testing (see reference). Figure 3 This allows us to meet the testing requirements of high-frequency and high-speed chips.

[0069] For example, refer to Figure 5 As shown, in some possible implementations, the high-speed region A1 and the low-speed region A2 of the chip are located on two test surfaces that are positioned opposite each other. In this case, refer to... Figure 6 As shown, tests can be performed on the high-speed zone A1 and the low-speed zone A2 respectively. The chip testing device 01 provided in this application is connected to the pins set in the high-speed zone A1 to perform electrical tests (such as high-speed loopback tests), while the low-speed zone A2 can be tested using existing testing devices.

[0070] Of course, for reference Figure 5 As shown, in some possible implementations, both test surfaces of the chip can be high-speed regions. In this case, both test surfaces can be tested using the chip testing device 01 provided in this application.

[0071] It should be understood that the data transfer rate of the chip in the high-speed zone A1 is usually higher than 56Gbps, while the data transfer rate in the low-speed zone A2 is usually lower than 56Gbps.

[0072] Of course, depending on actual needs, other components can also be installed in the chip testing device 01, such as the positioning pin 20 fixed between the test socket 10 and the PCB, etc. (See reference...) Figure 3 .

[0073] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A chip testing device, characterized in that, Includes circuit boards and test sockets; The test socket includes a socket body, an intermediate dielectric layer, multiple probes, and multiple conductive parts; The intermediate dielectric layer is disposed on the side of the socket body close to the circuit board, and the intermediate dielectric layer is provided with a plurality of pinholes, the conductive part being filled in the pinholes; The probe penetrates the socket body, and the tail of the probe extends into the conductive part and is electrically connected to the circuit board through the conductive part.

2. The chip testing apparatus according to claim 1, characterized in that, The thickness of the intermediate medium layer is less than or equal to 1 mm.

3. The chip testing apparatus according to claim 1 or 2, characterized in that, The ratio of the diameter of the pinhole to the diameter of the probe tail is greater than or equal to 5.

4. The chip testing apparatus according to any one of claims 1-3, characterized in that, The conductive part is made of flexible conductive material.

5. The chip testing apparatus according to any one of claims 1-4, characterized in that, The conductive part is made of conductive adhesive.

6. The chip testing apparatus according to any one of claims 1-4, characterized in that, The conductive part is made of a conductive film.

7. The chip testing apparatus according to any one of claims 1-6, characterized in that, The contact resistance between the probe tail and the conductive part is below 100 mohm.

8. The chip testing apparatus according to any one of claims 1-7, characterized in that, The intermediate medium layer includes plastic or rubber.

9. The chip testing apparatus according to any one of claims 1-8, characterized in that, The probe is a spring probe.

10. The chip testing apparatus according to any one of claims 1-9, characterized in that, The distance between two adjacent probes is less than or equal to 0.8 mm.

11. The chip testing apparatus according to any one of claims 1-10, characterized in that, The top of the probe protrudes from the socket body, and the top of the probe is used to connect to the pins of the high-speed area of ​​the chip.

12. The chip testing apparatus according to any one of claims 1-11, characterized in that, The socket body is made of metal. The plurality of probes includes a grounding probe, a signal probe, and a power supply probe; The sidewall of the grounding probe is in contact with the socket body, and a dielectric layer is provided between the sidewall of the signal probe, the sidewall of the power probe and the socket body.

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