Output power adjusting device and integrated circuit chip

Abstract

The invention discloses an output power adjusting device and an integrated circuit chip. The output power adjusting device comprises an interface circuit suitable for receiving a first signal and transmitting the received first signal to a load; the first driving unit is connected with the bias end of the interface circuit and is suitable for providing a power adjusting signal for the interface circuit, and the power adjusting signal is used for adjusting at least one of the bias voltage and the bias current of the interface circuit so as to change the output power of the interface circuit. By adopting the scheme, the influence on the signal transmission quality can be reduced in the process of adjusting the output power.

Description

Technical Field

[0001] This invention relates to the field of electronic circuit technology, specifically to an output power regulation device and an integrated circuit chip. Background Technology

[0002] In electronic engineering, output power refers to the instantaneous average power provided by a circuit, device, or system to the load in the form of electrical energy at the output port. It characterizes the rate at which energy is successfully transferred to the load per unit time and is a key indicator for evaluating drive capability, thermal design, and system efficiency.

[0003] In practical applications, since the power requirements and load-bearing capacity of load pairs are different, it is usually necessary to adjust the output power of the output port according to the actual power requirements and load-bearing capacity of different loads.

[0004] However, existing output power adjustment devices can affect signal transmission quality when adjusting output power. Summary of the Invention

[0005] The problem this invention aims to solve is to reduce the impact on signal transmission quality during the process of adjusting output power.

[0006] To address the aforementioned problems, this invention provides an output power adjustment device, comprising: an interface circuit adapted to receive a first signal and transmit the received first signal to a load; and a first driving unit connected to the bias terminal of the interface circuit, adapted to provide a power adjustment signal to the interface circuit, wherein the power adjustment signal is used to adjust at least one of the bias voltage and bias current of the interface circuit to change the output power of the interface circuit.

[0007] In one possible embodiment, the first driving unit includes: A reference source, suitable for providing a reference signal; The adjustment circuit is connected to the reference source and the interface circuit, and is adapted to adjust the reference signal to obtain the power adjustment signal.

[0008] In one possible embodiment, the reference signal is at least one of a reference voltage signal and a reference current signal with zero temperature coefficient.

[0009] In one possible embodiment, the adjustment circuit includes at least one of the following: A voltage trimming circuit is adapted to obtain the bias voltage of the interface circuit based on the reference current signal output by the reference source. The current trimmer circuit is adapted to obtain the bias current of the interface circuit based on the reference voltage signal output by the reference source.

[0010] In one possible embodiment, the voltage trimming sub-circuit includes: a third current mirror branch, a trimming controller, a fourth current mirror branch, and an output resistor; wherein: The adjustment controller is connected to the third current mirror branch and the fourth current mirror branch, and the output resistor is connected to the fourth current mirror branch; The fourth current mirror branch is used to replicate the current of the third current mirror branch and amplify it proportionally; the adjustment controller is used to control the magnitude of the current flowing through the output resistor.

[0011] In one possible embodiment, the current trimmer circuit includes: The adjustment module is connected to the reference source and is adapted to obtain a first adjustment current and a second adjustment current with zero temperature coefficient based on the reference voltage signal output by the reference source. And an amplification module, connected to the trimming module, adapted to amplify the first trimming current and the second trimming current with zero temperature coefficient to obtain the bias current of the interface circuit.

[0012] In one possible embodiment, the adjustment module includes: a second operational amplifier, a first adjustment MOSFET, a second adjustment MOSFET, and a third adjustment MOSFET; wherein: The second operational amplifier has a first input terminal connected to the reference source, a second input terminal connected to the drain of the first trim PMOS transistor, and an output terminal connected to the gate of the first trim PMOS transistor, the second trim PMOS transistor, and the gate of the third trim MOS transistor. The drain of the second adjustment PMOS transistor outputs a first adjustment current, and the drain of the third adjustment MOS transistor M3 outputs a second adjustment current.

[0013] In one possible embodiment, the amplification module is implemented using a dual-branch current mirror structure.

[0014] In one possible embodiment, the interface circuit is implemented using a current-mode logic structure, and the power adjustment signal is used to adjust the bias voltage and bias current of the current-mode logic structure.

[0015] In one possible embodiment, the output power regulation device further includes: The second driving unit is connected to the input terminal of the interface circuit, and is adapted to receive the first signal, amplify the first signal to obtain the second signal, and output it to the interface circuit.

[0016] In one possible embodiment, the second driving unit includes a first differential transconductance amplifier circuit and a second differential transconductance amplifier circuit.

[0017] In one possible embodiment, the output power regulation device further includes: The frequency divider unit is connected to the input terminal of the second drive unit and is adapted to receive the third signal, divide the third signal by frequency, and use it as the first signal.

[0018] In one possible embodiment, the frequency division unit is implemented using a dual-mode counting frequency divider or a programmable frequency divider.

[0019] This invention also provides an integrated circuit chip, which includes any of the above-described output power regulation devices.

[0020] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages: By employing the scheme of this invention, a first driving unit is provided, which can be connected to the bias terminal of the interface circuit. This allows for the adjustment of at least one of the bias voltage and bias current of the interface circuit via an output power adjustment signal, thereby changing the output power of the interface circuit. Since the first driving unit changes the output power of the interface circuit by adjusting at least one of the bias voltage and bias current, rather than changing the load impedance, it naturally does not affect the output impedance matching. This reduces the probability of signal reflection and distortion at high speeds, thereby improving signal transmission quality. Attached Figure Description

[0021] Figure 1 This is a schematic diagram of the structure of an output power regulation device according to an embodiment of the present invention; Figure 2 This is a schematic diagram of a current-mode logic circuit structure; Figure 3 This is a schematic diagram of another output power adjustment device in an embodiment of the present invention; Figure 4 This is a schematic diagram of the circuit structure of a bandgap reference source; Figure 5 This is a schematic diagram of the circuit structure of a trimming module; Figure 6 This is a schematic diagram of the circuit structure of an amplifier module; Figure 7 This is a schematic diagram of the circuit structure of a voltage trimmer circuit; Figure 8 This is a schematic diagram of the structure of another output power adjustment device in an embodiment of the present invention; Figure 9 This is a schematic diagram of the circuit structure of a second driving unit; Figure 10 This is a schematic diagram of the circuit structure of a frequency divider unit; Figure 11 This is a schematic diagram of the circuit structure of another frequency divider unit. Detailed Implementation

[0022] In analog integrated circuits, output power describes the ability of an output port to handle loads while maintaining good signal quality, and is crucial for signal exchange and transmission between systems. For example, the implementation of functions such as antennas, power amplifiers, cascading of circuits or chips, and signal testing all require sufficiently high output power from the output port to improve its driving capability.

[0023] However, different loads may have different actual power requirements and load-bearing capacities, so the output power of the output port needs to be adjusted.

[0024] The commonly used output power regulation scheme is to change the load impedance to change the output power. However, this scheme will affect the impedance matching of the output, which may cause signal reflection and distortion at high speeds, ultimately affecting the signal transmission quality.

[0025] To address this problem, the present invention provides an output power adjustment device. Using this device, the first driving unit can change the output power of the interface circuit by adjusting at least one of the bias voltage and bias current of the interface circuit. Compared with changing the impedance of the load, the impact on the output impedance matching can be reduced, thereby reducing the probability of signal reflection and distortion under high speed conditions, and thus improving the signal transmission quality.

[0026] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0027] Reference Figure 1 This invention provides an output power adjustment device 10, which may include an interface circuit 11 and a first driving unit 12. Wherein: The interface circuit 11 is adapted to receive the first signal S1 and transmit the received first signal S1 to the load 20.

[0028] The first driving unit 12 is connected to the bias terminal of the interface circuit 11 and is adapted to provide a power adjustment signal to the interface circuit 11. The power adjustment signal is used to adjust at least one of the bias voltage and bias current of the interface circuit to change the output power of the interface circuit 11.

[0029] In a specific implementation, the first signal S1 can be a signal within the frequency range required by the load 20. The interface circuit 11 connects the inside and outside of the chip, enabling the secure, accurate, and efficient integration of the internal and external components in terms of electrical, timing, protocol, and reliability dimensions. This allows the first signal S1 to be transmitted from the inside of the chip to the load 20 outside the chip. The load 20 can be any structure that receives the chip's output signals to drive other circuits or systems.

[0030] In a specific implementation, the interface circuit 11 has a bias terminal, which may include only a bias voltage terminal, only a bias current terminal, or both a bias voltage terminal and a bias current terminal. The specific configuration can be determined according to the actual structure of the interface circuit.

[0031] The power adjustment signal output by the first driving unit 12 can change the bias voltage connected to the bias voltage terminal of the interface circuit 11, thereby controlling the output power of the interface circuit 11, which in turn controls the swing of the output signal of the interface circuit 11. Similarly, the same power adjustment signal can also change the bias current connected to the bias current terminal of the interface circuit 11, which can also control the output power of the interface circuit 11, which in turn controls the swing of the output signal of the interface circuit 11.

[0032] In one embodiment, reference is made to Figure 2 The interface circuit 11 can adopt a current mode logic (CML) structure. The CML structure is often used as a high-speed serial interface circuit for low voltage differential signal transmission technology. It was once the only circuit that could meet the requirements of radio frequency operation. It has the advantages of low operating voltage, simple structure, large current, strong driving capability and high transmission rate. Due to its simple structure, it reduces the application of external devices. Also, because of its large dynamic current, it is suitable for high frequency operation.

[0033] Specifically, such as Figure 2 As shown, the interface circuit 11 of the CML structure may include: a first differential transistor N1, a second differential transistor N2, a first load resistor Rf1, a second load resistor Rf2, and a current source Io. The first differential transistor N1 and the second differential transistor N2 form a differential common-source pair. The first load resistor Rf1 and the second load resistor Rf2 serve as load resistors, typically implemented using an array of resistors, both with equal resistance values ​​of R0 (R is typically 50 ohms). One end of the first load resistor Rf1 and the second load resistor Rf2 is connected to the power supply voltage VDD.

[0034] In some embodiments, the interface circuit 11 of the CML structure may also include a first capacitor C1 and a second capacitor C2, which are used to isolate the common-mode voltage of the preceding circuit.

[0035] Under normal operating conditions, the first differential transistor N1 and the second differential transistor N2 operate in the saturation region. The differential input signals Din+ and Din- control the alternating conduction and cutoff of the first differential transistor N1 and the second differential transistor N2, thereby controlling the voltage level at the output terminal of the interface circuit 11. The current source Io acts as a tail current source, providing bias current to the first differential transistor N1 and the second differential transistor N2 to ensure the DC operating state of the circuit.

[0036] Since the gain of the interface circuit 11 equals the transconductance Impedance: With the impedance of interface circuit 11 fixed, changing the output power of interface circuit 11 can be achieved by changing its transconductance. The transconductance of interface circuit 11 is related to the bias current value I provided by current source Io. trim This is related to the gate voltages of the first differential transistor N1 and the second differential transistor N2. Therefore, the bias current value I provided by the current source Io can be changed by altering the gate voltages of the first differential transistor N1 and the second differential transistor N2. trim This can achieve the purpose of changing the output power of interface circuit 11.

[0037] Therefore, in embodiments of the present invention, a bias voltage Vtrim can be applied to the gate of the first differential transistor N1 via a first bias resistor Rs1, and a bias voltage Vtrim can be applied to the gate of the second differential transistor N2 via a second bias resistor Rs2. The gate voltages of the first differential transistor N1 and the second differential transistor N2 can be changed using the bias voltage Vtrim. The bias current value I of the current source Io can also be adjusted. trim This allows for simultaneous changes in the bias current of the interface circuit 11, thereby adjusting the output power of the interface circuit 11.

[0038] In addition, by changing the gate voltages of the first differential transistor N1 and the second differential transistor N2 using the bias voltage Vtrim, the linearity of the interface circuit 11 can be adjusted, thereby changing the upper limit of the output power of the interface circuit 11.

[0039] Of course, in other embodiments, the output power of the interface circuit 11 can be adjusted by simply changing the bias voltage or the bias current of the interface circuit 11.

[0040] In one embodiment of the present invention, reference is made to... Figure 3 The first driving unit 12 may include a reference source 121 and a tuning circuit. The reference source 121 is adapted to provide a reference signal, and the tuning circuit is connected to the reference source 121 and the interface circuit 11, and is adapted to tune the reference signal to obtain the power adjustment signal.

[0041] In specific implementations, the reference signal provided by the reference source 121 can be a reference voltage signal, a reference current signal, or both a reference voltage signal and a reference current signal simultaneously. The selection depends on whether the power adjustment signal is used to adjust the bias voltage or the bias current. For example, for... Figure 2 The interface circuit 11 of the CML structure shown can be selected from a reference source 121 that can simultaneously provide a reference voltage signal and a reference current signal.

[0042] In practical implementation, the reference source can be implemented using a bandgap reference source. As a cornerstone of many analog circuit designs, the bandgap reference source cleverly utilizes the physical properties of silicon semiconductors to precisely weight and sum voltages / currents with opposite temperature characteristics, ultimately generating a stable and reliable reference source that is almost unaffected by temperature changes, power supply voltage fluctuations, and process angle variations. Using the zero-temperature reference signal generated by the bandgap reference source to form the power regulation signal ensures that the power regulation signal is also a zero-temperature signal, thereby enabling more precise adjustment of the output power.

[0043] Figure 4 This is a schematic diagram of a common bandgap reference source circuit. (Refer to...) Figure 4 The bandgap reference source consists of a first operational amplifier 41, four PMOS transistors, two resistor arrays, two transistors, and a first fixed resistor R1. The four PMOS transistors are designated as a first bandgap MOS transistor K1, a second bandgap MOS transistor K2, a third bandgap MOS transistor K3, and a fourth bandgap MOS transistor K4. The two resistor arrays are designated as a first resistor array R1. trim1 and the second resistor array R trim2 The two transistors are transistor J1 and transistor J2.

[0044] The emitter of the first transistor J1 and the drain of the first bandgap MOSFET K1 are connected to the first input terminal of the first operational amplifier 41, while the base and collector of the first transistor J1 are grounded. The first resistor array R... trim1 The drains of the first fixed resistor R1 and the second bandgap MOSFET K2 are both connected to the second input terminal of the first operational amplifier 41. The first resistor array R... trim1 The other end is connected to the base of the second transistor J2, and the other end of the first fixed resistor R1 is connected to the emitter of the second transistor J2. The collector of the second transistor J2 is grounded. The gate of the third bandgap MOSFET K3 is connected to the gates of the first bandgap MOSFET K1, the second bandgap MOSFET K2, and the fourth bandgap MOSFET K4. The drain of the third bandgap MOSFET K3 serves as the reference voltage output terminal for the output reference voltage signal, which is connected to the second resistor array R1. trim2Grounded. The drain of the fourth bandgap MOSFET K4 serves as the reference current output terminal for the output reference current signal. The sources of the first bandgap MOSFET K1, the second bandgap MOSFET K2, the third bandgap MOSFET K3, and the fourth bandgap MOSFET K4 are all connected to the power supply voltage VDD.

[0045] The key modules in the above bandgap reference source circuit structure are the first operational amplifier 41, the first transistor J1, and the second transistor J2. Since the I / O characteristic curve of the transistor follows an exponential function trend, it can be specifically expressed as: (1) (2) Among them, I C For collector current, I S V is the reverse saturation current, and V is the base voltage and emitter voltage. T This is the voltage equivalent of temperature.

[0046] Based on the virtual short principle of the first operational amplifier 41, when the transistors across the first operational amplifier 41 are proportional to n, the voltage across the first fixed resistor R1 can be derived as follows: (3) n is a constant. represent The relationship is directly proportional to the temperature coefficient T, meaning the current in the first fixed resistor R1 is a positive temperature current. Furthermore, based on the semiconductor characteristics of the transistor, the voltage V... BE By finding the derivative of temperature, we can obtain the voltage V. BE It exhibits a negative temperature coefficient, meaning it is negatively correlated with temperature. Therefore, the first resistor array R... trim1 The current flowing through it is a negative temperature current; therefore, by combining positive and negative temperature coefficients, a zero temperature current I can be achieved. ZTAT The output. Similarly, the zero-temperature voltage V BG The voltage drop generated by the zero-temperature current flowing through the resistor can be mirrored by a mirror transistor composed of the third bandgap MOSFET K3 and the fourth bandgap MOSFET K4, and then utilized through the second resistor array R. trim2 A zero-temperature voltage is obtained. Therefore, this bandgap reference achieves a reference voltage V with zero temperature coefficient. BG and reference current I ZTAT Output.

[0047] In specific implementation, the adjustment objects based on the power adjustment signal vary, and reference should be made accordingly. Figure 3 The adjustment circuit may include at least one of a current adjustment circuit 1221 and a voltage adjustment circuit 1222. Wherein: The current trimmer circuit 1221 is adapted to obtain the bias current of the interface circuit 11 based on the reference voltage signal output by the reference source 121.

[0048] The voltage trimming circuit 1222 is adapted to obtain the bias voltage of the interface circuit 11 based on the reference current signal output by the reference source 121.

[0049] In one embodiment, the current trimming circuit 1221 may include a trimming module 1221a and an amplification module 1221b. Wherein: The adjustment module 1221a is connected to the reference source 121 and is adapted to obtain a first adjustment current and a second adjustment current with zero temperature coefficient based on the reference voltage signal output by the reference source 121. The amplification module 1221b is connected to the trimming module 1221a and is adapted to amplify the first trimming current and the second trimming current with zero temperature coefficient to obtain the bias current of the interface circuit 11.

[0050] Based on the reference voltage signal output by the reference source 121, the first and second adjustment currents with zero temperature coefficients are first obtained, and then the first and second adjustment currents with zero temperature coefficients are amplified to obtain a sufficiently high bias current value, thereby meeting the design requirements of high output power of the interface circuit 11.

[0051] In one embodiment of the present invention, reference is made to... Figure 5 The adjustment module 1221a may include: a second operational amplifier 51, a first adjustment MOSFET M1, a second adjustment MOSFET M2, and a third adjustment MOSFET M3. The drain of the second adjustment MOSFET M2 outputs a first adjustment current I. trim1 The drain of the third adjustment MOSFET M3 outputs a second adjustment current I. trim2 .

[0052] The reference voltage signal output by the reference source 121 is fed back to the other input of the second operational amplifier 51 through the negative feedback of the second operational amplifier 51 and the first trimmed MOSFET M1, thus realizing the voltage clamping function. The zero-temperature current output from the drain of the first trimmed MOSFET M1 is mirrored by the current formed by the second trimmed MOSFET M2 and the third trimmed MOSFET M3, which can replicate the drain current of the first trimmed MOSFET M1.

[0053] In some embodiments, the adjustment module 1221a may further include an adjustment resistor Rx. One end of the adjustment resistor Rx is connected to the drain of the first adjustment MOSFET M1, and the other end is grounded. The operating current of the first adjustment MOSFET M1 can be adjusted using the adjustment resistor Rx.

[0054] In some embodiments, the adjustment module 1221a may further include a multiplexer MUX, which is located between the adjustment resistor Rx and the drain of the first adjustment MOSFET M1, and is used to realize the external connection of the adjustment module 1221a, providing a feasible channel for off-chip testing. For example, the multiplexer MUX can be connected to the external circuitry to measure the reference voltage, or the multiplexer MUX can be connected to an external resistor to change the operating current of the first adjustment MOSFET M1.

[0055] After obtaining the first and second trimming currents with zero temperature coefficients, they can be amplified using the amplification module 1221b to obtain a larger bias current.

[0056] In one embodiment of the present invention, the amplification module 1221b can be implemented using a dual-branch current mirror structure.

[0057] Specifically, refer to Figure 6 The amplification module 1221b may include: a first current mirror branch composed of a first current mirror MOSFET Q1 and a second current mirror MOSFET Q2; a second current mirror branch composed of a third current mirror MOSFET Q3 and a fourth current mirror MOSFET Q4; and an output branch composed of a fifth current mirror MOSFET Q5 and a sixth current mirror MOSFET Q6. The gate of the first current mirror MOSFET Q1 is connected to the gate of the third current mirror MOSFET Q3. The gate of the second current mirror MOSFET Q2 is connected to the drain of the first current mirror MOSFET Q1 and the gate of the fifth current mirror MOSFET Q5. The gate of the fourth current mirror MOSFET Q4 is connected to the gate of the sixth current mirror MOSFET Q6.

[0058] The second current mirror branch provides bias voltage for the sixth current mirror MOSFET Q6. By connecting the gate of the fourth current mirror MOSFET Q4 to the drain of the second current mirror MOSFET Q3, the clamping problem of the drain voltage of the sixth current mirror MOSFET Q6 is eliminated. The first current mirror branch is used to provide bias for the common gate transistor. The second current mirror MOSFET Q2 constrains the source-drain voltage of the sixth current mirror MOSFET Q6.

[0059] use Figure 6 The amplification module 1221b shown in the figure solves the limitations of insufficient output impedance and small swing of the current source through the first current mirror branch and the second current mirror branch. It not only solves the clamping problem, but also makes the output swing margin higher.

[0060] In practice, the voltage trimmer circuit 1222 can be implemented using various circuit structures, and no restrictions are imposed here.

[0061] In one embodiment of the present invention, reference is made to... Figure 7The voltage trimming circuit 1222 may include: a third current mirror branch, a trimming controller 71, a fourth current mirror branch, and an output resistor R. out The adjustment controller is connected to the third current mirror branch and the fourth current mirror branch, and the output resistor R... out It is connected to the fourth current mirror branch. The fourth current mirror branch is used to replicate the current of the third current mirror branch and amplify it proportionally. The adjustment controller is used to control the current flowing through the output resistor R. out The magnitude of the current.

[0062] The third current mirror branch is the MOS transistor H1 and the source resistor R. L The system comprises: a MOSFET H1 connected to the reference source and the adjustment controller 71; and a current mirror array 72 including multiple current mirror branches, which replicate and amplify the drain current of the MOSFET H1. The adjustment controller 71 can be connected to the multiple current mirror branches of the current mirror array 72, thereby controlling the current flowing through the output resistor R. out The magnitude of the current.

[0063] Specifically, the drain of MOSFET H1 is connected to the reference current signal I. ZTAT The current source formed is connected to the source of MOSFET H1 through the source resistor R. L Connect the power supply voltage VDD. Source resistor R L The source degradation resistor of MOSFET H1 is used to resist PVT fluctuations. PVT fluctuations refer to performance fluctuations caused by changes in three key factors—process, voltage, and temperature—during electronic systems or manufacturing processes. Each current mirror branch of the current mirror array 72 can be composed of a branch resistor and a branch switch connected in series. The tuning controller 71 is connected to the gate of the branch switch in each current mirror branch of the current mirror array 72, thereby controlling the amplification ratio of the drain current of MOSFET H1 by controlling the conduction or disconnection of the branch switch.

[0064] The adjustment controller 71 can output an adjustment resistor control signal Ctrl[5:1] under the control of an external control signal. This adjustment resistor control signal Ctrl[5:1] can include multiple control bits (such as control bits CT1, CT2, CT3, CT4 and CT5) to control the conduction or disconnection of the branch switching transistors of each current mirror branch. Therefore, by controlling the different branch switching transistors, the bias voltage V can be changed. trim As the bias voltage of the interface circuit, it can meet the different magnitude requirements of the bias voltage of the interface circuit and achieve precise adjustment of output power and linearity.

[0065] In some embodiments, the voltage trimming circuit 1222 may further include a switching circuit 73. The switching circuit 73 may include an inverter F1 and a MOSFET H2. The inverter F1 is connected to the gate of the MOSFET H2. The drain of the MOSFET H2 is connected to the drain of the branch switching transistor within the current mirror array 72. The source of the MOSFET H2 is grounded. An external control signal can be connected to the input of the inverter F1 to control whether the MOSFET H2 is turned on or off, thereby controlling whether the voltage trimming circuit 1222 outputs a bias voltage V. trim .

[0066] In practical applications, considering the limited driving capability of the first signal S1, although it can meet the internal cascading requirements of the chip, it is usually unable to drive the interface circuit 11 when used for external testing and cascading scenarios due to the limited driving capability of the first signal S1.

[0067] To address this problem, in one embodiment of the present invention, referring to... Figure 8 The output power adjustment device 10 may further include a second driving unit 13, connected to the input terminal of the interface circuit 11, adapted to receive the first signal S1, amplify the first signal S1 to obtain a second signal S2, and output it to the interface circuit 11. By setting the second driving unit 13, the first signal S1 can be amplified before being output to the interface circuit 11, thereby improving the driving capability of the first signal S1.

[0068] In specific implementations, the second driving unit 13 can be implemented using various circuit structures, and no restrictions are imposed here.

[0069] In one embodiment of the present invention, reference is made to... Figure 9 The second driving unit 13 may include a first differential transconductance amplifier circuit 91 and a second differential transconductance amplifier circuit 92. The first differential transconductance amplifier circuit 91 and the second differential transconductance amplifier circuit 92 each have a first differential signal input terminal and a second differential signal input terminal. The first differential signal input terminal of the first differential transconductance amplifier circuit 91 and the second differential transconductance amplifier circuit 92 receives a first differential signal Vinn, and the second differential signal Vinn and the second differential signal Vinp receive a second differential signal Vinp. The first differential signal Vinn and the second differential signal Vinp have the same amplitude but opposite phase, forming the first signal S1.

[0070] The first differential transconductance amplifier circuit 91 includes a first amplifier transistor G1, a second amplifier transistor G2, a third amplifier transistor G3, and a fourth amplifier transistor G4. The gate of the first amplifier transistor G1 is connected to the gate of the second amplifier transistor G2 and the drain of the first amplifier transistor G1. The sources of the first amplifier transistor G1 and the second amplifier transistor G2 are connected to the power supply voltage VDD. The drain of the first amplifier transistor G1 is connected to the drain of the third amplifier transistor G3, and the drain of the second amplifier transistor G2 is connected to the drain of the fourth amplifier transistor G4. The sources of the third amplifier transistor G3 and the fourth amplifier transistor G4 are grounded. The gate of the third amplifier transistor G3 serves as the first differential signal input terminal, and the gate of the fourth amplifier transistor G4 serves as the second differential signal input terminal.

[0071] The second differential transconductance amplifier circuit 92 includes: a fifth amplifier transistor G5, a sixth amplifier transistor G6, a seventh amplifier transistor G7, and an eighth amplifier transistor G8. The gate of the fifth amplifier transistor G5 is connected to the gate of the sixth amplifier transistor G6 and the drain of the fifth amplifier transistor G5. The sources of the fifth amplifier transistor G5 and the sixth amplifier transistor G6 are connected to the power supply voltage VDD. The drain of the fifth amplifier transistor G5 is connected to the drain of the seventh amplifier transistor G7, and the drain of the sixth amplifier transistor G6 is connected to the drain of the eighth amplifier transistor G8. The sources of the seventh amplifier transistor G7 and the eighth amplifier transistor G8 are grounded. The gate of the seventh amplifier transistor G7 serves as the first differential signal input terminal, and the gate of the eighth amplifier transistor G8 serves as the second differential signal input terminal.

[0072] The first differential signal Vinn and the second differential signal Vinp are amplified by the first differential transconductance amplifier circuit 91 and the second differential transconductance amplifier circuit 92, respectively, to output the first differential result signal Voutn and the second differential result signal Voutp, forming the second signal S2. The second driving unit 13, composed of the first differential transconductance amplifier circuit 91 and the second differential transconductance amplifier circuit 92, can amplify the input signal while having low output impedance and a large output swing, thereby enhancing the driving capability of the second signal S2. Furthermore, a large output swing is a necessary condition for achieving high-power output from the interface circuit 11.

[0073] In specific implementation, refer to Figure 8 The frequency of the signal actually received by the output power regulating device may not meet the frequency requirements of the load. To obtain a first signal S1 that meets the load frequency requirements, the output power regulating device may further include a frequency divider unit 14. The frequency divider unit 14 is connected to the input terminal of the second drive unit 13 and is adapted to receive a third signal S3, and divide the third signal S3 to obtain the first signal S1. The third signal S3 is the signal actually received by the output power regulating device 10. Through the frequency divider unit 14, a first signal S1 covering a wider frequency range can be generated, thereby better meeting the load requirements.

[0074] Specifically, the frequency division unit 14 can be implemented using a dual-mode counting frequency divider or a programmable frequency divider.

[0075] Figure 10 This is a schematic diagram of a structure using a dual-mode counter frequency divider as the frequency division unit 14. (Refer to...) Figure 10 The frequency division unit 14 may include: a dual-mode prescaler 141, a first counter 142, and a second counter 143. Wherein: The dual-mode precalibrator 141 has its division ratio controlled by a calibration control signal to be P or P+1. The division ratio of the first counter 142 is N, and the division ratio of the second counter 143 is A, where N≥A.

[0076] When the circuit starts working, the dual-mode prescaler 141 is set to a division ratio of P+1. After P+1 clock cycles, the dual-mode prescaler 141 outputs a clock signal to the subsequent first counter 142 and second counter 143. Since the value of A is usually less than the value of N, when the second counter 143 receives A input clock edges, it first outputs a clock edge and then stops counting. At this time, the division unit 14 has received A... The clock edge of the second counter 143 is (P+1) cycles. The output clock edge of the second counter 143 changes the control signal of the dual-mode prescaler 141, changing its division ratio to P. After the first counter 142 receives (NA) output clock edges from the dual-mode prescaler 141, the dual-mode prescaler 141 reaches N counts and outputs one clock edge. This means that the frequency divider unit 14 has received P cycles again. (NA) clock edges. The output clock edge of the N counter resets the entire divider unit 14, and one divider cycle ends.

[0077] Therefore, within one frequency divider cycle, a total of A is received. (P+1)+P (NA) input clocks, which is N P+A clock cycles are used to achieve a division ratio of NP+A. This dual-mode divider architecture is also known as a pulse swallow counter, which has the advantages of high speed, low power consumption and simple circuitry.

[0078] Figure 11 This is a schematic diagram of a structure using a programmable frequency divider as the frequency division unit 14. (Refer to...) Figure 11The frequency division unit may include several 2 / 3 frequency divider circuits, such as 2 / 3 frequency divider circuits 1441 to 144n, where n > 1. Each 2 / 3 frequency divider circuit, in addition to input and output ports, also includes a mode port mod and an enable port P. The mode port mod is used to receive mode signals mod, such as mod1 to mod2. n The enable port P is used to input enable signals P1~P1. n The 2 / 3 frequency divider circuit 144 can be implemented using a D flip-flop.

[0079] Each 2 / 3 divider circuit 144 is cascaded to form a frequency division link. Its working principle is as follows: After entering a frequency division cycle, the unit at the end of the link generates a mode signal mod. This mode signal mod is transmitted upwards along the link stage by stage. Simultaneously, when the enable input of the 2 / 3 divider circuit 144 is 1, the mode signal mod will trigger the 2 / 3 divider circuit to perform a 3-fold frequency division operation. Therefore, the link composed of 2 / 3 divider circuits adjusts the period of the output signal to: (4) Among them, T in Given the period of the input signal IN, it can be seen from formula (4) that the frequency division ratio coverage range of the output signal is: However, the mode port can be designed as an expansion port, and can be implemented by adding some logic gates. arrive( The frequency division ratio within the range, of which Let n be any number less than n. This programmable frequency divider can be used to achieve ultra-wideband signal input.

[0080] In some embodiments, refer to Figure 8 The output power adjustment device 10 may further include a control unit 15. The control unit 15 can serve as an interface for adjusting and correcting the output power adjustment device 10. Specifically, the control unit 15 can output digital control signals to control the operation of the frequency divider unit 14 and the first drive unit 12. For example, the control unit 15 can control the first resistor array R in the reference source of the first drive unit 12 via digital control signals. trim1 and the second resistor array R trim2 The resistance value, current trimming circuit, multiplexer MUX and trimming resistor Rx in the current trimming circuit can also control the trimming controller in the voltage trimming circuit, thereby controlling the frequency and power of the output signal of the output power adjustment device 10.

[0081] By adopting the scheme in the embodiments of the present invention, at least one of the bias voltage and bias current of the interface circuit can be adjusted by the first driving unit, which can adjust the output power of the interface circuit with high precision and high stability, provide a reliable signal source for complex test environments, and meet the output power requirements in chip cascading scenarios, thus having a wider range of applications.

[0082] This invention also provides an integrated circuit chip, on which the output power regulation device is integrated.

[0083] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. An output power adjusting device, characterized by comprising: include: An interface circuit is adapted to receive a first signal and transmit the received first signal to the load; A first driving unit is connected to the bias terminal of the interface circuit and is adapted to provide a power adjustment signal to the interface circuit. The power adjustment signal is used to adjust at least one of the bias voltage and bias current of the interface circuit to change the output power of the interface circuit.

2. The output power adjustment apparatus of claim 1, wherein The first driving unit includes: A reference source, suitable for providing a reference signal; The adjustment circuit is connected to the reference source and the interface circuit, and is adapted to adjust the reference signal to obtain the power adjustment signal.

3. The output power adjustment apparatus of claim 2, wherein The reference signal is at least one of a reference voltage signal and a reference current signal with zero temperature coefficient.

4. The output power adjustment apparatus of claim 2, wherein The adjustment circuit includes at least one of the following: A voltage trimming circuit is adapted to obtain the bias voltage of the interface circuit based on the reference current signal output by the reference source. The current trimmer circuit is adapted to obtain the bias current of the interface circuit based on the reference voltage signal output by the reference source.

5. The output power adjustment apparatus of claim 4, wherein The voltage trimming sub-circuit includes: a third current mirror branch, a trimming controller, a fourth current mirror branch, and an output resistor; wherein: The adjustment controller is connected to the third current mirror branch and the fourth current mirror branch, and the output resistor is connected to the fourth current mirror branch; The fourth current mirror branch is used to replicate the current of the third current mirror branch and amplify it proportionally; the adjustment controller is used to control the magnitude of the current flowing through the output resistor.

6. The output power adjustment apparatus of claim 4, wherein The current trimmer circuit includes: The adjustment module is connected to the reference source and is adapted to obtain a first adjustment current and a second adjustment current with zero temperature coefficient based on the reference voltage signal output by the reference source. And an amplification module, connected to the trimming module, adapted to amplify the first trimming current and the second trimming current with zero temperature coefficient to obtain the bias current of the interface circuit.

7. The output power adjustment apparatus of claim 6, wherein The adjustment module includes: a second operational amplifier, a first adjustment MOSFET, a second adjustment MOSFET, and a third adjustment MOSFET; wherein: The second operational amplifier has a first input terminal connected to the reference source, a second input terminal connected to the drain of the first trim PMOS transistor, and an output terminal connected to the gate of the first trim PMOS transistor, the second trim PMOS transistor, and the gate of the third trim MOS transistor. The drain of the second adjustment PMOS transistor outputs a first adjustment current, and the drain of the third adjustment MOS transistor M3 outputs a second adjustment current.

8. The output power adjustment apparatus of claim 6, wherein The amplification module is implemented using a dual-branch current mirror structure.

9. The output power adjustment apparatus of claim 1, wherein The interface circuit is implemented using a current-mode logic structure, and the power adjustment signal is used to adjust the bias voltage and bias current of the current-mode logic structure.

10. The output power adjustment apparatus of any one of claims 1 to 9, wherein Also includes: The second driving unit is connected to the input terminal of the interface circuit, and is adapted to receive the first signal, amplify the first signal to obtain the second signal, and output it to the interface circuit.

11. The output power adjustment apparatus of claim 10, wherein The second driving unit includes a first differential transconductance amplifier circuit and a second differential transconductance amplifier circuit.

12. The output power adjustment apparatus of claim 10, wherein Also includes: A frequency division unit, connected with the input end of the second driving unit, adapted to receive a third signal and divide the third signal to generate the first signal.

13. The output power adjustment apparatus of claim 12, wherein The frequency division unit is implemented by a dual-mode counting frequency divider or a programmable frequency divider.

14. An integrated circuit chip, characterized by An output power regulating device comprising any one of claims 1 to 13.

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