Dynamic power consumption optimization system based on adaptive memory calculation
By using an adaptive in-memory computing dynamic power optimization system, which utilizes task-aware dynamic power management and thermal collaborative management technologies, the low resource utilization and energy waste problems in traditional in-memory computing architectures are solved, achieving high energy efficiency and high reliability in-memory computing.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-11-12
- Publication Date
- 2026-03-31
AI Technical Summary
Traditional in-memory computing architectures suffer from low resource utilization, energy waste, thermal throttling, and performance instability due to static resource allocation. In particular, in AI chips, computationally intensive tasks are hampered by data transfer restrictions between the processor and memory, leading to high power consumption and heat dissipation challenges.
The system employs an adaptive memory computing dynamic power optimization system, which achieves high-efficiency operation of the memory computing module through task-aware dynamic power management, dynamic reconfiguration of multi-precision computing units, and load migration and heat dissipation coordination technology based on thermal feedback.
It achieves high energy efficiency, low latency and high reliability operation of the in-memory computing module, solves the problems of static resource allocation and heat dissipation defects in traditional solutions, and improves resource utilization and energy efficiency.
Smart Images
Figure CN121765992A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of dynamic power consumption technology in memory computing, and belongs to the dynamic power consumption optimization system based on adaptive memory computing. Background Technology
[0002] AIGC and other emerging artificial intelligence technologies are booming, and computing power is a key support for them, with AI chips forming the foundation of computing power. Currently, the rapid iteration of AI technology presents numerous challenges to hardware deployment. First, the demand for computing power scale and density is urgent. The rise of large-scale models has dramatically increased the demand for large-scale chip computing power in AI. Traditional methods of simply stacking chips cannot effectively increase computing power scale; a multi-dimensional approach is needed, focusing on improving computing power density and integration. Second, chip energy efficiency is becoming increasingly prominent. High chip power consumption leads to heat dissipation problems, hindering computing power improvement and causing a surge in the cost of training and inference for large models. Current AI chips have low energy efficiency, high electricity costs, and poor economic viability. Third, AI chips encounter a "memory wall" when performing computationally intensive tasks. The power consumption and performance of computing chips are limited by data transfer between the processor and memory, severely restricting the progress of AI chips in terms of computing scale, density, and efficiency.
[0003] This invention proposes a dynamic power consumption optimization system based on adaptive memory computing. Through task-aware dynamic power management, reconfigurable computing unit arrays, and thermal collaborative management technology, it achieves high-energy-efficiency operation of the memory computing module and solves the static resource allocation and heat dissipation defects of traditional solutions. Summary of the Invention
[0004] To address the aforementioned technical problems, this invention provides a dynamic power consumption optimization system based on adaptive memory computing.
[0005] To achieve the above objectives, the present invention provides the following technical solution: A dynamic power consumption optimization system based on adaptive memory computing is provided, comprising: The memory controller is equipped with an instruction parsing module, which is used to capture and analyze the instruction stream sent by the processor in real time and extract instruction features; On the host side, a lightweight LSTM prediction model is deployed to analyze historical instruction sequences based on the extracted instruction features in order to predict the computational requirements within a specific future time window. Each memory sub-block is equipped with an independent power management chip. The power management chip dynamically adjusts the voltage and frequency of the corresponding sub-block according to the prediction results of the prediction model, thereby achieving multi-level voltage and dynamic frequency adjustment. The memory sub-block also integrates a reconfigurable computing unit that supports multiple computing precisions, and switches between different precision computing modes through logic circuits. The reconfigurable computing unit generates control signals by the coprocessor and dynamically activates the corresponding precision mode according to the prediction results of the prediction model. The thermal collaborative management module collects system load temperature data in real time through temperature sensors embedded in the memory sub-block, triggers task migration for overheated memory sub-blocks, and combines finite element analysis to predict hotspot trends, and performs thermal management control on the microchannels embedded in the memory module substrate.
[0006] Preferably, the instruction features include at least the extraction operation type, data precision identifier, and data volume.
[0007] Preferably, the independent power management chip supports multi-level voltage regulation and sends an electronic control gate signal to the logic circuit of the reconfigurable computing unit according to the prediction results of the prediction model, dynamically switching between different voltage levels.
[0008] Preferably, the memory sub-block also integrates a phase-locked loop (PLL), which dynamically adjusts the clock frequency according to the prediction results of the prediction model to match the computational load of the corresponding memory sub-block.
[0009] Preferably, the temperature sensor is a miniature thermocouple, embedded near the substrate or computing unit array of the memory sub-block, for real-time acquisition of local temperature data.
[0010] Preferably, the memory controller is further provided with a switching device connected to the power supply line of the memory sub-block; when the prediction model predicts that a memory sub-block will not have computing needs in a specific time window in the future, the switching device is configured to cut off the power supply to the sub-block.
[0011] Preferably, the multi-precision reconfigurable computing unit supports parallel mode, and two low-precision computing units are connected through an adder and a data bus to realize the calculation of the high-precision computing unit. When the system detects a sparse computing task, the idle units in the reconfigurable computing unit are reconfigured as a data compression engine for compressing sparse data.
[0012] Preferably, in the thermal collaborative management module: When the temperature of a sub-block exceeds the temperature threshold, the computation context of the high-temperature sub-block is retained, and the computation context, along with the data of the task to be migrated, is transferred to the adjacent sub-block with the lower temperature, and the flow rate of the microchannel coolant is adjusted. If the overall system temperature continues to rise while the sub-block temperature does not exceed the temperature threshold, the calculation accuracy will be reduced according to the task priority.
[0013] Compared with existing technologies, the present invention provides a dynamic power consumption optimization system based on adaptive memory computing, which has the following advantages: This invention addresses the problems of low resource utilization, energy waste, thermal throttling, and performance instability caused by static resource allocation, coarse-grained power consumption control, and passive heat dissipation in traditional in-memory computing architectures through three major technologies: task-aware dynamic power management, dynamic reconfiguration of multi-precision computing units, and load migration and heat dissipation coordination based on thermal feedback. It achieves high energy efficiency, low latency, and high reliability operation of in-memory computing modules.
[0014] The features and advantages of the present invention will be described in detail through embodiments and in conjunction with the accompanying drawings. Attached Figure Description
[0015] Figure 1 This is an architecture diagram of the dynamic power consumption optimization system based on adaptive memory computing of the present invention; Figure 2 This is a flowchart of the dynamic power consumption optimization system based on adaptive memory computing according to the present invention. Figure 3 This is a flowchart illustrating the thermal collaborative management process according to an embodiment of the present invention. Figure 4 This is a flowchart illustrating the operational logic of an embodiment of the present invention. Detailed Implementation
[0016] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. However, it should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of the invention. Furthermore, descriptions of well-known structures and technologies are omitted in the following description to avoid unnecessarily obscuring the concept of the invention.
[0017] See Figures 1-4 A dynamic power consumption optimization system based on adaptive memory computing, comprising: The memory controller is equipped with an instruction parsing module, which is used to capture and analyze the instruction stream sent by the processor in real time and extract instruction features; On the host side, a lightweight LSTM prediction model is deployed to analyze historical instruction sequences based on the extracted instruction features in order to predict the computational requirements within a specific future time window. Each memory sub-block is equipped with an independent power management chip (PMIC). The PMIC dynamically adjusts the voltage and frequency of the corresponding sub-block based on the prediction results of the prediction model, thereby achieving multi-level voltage and dynamic frequency adjustment. The memory sub-block also integrates a reconfigurable computing unit that supports multiple computing precisions, and switches between different precision computing modes through logic circuits. The reconfigurable computing unit generates control signals by the coprocessor and dynamically activates the corresponding precision mode according to the prediction results of the prediction model; the logic circuit is a switching multiplexer. The thermal collaborative management module collects system load temperature data in real time through temperature sensors embedded in the memory sub-block, triggers task migration for overheated memory sub-blocks, and combines finite element analysis to predict hotspot trends, and performs thermal management control on the microchannels embedded in the memory module substrate.
[0018] Specifically, the instruction features include at least the extraction operation type, data precision identifier, and data volume.
[0019] Specifically, the independent power management chip supports multi-level voltage regulation and sends an electronic control gate signal to the logic circuit of the reconfigurable computing unit based on the prediction results of the prediction model, dynamically switching between different voltage levels.
[0020] Specifically, the memory sub-block also integrates a phase-locked loop (PLL), which dynamically adjusts the clock frequency according to the prediction results of the prediction model to match the computational load of the corresponding memory sub-block.
[0021] Specifically, the temperature sensor is a miniature thermocouple, embedded near the substrate or computing unit array of the memory sub-block, for real-time acquisition of local temperature data.
[0022] Specifically, the memory controller is further provided with a switching device, which is connected to the power supply line of the memory sub-block; when the prediction model predicts that a certain memory sub-block will not have computing needs in a specific time window in the future, the switching device is configured to cut off the power supply to the sub-block, and the switching device may specifically be a MOSFET switch.
[0023] Specifically, the multi-precision reconfigurable computing unit supports parallel mode. Two low-precision computing units are connected through an adder and a data bus to realize the calculation of the high-precision computing unit. Specifically, the reconfigurable computing unit is configured to support multiple computing precisions such as FP32 / FP16 / INT8 / BF16, and two FP32 units are connected in parallel to realize FP64 calculation. When the system detects a sparse computing task, the idle units in the reconfigurable computing unit are reconfigured as a data compression engine, such as a CSR format conversion module, for compressing sparse data.
[0024] Specifically, in the thermal collaborative management module: when the temperature of a sub-block exceeds the temperature threshold, the computational context of the high-temperature sub-block is retained, and the computational context, together with the data of the task to be migrated, is transmitted to the adjacent sub-block with a lower temperature, and the flow rate of the microchannel coolant is adjusted; when the temperature of a sub-block does not exceed the temperature threshold, if the overall system temperature continues to rise, the computational accuracy is reduced according to the task priority.
[0025] Furthermore, in this invention, based on the type of computational task, the amount of data, and the complexity of the operation, the following specific mapping rules are established: Table 1. Mapping Rules for Task Type, Data Volume, and Operational Complexity By using refined task classification and mapping rules, precise linkage from LSTM prediction to PMIC voltage regulation is achieved. At the same time, by combining PLL frequency control and power gating technology, power consumption is minimized while ensuring performance.
[0026] Workflow Description: 1. Prediction Phase: A lightweight LSTM model continuously analyzes the GPU's historical instruction flow (such as the operation sequence over the past 100ms). Output the specific computation task for the next 5ms (e.g., "INT8 matrix multiplication, data size 128KB").
[0027] 2. Analysis and Decision-Making Stage: The task parser extracts key parameters (task type, data volume). Query the corresponding voltage (0.8V) and frequency (1.5GHz) according to the mapping rule table; Generate control signals: voltage regulation command (0.8V), frequency control word (1.5GHz), power gating signal (turn off FP unit).
[0028] 3. Execution Phase: The PLL receives the frequency control word and generates a 1.5GHz clock signal; The PMIC adjusts the corresponding memory sub-block to 0.8V according to the voltage command; The power gating unit cuts off the power to non-essential computing modules (such as FP32 / FP16 units); The computing core executes INT8 tasks at optimized voltage / frequency.
[0029] 4. Feedback Mechanism: Real-time monitoring of actual task execution status and feedback to the LSTM model; Dynamically correct prediction bias (e.g., temporarily increase the frequency when the actual data volume exceeds the predicted value).
[0030] This solution achieves precise linkage from LSTM prediction to PMIC voltage regulation through refined task classification and mapping rules. At the same time, it combines PLL frequency control and power gating technology to maximize power consumption reduction while ensuring performance.
[0031] For a specific application scenario, in one particular embodiment, the scenario is: a sudden AI inference task. 1) Initial state: Sub-blocks 1-4 all run training tasks in FP16 mode (1.0V).
[0032] 2) Inference request triggered: The processor detected the INT8 image classification task and executed: Sub-blocks 1-2 are switched to INT8 mode (0.8V), and the FP16 unit power supply is turned off.
[0033] Sub-blocks 3-4 remain in FP16 mode, with the voltage reduced to 0.9V to lower the priority.
[0034] Among them, the prerequisite logic, task awareness and demand prediction, are the core triggering conditions. Task access and detection: The processor receives externally submitted "INT8 image classification tasks" (such as CNN model inference), and the instruction stream enters the task awareness module.
[0035] Demand prediction: The task awareness module analyzes the instruction flow features through a lightweight LSTM model—extracting "Operation type = image classification reasoning", "Data precision identifier = INT8", and "Data volume = single frame 224×224 pixels"—and predicts that the core requirement is INT8 precision, no high-precision calculation is required, and low-power operation is necessary.
[0036] Coprocessor decision-making: The task-aware module transmits the prediction results to the RISC-V coprocessor, which generates two types of control signals: ① "precision + voltage" adjustment signal for the core execution sub-block; ② "low-power standby" signal for the spare sub-block.
[0037] 3) Thermal event handling: Subblock 1 temperature rises to 88℃, triggering: The task is moved to sub-block 4, and sub-block 1 enters the cooling state (microchannel flow rate is increased to 2ml / s).
[0038] Sub-block 4 limits the voltage to no more than 1.0V to prevent the formation of new hot spots.
[0039] The prerequisites are: the system's preset temperature threshold is 85℃ (over-temperature trigger threshold), and the current temperature of sub-block 4 is 62℃ (low-temperature standby state). Temperature acquisition and judgment: The thermal collaborative management module collects temperature data (88℃) in real time through thermocouples embedded in sub-block 1. Finite element analysis confirms that local hot spots have formed in sub-block 1 and the temperature continues to rise significantly.
[0040] Coprocessor triggers collaborative control: The thermal collaborative management module transmits temperature data and heat distribution prediction results to the RISC-V coprocessor, which then activates the "over-temperature emergency mechanism" and generates three major control signals.
[0041] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions or improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention.
Claims
1. A dynamic power consumption optimization system based on adaptive memory computing, characterized in that: include: The memory controller is equipped with an instruction parsing module, which is used to capture and analyze the instruction stream sent by the processor in real time and extract instruction features; On the host side, a lightweight LSTM prediction model is deployed to analyze historical instruction sequences based on the extracted instruction features, predict and output the computational requirements within a specific future time window; Each memory sub-block is equipped with an independent power management chip. The power management chip dynamically adjusts the voltage and frequency of the corresponding sub-block according to the prediction results of the prediction model, thereby achieving multi-level voltage and dynamic frequency adjustment. The memory sub-block also integrates a reconfigurable computing unit that supports multiple computing precisions, and switches between different precision computing modes through logic circuits. The reconfigurable computing unit generates control signals by the coprocessor and dynamically activates the corresponding precision mode according to the prediction results of the prediction model. The thermal collaborative management module collects system load temperature data in real time through temperature sensors embedded in the memory sub-block, triggers task migration for overheated memory sub-blocks, and combines finite element analysis to predict hotspot trends, and performs thermal management control on the microchannels embedded in the memory module substrate.
2. The dynamic power consumption optimization system based on adaptive memory computing according to claim 1, characterized in that: The instruction features include at least the extraction operation type, data precision identifier, and data volume.
3. The dynamic power consumption optimization system based on adaptive memory computing according to claim 1, characterized in that: The independent power management chip supports multi-level voltage regulation and sends an electronic control gate signal to the logic circuit of the reconfigurable computing unit based on the prediction results of the prediction model, dynamically switching between different voltage levels.
4. The dynamic power consumption optimization system based on adaptive memory computing according to claim 1, characterized in that: The memory sub-block also integrates a phase-locked loop (PLL), which dynamically adjusts the clock frequency according to the prediction results of the prediction model to match the computational load of the corresponding memory sub-block.
5. The dynamic power consumption optimization system based on adaptive memory computing according to claim 1, characterized in that: The temperature sensor is a miniature thermocouple, embedded near the substrate or computing unit array of the memory sub-block, for real-time acquisition of local temperature data.
6. The dynamic power consumption optimization system based on adaptive memory computing according to claim 1, characterized in that: The memory controller is also equipped with a switching device connected to the power supply line of the memory sub-block; when the prediction model predicts that a memory sub-block will not have computing needs in a specific time window in the future, the switching device is configured to cut off the power supply to the sub-block.
7. The dynamic power consumption optimization system based on adaptive memory computing according to claim 1, characterized in that: The multi-precision reconfigurable computing unit supports parallel mode, and two low-precision computing units are connected through an adder and a data bus to realize the calculation of the high-precision computing unit. When the system detects a sparse computing task, the idle units in the reconfigurable computing unit are reconfigured as a data compression engine for compressing sparse data.
8. The dynamic power consumption optimization system based on adaptive memory computing according to claim 1, characterized in that: In the thermal collaborative management module: When the temperature of a memory sub-block exceeds the temperature threshold, the computation context of the high-temperature sub-block is retained, and the computation context, along with the data of the task to be migrated, is transferred to the adjacent sub-block with the lower temperature, and the flow rate of the microchannel coolant is adjusted. If the overall system temperature continues to rise while the sub-block temperature does not exceed the temperature threshold, the calculation accuracy will be reduced according to the task priority.