Quantum error correction code design method and device, storage medium and electronic equipment
By constructing parameterized differentiable manifolds and geometry optimization algorithms, a hardware-optimized qubit layout scheme is generated, solving the problem that existing quantum error-correcting code design schemes rely on expert experience and realizing efficient quantum error-correcting code generation.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-22
- Publication Date
- 2026-03-31
AI Technical Summary
Existing quantum error correction code design schemes rely heavily on expert experience and manual trial and error, making it difficult to quickly generate high-performance quantum error correction codes that are adaptable to diverse hardware platforms.
By obtaining the physical error model and hardware architecture specifications of the target quantum hardware, a parameterized differentiable manifold is constructed, a hardware-optimized qubit layout scheme is generated using a geometric optimization algorithm, and a complete quantum error-correcting code specification is output.
The design of automated and customized quantum error-correcting codes has been achieved, which improves hardware adaptability, resource utilization efficiency and error correction performance, and enhances generation efficiency.
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Figure CN121766476A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of quantum computing technology, specifically to a quantum error correction code design method, apparatus, storage medium, and electronic device. Background Technology
[0002] Quantum error correction is the core foundation for building large-scale, fault-tolerant quantum computers. It aims to protect the coherence of quantum information and the reliability of computation in noisy environments by encoding logical information with redundant physical qubits and using quantum error-correcting codes to detect and correct physical errors. With the rapid development of various quantum computing platforms such as superconducting, ion traps, and optical quantum computing, designing efficient error-correcting codes that both meet the requirements of quantum information theory and adapt to specific hardware physical characteristics has become one of the key challenges in realizing practical fault-tolerant quantum computing.
[0003] Currently, mainstream quantum error-correcting code design schemes are mainly based on stable subcode frameworks, such as surface codes and color codes. These codes theoretically have a clear fault tolerance threshold and high resource efficiency. They are usually designed based on regular lattices or mathematical constructions, and their performance is analyzed and optimized under idealized, symmetric error models.
[0004] However, current quantum error-correcting code design schemes rely heavily on expert experience and manual trial and error, making it difficult to quickly generate high-performance quantum error-correcting codes for diverse hardware platforms. Summary of the Invention
[0005] This application provides a quantum error-correcting code design method, apparatus, storage medium, and electronic device, which can improve the generation efficiency of quantum error-correcting codes.
[0006] In a first aspect, embodiments of this application provide a quantum error-correcting code design method, including: To obtain the physical error model and hardware architecture specifications of the target quantum hardware; Based on the physical error model and the hardware architecture specification, a parameterized differentiable manifold for representing a stable sub-Hamiltonian of a quantum error-correcting code family is constructed. With the optimization objective of maximizing code distance or minimizing logic error rate, geometric optimization is performed on the parameterized differentiable manifold to obtain an optimized stable subset. Based on the hardware architecture specifications and the stable subset, a hardware-optimized qubit layout scheme is generated; Based on the stable subset and the qubit layout scheme, a complete quantum error correction code specification is output.
[0007] In the quantum error-correcting code design method provided in this application embodiment, the step of constructing a parameterized differentiable manifold for representing a stable sub-Hamiltonian of a quantum error-correcting code family based on the physical error model and the hardware architecture specification includes: Based on the physical error model, determine the parameterization priority direction of the stabilizer Hamiltonian; According to the hardware architecture specification, the allowed connection modes and parameter value ranges of the interaction terms in the stable sub-Hamiltonian are defined. Based on the parameterization priority direction, the allowed connection mode, and the parameter value range, the parameter space of the stable sub-Hamilton is constructed and constrained to form a parameterized differentiable manifold.
[0008] In the quantum error-correcting code design method provided in this application embodiment, the step of constructing and constraining the parameter space of the stable sub-Hamilton based on the parameterization priority direction, the allowed connection mode, and the parameter value range to form a parameterized differentiable manifold includes: The stabilizer Hamiltonian is converted into a parameter vector consisting of a set of continuous real parameters to obtain the parameter space; The parameter space is pre-structured based on the parameterization priority direction to construct an initial parameterized manifold; The initial parameterized manifold is constrained according to the allowed connection modes and the parameter value range to form a parameterized differentiable manifold.
[0009] In the quantum error-correcting code design method provided in this application embodiment, the step of constraining the initial parameterized manifold according to the allowed connection modes and the parameter value range to form a parameterized differentiable manifold includes: The allowed connection patterns are encoded as topological constraints of the initial parameterized manifold; The range of parameter values is mapped to the boundary constraints of the initial parameterized manifold; The initial parameterized manifold is constrained by the topological constraints and the boundary constraints to generate a parameterized differentiable manifold.
[0010] In the quantum error-correcting code design method provided in this application embodiment, the step of generating a hardware-optimized qubit layout scheme based on the hardware architecture specification and the stable subset includes: Map each stable sub-operator in the stable subset to the physical connection graph described by the hardware architecture specification; By using graph embedding algorithms, the number of two-qubit gates or the circuit depth required for the stabilizer measurement circuit are minimized to generate a hardware-optimized qubit layout scheme.
[0011] In the quantum error-correcting code design method provided in this application embodiment, the step of performing geometric optimization on the parameterized differentiable manifold with the optimization objective of maximizing code distance or minimizing logic error rate to obtain an optimized stable subset includes: Based on the parameterized differentiable manifold, an objective function that is positively correlated with code distance or negatively correlated with logic error rate is constructed. The objective function is iteratively optimized using a gradient-based optimization algorithm until the convergence condition is met, thereby obtaining the manifold parameters. The manifold parameters are decoded into combinations of Pauli operators to form an optimized stable subset.
[0012] In the quantum error-correcting code design method provided in this application embodiment, the step of employing a gradient-based optimization algorithm to iteratively optimize the objective function until the convergence condition is met to obtain the manifold parameters includes: Calculate the Riemann gradient of the objective function with respect to the current manifold parameters; The optimization search direction is determined based on the Riemann gradient. The parameters of the manifold are iteratively updated along the optimization search direction on the parameterized differentiable manifold until the convergence condition is met.
[0013] Secondly, embodiments of this application provide a quantum error-correcting code design apparatus, comprising: The acquisition unit is used to acquire the physical error model and hardware architecture specifications of the target quantum hardware; The building unit is used to construct a parameterized differentiable manifold for representing a stable sub-Hamiltonian of a quantum error-correcting code family, based on the physical error model and the hardware architecture specification. An optimization unit is used to perform geometric optimization on the parameterized differentiable manifold with the optimization objective of maximizing code distance or minimizing logic error rate, to obtain an optimized stable subset. The generation unit is used to generate a hardware-optimized qubit layout scheme based on the hardware architecture specifications and the stable subset. The output unit is used to output a complete quantum error correction code specification based on the stable subset and the qubit layout scheme.
[0014] Thirdly, this application provides a storage medium storing a plurality of instructions adapted for loading by a processor to execute the quantum error-correcting code design method described in any of the preceding claims.
[0015] Fourthly, this application provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the quantum error correction code design method described in any of the preceding claims.
[0016] In summary, the quantum error-correcting code design method provided in this application includes: obtaining a physical error model and hardware architecture specification of the target quantum hardware; constructing a parameterized differentiable manifold representing a stable sub-Hamiltonian for a family of quantum error-correcting codes based on the physical error model and the hardware architecture specification; performing geometric optimization on the parameterized differentiable manifold with the optimization objective of maximizing code distance or minimizing logic error rate to obtain an optimized stable subset; generating a hardware-optimized qubit layout scheme according to the hardware architecture specification and the stable subset; and outputting a complete quantum error-correcting code specification based on the stable subset and the qubit layout scheme. This application embodiment can improve the generation efficiency of quantum error-correcting codes. Attached Figure Description
[0017] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0018] Figure 1 This is a schematic diagram illustrating an application scenario of the quantum error-correcting code design method provided in the embodiments of this application.
[0019] Figure 2 This is a flowchart illustrating the quantum error-correcting code design method provided in the embodiments of this application.
[0020] Figure 3 This is a schematic diagram of the quantum error correction code design device provided in the embodiments of this application.
[0021] Figure 4 This is a schematic diagram of the structure of the electronic device provided in the embodiments of this application. Detailed Implementation
[0022] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.
[0023] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element. Furthermore, components, features, and elements with the same names in different embodiments of this application may have the same meaning or different meanings, the specific meaning of which must be determined by its interpretation in that specific embodiment or further in conjunction with the context of that specific embodiment.
[0024] It should be understood that the specific embodiments described herein are merely illustrative of this application and are not intended to limit this application.
[0025] In the following description, the use of suffixes such as "module," "part," or "unit" to denote elements is solely for the purpose of illustrative purposes and has no specific meaning in itself. Therefore, "module," "part," or "unit" may be used interchangeably.
[0026] In the description of this application, it should be noted that the terms "upper," "lower," "left," "right," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. In addition, terms such as "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.
[0027] Current mainstream quantum error-correcting code design schemes are mainly based on stable subcode frameworks, such as surface codes and color codes. These codes theoretically possess well-defined fault tolerance thresholds and high resource efficiency, and are typically designed based on regular lattices or mathematical constructions, with performance analysis and optimization performed under idealized, symmetric error models. However, current quantum error-correcting code design schemes heavily rely on expert experience and manual trial and error, making it difficult to quickly generate high-performance quantum error-correcting codes for diverse hardware platforms.
[0028] Based on this, embodiments of this application provide a quantum error correction code design method, apparatus, storage medium, and electronic device. Specifically, the quantum error correction code design apparatus can be integrated into an electronic device, which can be a server or a terminal, etc. The terminal can include mobile phones, wearable smart devices, tablets, laptops, and personal computers (PCs), etc., as well as other computer and auxiliary devices. The server can be a single server or a server cluster composed of multiple servers, and can be a physical server or a virtual server.
[0029] For example, such as Figure 1 As shown, the electronic device can acquire the physical error model and hardware architecture specification of the target quantum hardware; based on the physical error model and hardware architecture specification, a parameterized differentiable manifold for representing the stable sub-Hamiltonian of the quantum error-correcting code family is constructed; with the optimization objective of maximizing the code distance or minimizing the logic error rate, geometric optimization is performed on the parameterized differentiable manifold to obtain the optimized stable subset; according to the hardware architecture specification and the stable subset, a hardware-optimized qubit layout scheme is generated; based on the stable subset and the qubit layout scheme, the complete quantum error-correcting code specification is output.
[0030] The technical solutions shown in this application will be described in detail below through specific embodiments. It should be noted that the order of description of the following embodiments is not intended to limit the priority of the embodiments.
[0031] Please see Figure 2 , Figure 2 This is a flowchart illustrating the quantum error-correcting code design method provided in an embodiment of this application. The specific flow of the quantum error-correcting code design method is as follows: 101. Obtain the physical error model and hardware architecture specifications of the target quantum hardware.
[0032] Among them, target quantum hardware refers to a specific quantum processor platform for which quantum error correction codes are to be deployed, such as superconducting quantum chips, ion trap systems, or optical quantum platforms.
[0033] The physical error model is a comprehensive data and mathematical model used to account for the non-ideal characteristics of various quantum operations on the target quantum hardware. This physical error model includes, but is not limited to, one or more of the following elements: the operational error rate of single-qubit gates (such as X, Y, Z, H gates); the operational error rate of two-qubit gates (such as CNOT, CZ gates) and their potential crosstalk characteristics; the error rate of single-qubit measurement (readout); and the decoherence time parameters of the qubits (such as energy relaxation time T1 and phase coherence time T2). This physical error model is typically obtained through experimental calibration methods such as quantum process tomography or random benchmarking, and is provided in the form of probability distributions or error channel operators.
[0034] The hardware architecture specification describes the physical constraints and resource limitations of the target quantum hardware. This specification may include a qubit connection topology, a set of native gates, and resource constraints.
[0035] In this context, the qubit connectivity topology refers to the set of physical qubits defined in graph form, along with the connecting edges between them that allow for the direct execution of high-fidelity two-qubit gate operations. For example, it can be a two-dimensional grid, a linear array, or a lattice structure with specific neighbor relationships. The native gate set refers to the set of basic quantum gate operations that are natively supported by the hardware and offer optimal performance. Resource constraints may include factors such as the total number of qubits, the number of operations that can be executed in parallel, and limitations on control circuitry.
[0036] 102. Based on the physical error model and hardware architecture specifications, construct a parameterized differentiable manifold for representing stable sub-Hamiltonian quantities of quantum error-correcting codes.
[0037] In some embodiments, step 102 may include the following steps: 1021. Based on the physical error model, determine the parameterization priority direction of the stabilizer Hamiltonian.
[0038] Specifically, the physical error model can be analyzed to identify dominant or costly non-ideal characteristics in the target quantum hardware (e.g., a phase-flip error rate significantly higher than a bit-flip error rate). Based on this analysis, a bias can be mathematically set in the parameterization process. For example, when parameterizing the stabilizer Hamiltonian, directions that generate combinations of stabilizer operators with stronger suppression capabilities against dominant or costly non-ideal characteristics can be prioritized as parameterization directions.
[0039] 1022. According to the hardware architecture specification, define the allowed connection modes and parameter value ranges of the interaction terms in the stable sub-Hamiltonian.
[0040] In some embodiments, a qubit connection topology can be extracted from the hardware architecture specification, and then the allowed connection modes that the interaction terms in the stable sub-Hamilton must follow can be derived and formalized based on the qubit connection topology.
[0041] Since the qubit connection topology describes the direct operational connections between physical qubits in a graph structure, the following connection rules must be followed when parameterizing the stable sub-Hamilton: all qubits involved in each multi-qubit interaction term must belong to the same connected subgraph in the qubit connection topology. Alternatively, any two qubits coupled to each other in an interaction term must be directly connected by an edge in the qubit connection topology.
[0042] The aforementioned connection rules are defined as allowed connection modes, which are essentially constraint mappings of hardware physical connectivity in the mathematical parameter space. For example, if the target quantum hardware is a two-dimensional grid, this allowed connection mode stipulates that: if any interaction term contains two qubits, they must be horizontally or vertically adjacent on the grid; if it contains more qubits, the set of these qubits must form a connected subgraph on the grid.
[0043] For each interaction permitted by the "Allow Connectivity Mode", its strength or type parameter can be assigned a range of values determined by hardware characteristics. For example, the lower and upper limits of the parameter range may be determined by the minimum and maximum coupling strength achievable in the permitted connectivity mode, or by setting a safe range to avoid a known high-noise operating point.
[0044] 1023. Based on the parameterization priority direction, allowed connection modes and parameter value range, construct and constrain the parameter space of the stable sub-Hamilton to form a parameterized differentiable manifold.
[0045] First, the stable subset corresponding to the quantum error-correcting code to be designed can be mapped to a stable sub-Hamilton consisting of tensor products of multiple Pauli operators. Then, a set of discrete or continuous variables in this stable sub-Hamilton that determine the type and weight of each Pauli operator can be transformed into a set of parameter vectors consisting of continuous real parameters. All parameter vectors can then constitute a primitive parameter space.
[0046] Subsequently, the parameter space is pre-structured using a parameterization preference direction. For example, if Z-errors dominate in the target quantum hardware, the parameter vector can be initialized to favor generating more stable subterms containing Z operators, or the form of the parameterization function can be adjusted to prioritize exploring such structures, thus obtaining an initial parameterized manifold with preliminary biases. It is understandable that this pre-structuring is not a hard constraint, but rather provides a high-quality starting point or search bias for the optimization process, making it more likely to quickly approach a high-performance solution, thereby improving optimization efficiency.
[0047] Finally, hardware constraints can be applied to the initial parameterized manifold, making it a truly "hardware-aware" search space.
[0048] The hardware constraints include topological constraints and boundary constraints. In practice, allowed connection patterns can be encoded as topological constraints of the initial parameterized manifold; the range of parameter values can be mapped as boundary constraints of the initial parameterized manifold; and then the initial parameterized manifold can be constrained by the topological constraints and boundary constraints to generate a parameterized differentiable manifold.
[0049] As described above, step 1023 can specifically be as follows: convert the stabilizer Hamiltonian into a set of parameter vectors composed of continuous real parameters to obtain the parameter space; pre-structure the parameter space based on the parameterization priority direction to construct an initial parameterized manifold; constrain the initial parameterized manifold according to the allowed connection modes and parameter value ranges to form a parameterized differentiable manifold.
[0050] In this embodiment, by utilizing topological and boundary constraints to constrain the initial parameterized manifold, a parameterized differentiable manifold that satisfies all hardware physical limitations can be generated. Each point (a specific set of parameter vectors) on this parameterized differentiable manifold not only uniquely corresponds to a candidate quantum error-correcting code (i.e., a set of mutually commuting stables), but the structure of this quantum error-correcting code naturally satisfies the connectivity and performance boundary conditions of the target quantum hardware.
[0051] 103. With the optimization objective of maximizing code distance or minimizing logic error rate, perform geometric optimization on parameterized differentiable manifolds to obtain optimized stable subsets.
[0052] First, objective functions that are positively correlated with code distance or negatively correlated with logic error rate can be constructed based on parameterized differentiable manifolds.
[0053] In practical implementation, if maximizing the code distance is chosen as the optimization objective, an objective function positively correlated with the code distance needs to be constructed. Since the code distance itself is usually a discrete quantity (the weight of the smallest nontrivial logical operator), its differentiable approximation or surrogate function needs to be used in continuous optimization. For example, the weight spectrum of candidate logical operators in the null space of the stabilizer can be calculated, and a penalty function can be designed to make the optimization process tend to increase the minimum weight.
[0054] If minimizing the logic error rate is chosen as the optimization objective, then an objective function negatively correlated with the logic error rate needs to be constructed in conjunction with the physical error model. For example, for a candidate quantum error-correcting code corresponding to a parameter vector, the logic error rate of the candidate quantum error-correcting code can be estimated by using various error rates provided by the physical error model through numerical simulation (such as Monte Carlo sampling) or analytical approximation (such as calculation based on the error partition function), and this estimate can be used as the objective function.
[0055] Next, a gradient-based optimization algorithm can be used to iteratively optimize the objective function until the convergence condition is met, thus obtaining the manifold parameters. Specifically, the Riemann gradient of the objective function with respect to the current manifold parameters can be calculated first; then, the optimization search direction can be determined based on the Riemann gradient; finally, iterative updates can be performed along the optimization search direction on the parameterized differentiable manifold until the convergence condition is met, thus obtaining the manifold parameters.
[0056] Understandably, on a parameterized differentiable manifold, the ordinary Euclidean gradient of the objective function is not necessarily along the shortest ascending or descending direction of the manifold. Therefore, it is necessary to calculate its Riemann gradient. Specifically, the Euclidean gradient can be projected onto the tangent space of the parameterized differentiable manifold at the current parameter point, taking into account the metric tensor of the parameterized differentiable manifold itself (determined by the parameterization method). The Riemann gradient indicates the local direction in which the objective function value changes most rapidly under the constraints of the parameterized differentiable manifold.
[0057] The optimization search direction for this iteration can be determined based on the Riemann gradient. Then, the next iteration update is performed along this optimization search direction on the parameterized differentiable manifold.
[0058] It should be noted that the iteration terminates when the change in the objective function value is less than a preset threshold, the norm of the gradient is sufficiently small, or the maximum number of iterations is reached. The current parameter point obtained at this point is the (local) optimum found on the parameterized differentiable manifold. The parameters corresponding to this current parameter point are the manifold parameters.
[0059] Finally, the manifold parameters are decoded into combinations of Pauli operators to form an optimized stable subset.
[0060] The manifold parameter encodes the specific strength and type of all interaction terms in the stabilizer Hamiltonian. Through predefined decoding rules, the manifold parameter can be mapped back to a set of Pauli operators (such as the tensor product of X,Y,Z) that act on multiple qubits.
[0061] This set of Pauli operators constitutes an optimized stable subset. Each Pauli operator not only commutes with each other (satisfying the basic mathematical requirements of error-correcting codes), but it is also obtained through systematic optimization after comprehensively considering the physical error model and hardware architecture specifications of the target quantum hardware. Therefore, theoretically, it has excellent error-correcting performance potential for the target quantum hardware (manifested as high code distance or low logic error rate).
[0062] 104. Generate a hardware-optimized qubit layout scheme based on the hardware architecture specifications and stable subset.
[0063] In some embodiments, each stabilizing sub-operator in the stabilizing subset can be mapped to a physical connection graph (i.e., a qubit connection topology graph) described by the hardware architecture specification; the number of two-qubit gates or the circuit depth required for the stabilizing sub-measurement circuit is minimized by a graph embedding algorithm to generate a hardware-optimized qubit layout scheme.
[0064] Specifically, each stable sub-operator in the stable subset can first be mapped onto the physical connection graph described in the hardware architecture specification, based on the index of the qubit it acts upon. Each stable sub-operator and its acting qubit form a stable subgraph.
[0065] To "place" all stable subgraphs onto the physical connectivity graph, minimizing the total number of two-qubit gates required to execute all stable subgraph measurement circuits, or achieving the shallowest final measurement circuit depth, heuristic algorithms (such as simulated annealing, genetic algorithms) or dedicated graph embedding algorithms can be used.
[0066] Ultimately, the algorithm outputs a specific qubit layout scheme. This scheme explicitly specifies which specific physical qubit on the physical chip each logical data qubit and auxiliary measurement qubit corresponds to, and may include a SWAP operation network introduced to satisfy connectivity, but its overhead has been minimized.
[0067] 105. Based on stable subsets and qubit layout schemes, output complete quantum error correction code specifications.
[0068] The complete quantum error correction code specification defines quantum error correction codes that can be deployed and run on target quantum hardware.
[0069] The complete quantum error-correcting code specification may include basic coding parameters (such as the number of physical qubits, the number of logical qubits, and the code distance), stable sub-operators (all stable sub-operators listed in Pauli string form), logical operators (specific Pauli operators defining logical X and logical Z operations), qubit layout diagram, syndrome extraction circuit (based on the qubit layout scheme, describing in detail the sequence and timing of quantum gate operations for measuring each stable sub-operator), decoder recommendations (recommending efficient classical decoding algorithms that match the code), and expected performance metrics (such as the logic error rate threshold estimated based on the physical error model).
[0070] In summary, the quantum error-correcting code design method provided in this application includes: obtaining the physical error model and hardware architecture specification of the target quantum hardware; constructing a parameterized differentiable manifold for representing the stable sub-Hamiltonian of the quantum error-correcting code family based on the physical error model and hardware architecture specification; performing geometric optimization on the parameterized differentiable manifold with the optimization objective of maximizing code distance or minimizing logical error rate to obtain an optimized stable subset; generating a hardware-optimized qubit layout scheme according to the hardware architecture specification and stable subset; and outputting a complete quantum error-correcting code specification based on the stable subset and qubit layout scheme. This application achieves fully automated and customized quantum error-correcting code design starting from hardware characteristics, effectively solving the core problems of traditional quantum error-correcting code design being disconnected from actual hardware, having a single optimization dimension, and relying on manual trial and error. It significantly improves the hardware adaptability, resource utilization efficiency, overall error correction performance, and generation efficiency of quantum error-correcting codes.
[0071] To facilitate better implementation of the quantum error-correcting code design method provided in this application, this application also provides a quantum error-correcting code design apparatus. The meanings of the terms used are the same as in the quantum error-correcting code design method described above, and specific implementation details can be found in the descriptions within the method embodiments.
[0072] Please see Figure 3 , Figure 3 This is a schematic diagram of the structure of a quantum error-correcting code design device provided in an embodiment of this application. The quantum error-correcting code design device may include an acquisition unit 201, a construction unit 202, an optimization unit 203, a generation unit 204, and an output unit 205. Acquisition unit 201 is used to acquire the physical error model and hardware architecture specifications of the target quantum hardware; Building unit 202 is used to construct a parameterized differentiable manifold for representing a family of quantum error-correcting codes, based on a physical error model and hardware architecture specifications. The optimization unit 203 is used to perform geometric optimization on a parameterized differentiable manifold with the optimization objective of maximizing code distance or minimizing logic error rate, to obtain an optimized stable subset. The generation unit 204 is used to generate a hardware-optimized qubit layout scheme based on the hardware architecture specifications and stable subset; Output unit 205 is used to output a complete quantum error correction code specification based on a stable subset and a qubit layout scheme.
[0073] For specific implementation methods of each of the above units, please refer to the embodiments of the quantum error-correcting code design method described above, which will not be repeated here.
[0074] In summary, the quantum error-correcting code design apparatus provided in this application can acquire the physical error model and hardware architecture specification of the target quantum hardware through the acquisition unit 201; construct a parameterized differentiable manifold representing the stable sub-Hamiltonian of the quantum error-correcting code family based on the physical error model and hardware architecture specification by the construction unit 202; perform geometric optimization on the parameterized differentiable manifold with the optimization objective of maximizing the code distance or minimizing the logic error rate to obtain the optimized stable subset; generate a hardware-optimized qubit layout scheme based on the hardware architecture specification and the stable subset by the generation unit 204; and output a complete quantum error-correcting code specification based on the stable subset and the qubit layout scheme by the output unit 205. This application embodiment can improve the generation efficiency of quantum error-correcting codes.
[0075] This application also provides an electronic device that may integrate the quantum error correction code design device of this application, such as... Figure 4 As shown, it illustrates a structural schematic diagram of the electronic device involved in the embodiments of this application, specifically: The electronic device may include components such as a processor 301 with one or more processing cores and a memory 302 with one or more computer-readable storage media. Those skilled in the art will understand that... Figure 4 The electronic device structure shown does not constitute a limitation on the electronic device and may include more or fewer components than shown, or combine certain components, or have different component arrangements. Wherein: The processor 301 is the control center of the electronic device. It connects various parts of the electronic device via various interfaces and lines. By running or executing software programs stored in the memory 302 and / or this application, and by calling data stored in the memory 302, it performs various functions and processes data, thereby providing overall monitoring of the electronic device. Optionally, the processor 301 may include one or more processing cores; preferably, the processor 301 may integrate an application processor and a modem processor, wherein the application processor mainly handles the operation of the storage medium, user interface, and application programs, while the modem processor mainly handles wireless communication. It is understood that the modem processor may not be integrated into the processor 301.
[0076] The memory 302 can be used to store software programs and this application. The processor 301 executes various functional applications and data processing by running the software programs and this application stored in the memory 302. The memory 302 may mainly include a program storage area and a data storage area. The program storage area may store applications required for operating the storage medium and at least one function; the data storage area may store data created based on the use of the electronic device. In addition, the memory 302 may include high-speed random access memory and may also include non-volatile memory, such as at least one disk storage device, flash memory device, or other volatile solid-state storage device. Accordingly, the memory 302 may also include a memory controller to provide the processor 301 with access to the memory 302.
[0077] Although not shown, the electronic device may also include a display unit, an input unit, and a power supply, etc., which will not be described in detail here. Specifically, in this embodiment, the processor 301 in the electronic device loads the executable files corresponding to the processes of one or more application programs into the memory 302 according to the following instructions, and the processor 301 runs the application programs stored in the memory 302 to realize various functions, as follows: To obtain the physical error model and hardware architecture specifications of the target quantum hardware; Based on the physical error model and hardware architecture specifications, a parameterized differentiable manifold for representing stable sub-Hamiltonian quantities of quantum error-correcting codes is constructed. With the optimization objective of maximizing code distance or minimizing logic error rate, geometric optimization is performed on a parameterized differentiable manifold to obtain an optimized stable subset. Based on the hardware architecture specifications and stable subset, a hardware-optimized qubit layout scheme is generated; Based on stable subsets and qubit layout schemes, a complete quantum error-correcting code specification is output.
[0078] Those skilled in the art will understand that all or part of the steps in the various methods of the above embodiments can be performed by instructions, or by instructions controlling related hardware. These instructions can be stored in a computer-readable storage medium and loaded and executed by a processor.
[0079] Therefore, embodiments of this application provide a storage medium storing a plurality of instructions that can be loaded by a processor to execute steps in any of the methods provided in embodiments of this application. For example, the instructions can execute the following steps: To obtain the physical error model and hardware architecture specifications of the target quantum hardware; Based on the physical error model and hardware architecture specifications, a parameterized differentiable manifold for representing stable sub-Hamiltonian quantities of quantum error-correcting codes is constructed. With the optimization objective of maximizing code distance or minimizing logic error rate, geometric optimization is performed on a parameterized differentiable manifold to obtain an optimized stable subset. Based on the hardware architecture specifications and stable subset, a hardware-optimized qubit layout scheme is generated; Based on stable subsets and qubit layout schemes, a complete quantum error-correcting code specification is output.
[0080] For details on the implementation of each of the above operations, please refer to the previous examples, which will not be repeated here.
[0081] The storage medium may include: read-only memory (ROM), random access memory (RAM), disk or optical disk, etc.
[0082] Since the instructions stored in the storage medium can execute the steps of any method provided in the embodiments of this application, the beneficial effects that any method provided in the embodiments of this application can achieve can be realized. For details, please refer to the previous embodiments, which will not be repeated here.
[0083] The design method, apparatus, storage medium, and electronic device of the quantum error correction code provided in this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only for the purpose of helping to understand the core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.
Claims
1. A method of designing a quantum error-correcting code, comprising: The method comprises the following steps: acquiring a physical error model and a hardware architecture specification of a target quantum hardware; constructing a parameterized differentiable manifold for representing a stabilizer Hamiltonian of a quantum error correction code family based on the physical error model and the hardware architecture specification; performing geometric optimization on the parameterized differentiable manifold to obtain an optimized stabilizer set, with the optimization objective being to maximize code distance or to minimize logical error rate; generating a hardware-optimized qubit layout scheme according to the hardware architecture specification and the stabilizer set; and outputting a complete quantum error correction code specification based on the stabilizer set and the qubit layout scheme.
2. The quantum error-correcting code design method of claim 1, wherein, The step of constructing a parameterized differentiable manifold for representing a stabilizer Hamiltonian of a quantum error correction code family based on the physical error model and the hardware architecture specification comprises the following steps: determining a parameterized priority direction of the stabilizer Hamiltonian according to the physical error model; defining an allowed connection mode and a parameter value range of an interaction term in the stabilizer Hamiltonian according to the hardware architecture specification; and constructing and constraining a parameter space of the stabilizer Hamiltonian to form the parameterized differentiable manifold based on the parameterized priority direction, the allowed connection mode and the parameter value range.
3. The quantum error-correcting code design method of claim 2, wherein, The step of constructing and constraining a parameter space of the stabilizer Hamiltonian to form the parameterized differentiable manifold based on the parameterized priority direction, the allowed connection mode and the parameter value range comprises the following steps: converting the stabilizer Hamiltonian into a group of parameter vectors composed of continuous real parameters to obtain a parameter space; pre-structuring the parameter space based on the parameterized priority direction to construct an initial parameterized manifold; and constraining the initial parameterized manifold according to the allowed connection mode and the parameter value range to form the parameterized differentiable manifold.
4. The quantum error-correcting code design method of claim 3, wherein, The step of constraining the initial parameterized manifold according to the allowed connection mode and the parameter value range to form the parameterized differentiable manifold comprises the following steps: encoding the allowed connection mode as a topological constraint of the initial parameterized manifold; mapping the parameter value range as a boundary constraint of the initial parameterized manifold; and constraining the initial parameterized manifold by using the topological constraint and the boundary constraint to generate the parameterized differentiable manifold.
5. The quantum error-correcting code design method of claim 1, wherein, The step of generating a hardware-optimized qubit layout scheme according to the hardware architecture specification and the stabilizer set comprises the following steps: mapping each stabilizer operator in the stabilizer set to a physical connection graph described by the hardware architecture specification; and minimizing the number of two-qubit gates or the circuit depth required by a stabilizer measurement circuit by using a graph embedding algorithm to generate the hardware-optimized qubit layout scheme.
6. The quantum error-correcting code design method of claim 1, wherein, The step of performing geometric optimization on the parameterized differentiable manifold to obtain an optimized stabilizer set, with the optimization objective being to maximize code distance or to minimize logical error rate, comprises the following steps: constructing an objective function positively correlated with code distance or negatively correlated with logical error rate based on the parameterized differentiable manifold; performing iterative optimization on the objective function by using a gradient-based optimization algorithm until a convergence condition is met to obtain manifold parameters; and decoding the manifold parameters into a combination of Pauli operators to form the optimized stabilizer set.
7. The quantum error-correcting code design method of claim 6, wherein, The gradient-based optimization algorithm is used to iteratively optimize the target function until a convergence condition is met, obtaining manifold parameters, comprising: calculating the Riemannian gradient of the target function at the current manifold parameter; determining an optimization search direction according to the Riemannian gradient; iteratively updating along the optimization search direction on the parameterized differentiable manifold until a convergence condition is met, obtaining manifold parameters.
8. A quantum error correcting code design apparatus, characterized by comprising: Comprising: an acquisition unit configured to acquire a physical error model and a hardware architecture specification of target quantum hardware; a construction unit configured to construct a parameterized differentiable manifold representing a stabilizer Hamiltonian of a family of quantum error correction codes based on the physical error model and the hardware architecture specification; an optimization unit configured to perform geometric optimization on the parameterized differentiable manifold with the optimization objective of maximizing code distance or minimizing logical error rate, to obtain an optimized stabilizer set; a generation unit configured to generate a hardware-optimized qubit layout scheme according to the hardware architecture specification and the stabilizer set; an output unit configured to output a complete quantum error correction code specification based on the stabilizer set and the qubit layout scheme.
9. A storage medium, characterized by The storage medium stores a plurality of instructions adapted to be loaded by the processor to execute the quantum error correction code design method of any one of claims 1-7.
10. An electronic device, comprising: A computer program product comprising a memory, a processor, and a computer program stored on the memory and executable on the processor, wherein the processor implements the quantum error correction code design method of any one of claims 1-7 when executing the computer program.