Partition scanning compensation circuit and display panel

Abstract

The embodiment of the invention discloses a partition scanning compensation circuit and a display panel. In the partition scanning compensation circuit, a detection switching circuit is connected with at least two scanning lines and is connected to a voltage division circuit through a detection sensing line, the detection switching circuit is used for communicating at least part of the scanning lines with the voltage division circuit in a non-display period, and the frequencies of scanning signals transmitted by the two scanning lines are different. The voltage division circuit carries out preset proportion voltage division on the voltage of a scanning signal transmitted on a scanning line and carries out level conversion to obtain a detection voltage division signal, and the signal conversion circuit converts the detection voltage division signal into a digital pulse width signal. The conversion sampling circuit is used for sampling the digital pulse width signal to form a digital sampling signal according to a sampling clock signal in a period corresponding to the scanning signal. The display panel comprises a partition scanning compensation circuit and a scanning driving circuit, and the scanning driving circuit is adjusted and compensated to output scanning signals with different frequencies according to sampling signals.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a partitioned scan compensation circuit and a display panel. Background Technology

[0002] The display device includes a display panel and a data driving circuit and a scan driving circuit for driving the display panel. The data driving circuit provides data driving signals to the data lines of the display panel, while the scan driving circuit provides scan signals to the scan lines of the display panel for image display. Currently, when different areas of the display panel have different refresh rates, areas with different refresh rates are prone to different brightness, resulting in uneven brightness in the image display area of ​​the display panel. Summary of the Invention

[0003] In view of the aforementioned technical problems, this application provides a partitioned scan compensation circuit capable of compensating for scan signals in areas with different refresh rates, and provides a display panel including the partitioned scan compensation circuit.

[0004] In a first aspect, embodiments of this application disclose a partitioned scanning compensation circuit, including a detection switching circuit, a voltage divider circuit, a signal conversion circuit, and a conversion sampling circuit. The detection switching circuit connects at least two scan lines and is connected to the voltage divider circuit via a detection sensing line, for connecting at least a portion of the scan lines to the voltage divider circuit during non-display periods. The scan signals transmitted by the two scan lines have different frequencies. The voltage divider circuit is connected to the detection sensing line and the signal conversion circuit, for dividing the voltage of the scan signal transmitted on the scan lines by a preset ratio and performing level conversion to obtain a detection voltage divider signal. The signal conversion circuit is connected to the voltage divider circuit and the conversion sampling circuit, for converting the detection voltage divider signal into a digital pulse width signal. The conversion sampling circuit samples the digital pulse width signal according to a sampling clock signal within one cycle corresponding to the scan signal to form a digital sampling signal.

[0005] In one embodiment of this application, the detection switching circuit includes at least two switching transistors, which are respectively connected to a scan line and the voltage divider circuit. The switching transistors are selectively turned on or off under the control of a test switching signal. When the switching transistors are turned on, the scan line and the voltage divider circuit are electrically connected. When the switching transistors are turned off, the scan line and the voltage divider circuit are electrically disconnected. The test switching signal is valid during the non-display period and controls the switching transistors to turn on.

[0006] In one embodiment of this application, the voltage divider circuit includes a voltage divider input terminal, a voltage divider output terminal, a first voltage divider resistor, and a second voltage divider resistor. The input terminal is connected to the switching transistor through the scanning detection line, and the voltage divider output terminal is connected to the signal conversion circuit. The first voltage divider resistor and the second voltage divider resistor are connected in series between the voltage divider input terminal and the ground terminal. Any node between the first voltage divider resistor and the second voltage divider resistor is connected to the voltage divider output terminal to output the detection voltage divider signal.

[0007] In one embodiment of this application, the signal conversion circuit includes a conversion input terminal, a reference control terminal, and a conversion output terminal. The conversion input terminal is connected to the voltage divider output terminal and is used to receive the detected voltage divider signal. The reference control terminal is used to receive a reference signal. The conversion output terminal is connected to the conversion sampling circuit. The signal conversion circuit converts the time information of the detected voltage divider signal exceeding the corresponding reference threshold in the reference signal into the digital pulse width signal and outputs it from the conversion output terminal.

[0008] In one embodiment of this application, the signal conversion circuit includes a comparator, which includes a non-inverting input, an inverting input, and a comparison output. The non-inverting input is connected to the voltage divider output, the inverting input receives the reference signal to obtain the reference voltage, and the comparison output is connected to the conversion output. The comparator is used to convert the time information of the voltage divider detection signal corresponding to the scan signal being greater than the reference threshold into the digital pulse width signal. The digital pulse width signal is used to quantify the steepness of the rising edge of the scan signal.

[0009] In one embodiment of this application, the signal conversion circuit includes an operational amplifier, a unidirectional control circuit, an integrator circuit, and a control circuit. The operational amplifier is connected to the conversion input terminal and the unidirectional control circuit, and is used to form a voltage follower for the detected voltage divider signal and output a corresponding op-amp follower signal. The unidirectional control circuit is connected to the operational amplifier and is used to unidirectionally control the unidirectional transmission of the op-amp follower signal to the integrator circuit. The integrator circuit is connected to the unidirectional control circuit and is used to perform voltage-time area integration on the op-amp follower signal and obtain an integral conversion output voltage, which corresponds to the digital pulse width signal. The control circuit is connected to the integrator circuit and the conversion output terminal and is used to control the start and stop times of the integration of the op-amp follower signal by the integrator circuit.

[0010] In one embodiment of this application, the conversion sampling circuit includes an N-bit shift register, which receives the digital pulse width signal and samples the digital pulse width signal according to the sampling clock signal as the shift sampling clock to form a digital sampling signal; or, the conversion sampling circuit includes an analog-to-digital converter, which samples the digital pulse width signal and converts it into an N-bit digital sampling signal.

[0011] Secondly, this application also provides a display panel, including a display area, which includes multiple pixel units, multiple data lines, and multiple scan lines. The multiple scan lines extend along a first direction and are mutually insulated and arranged in parallel along a second direction. The multiple data lines extend along the second direction and are mutually insulated and arranged in parallel along the first direction. The first direction and the second direction are perpendicular to each other. A pixel unit is connected to one scan line and one data line. Along the second direction, the display area corresponds to at least a first partition and a second partition. The pixel units in the first partition and the second partition have different refresh rates when they are working, and the corresponding scan lines transmit scan lines at different frequencies. In one embodiment of this application, the display panel further includes a non-display area, which includes a timing control circuit, a data driving circuit, and a scan driving circuit. The timing control circuit is electrically connected to the data driving circuit and the scan driving circuit, and is used to output corresponding timing control signals to the data driving circuit and the scan driving circuit to control the timing of the scan driving circuit outputting corresponding scan signals and the timing of the data driving circuit outputting corresponding data signals. The data driving circuit is electrically connected to multiple data lines for transmitting the data signals to the pixel units. The scan driving circuit is electrically connected to multiple scan lines for outputting scan signals to the pixel units to control the timing of the pixel units receiving the data signals. The timing control circuit is connected to the partition scan compensation circuit and is used to receive the sampling signals during the initialization period after the display panel is powered on and before the image is displayed, and to adjust and compensate the scan signals according to the sampling signals.

[0012] In one embodiment of this application, the display panel further includes a level conversion circuit. The level conversion circuit is connected to the timing control circuit and the scan driving circuit. The level conversion circuit is used to provide a clock signal to the scan driving circuit under the control of the timing control circuit. The scan driving circuit outputs the scan signal according to the high and low levels of the clock signal. The timing control circuit adjusts the potential of the high level of the clock signal output by the level conversion circuit according to the sampling signal.

[0013] In one embodiment of this application, the scan driving circuit includes multiple cascaded scan driving units, each scan driving unit being connected to one of the scan lines and outputting the scan signal according to the clock signal; the scan driving unit includes a pull-up module, a pull-up node, a first pull-down module, a pull-down node, an output module, a second pull-down module, and a compensation module; the pull-up module is connected to an enable trigger terminal and a pull-up node, and is used to load a high-potential voltage provided by the enable trigger terminal to a first control node under the control of the enable trigger signal provided by the enable trigger terminal; the first pull-down module is connected to the pull-up node, the pull-down node, and the low-voltage power supply terminal, and is used to pull the voltage of the pull-up node down to a low potential when the pull-down node is at a high level; the output module is connected to the pull-up node, the clock signal input terminal, and the scan line. The scanning signal output terminal is used to output the clock signal provided by the clock signal input terminal as the scanning signal when the voltage of the pull-up node is high. The second pull-down module is connected to the pull-down node, the scanning signal output terminal, and the low-voltage power supply terminal, and is used to control the scanning signal output terminal to stop outputting the scanning signal when the pull-down node is high. The compensation module is connected to the clock signal input terminal, the pull-up node, the compensation control terminal, and the scanning signal output terminal. The compensation module is used to compensate the voltage adjustment of the scanning signal output terminal under the compensation control signal provided by the compensation control terminal during the scanning signal output period. The compensation control terminal is connected to the timing control circuit, and the timing control circuit outputs the compensation control signal according to the sampling signal. Compared to existing technologies, in this embodiment, when the display panel performs partitioned scanning to display images at different refresh rates, the partitioned scanning compensation circuit adjusts and compensates the scanning signal in real time during the initialization period after the display panel is powered on. That is, the scanning signal is adjusted and compensated before the actual image display, so that the pixel units of each partition can be accurately charged and receive data signals to perform image display. Attached Figure Description

[0014] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0015] Figure 1 This is a schematic diagram of the structure of a display device provided in an embodiment of this application; Figure 2 for Figure 1 The diagram shows the functional modules of the display device. Figure 3 for Figure 2 The diagram shows the planar layout structure of the display panel. Figure 4 As shown in one embodiment of this application Figure 3 The equivalent circuit diagram for any one of the sub-pixels is shown below. Figure 5 for Figures 1-2 The diagram shown illustrates the image display process performed by the display panel. Figure 6 for Figure 5 The diagram shows the partitioning of the display panel. Figure 7 For example Figure 5 The diagram shown is an example of a specific partition of the display panel. Figure 8 like Figure 7 A schematic diagram of the driving waveforms of the scanning signals for multiple partitions is shown. Figure 9 for Figure 6 The image shown is a screenshot of the display panel's partitioned image display effect. Figure 10 This is a schematic diagram of the partition scan compensation circuit structure of the display panel in the first embodiment of this application; Figure 11 This is a schematic diagram showing the connection method between the switching transistor and the display partition; Figure 12 This is a schematic diagram of the connection method between the switching transistor and the display partition in a modified embodiment of this application; Figure 13 For example Figure 10 A schematic diagram of the internal structure of the shift register shown. Figure 14 This is a schematic diagram of the circuit structure of the signal conversion circuit in the second embodiment of this application; Figure 15 for Figure 14 The timing diagram of the integrator circuit and the conversion sampling circuit is shown below; Figure 16 A schematic diagram of the waveform of the digital pulse width signal obtained for scanning signals corresponding to different refresh rates; Figure 17 For example Figure 3 The diagram shows the circuit structure of the timing control circuit adjusting the output voltage of the level conversion circuit. Figure 18 This is a schematic diagram of the clock signal and scan signal waveforms; Figure 19 This is a functional block diagram of the scan drive circuit in the third embodiment of this application; Figure 20 for Figure 19 The circuit structure diagram of the scanning drive unit is shown. Figure 21 for Figure 20 The diagram shows the waveform of the scan signal output by the scan drive circuit. Figure 22 As in another embodiment of this application Figure 20 The diagram shows the waveform of the scan signal output by the scan drive circuit. Figure 23 This is a schematic diagram of the functional structure of the timing control circuit in the fourth embodiment of this application; Figure 24 This is a schematic diagram showing the grayscale and brightness curves under different high-level voltages. Figure 25 Here is a flowchart of the partition scan compensation circuit. Figure 26 A graphical illustration of obtaining sampled signals for partial scan line detection during the display time of one frame of an image.

[0016] Explanation of reference numerals in the attached figures: Display device-1, display panel-10, bezel-FR, first circuit board-31, second circuit board-32, display area-10a, non-display area-10b, data lines-D1~Dm, scan lines-G1~Gn, first direction-F1, second direction-F2, timing control circuit-11, data driving circuit-12, scan driving circuit-13, pixel unit-P, i-th scan line-Gi, j-th data line-Sj, data signal-Data, liquid crystal capacitor-Clc, storage capacitor-Cst, transistor-T, pixel electrode-IT, common electrode-Vcom, first partition-AA1, second partition-AA2, third partition-AA3, time period-t1~t3, partition scan compensation Circuit-100, Detection Switching Circuit-101, Voltage Divider Circuit-102, Signal Conversion Circuit-103, Conversion Sampling Circuit-104, Switching Transistor-Tt, Gate-Gt, Source-St, Drain-Dt, Test Switching Signal-ENs, Switching Sensing Connection Line-Ls, First Voltage Divider Resistor-R1, Second Voltage Divider Resistor-R2, Voltage Divider Input-1021, Voltage Divider Output-1022, Conversion Input-1031, Reference Control-1032, Conversion Output-1033, Comparator-CP, Non-Inverting Input-IN1, Inverting Input-IN2, Comparator Output-Vo, Reference Voltage-Vref, Digital Pulse Width Signal-Sv, Shift Register-1041, Microcontroller- 1042, Analog-to-Digital Converter - 1043, Operational Amplifier - OP, Unidirectional Control Circuit - SC, Integrator Circuit - IL, Control Circuit - CC, Non-Inverting Input - OP1, Inverting Input - OP2, Operational Output - Po, Diode - D1, Integrating Resistor - RI, Holding Capacitor - Ch, First Control Switch - Q1, Second Control Switch - Q2, Voltage Supply Circuit - Pr, Boost Control Circuit - 21, Adjusting Switch M1, Adjusting Diode - D2, Filter Circuit - 22, Feedback Circuit - 23, Voltage Source - Ps, Energy Storage Inductor - L1, Wave Resistor - RL, Filter Capacitor - CL, Boost Control Circuit - 21, Pulse Width Signal Output - P1, Feedback Input - FB, First Feedback Circuit Resistor-Rf1, Second Feedback Resistor-Rf2, Digital-to-Analog Converter Circuit-DA, Pulse Width Signal-PWM, Sampled Data-Ss, Scan Drive Unit-GOA, Pull-up Module-301, Pull-up Node-PU, First Pull-down Module-302, Pull-down Node-PD, Output Module-303, Second Pull-down Module-304, Compensation Module-305, Enable Trigger Terminal-En, Compensation Control Terminal-Vcomp, Clock Signal Input Terminal-CLK, Clock Signal-CK, First Switch-T1, Second Switch-T2, Third Switch-T3, Fourth Switch-T4, Fifth Switch-T5, Sixth Switch-T6, Energy Storage Capacitor-Cc, Compensation Table-LUT, Steps-1000~3000. Detailed Implementation

[0017] Please see Figure 1 , Figure 1 This is a schematic diagram of the structure of a display device provided in one embodiment of this application.

[0018] like Figure 1 As shown, the display device 1 includes a display panel 10 and a frame FR. The display panel 10 is fixed within the frame FR, and the frame FR provides fixation and support for the display panel 10. In other embodiments of this application, when the display device 1 is a portable electronic device, such as a mobile phone or tablet computer, it is used.

[0019] Please see Figure 2 , Figure 2 for Figure 1 The diagram shows a functional module of display device 1. Figure 2 As shown, the display device 1 includes a display panel 10, a first circuit board 31, and a second circuit board 32.

[0020] The first circuit board 31 is electrically connected to the display panel 10 and the second circuit board 32. The first circuit board 31 and the display panel 10 can be connected by flexible conductive wires or flexible conductive films, so that the first circuit board 31 can rotate or be fixed to the display panel 10 relative to the display panel 10. Correspondingly, the first circuit board 31 and the second circuit board 32 are also connected by flexible wires, so that the second circuit board 32 can rotate around the first circuit board 31 and be fixed to the display panel 10.

[0021] In this embodiment, the first circuit board 31 is a driver circuit board (X). board), the second circuit board 32 is the control circuit board (C board). The first circuit board 31 and the second circuit board 32 can each be a separate drive circuit board (X). board) or control circuit board (C (Board) can also be integrated onto the same circuit board.

[0022] The second circuit board 32 serves as the control circuit board (C) The second circuit board 32 mainly includes a power management circuit 300 (PMIC) and a timing control circuit 11 (TCON). The second circuit board 32 is mainly used to receive display signals for image display provided externally by the display panel 10, and output data signals, control signals and power signals accordingly.

[0023] The first circuit board 31 serves as the driving circuit board (X) The first circuit board 31 (PCB) is mainly used to receive data signals and control signals provided by the first circuit board 31 and transmit them to multiple data driver chips (data driver circuits). In this embodiment, the first circuit board 31 includes a memory (not shown). The first circuit board 31 is connected to the display panel 10 via a chip-on-flex (COF) film, on which data driver chips are disposed. The data driver chips communicate via data lines (…). Figure 3 ) and pixel unit P ( Figure 3 ( ) connection to transmit data signals to pixel unit P for image display.

[0024] Please refer to the following: Figure 2 and Figure 3 , Figure 3 For example Figure 2 The diagram shows a planar layout of the display panel 10. Figure 3 As shown, the display area 10a of the display panel 10 includes multiple pixel units P arranged in an m×n matrix, m data lines D1~Dm, and n scan lines G1~Gn, where m and n are natural numbers greater than 1. The n scan lines G1~Gn extend along a first direction F1 and are mutually insulated and parallel along a second direction F2. The m data lines D1~Dm extend along the second direction F2 and are mutually insulated and parallel along the first direction F1. The first direction F1 and the second direction F2 are perpendicular to each other.

[0025] Corresponding to the non-display area 10b of the display panel 10, the display device 1 further includes a timing control circuit 11 for driving the pixel unit P to display images, a data driving circuit 12, and a scan driving circuit 13 disposed in the display panel 10.

[0026] The timing control circuit 11 is electrically connected to the data driving circuit 12 and the scan driving circuit 13. It is used to control the working timing of the data driving circuit 12 and the scan driving circuit 13, that is, to output the corresponding timing control signal to the data driving circuit 12 and the scan driving circuit 13, so as to control when the scan driving circuit 13 outputs the corresponding scan signal and when the data driving circuit 12 outputs the corresponding data signal.

[0027] The data driving circuit 12 is electrically connected to the m data lines D1~Dm and is used to transmit the data signal (Data) to be displayed to multiple pixel units P in the form of data voltage through the m data lines D1~Dm.

[0028] The scan driving circuit 13 is electrically connected to the n scan lines G1~Gn, and is used to output scan signals Scan to pixel unit P through the n scan lines G1~Gn to control when pixel unit P receives data signals Data. Specifically, the scan driving circuit 13 outputs scan signals Scan from the n scan lines G1~Gn in sequence according to their positional arrangement and in accordance with the scan cycle from scan lines G1, G2, ..., Gn.

[0029] In this embodiment, the display panel 10 in the display device 1 is a liquid crystal display panel, that is, the display medium in the pixel unit P is liquid crystal molecules.

[0030] Please see Figure 4 , Figure 4 for Figure 3 The diagram shows the equivalent circuit diagram for any pixel unit P. Figure 4 As shown, pixel unit P is any pixel unit arranged in the array in display panel 10. Pixel unit P includes transistor T, liquid crystal capacitor Clc, and storage capacitor Cst. The gate of transistor T is connected to the i-th scan line Gi, used to control transistor T to be turned on or off. The source of transistor T is connected to the j-th data line Dj, and the drain of transistor T is connected to the pixel electrode IT, so that under the control of the i-th scan line Gi, transistor T receives data signals from the j-th data line Dj and transmits them to the pixel electrode IT. i is a positive integer less than or equal to n, and j is a positive integer less than or equal to m.

[0031] It can be understood that the liquid crystal capacitor Clc is formed by the pixel electrode IT, the liquid crystal molecules that serve as the display medium, and the common electrode Vcom. The liquid crystal capacitor Clc and the storage capacitor Cst are connected in parallel. The storage capacitor Cst is used to maintain the electric field of the liquid crystal capacitor Clc between the pixel electrode IT and the common electrode Vcom before the next data signal Data is loaded.

[0032] Please see Figures 5-6 , Figure 5 for Figures 1-2 The diagram shown illustrates the image display process performed by the display panel. Figure 6 for Figure 5 The diagram shows the partitioning of the display panel.

[0033] Along the direction of data signal transmission, that is, along the second direction F2, the display panel 10 includes a first partition AA1, a second partition AA2, and a third partition AA3 in the display area 10a. Within the same frame of image display time, the refresh rates of corresponding pixel units P in the first partition AA1, the second partition AA2, and the third partition AA3 are different.

[0034] Specifically, the pixel unit P in the first partition AA1 operates at a first refresh rate of r1, the pixel unit P in the second partition AA2 operates at a second refresh rate of r2, and the pixel unit P in the third partition AA3 operates at a third refresh rate of r3. Where r1 = r2, and r1 < r2. For example, r1 and r2 are 10Hz to accommodate low-frequency image displays, and r2 is 240Hz to accommodate high-frequency image displays. Of course, in other embodiments, r1 and r2 are 60Hz, and r2 could also be 120Hz, and this is not a limited example.

[0035] By using different refresh rates for the corresponding pixel units P in the first partition AA1, the second partition AA2, and the third partition AA3, different areas of the display panel 10 achieve different refresh frequencies, thus realizing the partition frequency function. This is to adapt to the situation where some images in a frame are in a relatively static display state, while others are in a highly dynamic display state. For example, in a game interface, game characters need to be displayed in a highly dynamic state, while some labels and prompts are displayed in a more static state.

[0036] like Figure 6 As shown, the first partition AA1, the second partition AA2, and the third partition AA3 are... Figure 3 The scan line correspondence shown can be as follows: the first partition AA1 can correspond to scan lines G1~Gx, the second partition AA2 can correspond to scan lines Gx+1~Gy, and the third partition AA3 can correspond to scan lines Gy+1~Gn, where x and y are positive integers less than n, and y is greater than x. For example, if x is 200 and y is 1000, then the first partition AA1 can correspond to scan lines G1~G200, the second partition AA2 can correspond to scan lines G200~G1000, and the third partition AA3 can correspond to scan lines G1001~G1200. Of course, in other embodiments, the specific values ​​of x and y corresponding to partitions AA1~AA3 and scan lines can be adjusted according to the different number of scan lines set for different resolutions in the display panel 10 or the position of the dynamic image display area and the static image display area in the specific display interface, and are not limited to this example.

[0037] In this embodiment, for ease of explanation and understanding, such as Figure 7 As shown, the first partition AA1 corresponds to scan line G1, the second partition AA2 corresponds to scan lines G2~G3, and the third partition AA3 corresponds to scan lines G4~G6. Among these, Figure 7 For example Figure 5 The diagram shown illustrates an exemplary partition of the display panel.

[0038] Please see Figure 8 , its like Figure 7 The diagram shows the driving waveforms of the scan signals for multiple partitions. Figure 8 As shown, when the display panel 10 displays an image, the scan signals Gate1, Gate4~Gate6 output by the scan lines G1 corresponding to the first partition AA1 and the third partition AA3 are approximately square wave signals with a scan period of 1H, and their rising and falling edges are steep. The scan signals Gate2~G3 output by the scan lines G2~G3 corresponding to the second partition AA2 are pulse signals with a scan period of 1H, and their rising and falling edges are relatively slow.

[0039] like Figure 9 As shown, due to different refresh rates, the difference in the scanning signal gate corresponding to different zones will affect the on / off time of the pixel unit P in the corresponding zone, that is, it will affect the charging time of the pixel unit. For example, zone refresh will cause the scanning signal frequency corresponding to different zones of the panel to be different, which will lead to inconsistent offset of the transistors included in the pixel unit P in different zones, especially leakage current Ion. This will cause the output capability of the scanning signal gate corresponding to the high refresh rate area to decrease, resulting in different grayscale brightness of the image displayed in the high refresh rate and low refresh rate zones. Figure 9 As shown, a fairly obvious dividing line is present, resulting in poor image display quality on the display panel 10. Among these, Figure 9 for Figure 6 The image shown is a screenshot of the display panel's partitioned display effect.

[0040] To address the issue of uneven grayscale brightness that occurs when the display panel 10 performs partitioned scanning display of images at different refresh rates, real-time adjustment and compensation of the scanning signal are required to ensure that the pixel units P in each partition can be accurately charged and receive data signals to perform image display. Accordingly, this application provides a partitioned scanning compensation circuit for compensating scanning signals when the display panel 10 performs partitioned display, used to compensate for scanning signals of different frequencies.

[0041] Please see Figure 10 , Figure 10 This is a schematic diagram of the partition scan compensation circuit structure of the display panel in the first embodiment of this application.

[0042] like Figure 10 As shown, the partitioned scan compensation circuit 100 is connected to at least a portion of the scan lines and the timing control circuit 11. It is used to detect the scan signal transmitted on the scan line during non-image display periods and feed it back to the timing control circuit 11. The timing control circuit 11 determines the compensation signal for the scan signal based on the voltage magnitude of the scan signal, so as to directly control the scan drive circuit 13 to adjust the output scan signal magnitude, or adjust the high level VGH and low level VGL output by the level conversion circuit 15 to the scan drive circuit 13 through the timing control circuit 11, thereby adjusting the output scan signal.

[0043] The partitioned scanning compensation circuit 100 includes a detection switching circuit 101, a voltage divider circuit 102, a signal conversion circuit 103, and a conversion sampling circuit 104.

[0044] The detection switching circuit 101 is connected to the timing control circuit 11 and at least a portion of the scan lines, and is also connected to the voltage divider circuit 102 via the detection sensing line Ls. The detection switching circuit 101 is used to connect at least a portion of the scan lines to the voltage divider circuit 102 during non-display periods, so that the scan signal output by the scan drive circuit 13 can be transmitted to the voltage divider circuit 102 for voltage division detection. In this embodiment, the non-display period can be the initialization phase after the display panel 10 is powered on and before the image is officially displayed.

[0045] In this embodiment, at least some scan lines can be at least two scan lines, and the two scan lines correspond to scan lines that transmit scan signals of different frequencies in different refresh rate partitions.

[0046] The voltage divider circuit 102 is connected to the detection switching circuit 101 and the signal conversion circuit 103. It is used to divide the voltage of the scanning signal transmitted on the scanning line by a preset ratio and perform level conversion so as to adapt to the comparison and conversion of subsequent signals.

[0047] In this embodiment, the high level VGH of the scanning signal Gate is 25V and the low level is -6V. The voltage is reduced by scaling the scanning signal Gate by a preset ratio through the voltage divider circuit 102, for example, the preset ratio is 10:1, thereby obtaining a voltage divider signal of -0.6V to 2.5V. The dynamic range of the scanning signal Gate is adapted to the low-voltage operating range of the subsequent signal conversion circuit 103 and conversion sampling circuit 104 for comparison and conversion, so as to effectively ensure that the subsequent circuits operate within a safe voltage range and at the same time ensure the accuracy of the signal.

[0048] The signal conversion circuit 103 is connected to the voltage divider circuit 102 and the conversion sampling circuit 104. The signal conversion circuit 103 is used to convert the time information of the scan signal Gate exceeding the reference threshold Ref after the voltage reduction into a digital pulse width signal Sv, thereby quantifying the steepness of the rising edge of the scan signal Gate.

[0049] For example, when the voltage of the stepped-down scan signal Gate is greater than the reference threshold Ref, the digital pulse width signal Sv is at a high level; when the voltage of the stepped-down scan signal Gate is less than the reference threshold Ref, the digital pulse width signal Sv is at a low level, which is equivalent to determining the steepness of the rising edge of the scan signal Gate.

[0050] The conversion sampling circuit 104 is connected to the signal conversion circuit 103 and the timing control circuit 11. It is used to sample and store the pulse width of the digital pulse width signal Sv at high speed under the sampling clock signal CKs provided by the timing control circuit 11 within one cycle of the scanning signal Gate, forming a digital feature code that quantifies the degree of waveform variation. After completing one cycle of sampling, a digital signal of a preset number of bits is obtained to form a sampling signal corresponding to the waveform of the scanning signal Gate. Simultaneously, the sampling signal is fed back to the timing control circuit 11. In this embodiment, the sampling signal can be a 6-bit digital signal.

[0051] The conversion sampling circuit 104 can be connected to the timing control circuit 11 via the I²C bus, and the sampling signal can be transmitted to the timing control circuit 11 via the I²C bus.

[0052] The timing control circuit 11 determines the magnitude of the high level VGH and low level VGL output by the adjustment control level conversion circuit 14 based on the acquired signal, and / or adjusts the scanning drive circuit 13 to compensate for the voltage magnitude of the scanning output signal, thereby compensating for and adjusting the scanning signals of different partitions, so that the pixel unit P of the corresponding partition can accurately charge and load the data signal Data.

[0053] For more details, please refer to [link / reference]. Figure 10 : The detection switching circuit 101 includes at least one switching transistor Tt, which is connected to the timing control circuit 11, the scan line, and the voltage divider circuit 102. The switching transistor Tt receives the test switching signal ENs output by the timing control circuit 11 and selectively turns on or off under the control of the test switching signal ENs. When the switching transistor Tt is on, the scan line and the voltage divider circuit 102 are electrically connected, thereby allowing the scan signal output by the scan drive circuit 13 to be transmitted to the voltage divider circuit 102. When the switching transistor Tt is off, the scan line and the voltage divider circuit 102 are electrically disconnected, thereby allowing the scan signal output by the scan drive circuit 13 to be transmitted to the corresponding pixel unit P, turning on the pixel unit P to receive the data signal Data from the data line.

[0054] In this embodiment, the switching transistor Tt can be an N-type or P-type thin-film transistor or field-effect transistor, including a gate Gt, a source St, and a drain Dt. The gate Gt is connected to one of the control signal input / output terminals of the timing control circuit 11 to receive the test switching signal ENs. The source St is connected to the voltage divider circuit 102 through the switching sensing connection line Ls, and the drain Dt is connected to the scan line Gk.

[0055] When it is necessary to perform sensing and recognition compensation for the scan signals in each partition, when the switching transistor Tt is turned on under the control of the test switching signal ENs, the drain Dt and the source St are electrically connected, so that the scan line Gx is connected to the voltage divider circuit 102 through the switching sensing connection line Ls.

[0056] When the scan signals in each partition need to be loaded into the corresponding pixel unit P for image display, the switching transistor Tt is turned off under the control of the test switching signal ENs, and the drain Dt and source St are electrically disconnected, so that the scan line Gx is electrically disconnected from the switching sensing connection line Ls, and the scan signal is accurately transmitted to the pixel unit P through the scan line Gx.

[0057] In this embodiment, when the switching transistor Tt is an N-type thin-film transistor or a field-effect transistor, Tt is turned on when the test switching signal ENs is high, and turned off when ENs is low. In other embodiments of this application, when the switching transistor Tt is a P-type thin-film transistor or a field-effect transistor, Tt is turned on when the test switching signal ENs is low, and turned off when ENs is high.

[0058] Please continue to refer to this as well. Figure 10 and Figure 11 , Figure 11 This is to switch the connection method between the switching transistor Tt and the display partition.

[0059] like Figure 11 As shown, when the refresh rates corresponding to the first partition AA1, the second partition AA2 and the third partition AA3 are all fixed, the scan line that is arranged at the last position along the data signal transmission direction (the negative direction of the second direction F2) in each partition is taken as the scan line for detecting the scan signal of that partition.

[0060] For example, in the first partition AA1, Gx of scan lines G1~Gx is connected to the switching transistor Tt1 in the detection switching circuit 101; in the second partition AA2, Gy of scan lines Gx+1~Gy is connected to the switching transistor Tt2 in the detection switching circuit 101; and in the third partition AA3, Gn of scan lines Gy+1~Gn is connected to the switching transistor Tt3 in the detection switching circuit 101. In this embodiment, the number of switching transistors Tt is the same as the number of partitions in the display panel 10, that is, for each of the three partitions, the detection switching circuit 101 includes three switching transistors Tt.

[0061] For details that may be changed, please refer to the following: Figure 10 and Figure 12 , Figure 12 This is a modified embodiment of the present application showing the connection method between the switching transistor Tt and the display partition.

[0062] like Figure 12 As shown, since the refresh rates corresponding to the first partition AA1, the second partition AA2 and the third partition AA3 are not fixed, in order to ensure the accuracy of the scanning signal detection in each partition, each scanning line is connected to the voltage divider circuit 102 through a switching transistor Tt1 in the detection switching circuit 101.

[0063] For example, in the first partition AA1 to the third partition AA3, each scan line G1 to Gn is connected to the voltage divider circuit 102 through a switching transistor Tt. Specifically, scan line G1 is connected to switching transistor Tt1 in the detection switching circuit 101, scan line G2 is connected to switching transistor Tt2 in the detection switching circuit 101, scan line G3 is connected to switching transistor Tt3 in the detection switching circuit 101, and so on, with scan line Gn connected to switching transistor Ttn in the detection switching circuit 101. In this embodiment, the number of switching transistors Tt is the same as the number of scan lines in the display panel 10, that is, n scanning lines in the three partitions are connected to n switching transistors Tt in the switching circuit 101.

[0064] It is understood that in other embodiments of this application, the display panel 10 may include two partitions with different refresh rates, such as the first partition AA1 and the second partition AA2, or the second partition AA2 and the third partition AA3, and the number of switching transistors is adjusted accordingly.

[0065] Please continue reading. Figure 10 ,like Figure 10 As shown, the voltage divider circuit 102 includes two voltage divider resistors connected in series, a first voltage divider resistor R1 and a second voltage divider resistor R2, which are used to divide the voltage of the scan signal transmitted on the scan line by a preset ratio and perform level conversion.

[0066] The voltage divider circuit 102 includes a voltage divider input terminal 1021 and a voltage divider output terminal 1022. The voltage divider input terminal 1021 is connected to the source of the switching transistor Tt1 in the detection switching circuit 101 through the scanning detection line Ls. The voltage divider output terminal 1022 is connected to the signal conversion circuit 103. The first voltage divider resistor R1 and the second voltage divider resistor R2 are connected in series between the voltage divider input terminal 1021 and the ground terminal GND. Any node between the first voltage divider resistor R1 and the second voltage divider resistor R2 serves as the voltage divider output terminal 1022. In other words, the voltage divider output terminal 1022 is connected to any node between the first voltage divider resistor R1 and the second voltage divider resistor R2.

[0067] It is understood that the number of voltage divider resistors included in the voltage divider circuit 102 can be set according to actual needs, and the resistance value of the voltage divider resistors can also be set according to the preset ratio required during voltage conversion.

[0068] In this embodiment, both the first voltage divider resistor R1 and the second voltage divider resistor R2 are high-precision, low-temperature-drift resistors. For example, if the high and low levels of the scanning signal Gate are 25V and –6V respectively, the first voltage divider resistor R1 and the second voltage divider resistor R2 are divided in a preset ratio of 10:1 to obtain a voltage of -0.6V to 2.5V, which is then output from the voltage divider output terminal 1022 to the signal conversion circuit 103. The dynamic range of the -0.6V to 2.5V voltage signal can be adapted to the low-voltage operating range of the signal conversion circuit 103 and the conversion sampling circuit 104. As a voltage divider network, the voltage divider circuit 102 can effectively ensure that the signal conversion circuit 103 operates within a safe voltage range, while ensuring that the signal slope and dynamic characteristics are maintained.

[0069] The signal conversion circuit 103 includes a conversion input terminal 1031, a reference control terminal 1032, and a conversion output terminal 1033. The conversion input terminal 1031 is connected to the voltage divider output terminal 1022 of the voltage divider circuit 102, and is used to receive the detection voltage divider signal after the scan signal Gate has undergone voltage division processing according to a preset ratio. The reference control terminal 1032 is used to receive a reference signal or a control signal to determine the relative magnitude of the detection voltage divider signal and the reference threshold Ref. In this embodiment, the reference control terminal 1032 is connected to the timing control circuit 11, which provides a control signal or a reference voltage Vref as the reference signal. The conversion output terminal 1033 is connected to the conversion sampling circuit 104. The signal conversion circuit 103 converts the time information of the stepped-down scan signal Gate exceeding the reference threshold Ref into a digital pulse width signal Sv and outputs it to the conversion output terminal 1033.

[0070] Specifically, in this embodiment, the signal conversion circuit 103 includes a comparator CP, which includes a non-inverting input IN1, an inverting input IN2, and a comparison output Vo. The non-inverting input IN1 is connected to the voltage divider output 1022, and the inverting input IN2 receives a reference voltage Vref, which can be provided by the timing control circuit 11 or by an independent high-precision reference voltage source. The comparison output Vo is connected to the conversion output 1033 and is used to output a digital pulse width signal Sv. The received reference voltage Vref corresponds to the reference threshold Ref.

[0071] The comparator CP is used to convert the time information of the voltage divider detection signal of the corresponding scan signal Gate being greater than the reference threshold Ref into a digital pulse width signal Sv, thereby quantifying the steepness of the rising edge of the Gate waveform.

[0072] For example, when the voltage at the non-inverting input IN1 is higher than the reference threshold Ref at the inverting input IN2, the digital pulse width signal Sv at the comparator CP's comparison output Vo is high; when the non-inverting input voltage IN1 is less than the reference threshold Ref at the inverting input IN2, the digital pulse width signal Sv at the comparator CP's comparison output Vo is low. In this embodiment, the comparator CP is equivalent to determining whether the rising edge and peak value of the scan signal Gate waveform reach the reference threshold Ref. In this embodiment, the comparator CP can be an integrated high-speed comparator.

[0073] The conversion sampling circuit 104 is used to sample the digital pulse width signal Sv according to the sampling clock signal CKs provided by the timing control circuit 11, so as to obtain the sampling signal Ss corresponding to the preset bit digital pulse signal Sv after one cycle of sampling, and at the same time, the sampling signal Ss is fed back to the timing control circuit 11. In this embodiment, the sampling signal Ss can be a 6-bit digital signal.

[0074] The conversion sampling circuit 104 includes a shift register 1041 and a microcontroller 1042 (MCU). The shift register 1041 is an N-bit serial shift register. In this embodiment, N is 6.

[0075] The shift register 1041 receives the digital pulse width signal Sv output from the comparison output Vo of the comparator CP as data input, and receives the sampling clock signal CKs (Sampling Clock) from the timing control circuit 11 as the shift sampling clock to sample the digital pulse width signal Sv to form the sampling signal Ss.

[0076] The shift register 1041 includes a shift input terminal SR1 and multiple shift output terminals SR2. In this embodiment, there are six shift output terminals SR2. The shift input terminal SR1 is connected to the conversion output terminal 1033 to receive the digital pulse width signal Sv output from the comparison output terminal Vo. The multiple shift output terminals SR2 are connected to the microcontroller 1042.

[0077] In this embodiment, as Figure 13 As shown, it is as follows Figure 10 The diagram shows the internal structure of the shift register. Figure 13As shown, the shift register 1041 may include seven edge-triggered D flip-flops connected in series. Six of these edge-triggered D flip-flops are used to sample the digital pulse width signal Sv according to the sampling clock signal CKs and output a sampled signal Ss. Each edge-triggered D flip-flop corresponds to a shift output terminal SR2. Thus, for each rising or falling edge of the sampling clock signal CKs, one edge-triggered D flip-flop outputs a 1-bit digital signal based on the digital pulse width signal Sv. Within the signal period of a scan signal Gate, for example, within 1H, the shift register 1041 samples at high speed according to the sampling clock signal CKs to form a 6-bit sampled signal Ss. For example, if the digital pulse width signal Sv is high for all 1H, the 6-bit sampled signal Ss can be 111111. If the digital pulse width signal Sv is low for the first sampling clock signal CKs period within 1H, and high for the rest, the 6-bit sampled signal Ss can be 111110, and so on. The sampled signal Ss corresponds to the digital pulse width signal Sv of the scan signal Gate in digital form.

[0078] The microcontroller 1042 is connected to the shift register 1041 through multiple shift output terminals SR2 to receive the sampled signal Ss. The microcontroller 1042 is also connected to the timing controller 11 through the I²C bus to transmit the sampled signal Ss to the timing controller 11 for analysis and processing to facilitate compensation of the scan signal Gate.

[0079] In other embodiments of this application, the microcontroller 1042 may also be disposed inside the timing control circuit 11. In other words, if the timing control circuit 11 itself contains a microcontroller, the conversion sampling circuit 104 can directly share the microcontroller inside the timing control circuit 11 without having to be separately disposed, thereby simplifying the circuit structure of the conversion sampling circuit 104.

[0080] Please see Figure 14 This is a schematic diagram of the circuit structure of the signal conversion circuit 103 in the second embodiment of this application. In this embodiment, Figure 14 and Figure 10 The other circuits, connections, and operating modes shown are all the same; the only difference is the circuit structure of the signal conversion circuit 103 and the conversion sampling circuit 104.

[0081] Specifically, the signal conversion circuit 103 includes an operational amplifier OP, a unidirectional control circuit SC, an integrator circuit IL, and a control circuit CC.

[0082] Operational amplifier OP is connected to conversion input terminal 1031 and unidirectional control circuit SC to form a voltage follower for the detection voltage divider signal after voltage division processing of scan signal Gate according to a preset ratio. The integrator circuit IL provides low impedance drive and forms high impedance isolation for the detection voltage divider signal after voltage division processing of scan signal Gate according to a preset ratio.

[0083] Specifically, the operational amplifier OP includes a non-inverting input terminal OP1, an inverting input terminal OP2, and an operational output terminal Po. The non-inverting input terminal OP1 is connected to the voltage divider output terminal 1022, and the inverting input terminal OP2 is directly connected to the operational output terminal Po. The operational output terminal Po is connected to a unidirectional control circuit SC, which is used to output the op-amp follower signal formed by the isolated follower detection voltage divider signal.

[0084] A unidirectional control circuit SC is connected to the operational amplifier OP and includes a diode D1. The anode of diode D1 is connected to the operational output terminal Po, and the cathode of diode D1 is connected to the integrator circuit IL. The unidirectional control circuit SC controls the unidirectional transmission of the op-amp follower signal output from the operational output terminal Po to the integrator circuit IL through its included diode D1, thereby preventing current in the integrator circuit IL from flowing back into the operational amplifier OP. In this embodiment, diode D1 is a diode with a small forward voltage drop to reduce the error when the subsequent integrator circuit integrates the op-amp follower signal.

[0085] The integrating circuit IL is connected to the unidirectional control circuit SC and is used to receive and perform voltage-time area integration on the op-amp follower signal. Specifically, the integrating circuit IL is an RC integrating and holding circuit, including an integrating resistor RI and a holding capacitor Ch. One end of the integrating resistor RI is connected to the cathode of diode D1, and the other end of the integrating resistor RI is connected to one end of the holding capacitor Ch. The other end of the holding capacitor Ch is connected to ground GND. Since diode D1 can prevent directional conduction, the voltage on the holding capacitor Ch is maintained for a preset time after integration. In this embodiment, the other end of the integrating resistor RI and one end of the holding capacitor Ch are also connected to the conversion output terminal 1033.

[0086] In one embodiment, the integrating resistor RI is 470Ω, the holding capacitor Ch is 10nF, and the RC time constant of the integrating circuit IL satisfies the following: during the effective conduction period of the scan signal Gate, that is, during the high level period when the scan signal Gate controls the pixel unit P to conduct, the integrated conversion output voltage ILo of the holding capacitor Ch is ensured to accurately reflect the voltage-time area of ​​the scan signal Gate as a digital pulse width signal, and will not reach saturation quickly.

[0087] The control circuit CC is connected to the integrator circuit IL and the conversion output terminal 1033. It is used to control the start and stop times of the integrator circuit IL integrating the op-amp follower signal, thereby controlling the accurate output of the integrator conversion output voltage ILo.

[0088] In this embodiment, the control circuit CC includes a first control switch Q1 and a second control switch Q2.

[0089] The first control switch Q1 is used to precisely control the charging end time of the integrating circuit IL. In this embodiment, the first control switch Q1 is a transistor, with its gate connected to the timing control circuit 11 to receive the first control signal Ct1, its drain connected to the anode of diode D1, and its source connected to ground GND. The first control switch Q1 is selectively turned on or off under the control of the first control signal Ct1.

[0090] For example, when the diode D1 is turned on under the control of the first control signal Ct1 at a high level, its drain and source are connected, thereby connecting the anode of the diode D1 to the ground terminal GND. This cuts off the integration circuit IL from receiving the op-amp follower signal and controlling its charging integration time. When the diode D1 is turned off under the control of the first control signal Ct1 at a low level, its drain and source are disconnected, causing the anode of the diode D1 to connect to the operational output terminal Po of the operational amplifier OP. The integration circuit IL then receives the op-amp follower signal.

[0091] The second control switch Q2 is used to precisely switch the output terminal 1033 to stop outputting the digital pulse width signal Sv. In this embodiment, the second control switch Q2 is a transistor, with its gate connected to the timing control circuit 11 to receive the second control signal Ct2, its drain connected to the conversion output terminal 1033, and its source connected to ground GND. The second control switch Q2 is selectively turned on or off under the control of the second control signal Ct2.

[0092] For example, when the second control signal Ct2 is high, its drain and source are connected, thus connecting the conversion output terminal 1033 to ground GND. This stops the conversion output terminal 1033 from outputting the digital pulse width signal, thereby controlling the sampling duration. Simultaneously, this resets the conversion output terminal 1033 and discharges the holding capacitor Ch in the integrator circuit IL, preparing the integrator circuit IL for the next integration. When the second control signal Ct2 is low, its drain and source are disconnected, causing the conversion output terminal 1033 to output the integrated conversion output voltage ILo of the integrator circuit IL as the digital pulse width signal Sv.

[0093] The conversion sampling circuit 104 includes an analog-to-digital converter 1043 and a microcontroller 1042 (MCU), that is, it converts... Figure 9 The shift register 1041 shown is replaced with an analog-to-digital converter 1043.

[0094] Specifically, the analog-to-digital converter 1043 performs sampling of the digital pulse width signal Sv and converts it into a sampled signal Ss in N-bit digital form.

[0095] In this embodiment, the analog-to-digital converter 1043 can be an 8-bit or 16-bit analog-to-digital converter (ADC). It samples the digital pulse width signal Sv according to the sampling clock signal CKs to form a sampling signal Ss, which is then transmitted to the microcontroller 1042.

[0096] Please refer to the following: Figure 14 and Figure 15 ,in, Figure 15 for Figure 14 The timing diagram of the integrator circuit IL and the conversion sampling circuit 104 is shown.

[0097] like Figure 15 As shown, for any scan line Gj, the scan signal Gate is received for one cycle (high level and low level). The working time of the integrator circuit IL includes three consecutive time periods from t1 to t3.

[0098] During the first time period t1, the test switching signal ENs controls the detection switching circuit 101 to transmit the scan signal Gate to the voltage divider circuit 102. The voltage signal on the detection sensing line Ls corresponds to the same high level as the scan signal Gate, which is also a high level for one cycle. The first control signal Ct1 and the second control signal Ct2 are at low levels. At this time, the holding capacitor Ch in the integrator circuit IL integrates the operational amplifier follower signal after being divided by the voltage divider circuit 101 and processed by the voltage follower, and forms the integral conversion output voltage ILo, which is output from the conversion output terminal 1033.

[0099] During the second time period t2, the scan signal Gate changes from high to low, the test switching signal ENs also changes to low, and the first control signal Ct1 jumps to high. The integrator circuit IL stops receiving the op-amp follower signal from the self-evaluation amplifier OP and stops performing integration conversion. Simultaneously, due to the unidirectional conduction of diode D1, the charge in the holding capacitor Ch is preserved, and the integration conversion output voltage ILo serves as the digital pulse width signal Sv, maintaining a stable output at the self-conversion output terminal 1033. In this embodiment, the period and duty cycle of the first control signal Ct1 are the same as those of the test switching signal ENs, but their phases differ by 180°, meaning the level signals of the first control signal Ct1 and the test switching signal ENs are opposite.

[0100] Meanwhile, part of the sampling clock signal CKs is located in the second time period t2, and the other part is located in the third time period t3. In this embodiment, the rising edge of the sampling clock signal CKs must be within the second time period t2. Within the second time period t2, the analog-to-digital converter 1043 (or the shift register 1041) samples the digital pulse width signal Sv according to the sampling clock signal CKs to obtain the sampling signal Ss.

[0101] During the third time period t3, the second control signal Ct2 changes from a low level to a high level, controlling the second control switch Q2 to turn on, thereby stopping the output of the digital pulse width signal Sv from the conversion output terminal 1033. This also resets the conversion output terminal 1033 and discharges the holding capacitor Ch in the integrator circuit IL, preparing the integrator circuit IL for the next integration.

[0102] In this embodiment, the duty cycle of the second control signal Ct2 is less than that of the first control signal Ct1, and the rising and falling edges of the second control signal Ct2 are located during the low-level period of the test switching signal ENs. Furthermore, the falling edge of the second control signal Ct2 must arrive before the rising edge of the next test switching signal ENs to ensure that the digital pulse width signal Sv is completely reset to zero before the arrival of the scan signal Gate in the next cycle.

[0103] Please see Figure 16 , Figure 16 This is a schematic diagram of the waveform of the digital pulse width signal Sv obtained for scanning signals corresponding to different refresh rates.

[0104] like Figure 16 As shown, for example, corresponding to three non-frequency scanning signals Gate1, Gate2, and Gate3, the obtained digital pulse width signals Sv1 to Sv3 are 1.885V, 1.702V, and 1.279V, respectively, and the pulse width time of digital pulse width signals Sv1 to Sv3 is significantly increased. It can be seen that in this embodiment, the partitioned scanning compensation circuit 100, through the cooperation of the detection switching circuit 101, the voltage divider circuit 102, and the signal conversion circuit 103, can accurately obtain the corresponding voltage, and then through subsequent sampling, the sampling signal Ss can be accurately obtained to accurately detect and identify the scanning signal Gate.

[0105] Please see Figure 17 , its like Figure 3 The diagram shows the circuit structure of the timing control circuit that adjusts the output voltage of the level conversion circuit.

[0106] like Figure 17 As shown, the voltage adjustment circuit 20 includes a voltage supply circuit Pr, a boost control circuit 21, an adjustment switch M1, an adjustment diode D2, a filter circuit 22, and a feedback circuit 23.

[0107] The voltage supply circuit Pr is used to provide a stable output supply voltage, including a voltage source Ps and an energy storage inductor L1. In this embodiment, the power supply circuit Pr is connected to the regulating switch M1 and the regulating diode D2, and is used to selectively transfer the supply voltage to the regulating diode D2 under the control of the regulating switch M1.

[0108] In this embodiment, the positive voltage terminal of the voltage source Ps is connected to one end of the energy storage inductor L1, the negative voltage terminal of the voltage source Ps is connected to the ground terminal GND, and the other end of the energy storage inductor L1 is connected to the adjustment diode D2.

[0109] Adjusting diode D2 is connected between filter circuit 22 and voltage output terminal Vout. Adjusting diode D2 controls the unidirectional transmission of the supply voltage provided by voltage supply circuit Pr to filter circuit 22 and voltage output terminal Vout, preventing the voltage at voltage output terminal Vout from flowing back into power supply circuit Pr. In this embodiment, the positive terminal of adjusting diode D2 is connected to the other end of energy storage inductor L1, and the negative terminal of adjusting diode D2 is connected to voltage output terminal Vout.

[0110] The filter circuit 22 includes a filter resistor RL and a filter capacitor CL. The filter resistor RL and the filter capacitor CL are connected in parallel between the voltage output terminal Vout and the ground terminal GND. They are used to filter the high level VGH output from the voltage output terminal Vout to eliminate noise in the high level VGH and ensure the stability of the high level.

[0111] The boost controller 21 includes a pulse width signal output terminal P1 and a feedback input terminal FB. The pulse width signal output terminal P1 is connected to the control adjustment switch M1, and the feedback input terminal FB is connected to the feedback circuit 23.

[0112] The boost control circuit 21 adjusts the duty cycle of the pulse width signal (PWM) output from the pulse width signal output terminal P1 based on the feedback voltage obtained from the feedback input terminal FB, thereby controlling the on-time of the switching transistor M1 and consequently controlling the magnitude of the high-level voltage VGH output from the voltage output terminal Vout. In this embodiment, the boost control circuit 21 is an integrated circuit, such as a standalone chip.

[0113] Feedback circuit 23 includes a first feedback resistor Rf1 and a second feedback resistor Rf2 connected in series between the voltage output terminal Vout and the ground terminal GND. Any node between the first feedback resistor Rf1 and the second feedback resistor Rf2 serves as the feedback output feed point Nfb of the feedback voltage. The feedback output feed point Nfb is connected to the feedback input terminal FB.

[0114] In this embodiment, the feedback output feed point Nfb is also connected to the timing control circuit 11 through the digital-to-analog converter circuit DA. The timing control circuit 11 determines the voltage of the feedback output feed point Nfb based on the sampling signal Ss output by the self-conversion sampling circuit 104, in conjunction with the first feedback resistor Rf1 and the second feedback resistor Rf2.

[0115] In this embodiment, the boost controller 21 detects and identifies the voltage of the feedback output feed point Nfb through the feedback input terminal FB, and adjusts the duty cycle of the pulse width signal PWM accordingly to adjust the voltage value of the high level VGH.

[0116] If the high-level voltage VGH is 24V, then the voltage at the feedback output feed point Nfb in the feedback circuit 23 can be expressed as: 24V = 1.2V × (1 + Rf1 / Rf2). Here, R1 and R2 represent the resistance values ​​of the first feedback resistor Rf1 and the second feedback resistor Rf2, respectively, and 1.2V is the high-precision low-temperature drift reference voltage generated internally by the boost integrated circuit 21, such as a bandgap reference voltage.

[0117] For example, Rf1 can be 190K and Rf2 can be 10K. The voltage at the feedback input point Nfb is obtained by dividing Rf1 / Rf2.

[0118] For the boost integrated circuit 21, when the voltage at the feedback input terminal FB is less than 1.2V, the duty cycle of the output pulse width signal PWM will be increased, correspondingly increasing the on-time of the switching transistor M1, thereby increasing the voltage value of the high level VGH; when the voltage at the feedback input terminal FB is greater than 1.2V, the duty cycle of the pulse width signal PWM will be decreased, correspondingly decreasing the on-time of the switching transistor M1, thereby decreasing the voltage value of the high level VGH.

[0119] In this embodiment, since the feedback input point Nfb is also connected to the digital-to-analog converter circuit DA controlled by the timing control circuit 11, the voltage of the feedback input terminal FB is controlled not only by the first feedback resistor Rf1 and the second feedback resistor Rf2, but also by the timing control circuit 11. For example, when the timing control circuit 11 controls the digital-to-analog converter circuit to form a dynamic adjustment module, the feedback input terminal FB is also controlled by the voltage output of the digital-to-analog converter circuit DA. Because the digital-to-analog converter circuit DA is directly connected to the timing control circuit 11 through the input / output interface (I / O interface), the data transmission speed is very fast, and it can achieve a microsecond (µs) level response, thereby improving the rate of high-level VGH and scan signal adjustment compensation.

[0120] The specific working process of voltage regulation circuit 20 is explained as follows: When a high-level voltage of 24V is required for VGH, or when the high-level voltage of VGH is controlled solely by the boost IC 21, the timing control circuit 11 controls the output voltage of the digital-to-analog converter (DA) to be equal to 1.2V. The boost IC 21 then controls the duty cycle of the pulse width signal (PWM) to a preset value, thereby ensuring that the high-level voltage of VGH is 24V. It can be understood that the preset duty cycle of the PWM corresponds to a high-level voltage of 24V for VGH.

[0121] When the required high-level voltage VGH is greater than 24V, the timing control circuit 11 controls the output voltage of the digital-to-analog converter circuit DA to be lower than 1.2V. Then, the voltage of the feedback input feed point Nfb is higher than the output voltage of the digital-to-analog converter circuit DA, and the current of the feedback input feed point Nfb will flow into the digital-to-analog converter circuit DA. As a result, the current flowing through the second feedback resistor Rf2 decreases, which leads to a decrease in the voltage of the feedback input terminal FB and slightly lower than 1.2V. As a result, the boost integrated circuit 21 will correspondingly increase the duty cycle of the pulse width signal PWM, thereby increasing the high-level voltage VGH.

[0122] When the required high-level voltage VGH is less than 24V, the timing control circuit 11 controls the output voltage of the digital-to-analog converter circuit DA to be higher than 1.2V. Then, the output voltage of the digital-to-analog converter circuit DA is higher than the voltage of the feedback input feed point Nfb. The current of the digital-to-analog converter circuit DA flows into the feedback input feed point Nfb, thereby increasing the current flowing through the second feedback resistor Rf2, which leads to an increase in the voltage of the feedback input terminal FB and slightly higher than 1.2V. As a result, the boost integrated circuit 21 will correspondingly reduce the duty cycle of the pulse width signal PWM, thereby making the high-level voltage VGH smaller.

[0123] Understandable, such as Figure 18 As shown, when the high level VGH increases, the voltage value of the corresponding clock signal CK increases accordingly, and thus the potential of the corresponding scan signal also increases, thereby compensating for the scan signal. The dashed line in the figure represents the voltage value before adjustment, and the solid line represents the voltage value after adjustment. Figure 18 This is a schematic diagram of the clock signal and the scan signal waveforms.

[0124] Please see Figure 19 and Figure 20 , Figure 19 This is a functional block diagram of the scan drive circuit in the third embodiment of this application. Figure 20 for Figure 16 The circuit structure diagram of the scanning drive unit is shown.

[0125] like Figure 19As shown, the scan drive circuit 13 includes multiple cascaded scan drive units (GOAs), which receive multiple clock signals (CK) and start signals (STV). Each cascaded scan drive unit (GOA) is connected to a corresponding scan line and outputs a corresponding scan drive signal. In this embodiment, the number of corresponding scan lines is the same as the number of scan drive units (GOAs).

[0126] like Figure 20 As shown, the scan drive unit GOA includes a pull-up module 301, a pull-up node PU, a first pull-down module 302, a pull-down node PD, an output module 303, a second pull-down module 304, and a compensation module 305.

[0127] The pull-up module 301 connects the enable trigger terminal En and the pull-up node PU. It is used to apply the high potential voltage provided by the enable trigger terminal En to the first control node PU under the control of the enable trigger signal provided by the enable trigger terminal En, thereby controlling the voltage of the first control node PU to be at a high potential.

[0128] The first pull-down module 302 is connected to the pull-up node PU, the pull-down node PD, and the low-voltage power supply terminal VGL. It is used to pull down the voltage of the pull-up node PU to a low potential when the pull-down node PD is at a high level.

[0129] The output module 303 is connected to the pull-up node PU, the clock signal input terminal CLK, and the scan signal output terminal Gout. It is used to output the clock signal CK provided by the clock signal input terminal CLK as the scan signal Gate when the voltage of the pull-up node PU is high, and to maintain the voltage of the pull-up node PU at a high potential for a preset period of time.

[0130] The second pull-down module 304 connects the pull-down node PD, the scan signal output terminal Gout, and the low-voltage power supply terminal VGL. It is used to pull down the voltage of the scan signal output terminal Gout to a low potential when the pull-down node PD is high, thereby causing the scan signal output terminal Gout to stop outputting the scan signal Gate.

[0131] The compensation module 305 is connected to the clock signal input terminal CLK, the pull-up node PU, the compensation control terminal Vcomp, and the scan signal output terminal Gout. The compensation module 305 is used to compensate the voltage of the scan signal output terminal Gout under the compensation control signal provided by the compensation control terminal Vcomp when the pull-up node PU is at a high potential, that is, during the output period of the scan signal Gate. In other words, it adjusts the potential of the compensation scan signal Gate.

[0132] More specifically, the pull-up module 301 includes a first switch T1, which can be a thin-film transistor (TFT). Its gate and drain are connected to the enable trigger terminal En, and its source is connected to the pull-up node PU. The first switch T1 is turned on under the control of the enable trigger signal En, and applies the high potential voltage provided by the enable trigger signal En to the pull-up node PU. Conversely, the first switch T1 is in the off state when the enable trigger signal En is low.

[0133] In this embodiment, the first switch T1 is an N-type thin-film transistor (TFT). In other embodiments of the application, the first switch T1 can also be a P-type thin-film transistor, in which case the corresponding enable trigger signal is low level.

[0134] The first pull-down module 302 includes a second switch T2, which can be a thin-film transistor. Its gate is connected to the pull-down node PD, its drain is connected to the pull-up node PU, and its source is connected to the low-voltage power supply terminal VGL. The low-voltage power supply terminal VGL provides a low potential. The second switch T2 is used to turn on or off under the control of the pull-down node PD, and when on, it pulls the voltage of the pull-up node PU down to a low potential.

[0135] In this embodiment, the second switch T2 is an N-type thin-film transistor (TFT). In other embodiments of the application, the second switch T2 may also be a P-type thin-film transistor.

[0136] The output module 303 includes a third switch T3 and an energy storage capacitor Cc. The third switch T3 is a transistor with its gate connected to the pull-up node PU, its drain connected to the clock signal input terminal CLK, and its source connected to the scan signal output terminal Gout. The third switch T3 is turned on when the pull-up node PU is at a high potential, thus using the high potential of the clock signal CK provided by the clock signal input terminal CLK as the scan signal Gate output. The third switch T3 is turned off when the pull-up node PU is at a low potential, thus stopping the output of the scan signal Gate. The energy storage capacitor Cc is connected between the pull-up node PU and the scan signal output terminal Gout. The energy storage capacitor Cc is used to maintain the voltage of the pull-up node PU at a high potential, ensuring that the scan signal output terminal Gout accurately outputs the scan signal Gate.

[0137] In this embodiment, the third switch T3 is an N-type thin-film transistor (TFT). In other embodiments of the application, the third switch T3 may also be a P-type thin-film transistor.

[0138] The second pull-down module 304 includes a fourth switch T4, which can be a thin-film transistor. Its gate is connected to the pull-down node PD, its drain is connected to the scan signal output terminal Gout, and its source is connected to the low-voltage power supply terminal VGL. The fourth switch T4 is used to turn on or off under the control of the pull-down node PD. When on, it pulls the voltage of the scan signal output terminal Gout down to a low potential, thereby stopping the output of the scan signal Gate.

[0139] In this embodiment, the fourth switch T4 is an N-type thin-film transistor (TFT). In other embodiments of the application, the fourth switch T4 may also be a P-type thin-film transistor.

[0140] The compensation module 305 includes a fifth switch T5 and a sixth switch T6.

[0141] The fifth switch T5 and the sixth switch T6 can be thin-film transistors. Their gates are connected to the compensation control terminal Vcomp, their drains are connected to the clock signal input terminal CLK, and their sources are connected to the drain of the sixth switch. The gate of the sixth switch T6 is connected to the pull-up node PU, and its source is connected to the scan signal output terminal Gout.

[0142] In this embodiment, the compensation control signal received by the compensation control terminal Vcomp is used to control the conduction level of the fifth switch T5. That is, the fifth switch T5 has different conduction levels and different on-resistances depending on the compensation control signal being in the variable resistance region. This controls the voltage applied to the scan signal output terminal Gout by the clock signal CK provided by the clock signal input terminal CLK, thereby achieving compensation and adjustment of the voltage of the scan signal Gate. In other words, the fifth switch T5 can be equivalent to a variable resistor. When the fifth switch T5 is fully turned on, it is equivalent to doubling the output capability of the scan signal Gate.

[0143] Please see Figure 21 , it is Figure 20 The diagram shows the waveform of the scan signal output by the scan drive circuit. Figure 21 As shown, the compensation control signal is a continuous high-level pulse signal. When the compensation module 305 compensates the scan drive signal Gate according to the compensation control signal, the potential of the compensated scan signal also increases accordingly, thereby compensating the scan signal.

[0144] In this embodiment, the compensation control signal can be a high-speed square wave signal with an adjustable duty cycle, thus allowing adjustment of the conduction state of the fifth switch T5 to different degrees, such as... Figure 22 As shown, when only a small amount of compensation is needed, reducing the duty cycle of the compensation control signal can reduce power consumption to some extent. Specifically, Figure 22 In another embodiment of this application Figure 20 The diagram shows the waveform of the scan signal output by the scan drive circuit.

[0145] Please see Figure 23 , Figure 23 This is a schematic diagram of the functional structure of the timing control circuit in the fourth embodiment of this application.

[0146] like Figure 23 As shown, the timing control circuit 11 includes a storage unit 110, which stores multiple compensation data tables (LUTs). Each compensation data table (LUT) is a compensation data table corresponding to a different scanning signal. Specifically, each compensation data table (LUT) is a data table corresponding to a sampled data Ss.

[0147] The table below illustrates the correspondence between sampled data Ss and compensation data in a compensation data table (LUT). For different sampled data Ss, for example, Ss = 1111100, the corresponding scan signal requires 0.05V compensation; Ss = 1111001, the corresponding scan signal requires 0.07V compensation.

[0148]

[0149] During the manufacturing process of the display panel 10, multiple simulated voltage tests are required, especially for the high-level VGH. By adjusting and reducing the high-level VGH voltage value, the insufficient voltage value of the scan signal Gate output by the scan drive unit GOA due to the characteristic deviation of transistor devices after long-term operation is simulated. Therefore, by testing the voltage value An of the scan signal Gate output by the scan drive unit GOA under different high-level VGH voltages and the corresponding brightness curve Bn, a compensation data table LUT for the voltage value of the scan signal Gate is obtained.

[0150] Specifically, such as Figure 24 As shown, the initial voltage value of the high-level VGH is set to 25V, corresponding to the detection scan signal Gate as A0, and the brightness curves B0 at different gray levels are measured. In this embodiment, the brightness curves at different gray levels are also known as Luminace-Gray Levels. Figure 24 This is a schematic diagram showing the grayscale and brightness curves under different high-level voltages (VGH).

[0151] The voltage value of the high-level VGH is reduced according to the preset step size voltage, and the corresponding scanning signals Gate A1~An are detected, and the brightness curves B1~Bn under different gray levels are measured.

[0152] The compensation data table (LUT) corresponding to each scan signal Gate is calculated based on the brightness curves B0~Bn under different gray levels.

[0153] The brightness L100 at a high level VGH of 20V is significantly lower than that at a high level VGH of 25V, while the brightness L120 in the curve at a high level VGH of 20V is the same as that of L100 at a high level VGH of 25V. If the scan signal Gate output is insufficient, the brightness attenuation is most likely to occur in the low to medium gray levels, i.e., 63~127, and corresponding compensation adjustments should be made.

[0154] The following is combined Figures 10-25 This section details the operation of the partitioned scan compensation circuit. Figure 25 This is a flowchart of the operation of the partition scan compensation circuit 100.

[0155] like Figure 25 As shown, in step 1000, the display panel 10 is powered on and performs initialization work.

[0156] Specifically, the power management circuit in the display panel 10 outputs a power signal. During the initialization process, the power signal is not output to the backlight, and the data driving circuit is controlled to output a black screen data signal.

[0157] Step 2000: During the initialization period, the partition scan compensation circuit 100 detects and identifies the scan signal to obtain the sampling signal Ss, and adjusts the compensation scan signal Gate according to the sampling signal Ss.

[0158] Specifically, corresponding Figure 10 As shown, the detection switching circuit 101 is connected to the last scan line in the first partition AA1, the second partition AA2 and the third partition AA3. Thus, the partition scan compensation circuit 100 detects and identifies the corresponding sampling signal Ss for the three scan lines respectively.

[0159] correspond Figure 11 Each scan line in the first partition AA1, the second partition AA2, and the third partition AA3 shown is connected to the detection switching circuit 101. Considering that the scan signals Gate output by two adjacent scan lines overlap in time, in order to improve detection accuracy, odd-numbered rows and even-numbered rows are detected separately. For example, during the first frame image display time, only the scan signals Gate1, Gate3, and Gate5 in the odd-numbered scan lines are detected, and during the second frame image display time, only the scan signals Gate2, Gate4, and Gate6 in the even-numbered scan lines are detected.

[0160] Please see Figure 26 This is a graphical illustration of obtaining the sampled signal Ss by detecting a portion of the scan lines during the display time of one frame of an image, as shown below. Figure 26As shown, for example, during the display time of the first frame image, only the scan signals Gate1, Gate3 and Gate5 in the odd-numbered scan lines are detected to obtain the digital sample signal Ss. The sample signal Ss of scan signal Gate1 is 111111, the sample signal Ss of scan signal Gate3 is 001111, and the sample signal Ss of scan signal Gate3 is 111111.

[0161] It should be noted that the slower the rising edge of the scan signal Gate, the more low-order zeros there are. Therefore, it can be determined that the rising edge of the sample signal Ss is 110000, which is slower than the rising edge of the sample signal Ss is 111100. It can be seen that the digital sample signal Ss can quantify the voltage value and the rate of change of the signal output by the scan signal Gate.

[0162] The timing control circuit 11 groups the sampling signals Ss according to the refresh rate partitions corresponding to the scanning signals Gate. For example, the sampling signals Ss belonging to the 120Hz partition are classified into the first group, the sampling signals Ss belonging to the 60Hz partition are classified into the first group, and so on.

[0163] The timing control circuit 11 uses the voltage adjustment circuit 20 to make a wide-range global adjustment to the high level VGH according to the sampling signal Ss. Then, it outputs a compensation control signal to the compensation module 305 in the scan drive unit GOA to make a small-range fine compensation adjustment to the voltage of the scan signal Gate. Finally, the scan signal is calibrated by the compensation data table LUT to form a multi-level collaborative compensation system, so as to accurately compensate and adjust the scan signal for different refresh rate partitions, and ensure the charging time of the pixel unit to accurately receive the data signal.

[0164] Step 3000: Display panel 10 enters the image display period and performs image display.

[0165] The timing control circuit converts the RGB image data received from the outside into a data signal and transmits it to the data driving circuit 12. The corresponding gray level voltage is then transmitted to the pixel unit. The scan driving circuit 13 outputs the scan signal Gate according to the compensated form, so that the pixel unit receives the data signal and displays the image.

[0166] Compared to the prior art, in this embodiment of the application, when the display panel 10 performs partition scanning to display images at different refresh rates, the scanning signal is adjusted and compensated in real time during the initialization period after the display panel 10 is powered on. That is, the scanning signal is adjusted and compensated before the actual image display, so that the pixel units P of each partition can be accurately charged and receive data signals to perform image display.

[0167] It should be understood that the application of the present invention is not limited to the examples above. Those skilled in the art can make improvements or modifications based on the above description, and all such improvements and modifications should fall within the protection scope of the appended claims.

Claims

1. A partition scan compensation circuit, characterized by, The detection switching circuit, the voltage dividing circuit, the signal conversion circuit and the conversion sampling circuit are connected, wherein, The detection switching circuit is connected with at least two scan lines and the voltage dividing circuit through a detection sensing line, and is used for connecting the at least part of scan lines with the voltage dividing circuit in a non-display period, wherein the frequencies of the scan signals transmitted by the two scan lines are different; The voltage dividing circuit is connected with the detection sensing line and the signal conversion circuit, and is used for pre-setting proportional voltage division of the scan signals transmitted by the scan lines and performing level conversion to obtain a detection voltage dividing signal; The signal conversion circuit is connected with the voltage dividing circuit and the conversion sampling circuit, and is used for converting the detection voltage dividing signal into a digital pulse width signal; The conversion sampling circuit is used for sampling the digital pulse width signal to form a digital sampling signal according to a sampling clock signal in a period corresponding to the scan signal.

2. The zoned scan compensation circuit of claim 1, wherein, The detection switching circuit includes at least two switching transistors, the switching transistors are respectively connected with one of the scan lines and the voltage dividing circuit, the switching transistors are selectively turned on or turned off under the control of a test switching signal, the scan line is electrically connected with the voltage dividing circuit when the switching transistor is turned on, the scan line is electrically disconnected with the voltage dividing circuit when the switching transistor is turned off, and the test switching signal is effective in the non-display period and controls the switching transistor to be turned on.

3. The zoned scan compensation circuit of claim 2, wherein, The voltage dividing circuit includes a voltage dividing input end, a voltage dividing output end, a first voltage dividing resistor and a second voltage dividing resistor, the voltage dividing input end is connected with the switching transistor through the scan detection line, the voltage dividing output end is connected with the signal conversion circuit, the first voltage dividing resistor and the second voltage dividing resistor are connected in series between the voltage dividing input end and a ground end, and any one node between the first voltage dividing resistor and the second voltage dividing resistor is connected with the voltage dividing output end to output the detection voltage dividing signal.

4. The zoned scan compensation circuit of claim 3, wherein, The signal conversion circuit includes a conversion input end, a reference control end and a conversion output end, The conversion input end is connected with the voltage dividing output end and is used for receiving the detection voltage dividing signal, the reference control end is used for receiving a reference signal, the conversion output end is connected with the conversion sampling circuit, and the signal conversion circuit converts time information, in which the detection voltage dividing signal exceeds a corresponding reference threshold value in the reference signal, into the digital pulse width signal and outputs the digital pulse width signal from the conversion output end.

5. The zoned scan compensation circuit of claim 4, wherein, The signal conversion circuit includes a comparator, the comparator includes a non-inverting input end, an inverting input end and a comparison output end, the non-inverting input end is connected with the voltage dividing output end, the inverting input end receives the reference signal to obtain the reference voltage, and the comparison output end is connected with the conversion output end, the comparator is used for converting time information, in which the voltage dividing detection signal corresponding to the scan signal is greater than the reference threshold value, into the digital pulse width signal, and the digital pulse width signal is used for quantifying the steepness of the rising edge of the scan signal.

6. The zoned scan compensation circuit of claim 4, wherein, The signal conversion circuit includes an operational amplifier, a one-way control circuit, an integration circuit and a control circuit; The operational amplifier is connected to the conversion input end and the one-way control circuit, and is used for forming a voltage follower for the detection voltage division signal and outputting an operational amplifier follower signal; The one-way control circuit is connected to the operational amplifier, and is used for one-way control of one-way transmission of the operational amplifier follower signal to the integration circuit; The integration circuit is connected to the one-way control circuit, and is used for voltage-time area integration of the operational amplifier follower signal and obtaining an integrated conversion output voltage corresponding to the digital pulse width signal; The control circuit is connected to the integration circuit and the conversion output end, and is used for controlling the integration circuit to start and stop the integration of the operational amplifier follower signal.

7. The zoned scan compensation circuit of claim 5 or 6, wherein, The conversion sampling circuit includes an N-bit shift register, which receives the digital pulse width signal and samples the digital pulse width signal according to the sampling clock signal as a shift sampling clock to form a digital sampling signal; or the conversion sampling circuit includes an analog-to-digital converter, which is used for sampling and converting the digital pulse width signal into an N-bit digital sampling signal.

8. A display panel, characterized by, The display panel further includes a display area, and the display area includes a plurality of pixel units, a plurality of data lines and a plurality of scan lines. The plurality of scan lines extend along a first direction and are arranged in parallel along a second direction. The plurality of data lines extend along the second direction and are arranged in parallel along the first direction. The first direction and the second direction are perpendicular to each other. One pixel unit is connected to one scan line and one data line. The display area includes at least a first sub-area and a second sub-area along the second direction. The pixel units in the first sub-area and the second sub-area have different refresh rates when working, and the corresponding scan signals transmitted by the scan lines have different frequencies.

9. The display panel of claim 8, wherein, The display panel further includes a non-display area, and the non-display area includes a timing control circuit, a data driving circuit and a scan driving circuit. The sub-area scan compensation circuit is arranged in the non-display area. The timing control circuit is electrically connected to the data driving circuit and the scan driving circuit, and is used for outputting corresponding timing control signals to the data driving circuit and the scan driving circuit to control the time when the scan driving circuit outputs corresponding scan signals and the time when the data driving circuit outputs corresponding data signals. The data driving circuit is electrically connected to the plurality of data lines, and is used for transmitting the data signals to the pixel units. The scan driving circuit is electrically connected to the plurality of scan lines, and is used for outputting the scan signals to the pixel units to control the time when the pixel units receive the data signals. The timing control circuit is connected to the sub-area scan compensation circuit, and is used for receiving the sampling signal during an initialization period after the display panel is powered on and before image display, and adjusting the compensation of the scan signal according to the sampling signal.

10. The display panel of claim 9, wherein, The display panel further comprises a level conversion circuit connected to the timing control circuit and the scan driving circuit, the level conversion circuit being configured to provide a clock signal to the scan driving circuit under the control of the timing control circuit, and the scan driving circuit being configured to output the scan signal according to high and low levels of the clock signal. The timing control circuit adjusts a potential of a high level of the clock signal output by the level conversion circuit according to the sampling signal.

11. The display panel of claim 9, wherein, The scan driving circuit comprises a plurality of cascaded scan driving units, each of which is connected to one of the scan lines and configured to output the scan signal according to the clock signal. The scan driving unit comprises a pull-up module, a pull-up node, a first pull-down module, a pull-down node, an output module, a second pull-down module and a compensation module. The pull-up module is connected to an enable trigger end and the pull-up node, and is configured to load a high potential voltage provided by the enable trigger end to the first control node under the control of an enable trigger signal provided by the enable trigger end. The first pull-down module is connected to the pull-up node, the pull-down node and the low-voltage power supply end, and is configured to pull down a voltage of the pull-up node to a low potential when the pull-down node is at a high level. The output module is connected to the pull-up node, the clock signal input end and the scan signal output end, and is configured to output a clock signal provided by the clock signal input end as the scan signal when a voltage of the pull-up node is at a high potential. The second pull-down module is connected to the pull-down node, the scan signal output end and the low-voltage power supply end, and is configured to control the scan signal output end to stop outputting the scan signal when the pull-down node is at a high level. The compensation module is connected to the clock signal input end, the pull-up node, a compensation control end and the scan signal output end, and is configured to compensate a voltage of the scan signal output end under a compensation control signal provided by the compensation control end during a scan signal output period, adjust a potential of the compensated scan signal, and output the compensated scan signal.

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