Pre-decoder with write logic bypass path and memory structure including same

Abstract

The invention relates to a predecoder with a write logic bypass path and a memory structure including the predecoder. The invention discloses a predecoder and a structure including the predecoder. Each pre-decoder includes, among other components, first and second latches controlled by a write clock signal and a read clock signal, respectively, and a multiplexer-enabled write logic bypass path. During write, an address signal is latched by a first latch and propagated through a logical downstream of the first latch, including through a write logic block, to a second latch (which is pass through). During read, the write logic bypass path is activated such that the address signal bypasses the first latch and the write logic block, and instead, propagates only through logical downstream of the write logic block to the second latch (which periodically latches the received signal). In both operations, the pre-decoded address signal is output, but the time between receiving the address signal and outputting the pre-decoded address signal is reduced due to the write logic bypass path being activated during the read.

Description

Technical Field

[0001] This disclosure relates to memory structures, and more specifically, to embodiments of pre-decoders and memory structures including pre-decoders. Background Technology

[0002] A non-volatile memory (NVM) architecture may include one or more memory banks and peripheral circuitry for each memory bank, such as column address decoders and row address decoders. An NVM architecture may also include column address pre-decoders and row address pre-decoders. For a given memory operation (e.g., a read or write operation) associated with a particular memory address signal, the memory address signal may be divided into column and row portions. In some NVM architectures (e.g., in NVM architectures supporting sector erase operations, etc.), each pre-decoder may include an input address latch, a write logic block, a pre-decode logic block, and an output buffer connected between the address signal input node and the address signal output node. Optionally, the row address decoder may include a redundant logic block parallel to the pre-decode logic between the input address latch and the output buffer. In any case, during read and write operations, the address signal received at the address signal input node (i.e., column address signal or row address signal, if applicable) is typically latched and propagated through the write logic block before any further downstream processing by any other logic circuitry. Summary of the Invention

[0003] This document discloses an embodiment of a structure (e.g., a pre-decoder). In some embodiments, the structure may include a multiplexer having input terminals, additional input terminals, and output terminals. The input terminals of the multiplexer may be connected to a first signal node. The structure may further include a first latch controlled by a first clock signal (e.g., a write clock signal). The structure may further include a write logic block. The first latch and the write logic block may be connected between the first signal node and the additional input terminals. The structure may further include a pre-decoder logic block and a second latch. The second latch may be controlled by a second clock signal different from the first clock signal (e.g., a read clock signal). Furthermore, the pre-decoder logic block and the second latch may be connected between the output terminals and the second signal node.

[0004] In other embodiments, the structure may include: a first multiplexer having a first input terminal, an additional first input terminal, and a first output terminal. The first input terminal of the first multiplexer may be connected to a first signal node. The structure may further include: a first latch controlled by a first clock signal (e.g., a write clock signal). The structure may further include a write logic block. The first latch and the write logic block may be connected between the first signal node and the additional first input terminal of the first multiplexer. The structure may further include: a second multiplexer having a second input terminal, an additional second input terminal, and a second output terminal. The structure may further include: a redundancy logic block connected between the first output terminal of the first multiplexer and the second input terminal of the second multiplexer. The structure may further include: a pre-decoding logic block connected between the first output terminal of the first multiplexer and the additional second input terminal of the second multiplexer. The structure may further include: a second latch controlled by a second clock signal different from the first clock signal (e.g., a read clock signal). The second latch can be connected between the second output terminal and the second signal node.

[0005] This document also discloses an embodiment of a memory structure. The memory structure may include an address decoder for a memory bank. The memory structure may further include an address pre-decoder connected to the address decoder. The address pre-decoder may include a multiplexer having input terminals, additional input terminals, and output terminals. The input terminals of the multiplexer may be connected to a first signal node. The address pre-decoder may further include a first latch controlled by a first clock signal (e.g., a write clock signal). The structure may further include a write logic block. The first latch and the write logic block may be connected between the first signal node and the additional input terminals. The structure may further include a pre-decode logic block and a second latch controlled by a second clock signal different from the first clock signal (e.g., a read clock signal). The pre-decode logic block and the second latch may be connected between the output terminals and the second signal node.

[0006] It should be noted that all aspects, examples, and features of the disclosed embodiments mentioned in the above overview can be combined in any technically possible manner. That is, two or more aspects of any embodiment in the disclosed embodiments (including those described in this overview section) can be combined to form implementations not specifically described herein. Details of one or more implementations are set forth in the accompanying drawings and the following description. Other features, objects, and advantages will be apparent from the specification, drawings, and claims. Attached Figure Description

[0007] This disclosure will be better understood through the following detailed description with reference to the accompanying drawings, which are not necessarily drawn to scale, wherein:

[0008] Figure 1 This is a schematic diagram illustrating an embodiment of a memory structure, and also illustrating embodiments of a column address predecoder and a row address predecoder;

[0009] Figure 2 This is a schematic diagram illustrating another embodiment of the memory structure and also showing embodiments of the column address predecoder and row address predecoder;

[0010] Figure 3 It shows that it can be shown Figure 1 or Figure 2 A schematic diagram of an example NVM primitive structure used in a memory library with a memory structure;

[0011] Figure 4A This indicates that during a read operation, by Figure 1 or Figure 2 The timing diagram of the example read and write clock signals used in the pre-decoder in the memory structure; and

[0012] Figure 4B This indicates that during a write operation, by Figure 1 or Figure 2 The timing diagram of the example read and write clock signals used in the pre-decoder in the memory structure. Detailed Implementation

[0013] As described above, an NVM architecture may include one or more memory banks and peripheral circuitry for each memory bank, such as column address decoders and row address decoders. An NVM architecture may also include column address pre-decoders and row address pre-decoders. For a given memory operation (e.g., a read or write operation) associated with a specific memory address, the memory address signal may be divided into column and row portions. In some NVM architectures (e.g., in NVM architectures supporting sector erase operations, etc.), each pre-decoder may include an input address latch, a write logic block, a pre-decode logic block, and an output buffer connected between the address signal input node and the address signal output node. Optionally, the row address decoder may also include a redundant logic block parallel to the pre-decode logic between the input address latch and the output buffer. In any case, during read and write operations, the address signal received at the address signal input node (i.e., column address signal or row address signal, if applicable) is typically latched before being processed by any downstream logic circuitry and then propagated through the write logic block. However, the propagation of the address signal by writing to the logic block is unnecessary for the read operation, thus delaying the read operation setup time.

[0014] In view of the above, this document discloses embodiments of predecoders (e.g., column address predecoders and row address predecoders) specifically configured to reduce setup time, particularly during read operations. In addition to some conventional predecoder components (e.g., as described above, write logic blocks, predecode logic blocks, and optional redundant logic blocks in the case of row address predecoders), the predecoders disclosed herein may also include first and second latches (also referred to herein as input and output latches) controlled by different write and read clock signals, respectively, and a write logic bypass path enabled by a multiplexer. During a write operation, the address signal received at the input node can be latched by the first latch (based on the logic 1 state of the write clock signal) and further propagated downstream of the first latch (including through the write logic block, predecode logic block, and redundant logic blocks in the case of row address predecoders) to the second latch (which is transparent based on the logic 0 state of the read clock signal). Therefore, the predecoded address signal is output at the output node. During a read operation, a write logic bypass path is activated, causing the address signal received at the input node to bypass the first latch and the write logic block, and instead propagate only downstream of the write logic block (the pre-decoding logic block, and redundant logic blocks in the case of the row address pre-decoder) to the second latch (which periodically latches the pre-decoded address signal according to the periodic transition of the read clock signal). Since processing through the write logic block is completely bypassed during the read operation, and address signal pre-decoding is performed before the read clock signal opens the second latch, the setup time from receiving the address signal at the input node to outputting the pre-decoded address signal at the output node is significantly reduced compared to the setup time typically seen in prior art pre-decoders that include only a single input address latch upstream of all logic blocks. Therefore, the read cycle time is also significantly reduced compared to such prior art pre-decoders. Embodiments of memory structures (e.g., NVM structures) incorporating such a pre-decoder are also disclosed herein.

[0015] More specifically, Figure 1-2 This is a schematic diagram illustrating embodiments of memory structures 100 and 200, and also illustrating embodiments of column address predecoders 130 and 230 and row address predecoders 140 and 240 incorporated into memory structures 100 and 200.

[0016] Memory structures 100 and 200 may include one or more memory banks 1100-110 n 2100-210 n (Hereinafter referred to as the library). Each library contains 1100-110. n 2100-210 nAn array of memory primitives 101, 201 (hereinafter referred to as primitives) may be included. Primitives 101, 201 may be, for example, non-volatile memory (NVM) primitives, such that memory structures 100, 200 are NVM structures. In any case, primitives 101, 201 may be arranged in columns (e.g., see columns C0-Cm) and rows (e.g., see rows R0-Rn). In some embodiments, the total number of columns may be, for example, 128 (i.e., m+1 = 128). For ease of illustration, the columns shown in the drawings are oriented in the Y direction (i.e., from top to bottom), and the rows shown in the drawings are oriented in the X direction (i.e., from one side to the other). The column and row orientations of primitives 101, 201 shown in the figures are not intended to be limiting. Alternatively, columns may be oriented in the X direction and rows may be oriented in the Y direction. In any case, columns may be substantially perpendicular to rows, wherein each primitive 101, 201 is located at an address at the intersection of a column and a row within the memory bank. In some embodiments, each library has 1100-110 n 2100-210 n It can be organized into multiple sectors. Each sector may include a certain number of consecutive rows. For example, in some embodiments, each sector may include four consecutive rows, each row having 128 primitives (corresponding to the total number of columns). In this case, sector 0 may include R0 / C0-C127, R1 / C0-C127, R2 / C0-C127, and R3 / C0-C127; sector 1 may include R4 / C0-C127, R5 / C0-C127, R6 / C0-C127, and R7 / C0-C127; and so on. Memory structures 100 and 200 may also include libraries 1100-110. n 2100-210 n Associated peripheral circuitry. For each library, the peripheral circuitry may include a column control block containing at least column address decoders 192, 292 and a row control block containing at least row address decoders 191, 291.

[0017] As mentioned above, primitives 101 and 201 can be NVM primitives. Each library has 1100-110. n 2100-210 n This can include bit lines 111, 211 and source lines 113, 213 for columns C0-Cm, respectively, and each bit line 111, 211 and optionally each source line 113, 213 can be connected to the column address decoder 192, 292 of the library. Each library 1100-110 n 2100-210 nIt may also include word lines 112 and 212 for rows R0-Rn, and each word line 112 and 212 may be connected to the row address decoder 191 and 291 of the library. Furthermore, in each library 1100-110... n 2100-210 n Within a column, all primitives 101 and 201 can be electrically connected between the source lines 113 and 213 and the bit lines 111 and 211 of that column. All primitives 101 and 201 in a row can be electrically connected to the word lines 112 and 212 of that row.

[0018] Figure 3 This shows that it can be found in library 1100-110. n 2100-210 nThe diagram illustrates an example NVM primitive structure. This NVM primitive includes a programmable resistor 320 (also referred to herein as a variable resistor, memristor, and / or other similar component) and an access transistor 310 connected in series between a bit line 311 of the column and a source line 313 of the same column. Specifically, the programmable resistor 320 may have a first terminal 321 connected to the bit line 311 of the column and a second terminal 322 connected to the drain region of the access transistor 310. For example, the access transistor 310 may be an N-type field-effect transistor (NFET) whose source region may be connected to the source line 313 of the column and its gate connected to the word line 312 of the row. In this resistive programmable NVM primitive, the programmable resistor 320 may be any type of programmable resistor suitable for resistive NVM primitives. For example, the programmable resistor 320 may be a magnetic tunnel junction (MTJ) type programmable resistor (for magnetic random access memory (MRAM) cells), a phase-change memory (PCM) type programmable resistor (for PCM cells), or a resistive random access memory (RRAM) type programmable resistor (for RRAM cells), or any other suitable type of programmable resistor configured to change the resistance of the programmable resistor 320 between at least two different stable resistance states by applying specific bias conditions to one or both terminals. For example, the resistance state of such a programmable resistor 320 may change to a high resistance state to store a logic value (e.g., logic value "1"), or change to a low resistance state to store a different logic value (e.g., logic value "0"). It should be noted that in some NVM structures, the source line is continuously discharged to ground and programming is achieved through bit line bias. In other NVM structures, programming can be achieved through a combination of bit line and source line bias. In any case, NVM primitives, including access transistors and programmable resistors (such as MTJ-type programmable resistors, PCM-type programmable resistors, and RRAM-type programmable resistors), are well known in the art. Therefore, a more detailed description of these NVM primitives is omitted in this specification so that the reader can focus on the prominent aspects of the disclosed embodiments (e.g., those related to novel components of the pre-decoder discussed in more detail below).

[0019] Memory structures 100 and 200 may also include global control circuitry connected to each library 1100-110. n 2100-210 nThe peripheral circuitry. Global control circuitry may include, but is not limited to, column address pre-decoders 130 and 230 connected to column address decoders 192 and 292, and row address pre-decoders 140 and 240 connected to row address decoders 191 and 291. It should be noted that column address pre-decoder 130 of memory structure 100 and column address pre-decoder 230 of memory structure 200 are substantially the same. However, row address pre-decoder 240 of memory structure 200 is modified from row address pre-decoder 140 of memory structure 100 to include an optional redundant logic block 245.

[0020] refer to Figure 1 and 2 Typically, column address pre-decoders 130 and 230 can be connected to receive the column address signal (Add_C) portion of a specific memory address signal from a memory controller (not shown) at first signal nodes 139a and 239a (referred to herein as column address input nodes), and can output the pre-decoded column address signal at second signal nodes 139b and 239b (referred herein as pre-decoded column address output nodes). The pre-decoded column address signal (also referred herein as partially decoded column address signal or intermediate column address signal) refers to the column address signal that has been partially decoded by column address pre-decoders 130 and 230 before being received and processed by column address decoders 192 and 292 (e.g., to indicate a specific library and its columns for memory operations). Similarly, row address pre-decoders 140 and 240 can be connected to receive the row address signal (Add_R) portion of a specific memory address signal from a memory controller (not shown) at first signal nodes 149a and 249a (referred to herein as row address input nodes), and can output the pre-decoded row address signal (Add-Rpd) at second signal nodes 149b and 249b (referred herein as pre-decoded row address output nodes). The pre-decoded row address signal (also referred herein as partially decoded row address signal or intermediate column address signal) refers to the row address signal that has been partially decoded by row address pre-decoders 140 and 240 before being received and processed by row address decoders 191 and 291 (e.g., to indicate a specific library and its rows for memory operations).

[0021] More specifically, column address predecoders 130, 230 and row address predecoders 140, 240 may include some conventional predecoder components. For example, column address predecoders 130, 230 and row address predecoders 140, 240 may each include write logic blocks (see column address write logic blocks 132, 232 and row address write logic blocks 142, 242) and predecoding logic blocks (see column address predecoding logic blocks 134, 234 and row address predecoding logic blocks 144, 244). Optionally, row address predecoders 140, 240 may also include redundant logic blocks (e.g., see only...). Figure 2 (Redundant logic block 245 in row address pre-decoder 240 of memory structure 200).

[0022] Write logic blocks may include logic circuitry specifically configured to facilitate write operations. For example, these write logic blocks may include, but are not limited to, address counters. As described above, in some embodiments, each library may be divided into sectors. Each sector may include a number of consecutive rows. For example, each sector may include four consecutive rows, each row may include 128 primitives (corresponding to the total number of columns). In this case, sector 0 may include R0 / C0-C127, R1 / C0-C127, R2 / C0-C127, and R3 / C0-C12; sector 1 may include R4 / C0-C127, R5 / C0-C127, R6 / C0-C127, and R7 / C0-C127; and so on. To improve performance by enabling sequential automatic write operations relative to all memory primitives in a sector after receiving the memory address associated with the first primitive in the sector, without needing to receive each individual memory address, column address predecoders 130, 230 and row address predecoders 140, 240 (which may include write logic blocks with address counters, as discussed in more detail below) can be configured to automatically increment the column and row addresses until all primitives in the sector have been written. That is, the column address counters in write logic blocks 132, 232 can be configured to increment the column address from C0 to Cm for each row address, while the row address counters in write logic blocks 142, 242 can be configured to increment the row address after every m+1 write cycles. For example, for a second sector comprising four rows of 128 primitives, the column address counters in write logic blocks 132 and 232 can be configured to increment the column address from C0 to C127 for each row address (starting from the initial row in the sector and ending at the last row in the sector), while the row address counters in write logic blocks 142 and 242 can be configured to increment the row address after every 128 write cycles. Such write logic blocks are well known in the art, and therefore, their more specific details are omitted in the specification so that the reader can focus on the salient aspects of the disclosed embodiments (e.g., those relating to novel components of the pre-decoder discussed in more detail below).

[0023] The pre-decoding logic block may include logic circuitry configured to pre-decode (or partially decode) the received address signal. Specifically, the received memory address may include information indicating the memory cell location to be accessed during a read or write operation. However, this information may indicate the memory cell location within the entire memory structure, rather than within a given library. For example, memory structures 100, 200 as a whole may include a relatively large number of columns and a relatively large number of rows. Columns and / or rows may be segmented to form libraries 1100-110. n 2100-210 n (For example, each library has the same number of columns and the same number of rows). The column address signals and row address signals received by column address pre-decoders 130, 230 and row address pre-decoders 140, 240, respectively, can be associated with the entire memory structure 100, 200 (before partitioning). Column address pre-decoding logic blocks 134, 234 can be configured to pre-decode Add_C such that Add_Cpd indicates a specific library and its columns. Similarly, row address pre-decoding logic blocks 144, 244 can be configured to pre-decode Add_R such that Add_Rpd indicates a specific library and its rows. Such pre-decoding logic blocks are well known in the art, and therefore, their more specific details are omitted in the specification so that the reader can focus on the salient aspects of the disclosed embodiments (e.g., those relating to novel components of the pre-decoders discussed in more detail below).

[0024] Redundant logic blocks may optionally be included in the line address predecoder (e.g., see [reference]). Figure 2 The redundant logic block 245 in the row address pre-decoder 240 of the memory structure 200. This redundant logic block 245 can be configured to enable a row redundancy scheme. For example, in the memory structure 200, performance can be improved by using primitives 201 of one or more redundant rows (also called spare rows or auxiliary rows) so that if / when it is determined that one or more primitives in the main row of the library are defective, the redundant row (in the same or different libraries) can be used, thereby avoiding memory failure. To implement the redundancy scheme, defective row information can be stored in defective row memory (e.g., fuse-based memory), and the row redundancy logic block 245 (also referred to herein as row redundancy control circuitry) can be configured to determine, based on the defective row information, whether to use the main row (as indicated by the received row address signal) or one of the redundant rows, and can output appropriate signals to achieve this. Such row redundancy logic blocks are well known in the art, and therefore, their more specific details are omitted in the specification so that the reader can focus on the prominent aspects of the disclosed embodiments (e.g., those related to novel components of the pre-decoder discussed in more detail below).

[0025] As described above, in some NVM architectures (e.g., NVM architectures supporting sector erasure, etc.), the received address signals (i.e., column address signals or row address signals, if applicable) can be latched by input address latches in both the column address predecoder and the row address predecoder, and then propagated through the write logic block during any type of memory operation (i.e., during write and read operations). However, the propagation of address signals through the write logic block is unnecessary for read operations, resulting in an unnecessary delay in read operation setup time. To avoid this unnecessary increased setup time delay during read operations, the disclosed predecoder embodiments each include a combination of first and second latches (also referred to herein as input and output latches) controlled by different write and read clock signals, respectively, and a write logic bypass path enabled by a multiplexer. In these embodiments, during read operations, processing through the write logic block is completely bypassed, and address signal predecoding is performed before the read clock signal opens the second latch. Therefore, the setup time between receiving the address signal and outputting the pre-decoded address signal is significantly reduced compared to the setup time typically seen in prior art pre-decoders that include only a single input address latch upstream of all logic blocks. Consequently, the read cycle time is also significantly reduced compared to such conventional pre-decoders.

[0026] More specifically, see reference Figure 1 and 2 The column address pre-decoders 130 and 230 of memory structures 100 and 200 may include first signal nodes 139a and 239a (also referred to herein as column address input nodes) connected to receive Add_C. The column address pre-decoders 130 and 230 may also include second signal nodes 139b and 239b (also referred herein as pre-decoded column address output nodes) for outputting Add_Cpd. Between the first signal nodes 139a and 239a and the second signal nodes 139b and 239b, the column address pre-decoders 130 and 230 may also include multiplexers 133 and 233. Multiplexers 133 and 233 may include two input terminals: one input terminal 133a and 233a connected to the first signal nodes 139a and 239a; and an additional input terminal 133b and 233b. Multiplexers 133 and 233 may also include output terminals 133c and 233c.

[0027] The column address pre-decoders 130 and 230 may also include first latches 131 and 231 and column address write logic blocks 132 and 232 (e.g., including column address counters, as discussed above) controlled by a first clock signal (also referred to herein as the write clock signal (CLKw)). The first latches 131 and 231 and the write logic blocks 132 and 232 may be connected in series between the first signal nodes 139a and 239a and the additional input terminals 133b and 233b of the multiplexers 133 and 233.

[0028] The column address predecoders 130 and 230 may further include column address predecoding logic blocks 134 and 234 (as discussed in more detail above) and a second latch 137 (also referred to herein as a predecoding column address output latch), which are connected in series between the output terminals 133c and 233c of the multiplexers 133 and 233 and the second signal nodes 139b and 239b. The second latches 137 and 237 may be controlled by a second clock signal (also referred herein as a read clock signal (CLKr)). Optionally, the column address predecoders 130 and 230 may further include output buffers 138 and 238, which are connected in series between the second latches 137 and 237 and the second signal nodes 139b and 239b.

[0029] For specific references Figure 1 In the memory structure 100, the row address predecoder 140 can be configured similarly to the column address predecoder 130. That is, the row address predecoder 140 may include a first signal node 149a (also referred to herein as a row address input node) connected to receive Add_R. The row address predecoder 140 may also include a second signal node 149b (also referred herein as a pre-decoded row address output node) for outputting Add_Rpd. Between the first signal node 149a and the second signal node 149b, the row address predecoder 140 may also include a multiplexer 143. The multiplexer 143 may include two input terminals: an input terminal 143a connected to the first signal node 149a; and an additional input terminal 143b. The multiplexer 143 may also include an output terminal 143c.

[0030] The row address pre-decoder 140 may also include a first latch 141 (also referred to herein as a row address input latch) controlled by CLKw and a row address write logic block 142 (e.g., including a row address counter, as discussed above). The first latch 141 and the write logic block 142 may be connected in series between the first signal node 149a and the additional input terminal 143b of the multiplexer 143.

[0031] The row address predecoder 140 may further include a row address predecoding logic block 144 (as discussed in more detail above) and a second latch 147 (also referred to herein as the predecoding row address output latch), which are connected in series between the output terminal 143c of the multiplexer 143 and the second signal node 149b. The second latch 147 may be controlled by CLKr. Optionally, the row address predecoder 140 may further include an output buffer 148, which is connected in series between the second latch 147 and the second signal node 149b.

[0032] For specific references Figure 2 The memory structure 200, the row address pre-decoder 240, can be slightly more complex than the row address pre-decoder 140 because it also includes redundant logic blocks 245 (discussed in more detail below). In this case, the row address pre-decoder 240 may include a first signal node 249a (also referred to herein as a row address input node), which is connected to receive Add_R. The row address pre-decoder 240 may also include a second signal node 249b (also referred herein as a pre-decoded row address output node) for outputting Add_Rpd. Between the first signal node 249a and the second signal node 249b, the row address pre-decoder 240 may also include a first multiplexer 243. The first multiplexer 243 may include two first input terminals: a first input terminal 243a connected to the first signal node 249a; and an additional first input terminal 243b. The first multiplexer 243 may also include a first output terminal 243c.

[0033] The row address pre-decoder 240 may also include a first latch 241 (also referred to herein as a row address input latch) controlled by CLKw and a row address write logic block 242 (e.g., including a row address counter, as discussed above). The first latch 241 and the write logic block 242 may be connected in series between the first signal node 249a and an additional first input terminal 243b of the first multiplexer 243.

[0034] The row address pre-decoder 240 may further include a second multiplexer 246. The second multiplexer 246 may have two second input terminals (i.e., second input terminal 246a and an additional second input terminal 246b) and a second output terminal 246c. The second multiplexer 246 may be controlled, for example, by a pre-decode / redundancy selection signal (SELpre / red). The row address pre-decoder 240 may further include a redundancy logic block 245 and a row address pre-decoder logic block 244 (as discussed in more detail above). The redundancy logic block 245 may be connected between the first output terminal 243c of the first multiplexer 243 and the second input terminal 246a of the second multiplexer 246. The pre-decoder logic block 244 may be connected between the first output terminal 243c of the first multiplexer 243 and the additional second input terminal 246b of the second multiplexer 246. Therefore, redundant logic block 245 and pre-decoding logic block 244 are connected in parallel between the first multiplexer 243 and the second multiplexer 246.

[0035] The row address predecoder 240 may further include a second latch 247 connected between the second output terminal 246c of the second multiplexer 246 and the second signal node 249b. The second latch 247 may be controlled by CLKr. Optionally, the row address predecoder 240 may further include an output buffer 248 connected in series between the second latch 247 and the second signal node 249b.

[0036] Combined with references again Figure 1 and 2 In the column address predecoders 130, 230 and the row address predecoders 140, 240, multiplexers 133, 233 and 143, 243 can be controlled by the same read / write select signal (SELrw). SELrw can be switchable so that multiplexers 133, 233 and 143, 243 connect only one of their two input terminals to the output terminal, depending on whether a write or read operation is to be performed.

[0037] For example, consider Figure 1 The column address pre-decoder 130 shown is... Figure 2As shown in 230. During a write operation, SELrw can switch to a first state, causing multiplexers 133 and 233 to connect additional input terminals 133b and 233b (thereby connecting write logic blocks 132 and 232) to output terminals 133c and 233c (thereby connecting to pre-decoding logic blocks 134 and 234). However, during a read operation, SELrw can switch to a second state, causing multiplexers 133 and 233 to connect input terminals 133a and 233a (thereby connecting first signal nodes 139a and 239a) to output terminals 133c and 233c (thereby connecting to pre-decoding logic blocks 134 and 234). Therefore, during the read operation, write logic bypass paths 150 and 250 (also referred to herein as multiplexer-enabled write logic bypass paths) are created to provide Add_C to pre-decoding logic blocks 134 and 234, without going through the first latches 131 and 231 or write logic blocks 132 and 232, in order to reduce the read operation setup time.

[0038] Also considering Figure 1 The row address pre-decoder 140 is shown. During a write operation, SELrw can switch to a first state, causing multiplexer 144 to connect additional input terminal 143b (thereby connecting write logic block 142) to output terminal 143c (thereby connecting to pre-decode logic block 144). However, during a read operation, SELrw can switch to a second state, causing multiplexer 143 to connect input terminal 143a (thereby connecting first signal node 149a) to output terminal 143c (thereby connecting to pre-decode logic block 144). Therefore, in a read operation, a write logic bypass path 160 is created to provide Add_R to pre-decode logic block 144 without going through first latch 141 or write logic block 142, thereby reducing read operation setup time.

[0039] Also considering Figure 2The row address pre-decoder 240 is shown. During a write operation, SELrw can switch to a first state, causing the first multiplexer 243 to connect an additional first input terminal 243b (thereby connecting write logic block 242) to the first output terminal 243c (thereby connecting to pre-decode logic block 244 and redundant logic block 245). However, during a read operation, SELrw can switch to a second state, causing the first multiplexer 243 to connect the first input terminal 243a (thereby connecting the first signal node 249a) to the first output terminal 243c (thereby connecting to pre-decode logic block 244 and redundant logic block 245). Therefore, during a read operation, a write logic bypass path 260 (also referred to herein as a multiplexer-enabled write logic bypass path) is created to provide Add_R to pre-decode logic block 244 and redundant logic block 245 without going through the first latch 241 or write logic block 242, thereby reducing read operation setup time. In this configuration, the output from the first multiplexer 243 is propagated through the redundancy logic block 245 and the pre-decoding logic block 244 to the two second input terminals 246a-246b of the second multiplexer. The second multiplexer 246 can be controlled, for example, by a pre-decoding / redundancy selection signal (SELpre / red). SELpre / red can be switchable to allow the second multiplexer 246 to connect the second input terminal 246a or an additional second input terminal 246b to the second output terminal 246c (i.e., disable or enable redundancy). Specifically, if redundancy is disabled, SELpre / red can switch to a first state, allowing the second multiplexer 246 to connect the additional second input terminal 246b (and thus the pre-decoding logic block 244) to the second output terminal 246c (and thus to the second latch 247). However, if redundancy is enabled, SELpre / red can switch to a second state so that the second multiplexer 246 connects the second input terminal 246a (thereby connecting the redundant logic block 245) to the second output terminal 246c (thereby connecting to the second latch 237).

[0040] As described above in detail and Figure 1 and 2 In each of the pre-decoders 130, 140, 230, and 240 shown, the first latches 131, 141, 231, and 241 are controlled by a first clock signal, specifically a write clock signal (CLKw), and the second latches 137, 147, 237, and 247 are controlled by a second clock signal, specifically a read clock signal (CLKr). CLKw and CLKr can be asynchronous clock signals, varying depending on whether a read or write operation is being performed. Figure 4AThis is an example timing diagram illustrating CLKw and CLKr during a read operation. As shown, CLKw goes low (e.g., to logic 0) during a read operation, therefore, the first latches 131, 141, 231, and 241 are pass-through. That is, during a read operation, the outputs from the first latches 131, 141, 231, and 241 pass-through following the input with a small delay. CLKr becomes periodic (e.g., with a fixed period between low and high levels), therefore, according to the transition of CLKr, the pre-decoded address signal output is latched to output buffers 138, 148, 238, and 248, and thereby latched to the second signal nodes 139b, 149b, 239b, and 249b. Figure 4B This is an example timing diagram illustrating CLKw and CLKr during a write operation. As shown, CLKw goes high (e.g., becomes logic 1) during a write operation to latch the input address signal. CLKr goes low (e.g., becomes logic 0) during a write operation, therefore, the second latches 137, 147, 237, and 247 are pass-through. That is, during a write operation, the outputs from the second latches 137, 147, 237, and 247 pass-through following the input with a small delay.

[0041] In the above and Figure 1 and 2 In the illustrated embodiments, the logic bypass paths 150, 160, 250, and 260 enabled by the multiplexers of the pre-decoders 130, 140, 230, and 240 effectively reduce the turn-around time during read operations from receiving the address signal at the input node to outputting the pre-decoded address signal at the output node. Furthermore, the disclosed embodiments achieve this performance advantage with only a minimal increase in area (e.g., less than 1%) and substantially no impact on leakage or dynamic power, as the increased logic for implementation resides in the non-repetitive global control circuitry.

[0042] It should be understood that the terminology used herein is for describing the disclosed structures and methods and is not intended to be limiting. For example, as used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms, unless the context clearly indicates otherwise. Furthermore, as used herein, the terms “comprises,” “comprising,” “includes,” and / or “including” specify the presence of the stated features, integrals, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof. Moreover, as used herein, when oriented and shown in figures, terms such as “right,” “left,” “vertical,” “horizontal,” “top,” “bottom,” “upper,” “lower,” “below,” “under,” “under,” “above,” “overlapping,” “parallel,” “vertical,” etc., are intended to describe relative positions (unless otherwise stated), and terms such as “touches,” “directly contacts,” “adjacent,” “directly adjacent,” “closely adjacent,” etc., are intended to indicate that at least one element is in physical contact with another element (without any other element separating the elements). The term "lateral" is used herein to describe the relative position of elements, and more specifically, when elements are oriented and shown in a figure, to indicate that one element is located to the side of another element, rather than above or below it. For example, an element laterally adjacent to another element will be beside the other element, an element laterally directly adjacent to another element will be directly beside the other element, and an element laterally surrounding another element will be adjacent to and bound to the outer wall of the other element. All corresponding structures, materials, actions, and equivalents of the means or steps plus functional elements in the following claims are intended to include any structures, materials, or actions used to perform a function in combination with other elements of the specific claims.

[0043] The methods described above are used for the manufacture of integrated circuit chips. The resulting integrated circuit chips can be distributed by the manufacturer in the form of raw wafers (i.e., as a single wafer with multiple unpackaged chips), as bare dies, or in packages. In the latter case, the chips are mounted in single-chip packages (e.g., plastic carriers with leads attached to a motherboard or other higher-level carriers) or multi-chip packages (e.g., ceramic carriers with surface interconnects or buried interconnects, or both). In any case, the chips are then integrated with other chips, discrete circuit elements, and / or other signal processing devices as part of (a) an intermediate product (e.g., a motherboard) or (b) a final product. The final product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products with displays, keyboards or other input devices, and central processing units.

[0044] Various disclosed embodiments have been described for illustrative purposes, but are not intended to be exhaustive or limiting. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the disclosed embodiments. The terminology used herein has been chosen to best explain the principles of the embodiments, practical applications of techniques found in the market, or improvements to techniques, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A structure comprising: a multiplexer including an input terminal connected to a first signal node; an additional input terminal; and an output terminal; a first latch controlled by a first clock signal; a write logic block, wherein the first latch and the write logic block are connected between the first signal node and the additional input terminal; a predecode logic block; and a second latch controlled by a second clock signal different from the first clock signal, wherein the predecode logic block and the second latch are connected between the output terminal and a second signal node.

2. The structure of claim 1, wherein, the multiplexer is controlled by a select signal, and wherein the select signal causes the multiplexer to connect the predecode logic block to one of the first signal node and the write logic block.

3. The structure of claim 2, wherein the first signal node receives an address signal, and wherein the select signal causes the multiplexer to connect the predecode logic block to the write logic block during a write operation, and further causes the multiplexer to connect the predecode logic block to the first signal node during a read operation to create a multiplexer-enabled write logic bypass path for the address signal during the read operation.

4. The structure of claim 3, wherein, the address signal is a row address signal, and wherein the second signal node outputs a predecoded row address signal to a row address decoder of a memory bank.

5. The structure of claim 3, wherein, the address signal is a column address signal, and wherein the second signal node outputs a predecoded column address signal to a column address decoder of a memory bank.

6. The structure of claim 1, wherein during a read operation, the first clock signal toggles to logic 0 to cause the first latch to pass through, and the second clock signal is periodic, and wherein, during a write operation, the second clock signal toggles to logic 0 to cause the second latch to pass through, and the first clock signal toggles to logic 1.

7. The structure of claim 1, further comprising: an output buffer connected between the second latch and the second signal node.

8. A structure comprising: a first multiplexer having a first input terminal connected to a first signal node; an additional first input terminal; and a first output terminal; a first latch controlled by a first clock signal; a write logic block, wherein the first latch and the write logic block are connected between the first signal node and the additional first input terminal; a second multiplexer having a second input terminal; an additional second input terminal; and a second output terminal; a redundancy logic block connected between the first output terminal and the second input terminal; a predecode logic block connected between the first output terminal and the additional second input terminal; and a second latch controlled by a second clock signal different from the first clock signal, wherein the second latch is connected between the second output terminal and a second signal node.

9. The structure of claim 8, wherein, The first multiplexer is controlled by a first select signal, and wherein the first select signal causes the first multiplexer to connect the redundant logic block and the predecode logic block to one of the first signal node and the write logic block.

10. The structure of claim 9, wherein The first signal node receives a row address signal, and wherein the first select signal causes the first multiplexer to connect the redundant logic block and the predecode logic block to the write logic block during a write operation, and further causes the first multiplexer to connect the redundant logic block and the predecode logic block to the first signal node during a read operation, so as to create a multiplexer-enabled write logic bypass path for the row address signal during the read operation.

11. The structure of claim 10, wherein, The second multiplexer is controlled by a second select signal, and wherein the second select signal causes the second multiplexer to connect the second latch to one of the redundant logic block and the predecode logic block.

12. The structure of claim 10, wherein, The second signal node outputs a predecoded row address signal to a row address decoder of a memory bank.

13. The structure of claim 8, wherein, During a read operation, the first clock signal toggles to logic 0 to make the first latch transparent, and the second clock signal is periodic, and wherein, during a write operation, the second clock signal toggles to logic 0 to make the second latch transparent, and the first clock signal toggles to logic 1.

14. The structure of claim 8, further comprising: An output buffer connected between the second latch and the second signal node.

15. A structure comprising: an address decoder for a memory bank; and an address a predecoder connected to the address decoder and comprising: a multiplexer comprising: an input terminal connected to a first signal node; an additional input terminal; and an output terminal; a first latch controlled by a first clock signal; a write logic block, wherein the first latch and the write logic block are connected between the first signal node and the additional input terminal; a predecode logic block; and a second latch controlled by a second clock signal different from the first clock signal, wherein the predecode logic block and the second latch are connected between the output terminal and a second signal node.

16. The structure of claim 15, wherein, The multiplexer is controlled by a select signal, and wherein the select signal causes the multiplexer to connect the predecode logic block to one of the first signal node and the write logic block.

17. The structure of claim 16, wherein The address decoder is a column address decoder, wherein the address predecoder is a column address predecoder, wherein the first signal node receives a column address signal, wherein the select signal causes the multiplexer to connect the predecode logic block to the write logic block during a write operation, and further causes the multiplexer to connect the predecode logic block to the first signal node during a read operation, so as to create a write logic bypass path for the address signal during the read operation, and wherein the second signal node outputs a pre-decoded column address signal to the column address decoder.

18. The structure of claim 17, further comprising: a row address decoder for the memory bank; and a row address pre-decoder connected to the row address decoder, wherein the row address pre-decoder comprises at least two latches controlled by the first clock signal and the second clock signal, respectively, a multiplexer, and a write logic block and a pre-decode logic block with a multiplexer-enabled write logic bypass path for read operations.

19. The structure of claim 17, further comprising: a row address decoder for the memory bank; and a row address pre-decoder connected to the row address decoder, wherein the row address pre-decoder comprises at least two latches controlled by the first clock signal and the second clock signal, respectively, two multiplexers, and a write logic block, a pre-decode logic block, and a redundancy logic block with a multiplexer-enabled write logic bypass path for read operations.

20. The structure of claim 15, wherein during a read operation, the first clock signal is toggled to logic 0 to make the first latch transparent, and the second clock signal is periodic, and wherein, during a write operation, the second clock signal is toggled to logic 0 to make the second latch transparent, and the first clock signal is toggled to logic 1.

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