Semiconductor optical amplifier and preparation method thereof

Abstract

The invention relates to the technical field of optical amplifiers, in particular to a semiconductor optical amplifier and a preparation method and a stacking structure thereof, and the stacking structure comprises a substrate, an N cladding, an N-type etching stop layer, an N waveguide layer, an active region, a P waveguide layer, a P cladding and an electrode contact layer which are stacked in sequence; the two shallow trenches are arranged at intervals along a first direction, and a stacked structure between the two shallow trenches is used as a ridge waveguide; the deep grooves are located in the side, away from the ridge waveguide, of any shallow groove, the deep grooves and the shallow grooves are arranged at intervals, and the deep grooves sequentially penetrate through the electrode contact layer, the P cladding, the P waveguide layer and the active region in the thickness direction of the stacked structure and extend into the N waveguide layer; the P-surface metal electrode is at least located on the top surface of the ridge waveguide; and the N-face metal electrode is at least located on a part of the N waveguide layer at the bottom of the deep groove. The coplanar electrode structure is at least beneficial to improving the uniformity of carrier injection in the coplanar electrode structure, so that a more uniform gain characteristic is realized.

Description

Technical Field

[0001] This invention belongs to the field of optical amplifier technology, and particularly relates to a semiconductor optical amplifier and its fabrication method. Background Technology

[0002] Photonic integrated circuits utilize mature manufacturing processes and packaging technologies of complementary metal-oxide-semiconductor (CMOS) circuits, and have wide applications in intercity and short-distance data communication, as well as fiber optic sensing. However, with the increasing variety and number of devices on integrated circuits, system complexity also gradually increases, leading to a significant increase in optical transmission loss in the circuit. This results in integrated circuits being unable to provide sufficient optical gain or achieve uniform gain characteristics. Summary of the Invention

[0003] In view of this, the present invention aims to provide a semiconductor optical amplifier and its fabrication method, which at least helps to improve the uniformity of carrier injection in the coplanar electrode structure, thereby achieving more uniform gain characteristics.

[0004] To achieve the above objectives, the technical solution created by this invention is implemented as follows: This invention provides a semiconductor optical amplifier, comprising: a stacked structure, the stacked structure including a substrate, an N-cladding layer, an N-type etch stop layer, an N-waveguide layer, an active region, a P-waveguide layer, a P-cladding layer, and an electrode contact layer stacked sequentially; two shallow trenches disposed within the stacked structure, the two shallow trenches being spaced apart along a first direction, and each shallow trench penetrating the electrode contact layer and extending into the P-cladding layer along the thickness direction of the stacked structure, the stacked structure between the two shallow trenches serving as a ridge waveguide; deep trenches disposed within the stacked structure, the deep trenches being located on the side of any shallow trench away from the ridge waveguide, and the deep trenches being spaced apart from the shallow trenches, the deep trenches sequentially penetrating the electrode contact layer, the P-cladding layer, the P-waveguide layer, and the active region along the thickness direction of the stacked structure and extending into the N-waveguide layer; a P-side metal electrode, the P-side metal electrode being at least located on the top surface of the ridge waveguide; and an N-side metal electrode, the N-side metal electrode being at least located on a portion of the N-waveguide layer at the bottom of the deep trench.

[0005] Furthermore, the semiconductor optical amplifier also includes an insulating layer located on the remaining stacked structure without P-side and N-side metal electrodes.

[0006] Furthermore, the P-plane metal electrode, shallow trench, and ridge waveguide all extend along the second direction, and the minimum angle between the second direction and the first direction is in the range of 80° to 86°.

[0007] Furthermore, the band gap of the N-type etch stop layer is narrower than that of the N-cladding layer, the band gap of the N-type etch stop layer is wider than that of the N-waveguide layer, and the band gap of the N-type etch stop layer is wider than that of the active region.

[0008] Furthermore, along the first direction, the distance between the P-side metal electrode and the N-side metal electrode is not less than 20 micrometers.

[0009] Furthermore, along the first direction, the width of the P-face metal electrode located on the top surface of the ridge waveguide is smaller than the width of the top surface of the ridge waveguide, and the distance from the P-face metal electrode located on the top surface of the ridge waveguide to the shallow trenches on both sides is the same.

[0010] Furthermore, in the first direction, the width of the N-face metal electrode on the N-waveguide layer at the bottom of the deep trench is smaller than the width of the bottom of the deep trench, and the distance from the N-face metal electrode on the N-waveguide layer at the bottom of the deep trench to the sidewalls of the deep trench on both sides is the same.

[0011] Furthermore, the P-side metal electrode includes a first contact portion and a first conductive portion connected together. The first contact portion is located on the top surface of the ridge waveguide, and the first conductive portion is located on the insulating layer on the side of the first contact portion away from the N-side metal electrode. The first conductive portion extends from the first contact portion to the first end of the stacked structure in the first direction.

[0012] Furthermore, the N-side metal electrode includes a second contact portion and a second conductive portion connected together. The second contact portion is located on a portion of the N-waveguide layer at the bottom of the deep trench, and the second conductive portion is located on an insulating layer on the side of the second contact portion away from the P-side metal electrode. The second conductive portion extends from the second contact portion to the second end of the stacked structure in the first direction.

[0013] Another aspect of this invention provides a method for fabricating a semiconductor optical amplifier, used to form the aforementioned semiconductor optical amplifier. The method for fabricating the semiconductor optical amplifier includes: forming a stacked structure, the stacked structure including a substrate, an N-cladding layer, an N-type etch stop layer, an N-waveguide layer, an active region, a P-waveguide layer, a P-cladding layer, and an electrode contact layer stacked sequentially; forming two shallow trenches within the stacked structure, the two shallow trenches being spaced apart along a first direction, and each shallow trench penetrating the electrode contact layer and extending into the P-cladding layer along the thickness direction of the stacked structure, the stacked structure between the two shallow trenches serving as a ridge waveguide; forming deep trenches within the stacked structure, the deep trenches being located on the side of any shallow trench away from the ridge waveguide, and the deep trenches being spaced apart from the shallow trenches, the deep trenches penetrating the electrode contact layer, the P-cladding layer, the P-waveguide layer, and the active region sequentially along the thickness direction of the stacked structure and extending into the N-waveguide layer; forming a P-surface metal electrode, the P-surface metal electrode being at least located on the top surface of the ridge waveguide; and forming an N-surface metal electrode, the N-surface metal electrode being at least located on the N-waveguide layer at the bottom portion of the deep trench.

[0014] Compared with the prior art, the present invention can achieve the following beneficial effects: In the semiconductor optical amplifier provided by the present invention, the N-side metal electrode and the P-side metal electrode are both located on the same side of the device. Most of the electrons injected from the N-side metal electrode are extended with low loss through the N-type etch stop layer to the bottom of the entire active region, and then injected vertically upward into the active region to recombine with the holes injected from the P-side metal electrode through the electrode contact layer. This achieves a uniform and low-resistance carrier injection path, alleviates the problem of uneven lateral carrier injection in the traditional coplanar electrode structure, and improves the gain uniformity of the semiconductor optical amplifier. The deep trench of the N-side metal electrode extends to the N-waveguide layer, and the shallow trench of the ridge waveguide extends to the P-cladding. In this way, not only can the resistance be reduced, the current injection efficiency improved, and sufficient optical gain provided, but the problem of uneven carrier injection in the traditional coplanar structure can also be overcome, which is conducive to obtaining more uniform gain characteristics. Moreover, the deep trench is conducive to improving the heat dissipation of the device, reducing heat accumulation, and reducing the impact of temperature changes on the gain characteristics of the semiconductor optical amplifier. This is conducive to further utilizing the semiconductor optical amplifier to realize complex, efficient, and powerful photonic integrated circuits. Attached Figure Description

[0015] The accompanying drawings, which form part of this invention, are used to provide a further understanding of the invention. The illustrative embodiments and descriptions of the invention are used to explain the invention and do not constitute an undue limitation of the invention. In the drawings: Figure 1 This is a schematic diagram of the structure of the semiconductor optical amplifier described in an embodiment of the present invention. Detailed Implementation

[0016] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and do not constitute a limitation thereof.

[0017] It should be noted that, unless otherwise specified, the embodiments and features described in the present invention can be combined with each other.

[0018] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," and "counterclockwise," etc., indicating orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on this invention. Furthermore, the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, features defined with "first," "second," etc., may explicitly or implicitly include one or more of that feature. In the description of this invention, unless otherwise stated, "a plurality of" means two or more.

[0019] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art will understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0020] The present invention will now be described in detail with reference to the accompanying drawings and embodiments.

[0021] refer to Figure 1 This invention provides a semiconductor optical amplifier, comprising: a stacked structure including a substrate 1, an N-cladding layer 2, an N-type etch stop layer 3, an N-waveguide layer 4, an active region 7, a P-waveguide layer 8, a P-cladding layer 9, and an electrode contact layer 10 stacked sequentially; two shallow trenches disposed within the stacked structure, the two shallow trenches being spaced apart along a first direction X, and each shallow trench penetrating the electrode contact layer 10 and extending into the P-cladding layer 9 along the thickness direction of the stacked structure, the stacked structure between the two shallow trenches serving as a ridge waveguide; deep trenches disposed within the stacked structure, the deep trenches being located on the side of any shallow trench away from the ridge waveguide, and the deep trenches being spaced apart from the shallow trenches, the deep trenches penetrating the electrode contact layer 10, the P-cladding layer 9, the P-waveguide layer 8, and the active region 7 sequentially along the thickness direction of the stacked structure and extending into the N-waveguide layer 4; a P-side metal electrode 11, the P-side metal electrode 11 being at least located on the top surface of the ridge waveguide; and an N-side metal electrode 6, the N-side metal electrode 6 being at least located on a portion of the N-waveguide layer 4 at the bottom of the deep trench.

[0022] The band gap of the N-type etch stop layer is narrower than that of the N-cladding layer, and the band gap of the N-type etch stop layer is wider than that of the N-waveguide layer. The band gap of the N-type etch stop layer is also wider than that of the active region. Thus, the N-type etch stop layer will not generate additional absorption loss for the operating wavelength of the device.

[0023] This invention places the N-side metal electrode 6 and the P-side metal electrode 11 on the same side of the device, which facilitates heterogeneous integration of semiconductor optical amplifiers and other devices. This effectively alleviates the loss problems existing in current photonic integrated circuits and provides sufficient optical gain for the integrated system. By using shallow trenches to define ridge waveguides and combining them with the N-side metal electrode 6 located at the bottom of deep trenches, it is possible to simultaneously manage the optical field mode and electrical performance. This ensures single-mode transmission while reducing resistance and improving heat dissipation, further optimizing the performance of the semiconductor optical amplifier.

[0024] Furthermore, in the semiconductor optical amplifier provided by this invention, most of the electrons injected from the N-side metal electrode 6 are extended with low loss through the N-type etch stop layer 3 to the bottom of the entire active region 7, and then injected vertically upward into the active region 7, where they recombine with the holes injected from the P-side metal electrode 11 through the electrode contact layer 10. This achieves a uniform and low-resistance carrier injection path, alleviating the problem of uneven lateral carrier injection and improving the gain uniformity of the semiconductor optical amplifier. In addition, the semiconductor optical amplifier has a dual-channel heat dissipation path. Some heat can be dissipated through the P-side metal electrode 11 above the ridge waveguide, and the wide deep trench also increases the heat dissipation area, forming an independent heat dissipation path to the substrate 1. This dual-path heat dissipation design helps reduce thermal resistance, suppresses the temperature rise of the active region 7 of the semiconductor optical amplifier under high drive current, and ensures high saturation power output under continuous conditions.

[0025] In some embodiments, substrate 1 is an InP-based substrate 1. It is understood that the choice of substrate 1 material determines the lasing wavelength. In other embodiments, substrate 1 material can also be highly doped GaAs. The active region 7 can be composed of InGaAsP multiple quantum wells and a barrier layer. In this way, it is easier to achieve the population inversion distribution condition and thus obtain higher gain output. The electrode contact layer 10 is a P-type heavily doped InGaAs material.

[0026] In some embodiments, in the stacked structure, the N-cladding layer 2 is an N-type highly doped material grown on the substrate 1, typically using the same material as the substrate 1, used to confine the optical field and transport electrons; the N-waveguide layer 4 is an N-type doped material grown on the N-type etch stop layer 3, which can be a single N-type doped material or a diluted waveguide with alternating growth of two materials; the active region 7 can be composed of alternating 5 InGaAsP quantum wells and 6 InGaAsP barriers, serving as the gain region of the amplifier and providing sufficient optical gain during electrical injection. The P-waveguide layer 8 is grown on the active region 7 and can be a single P-type doped material or a diluted waveguide with alternating growth of two materials. The P-cladding layer 9 is grown on the P-waveguide layer 8 and can be the same highly doped P-type material as the N-cladding layer 2, used to confine the optical field and transport holes. The electrode contact layer 10 is grown on the P-cladding layer 9, which is beneficial for forming P-plane ohmic contacts. The material of the N-plane metal electrode 6 can be a mixed metal including Au, Ge and Ni, and the material of the P-plane metal electrode 11 can be a mixed metal including Ti, Pt and Au.

[0027] The N-type etch stop layer 3 can be N-type doped InGaAsP, and the lateral resistance of the N-type etch stop layer 3 is lower than that of the N-cladding layer 2. The N-type etch stop layer 3 can provide a low-resistance horizontal carrier expansion channel, ensuring that electrons injected from the N-side metal electrode 6 can be uniformly injected from the bottom of the entire active region 7, which greatly improves the stability of the device.

[0028] In some embodiments, the width of the semiconductor optical amplifier is in the range of 480 micrometers to 520 micrometers, and the width of the deep trench is in the range of 324 micrometers to 360 micrometers. In this way, the deep trench can significantly increase the heat dissipation area and improve the heat dissipation performance of the device.

[0029] Furthermore, the semiconductor optical amplifier also includes an insulating layer 5, which is located on the remaining stacked structure without the P-side metal electrode 11 and the N-side metal electrode 6. In some examples, the insulating layer 5 may be made of silicon dioxide.

[0030] Furthermore, the P-plane metal electrode, shallow trench, and ridge waveguide all extend along the second direction Y, and the minimum angle between the second direction Y and the first direction X is in the range of 80° to 86°.

[0031] Furthermore, the minimum angle between the second direction Y and the first direction X is 83°. Thus, through the abrupt change in refractive index on both sides of the ridge waveguide, the hole injection path is steeper, and the lateral expansion to both sides is less, thereby effectively reducing transmission loss.

[0032] Furthermore, along the first direction X, the distance between the P-side metal electrode 11 and the N-side metal electrode 6 is not less than 20 micrometers. This helps to avoid the impact on device performance caused by the P-side metal electrode 11 and the N-side metal electrode 6 being too close.

[0033] Furthermore, along the first direction X, the width of the P-plane metal electrode 11 located on the top surface of the ridge waveguide is smaller than the width of the top surface of the ridge waveguide, and the distance from the P-plane metal electrode 11 to the shallow trenches on both sides is the same. Thus, the top surfaces of the ridge waveguide on both sides of the P-plane metal electrode 11 have insulating layers 5. The insulating layers 5 on the top surface of the ridge waveguide can achieve current blocking, reduce lateral current diffusion, improve injection efficiency, and lower the threshold current density. This design of the P-plane metal electrode 11 also ensures a high degree of spatial overlap between the current and the optical waveguide mode, thereby maximizing mode gain.

[0034] In some embodiments, the width of the P-plane metal electrode 11 located on the top surface of the ridge waveguide along the first direction X is 2 micrometers, and the width of the ridge waveguide is 6 micrometers.

[0035] Furthermore, in the first direction X, the width of the N-face metal electrode 6 on the N-waveguide layer 4 at the bottom of the deep trench is smaller than the width of the bottom of the deep trench, and the distance from the N-face metal electrode 6 on the N-waveguide layer 4 at the bottom of the deep trench to the sidewalls of the deep trench on both sides is the same.

[0036] Furthermore, the P-side metal electrode 11 includes a first contact portion and a first conductive portion connected together. The first contact portion is located on the top surface of the ridge waveguide, and the first conductive portion is located on the insulating layer 5 on the side of the first contact portion away from the N-side metal electrode 6. The first conductive portion extends from the first contact portion to the first end of the stacked structure in the first direction X.

[0037] Furthermore, the N-side metal electrode 6 includes a second contact portion and a second conductive portion connected together. The second contact portion is located on a portion of the N-waveguide layer 4 at the bottom of the deep trench, and the second conductive portion is located on the insulating layer 5 on the side of the second contact portion away from the P-side metal electrode 11. The second conductive portion extends from the second contact portion to the second end of the stacked structure in the first direction X.

[0038] Another aspect of this invention provides a method for fabricating a semiconductor optical amplifier, used to form the aforementioned semiconductor optical amplifier. The method for fabricating the semiconductor optical amplifier includes: forming a stacked structure, the stacked structure including a substrate 1, an N-cladding layer 2, an N-type etch stop layer 3, an N-waveguide layer 4, an active region 7, a P-waveguide layer 8, a P-cladding layer 9, and an electrode contact layer 10 stacked sequentially; forming two shallow trenches within the stacked structure, the two shallow trenches being spaced apart along a first direction X, and each shallow trench penetrating the electrode contact layer 10 and extending to the P-cladding layer along the thickness direction of the stacked structure. Within 9, the stacked structure between the two shallow trenches serves as a ridge waveguide; a deep trench is formed within the stacked structure, located on the side of any shallow trench away from the ridge waveguide, and the deep trenches are arranged alternately with the shallow trenches, the deep trenches sequentially penetrating the electrode contact layer 10, the P-cladding layer 9, the P-waveguide layer 8, and the active region 7 along the thickness direction of the stacked structure and extending into the N-waveguide layer 4; a P-surface metal electrode 11 is formed, the P-surface metal electrode 11 being located at least on the top surface of the ridge waveguide; an N-surface metal electrode 6 is formed, the N-surface metal electrode 6 being located at least on the portion of the N-waveguide layer 4 at the bottom of the deep trench.

[0039] In some embodiments, forming two shallow trenches within the stacked structure includes: rinsing the surface of the stacked structure with acetone and isopropanol solution to remove impurities, then rinsing with deionized water, drying with N2, and baking at 120°C for 5 minutes to completely remove surface moisture and ensure a more robust subsequent mask layer growth; growing a 400 nm thick silicon oxide layer on the stacked structure as a mask layer using plasma-enhanced chemical vapor deposition; placing the mask layer in an adhesion enhancer at approximately 130°C for 20 minutes to enhance the adhesion of the photoresist to the mask layer; spin-coating a layer of positive photoresist with a thickness of approximately 1 μm, heating it on a 100°C heating plate for 1 minute and 30 seconds to remove the solvent from the photoresist; and then performing photolithography using an I-line lithography machine with a precision of 1 μm, based on the photoresist thickness and the theoretical ridge waveguide pattern. The shape and size were determined, and the exposure time was set to 7.5s and the development time to 35s. The pattern on the photomask was accurately transferred to the photoresist, and then it was placed on a hot plate at 110℃ and heated for 1 minute to complete the hardening process, which improves the process stability of the photoresist in the subsequent etching process. Then, a plasma resist remover was used to optimize the photoresist morphology of the sidewalls. A thin layer of silicone oil was applied to the back of the stacked structure, which was then attached to a clean silicon wafer and placed in the chamber of an inductively coupled plasma etching equipment for etching of the mask layer, with an over-etching amount of 20%. After etching, the residual photoresist and silicone oil and other impurities were removed by repeated ultrasonic cleaning with acetone and isopropanol solution. The etching continued to the P-cladding layer 9, and the mask layer on the surface was removed by wet etching with a mixed solution of ammonium fluoride and hydrofluoric acid to obtain a stacked structure with two shallow trenches.

[0040] In some embodiments, forming deep trenches within the stacked structure includes: baking at 120°C for 5 minutes to completely remove surface moisture and ensure a more robust subsequent mask layer growth; growing a 400 nm thick silicon oxide layer as a mask layer on the stacked structure using plasma-enhanced chemical vapor deposition; spin-coating a layer of positive photoresist with a thickness of approximately 1 μm; heating on a 100°C hot plate for 1 minute and 30 seconds to remove the solvent from the photoresist; then performing photolithography using an I-line lithography machine; setting the exposure time to 7.5 seconds and the development time to 35 seconds based on the photoresist thickness and the theoretical deep trench pattern size; and precisely transferring the pattern on the photomask to the desired depth. The photoresist is then placed on a hot plate at 110°C and heated for 1 minute to complete the hardening process, improving the process stability of the photoresist in the subsequent etching process. The photoresist morphology of the sidewalls is then optimized using a plasma resist remover. A thin layer of silicone oil is applied to the back of the stacked structure, which is then attached to a clean silicon wafer and placed in the etching chamber of the etching equipment for etching of the mask layer, with an over-etching amount of 15%. After etching, the residual photoresist and silicone oil are removed by repeated ultrasonic cleaning with acetone and isopropanol solution. The etching continues until the N-waveguide layer 4 is reached. The mask layer on the surface is removed by wet etching with a mixed solution of ammonium fluoride and hydrofluoric acid to obtain the stacked structure with deep trenches.

[0041] In some cases, after obtaining a stacked structure with two shallow trenches and one deep trench, the stacked structure is baked at 120°C for 5 minutes to ensure that the subsequent insulating layer 5 is grown more firmly. A silicon oxide layer with a thickness of 300 nm is grown as the insulating layer 5 using plasma-enhanced chemical vapor deposition.

[0042] In some examples, the formation of the P-side metal electrode 11 is preceded by the formation of the P-side current injection window. Specifically, a layer of positive photoresist with a thickness of about 1 μm is spin-coated on the top surface of the insulating layer 5 and baked at 100°C for 1 min 30 s. The current injection window pattern on the photomask is projected onto the photoresist using a standard I-line lithography machine with an exposure time of 7.5 s and a development time of 35 s. The photoresist is then heated on a hot plate at 110°C for 1 min to complete the hardening process, thereby improving the process stability of the photoresist in the subsequent etching process. The photoresist morphology of the sidewalls is optimized using a plasma resist remover. A thin layer of silicone oil is coated on the back of the stacked structure and adhered to a clean silicon wafer. The wafer is then placed in the etching chamber for etching with an over-etching amount of 15% to ensure complete etching through the insulating layer 5 and exposing part of the electrode contact layer on the top surface of the ridge waveguide structure to facilitate the formation of a uniform, low-resistance ohmic contact with the P-side metal electrode 11, i.e., the formation of the P-side current injection window. After etching, the residual photoresist and silicone oil are removed by repeated ultrasonic cleaning with acetone and isopropanol solutions.

[0043] In some examples, forming the P-side metal electrode 11 includes: first forming an initial P-side metal electrode 11 layer, and then removing part of the initial P-side metal electrode 11 layer using a photolithography process to form the P-side metal electrode 11. A mixed metal with a thickness of about 300 nm and a composition including Ti, Pt and Au can be grown using a standard magnetron sputtering device as the initial P-side metal electrode 11 layer.

[0044] In some examples, after forming the P-side metal electrode 11, the process further includes: thermal annealing at 380°C for 90 seconds to obtain a robust metal deposition, thereby enabling the P-side metal electrode 11 to form a good ohmic contact with the electrode contact layer 10.

[0045] The method of forming the N-side metal electrode 6 is similar to that of forming the P-side metal electrode 11, and will not be described in detail here.

[0046] In some examples, after forming the N-side metal electrode 6, the substrate 1 is thinned and polished.

[0047] It should be understood that the various forms of processes shown above can be used to reorder, add, or delete steps. For example, the steps described in this invention disclosure can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution disclosed in this invention can be achieved, and this is not limited herein.

[0048] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A semiconductor optical amplifier, characterized by, The semiconductor optical amplifier comprises: a stack structure comprising a substrate, an N cladding layer, an N-type etching stop layer, an N waveguide layer, an active region, a P waveguide layer, a P cladding layer and an electrode contact layer stacked in sequence; two shallow trenches arranged in the stack structure, the two shallow trenches are arranged in a first direction and each shallow trench penetrates the electrode contact layer and extends into the P cladding layer along the thickness direction of the stack structure, and the stack structure between the two shallow trenches serves as a ridge waveguide; a deep trench arranged in the stack structure, the deep trench is located on a side of any shallow trench away from the ridge waveguide, and the deep trench is arranged in a second direction and penetrates the electrode contact layer, the P cladding layer, the P waveguide layer and the active region in sequence along the thickness direction of the stack structure and extends into the N waveguide layer; a P-face metal electrode located on at least the top surface of the ridge waveguide; an N-face metal electrode located on at least part of the N waveguide layer at the bottom of the deep trench.

2. The semiconductor optical amplifier of claim 1, wherein, The semiconductor optical amplifier further comprises an insulating layer located on the remaining stack structure which is not provided with the P-face metal electrode and the N-face metal electrode.

3. The semiconductor optical amplifier of claim 1, wherein, The P-face metal electrode, the shallow trenches and the ridge waveguide all extend along a second direction, and the smallest included angle between the second direction and the first direction is in the range of 80°-86°.

4. The semiconductor optical amplifier of claim 1, wherein, The band gap of the N-type etching stop layer is narrower than that of the N cladding layer, wider than that of the N waveguide layer, and wider than that of the active region.

5. The semiconductor optical amplifier of claim 1, wherein, In the first direction, the distance between the P-face metal electrode and the N-face metal electrode is not less than 20 microns.

6. The semiconductor optical amplifier of claim 1, wherein, In the first direction, the width of the P-face metal electrode on the top surface of the ridge waveguide is less than the width of the top surface of the ridge waveguide, and the distance from the P-face metal electrode on the top surface of the ridge waveguide to the shallow trenches on both sides is the same.

7. The semiconductor optical amplifier of claim 1, wherein, In the first direction, the width of the N-face metal electrode on the N waveguide layer at the bottom of the deep trench is less than the width of the bottom of the deep trench, and the distance from the N-face metal electrode on the N waveguide layer at the bottom of the deep trench to the sidewalls of the deep trenches on both sides is the same.

8. The semiconductor optical amplifier of claim 2, wherein, The P-face metal electrode comprises a first contact portion and a first lead portion connected in sequence, the first contact portion is located on the top surface of the ridge waveguide, the first lead portion is located on the insulating layer away from the N-face metal electrode on a side of the first contact portion, and the first lead portion extends from the first contact portion to a first end of the stack structure in the first direction.

9. The semiconductor optical amplifier of claim 2, wherein, The N-face metal electrode comprises a second contact portion and a second lead portion connected in sequence, the second contact portion is located on part of the N waveguide layer at the bottom of the deep trench, the second lead portion is located on the insulating layer away from the P-face metal electrode on a side of the second contact portion, and the second lead portion extends from the second contact portion to a second end of the stack structure in the first direction.

10. A method of fabricating a semiconductor optical amplifier, characterized by, The application relates to a semiconductor optical amplifier and a preparation method thereof. A stack structure is formed, which comprises a substrate, an N cladding layer, an N-type etching stop layer, an N waveguide layer, an active region, a P waveguide layer, a P cladding layer and an electrode contact layer which are sequentially stacked; Two shallow trenches are formed in the stack structure, the two shallow trenches are arranged at intervals along a first direction, and each shallow trench penetrates the electrode contact layer and extends into the P cladding layer along the thickness direction of the stack structure, and the stack structure between the two shallow trenches serves as a ridge waveguide; A deep trench is formed in the stack structure, the deep trench is located on the side of any shallow trench away from the ridge waveguide, and the deep trench is arranged at intervals with the shallow trench, and the deep trench penetrates the electrode contact layer, the P cladding layer, the P waveguide layer and the active region in sequence along the thickness direction of the stack structure and extends into the N waveguide layer; A P-face metal electrode is formed, and the P-face metal electrode is located at least on the top surface of the ridge waveguide; An N-face metal electrode is formed, and the N-face metal electrode is located at least on the N waveguide layer of part of the bottom of the deep trench.

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